1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (C) 2012-2014, 2018-2021 Intel Corporation
4  * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
5  * Copyright (C) 2015-2017 Intel Deutschland GmbH
6  */
7 #include <linux/devcoredump.h>
8 #include "iwl-drv.h"
9 #include "runtime.h"
10 #include "dbg.h"
11 #include "debugfs.h"
12 #include "iwl-io.h"
13 #include "iwl-prph.h"
14 #include "iwl-csr.h"
15 #include "pnvm.h"
16 
17 /*
18  * Note: This structure is read from the device with IO accesses,
19  * and the reading already does the endian conversion. As it is
20  * read with u32-sized accesses, any members with a different size
21  * need to be ordered correctly though!
22  */
23 struct iwl_error_event_table {
24 	u32 valid;		/* (nonzero) valid, (0) log is empty */
25 	u32 error_id;		/* type of error */
26 	u32 trm_hw_status0;	/* TRM HW status */
27 	u32 trm_hw_status1;	/* TRM HW status */
28 	u32 blink2;		/* branch link */
29 	u32 ilink1;		/* interrupt link */
30 	u32 ilink2;		/* interrupt link */
31 	u32 data1;		/* error-specific data */
32 	u32 data2;		/* error-specific data */
33 	u32 data3;		/* error-specific data */
34 	u32 bcon_time;		/* beacon timer */
35 	u32 tsf_low;		/* network timestamp function timer */
36 	u32 tsf_hi;		/* network timestamp function timer */
37 	u32 gp1;		/* GP1 timer register */
38 	u32 gp2;		/* GP2 timer register */
39 	u32 fw_rev_type;	/* firmware revision type */
40 	u32 major;		/* uCode version major */
41 	u32 minor;		/* uCode version minor */
42 	u32 hw_ver;		/* HW Silicon version */
43 	u32 brd_ver;		/* HW board version */
44 	u32 log_pc;		/* log program counter */
45 	u32 frame_ptr;		/* frame pointer */
46 	u32 stack_ptr;		/* stack pointer */
47 	u32 hcmd;		/* last host command header */
48 	u32 isr0;		/* isr status register LMPM_NIC_ISR0:
49 				 * rxtx_flag */
50 	u32 isr1;		/* isr status register LMPM_NIC_ISR1:
51 				 * host_flag */
52 	u32 isr2;		/* isr status register LMPM_NIC_ISR2:
53 				 * enc_flag */
54 	u32 isr3;		/* isr status register LMPM_NIC_ISR3:
55 				 * time_flag */
56 	u32 isr4;		/* isr status register LMPM_NIC_ISR4:
57 				 * wico interrupt */
58 	u32 last_cmd_id;	/* last HCMD id handled by the firmware */
59 	u32 wait_event;		/* wait event() caller address */
60 	u32 l2p_control;	/* L2pControlField */
61 	u32 l2p_duration;	/* L2pDurationField */
62 	u32 l2p_mhvalid;	/* L2pMhValidBits */
63 	u32 l2p_addr_match;	/* L2pAddrMatchStat */
64 	u32 lmpm_pmg_sel;	/* indicate which clocks are turned on
65 				 * (LMPM_PMG_SEL) */
66 	u32 u_timestamp;	/* indicate when the date and time of the
67 				 * compilation */
68 	u32 flow_handler;	/* FH read/write pointers, RX credit */
69 } __packed /* LOG_ERROR_TABLE_API_S_VER_3 */;
70 
71 /*
72  * UMAC error struct - relevant starting from family 8000 chip.
73  * Note: This structure is read from the device with IO accesses,
74  * and the reading already does the endian conversion. As it is
75  * read with u32-sized accesses, any members with a different size
76  * need to be ordered correctly though!
77  */
78 struct iwl_umac_error_event_table {
79 	u32 valid;		/* (nonzero) valid, (0) log is empty */
80 	u32 error_id;		/* type of error */
81 	u32 blink1;		/* branch link */
82 	u32 blink2;		/* branch link */
83 	u32 ilink1;		/* interrupt link */
84 	u32 ilink2;		/* interrupt link */
85 	u32 data1;		/* error-specific data */
86 	u32 data2;		/* error-specific data */
87 	u32 data3;		/* error-specific data */
88 	u32 umac_major;
89 	u32 umac_minor;
90 	u32 frame_pointer;	/* core register 27*/
91 	u32 stack_pointer;	/* core register 28 */
92 	u32 cmd_header;		/* latest host cmd sent to UMAC */
93 	u32 nic_isr_pref;	/* ISR status register */
94 } __packed;
95 
96 #define ERROR_START_OFFSET  (1 * sizeof(u32))
97 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
98 
99 static void iwl_fwrt_dump_umac_error_log(struct iwl_fw_runtime *fwrt)
100 {
101 	struct iwl_trans *trans = fwrt->trans;
102 	struct iwl_umac_error_event_table table = {};
103 	u32 base = fwrt->trans->dbg.umac_error_event_table;
104 	char pnvm_name[MAX_PNVM_NAME];
105 
106 	if (!base &&
107 	    !(fwrt->trans->dbg.error_event_table_tlv_status &
108 	      IWL_ERROR_EVENT_TABLE_UMAC))
109 		return;
110 
111 	iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table));
112 
113 	if (table.valid)
114 		fwrt->dump.umac_err_id = table.error_id;
115 
116 	if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
117 		IWL_ERR(trans, "Start IWL Error Log Dump:\n");
118 		IWL_ERR(trans, "Transport status: 0x%08lX, valid: %d\n",
119 			fwrt->trans->status, table.valid);
120 	}
121 
122 	if ((table.error_id & ~FW_SYSASSERT_CPU_MASK) ==
123 	    FW_SYSASSERT_PNVM_MISSING) {
124 		iwl_pnvm_get_fs_name(trans, pnvm_name, sizeof(pnvm_name));
125 		IWL_ERR(fwrt, "PNVM data is missing, please install %s\n",
126 			pnvm_name);
127 	}
128 
129 	IWL_ERR(fwrt, "0x%08X | %s\n", table.error_id,
130 		iwl_fw_lookup_assert_desc(table.error_id));
131 	IWL_ERR(fwrt, "0x%08X | umac branchlink1\n", table.blink1);
132 	IWL_ERR(fwrt, "0x%08X | umac branchlink2\n", table.blink2);
133 	IWL_ERR(fwrt, "0x%08X | umac interruptlink1\n", table.ilink1);
134 	IWL_ERR(fwrt, "0x%08X | umac interruptlink2\n", table.ilink2);
135 	IWL_ERR(fwrt, "0x%08X | umac data1\n", table.data1);
136 	IWL_ERR(fwrt, "0x%08X | umac data2\n", table.data2);
137 	IWL_ERR(fwrt, "0x%08X | umac data3\n", table.data3);
138 	IWL_ERR(fwrt, "0x%08X | umac major\n", table.umac_major);
139 	IWL_ERR(fwrt, "0x%08X | umac minor\n", table.umac_minor);
140 	IWL_ERR(fwrt, "0x%08X | frame pointer\n", table.frame_pointer);
141 	IWL_ERR(fwrt, "0x%08X | stack pointer\n", table.stack_pointer);
142 	IWL_ERR(fwrt, "0x%08X | last host cmd\n", table.cmd_header);
143 	IWL_ERR(fwrt, "0x%08X | isr status reg\n", table.nic_isr_pref);
144 }
145 
146 static void iwl_fwrt_dump_lmac_error_log(struct iwl_fw_runtime *fwrt, u8 lmac_num)
147 {
148 	struct iwl_trans *trans = fwrt->trans;
149 	struct iwl_error_event_table table = {};
150 	u32 val, base = fwrt->trans->dbg.lmac_error_event_table[lmac_num];
151 
152 	if (fwrt->cur_fw_img == IWL_UCODE_INIT) {
153 		if (!base)
154 			base = fwrt->fw->init_errlog_ptr;
155 	} else {
156 		if (!base)
157 			base = fwrt->fw->inst_errlog_ptr;
158 	}
159 
160 	if (base < 0x400000) {
161 		IWL_ERR(fwrt,
162 			"Not valid error log pointer 0x%08X for %s uCode\n",
163 			base,
164 			(fwrt->cur_fw_img == IWL_UCODE_INIT)
165 			? "Init" : "RT");
166 		return;
167 	}
168 
169 	/* check if there is a HW error */
170 	val = iwl_trans_read_mem32(trans, base);
171 	if (((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50)) {
172 		int err;
173 
174 		IWL_ERR(trans, "HW error, resetting before reading\n");
175 
176 		/* reset the device */
177 		err = iwl_trans_sw_reset(trans, true);
178 		if (err)
179 			return;
180 
181 		err = iwl_finish_nic_init(trans);
182 		if (err)
183 			return;
184 	}
185 
186 	iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table));
187 
188 	if (table.valid)
189 		fwrt->dump.lmac_err_id[lmac_num] = table.error_id;
190 
191 	if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
192 		IWL_ERR(trans, "Start IWL Error Log Dump:\n");
193 		IWL_ERR(trans, "Transport status: 0x%08lX, valid: %d\n",
194 			fwrt->trans->status, table.valid);
195 	}
196 
197 	/* Do not change this output - scripts rely on it */
198 
199 	IWL_ERR(fwrt, "Loaded firmware version: %s\n", fwrt->fw->fw_version);
200 
201 	IWL_ERR(fwrt, "0x%08X | %-28s\n", table.error_id,
202 		iwl_fw_lookup_assert_desc(table.error_id));
203 	IWL_ERR(fwrt, "0x%08X | trm_hw_status0\n", table.trm_hw_status0);
204 	IWL_ERR(fwrt, "0x%08X | trm_hw_status1\n", table.trm_hw_status1);
205 	IWL_ERR(fwrt, "0x%08X | branchlink2\n", table.blink2);
206 	IWL_ERR(fwrt, "0x%08X | interruptlink1\n", table.ilink1);
207 	IWL_ERR(fwrt, "0x%08X | interruptlink2\n", table.ilink2);
208 	IWL_ERR(fwrt, "0x%08X | data1\n", table.data1);
209 	IWL_ERR(fwrt, "0x%08X | data2\n", table.data2);
210 	IWL_ERR(fwrt, "0x%08X | data3\n", table.data3);
211 	IWL_ERR(fwrt, "0x%08X | beacon time\n", table.bcon_time);
212 	IWL_ERR(fwrt, "0x%08X | tsf low\n", table.tsf_low);
213 	IWL_ERR(fwrt, "0x%08X | tsf hi\n", table.tsf_hi);
214 	IWL_ERR(fwrt, "0x%08X | time gp1\n", table.gp1);
215 	IWL_ERR(fwrt, "0x%08X | time gp2\n", table.gp2);
216 	IWL_ERR(fwrt, "0x%08X | uCode revision type\n", table.fw_rev_type);
217 	IWL_ERR(fwrt, "0x%08X | uCode version major\n", table.major);
218 	IWL_ERR(fwrt, "0x%08X | uCode version minor\n", table.minor);
219 	IWL_ERR(fwrt, "0x%08X | hw version\n", table.hw_ver);
220 	IWL_ERR(fwrt, "0x%08X | board version\n", table.brd_ver);
221 	IWL_ERR(fwrt, "0x%08X | hcmd\n", table.hcmd);
222 	IWL_ERR(fwrt, "0x%08X | isr0\n", table.isr0);
223 	IWL_ERR(fwrt, "0x%08X | isr1\n", table.isr1);
224 	IWL_ERR(fwrt, "0x%08X | isr2\n", table.isr2);
225 	IWL_ERR(fwrt, "0x%08X | isr3\n", table.isr3);
226 	IWL_ERR(fwrt, "0x%08X | isr4\n", table.isr4);
227 	IWL_ERR(fwrt, "0x%08X | last cmd Id\n", table.last_cmd_id);
228 	IWL_ERR(fwrt, "0x%08X | wait_event\n", table.wait_event);
229 	IWL_ERR(fwrt, "0x%08X | l2p_control\n", table.l2p_control);
230 	IWL_ERR(fwrt, "0x%08X | l2p_duration\n", table.l2p_duration);
231 	IWL_ERR(fwrt, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid);
232 	IWL_ERR(fwrt, "0x%08X | l2p_addr_match\n", table.l2p_addr_match);
233 	IWL_ERR(fwrt, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel);
234 	IWL_ERR(fwrt, "0x%08X | timestamp\n", table.u_timestamp);
235 	IWL_ERR(fwrt, "0x%08X | flow_handler\n", table.flow_handler);
236 }
237 
238 /*
239  * TCM error struct.
240  * Note: This structure is read from the device with IO accesses,
241  * and the reading already does the endian conversion. As it is
242  * read with u32-sized accesses, any members with a different size
243  * need to be ordered correctly though!
244  */
245 struct iwl_tcm_error_event_table {
246 	u32 valid;
247 	u32 error_id;
248 	u32 blink2;
249 	u32 ilink1;
250 	u32 ilink2;
251 	u32 data1, data2, data3;
252 	u32 logpc;
253 	u32 frame_pointer;
254 	u32 stack_pointer;
255 	u32 msgid;
256 	u32 isr;
257 	u32 hw_status[5];
258 	u32 sw_status[1];
259 	u32 reserved[4];
260 } __packed; /* TCM_LOG_ERROR_TABLE_API_S_VER_1 */
261 
262 static void iwl_fwrt_dump_tcm_error_log(struct iwl_fw_runtime *fwrt, int idx)
263 {
264 	struct iwl_trans *trans = fwrt->trans;
265 	struct iwl_tcm_error_event_table table = {};
266 	u32 base = fwrt->trans->dbg.tcm_error_event_table[idx];
267 	int i;
268 	u32 flag = idx ? IWL_ERROR_EVENT_TABLE_TCM2 :
269 			 IWL_ERROR_EVENT_TABLE_TCM1;
270 
271 	if (!base || !(fwrt->trans->dbg.error_event_table_tlv_status & flag))
272 		return;
273 
274 	iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table));
275 
276 	IWL_ERR(fwrt, "TCM%d status:\n", idx + 1);
277 	IWL_ERR(fwrt, "0x%08X | error ID\n", table.error_id);
278 	IWL_ERR(fwrt, "0x%08X | tcm branchlink2\n", table.blink2);
279 	IWL_ERR(fwrt, "0x%08X | tcm interruptlink1\n", table.ilink1);
280 	IWL_ERR(fwrt, "0x%08X | tcm interruptlink2\n", table.ilink2);
281 	IWL_ERR(fwrt, "0x%08X | tcm data1\n", table.data1);
282 	IWL_ERR(fwrt, "0x%08X | tcm data2\n", table.data2);
283 	IWL_ERR(fwrt, "0x%08X | tcm data3\n", table.data3);
284 	IWL_ERR(fwrt, "0x%08X | tcm log PC\n", table.logpc);
285 	IWL_ERR(fwrt, "0x%08X | tcm frame pointer\n", table.frame_pointer);
286 	IWL_ERR(fwrt, "0x%08X | tcm stack pointer\n", table.stack_pointer);
287 	IWL_ERR(fwrt, "0x%08X | tcm msg ID\n", table.msgid);
288 	IWL_ERR(fwrt, "0x%08X | tcm ISR status\n", table.isr);
289 	for (i = 0; i < ARRAY_SIZE(table.hw_status); i++)
290 		IWL_ERR(fwrt, "0x%08X | tcm HW status[%d]\n",
291 			table.hw_status[i], i);
292 	for (i = 0; i < ARRAY_SIZE(table.sw_status); i++)
293 		IWL_ERR(fwrt, "0x%08X | tcm SW status[%d]\n",
294 			table.sw_status[i], i);
295 }
296 
297 /*
298  * RCM error struct.
299  * Note: This structure is read from the device with IO accesses,
300  * and the reading already does the endian conversion. As it is
301  * read with u32-sized accesses, any members with a different size
302  * need to be ordered correctly though!
303  */
304 struct iwl_rcm_error_event_table {
305 	u32 valid;
306 	u32 error_id;
307 	u32 blink2;
308 	u32 ilink1;
309 	u32 ilink2;
310 	u32 data1, data2, data3;
311 	u32 logpc;
312 	u32 frame_pointer;
313 	u32 stack_pointer;
314 	u32 msgid;
315 	u32 isr;
316 	u32 frame_hw_status;
317 	u32 mbx_lmac_to_rcm_req;
318 	u32 mbx_rcm_to_lmac_req;
319 	u32 mh_ctl;
320 	u32 mh_addr1_lo;
321 	u32 mh_info;
322 	u32 mh_err;
323 	u32 reserved[3];
324 } __packed; /* RCM_LOG_ERROR_TABLE_API_S_VER_1 */
325 
326 static void iwl_fwrt_dump_rcm_error_log(struct iwl_fw_runtime *fwrt, int idx)
327 {
328 	struct iwl_trans *trans = fwrt->trans;
329 	struct iwl_rcm_error_event_table table = {};
330 	u32 base = fwrt->trans->dbg.rcm_error_event_table[idx];
331 	u32 flag = idx ? IWL_ERROR_EVENT_TABLE_RCM2 :
332 			 IWL_ERROR_EVENT_TABLE_RCM1;
333 
334 	if (!base || !(fwrt->trans->dbg.error_event_table_tlv_status & flag))
335 		return;
336 
337 	iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table));
338 
339 	IWL_ERR(fwrt, "RCM%d status:\n", idx + 1);
340 	IWL_ERR(fwrt, "0x%08X | error ID\n", table.error_id);
341 	IWL_ERR(fwrt, "0x%08X | rcm branchlink2\n", table.blink2);
342 	IWL_ERR(fwrt, "0x%08X | rcm interruptlink1\n", table.ilink1);
343 	IWL_ERR(fwrt, "0x%08X | rcm interruptlink2\n", table.ilink2);
344 	IWL_ERR(fwrt, "0x%08X | rcm data1\n", table.data1);
345 	IWL_ERR(fwrt, "0x%08X | rcm data2\n", table.data2);
346 	IWL_ERR(fwrt, "0x%08X | rcm data3\n", table.data3);
347 	IWL_ERR(fwrt, "0x%08X | rcm log PC\n", table.logpc);
348 	IWL_ERR(fwrt, "0x%08X | rcm frame pointer\n", table.frame_pointer);
349 	IWL_ERR(fwrt, "0x%08X | rcm stack pointer\n", table.stack_pointer);
350 	IWL_ERR(fwrt, "0x%08X | rcm msg ID\n", table.msgid);
351 	IWL_ERR(fwrt, "0x%08X | rcm ISR status\n", table.isr);
352 	IWL_ERR(fwrt, "0x%08X | frame HW status\n", table.frame_hw_status);
353 	IWL_ERR(fwrt, "0x%08X | LMAC-to-RCM request mbox\n",
354 		table.mbx_lmac_to_rcm_req);
355 	IWL_ERR(fwrt, "0x%08X | RCM-to-LMAC request mbox\n",
356 		table.mbx_rcm_to_lmac_req);
357 	IWL_ERR(fwrt, "0x%08X | MAC header control\n", table.mh_ctl);
358 	IWL_ERR(fwrt, "0x%08X | MAC header addr1 low\n", table.mh_addr1_lo);
359 	IWL_ERR(fwrt, "0x%08X | MAC header info\n", table.mh_info);
360 	IWL_ERR(fwrt, "0x%08X | MAC header error\n", table.mh_err);
361 }
362 
363 static void iwl_fwrt_dump_iml_error_log(struct iwl_fw_runtime *fwrt)
364 {
365 	struct iwl_trans *trans = fwrt->trans;
366 	u32 error, data1;
367 
368 	if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) {
369 		error = UMAG_SB_CPU_2_STATUS;
370 		data1 = UMAG_SB_CPU_1_STATUS;
371 	} else if (fwrt->trans->trans_cfg->device_family >=
372 		   IWL_DEVICE_FAMILY_8000) {
373 		error = SB_CPU_2_STATUS;
374 		data1 = SB_CPU_1_STATUS;
375 	} else {
376 		return;
377 	}
378 
379 	error = iwl_read_umac_prph(trans, UMAG_SB_CPU_2_STATUS);
380 
381 	IWL_ERR(trans, "IML/ROM dump:\n");
382 
383 	if (error & 0xFFFF0000)
384 		IWL_ERR(trans, "0x%04X | IML/ROM SYSASSERT\n", error >> 16);
385 
386 	IWL_ERR(fwrt, "0x%08X | IML/ROM error/state\n", error);
387 	IWL_ERR(fwrt, "0x%08X | IML/ROM data1\n",
388 		iwl_read_umac_prph(trans, data1));
389 
390 	if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000)
391 		IWL_ERR(fwrt, "0x%08X | IML/ROM WFPM_AUTH_KEY_0\n",
392 			iwl_read_umac_prph(trans, SB_MODIFY_CFG_FLAG));
393 }
394 
395 #define FSEQ_REG(x) { .addr = (x), .str = #x, }
396 
397 static void iwl_fwrt_dump_fseq_regs(struct iwl_fw_runtime *fwrt)
398 {
399 	struct iwl_trans *trans = fwrt->trans;
400 	int i;
401 	struct {
402 		u32 addr;
403 		const char *str;
404 	} fseq_regs[] = {
405 		FSEQ_REG(FSEQ_ERROR_CODE),
406 		FSEQ_REG(FSEQ_TOP_INIT_VERSION),
407 		FSEQ_REG(FSEQ_CNVIO_INIT_VERSION),
408 		FSEQ_REG(FSEQ_OTP_VERSION),
409 		FSEQ_REG(FSEQ_TOP_CONTENT_VERSION),
410 		FSEQ_REG(FSEQ_ALIVE_TOKEN),
411 		FSEQ_REG(FSEQ_CNVI_ID),
412 		FSEQ_REG(FSEQ_CNVR_ID),
413 		FSEQ_REG(CNVI_AUX_MISC_CHIP),
414 		FSEQ_REG(CNVR_AUX_MISC_CHIP),
415 		FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM),
416 		FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR),
417 	};
418 
419 	if (!iwl_trans_grab_nic_access(trans))
420 		return;
421 
422 	IWL_ERR(fwrt, "Fseq Registers:\n");
423 
424 	for (i = 0; i < ARRAY_SIZE(fseq_regs); i++)
425 		IWL_ERR(fwrt, "0x%08X | %s\n",
426 			iwl_read_prph_no_grab(trans, fseq_regs[i].addr),
427 			fseq_regs[i].str);
428 
429 	iwl_trans_release_nic_access(trans);
430 }
431 
432 void iwl_fwrt_dump_error_logs(struct iwl_fw_runtime *fwrt)
433 {
434 	if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) {
435 		IWL_ERR(fwrt,
436 			"DEVICE_ENABLED bit is not set. Aborting dump.\n");
437 		return;
438 	}
439 
440 	iwl_fwrt_dump_lmac_error_log(fwrt, 0);
441 	if (fwrt->trans->dbg.lmac_error_event_table[1])
442 		iwl_fwrt_dump_lmac_error_log(fwrt, 1);
443 	iwl_fwrt_dump_umac_error_log(fwrt);
444 	iwl_fwrt_dump_tcm_error_log(fwrt, 0);
445 	iwl_fwrt_dump_rcm_error_log(fwrt, 0);
446 	iwl_fwrt_dump_tcm_error_log(fwrt, 1);
447 	iwl_fwrt_dump_rcm_error_log(fwrt, 1);
448 	iwl_fwrt_dump_iml_error_log(fwrt);
449 	iwl_fwrt_dump_fseq_regs(fwrt);
450 
451 	if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
452 		u32 scratch = iwl_read32(fwrt->trans, CSR_FUNC_SCRATCH);
453 
454 		IWL_ERR(fwrt, "Function Scratch status:\n");
455 		IWL_ERR(fwrt, "0x%08X | Func Scratch\n", scratch);
456 	}
457 }
458 IWL_EXPORT_SYMBOL(iwl_fwrt_dump_error_logs);
459