1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2012-2014, 2018-2023 Intel Corporation 4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/devcoredump.h> 8 #include "iwl-drv.h" 9 #include "runtime.h" 10 #include "dbg.h" 11 #include "debugfs.h" 12 #include "iwl-io.h" 13 #include "iwl-prph.h" 14 #include "iwl-csr.h" 15 #include "pnvm.h" 16 17 #define FW_ASSERT_LMAC_FATAL 0x70 18 #define FW_ASSERT_LMAC2_FATAL 0x72 19 #define FW_ASSERT_UMAC_FATAL 0x71 20 #define UMAC_RT_NMI_LMAC2_FATAL 0x72 21 #define RT_NMI_INTERRUPT_OTHER_LMAC_FATAL 0x73 22 #define FW_ASSERT_NMI_UNKNOWN 0x84 23 24 /* 25 * Note: This structure is read from the device with IO accesses, 26 * and the reading already does the endian conversion. As it is 27 * read with u32-sized accesses, any members with a different size 28 * need to be ordered correctly though! 29 */ 30 struct iwl_error_event_table { 31 u32 valid; /* (nonzero) valid, (0) log is empty */ 32 u32 error_id; /* type of error */ 33 u32 trm_hw_status0; /* TRM HW status */ 34 u32 trm_hw_status1; /* TRM HW status */ 35 u32 blink2; /* branch link */ 36 u32 ilink1; /* interrupt link */ 37 u32 ilink2; /* interrupt link */ 38 u32 data1; /* error-specific data */ 39 u32 data2; /* error-specific data */ 40 u32 data3; /* error-specific data */ 41 u32 bcon_time; /* beacon timer */ 42 u32 tsf_low; /* network timestamp function timer */ 43 u32 tsf_hi; /* network timestamp function timer */ 44 u32 gp1; /* GP1 timer register */ 45 u32 gp2; /* GP2 timer register */ 46 u32 fw_rev_type; /* firmware revision type */ 47 u32 major; /* uCode version major */ 48 u32 minor; /* uCode version minor */ 49 u32 hw_ver; /* HW Silicon version */ 50 u32 brd_ver; /* HW board version */ 51 u32 log_pc; /* log program counter */ 52 u32 frame_ptr; /* frame pointer */ 53 u32 stack_ptr; /* stack pointer */ 54 u32 hcmd; /* last host command header */ 55 u32 isr0; /* isr status register LMPM_NIC_ISR0: 56 * rxtx_flag */ 57 u32 isr1; /* isr status register LMPM_NIC_ISR1: 58 * host_flag */ 59 u32 isr2; /* isr status register LMPM_NIC_ISR2: 60 * enc_flag */ 61 u32 isr3; /* isr status register LMPM_NIC_ISR3: 62 * time_flag */ 63 u32 isr4; /* isr status register LMPM_NIC_ISR4: 64 * wico interrupt */ 65 u32 last_cmd_id; /* last HCMD id handled by the firmware */ 66 u32 wait_event; /* wait event() caller address */ 67 u32 l2p_control; /* L2pControlField */ 68 u32 l2p_duration; /* L2pDurationField */ 69 u32 l2p_mhvalid; /* L2pMhValidBits */ 70 u32 l2p_addr_match; /* L2pAddrMatchStat */ 71 u32 lmpm_pmg_sel; /* indicate which clocks are turned on 72 * (LMPM_PMG_SEL) */ 73 u32 u_timestamp; /* indicate when the date and time of the 74 * compilation */ 75 u32 flow_handler; /* FH read/write pointers, RX credit */ 76 } __packed /* LOG_ERROR_TABLE_API_S_VER_3 */; 77 78 /* 79 * UMAC error struct - relevant starting from family 8000 chip. 80 * Note: This structure is read from the device with IO accesses, 81 * and the reading already does the endian conversion. As it is 82 * read with u32-sized accesses, any members with a different size 83 * need to be ordered correctly though! 84 */ 85 struct iwl_umac_error_event_table { 86 u32 valid; /* (nonzero) valid, (0) log is empty */ 87 u32 error_id; /* type of error */ 88 u32 blink1; /* branch link */ 89 u32 blink2; /* branch link */ 90 u32 ilink1; /* interrupt link */ 91 u32 ilink2; /* interrupt link */ 92 u32 data1; /* error-specific data */ 93 u32 data2; /* error-specific data */ 94 u32 data3; /* error-specific data */ 95 u32 umac_major; 96 u32 umac_minor; 97 u32 frame_pointer; /* core register 27*/ 98 u32 stack_pointer; /* core register 28 */ 99 u32 cmd_header; /* latest host cmd sent to UMAC */ 100 u32 nic_isr_pref; /* ISR status register */ 101 } __packed; 102 103 #define ERROR_START_OFFSET (1 * sizeof(u32)) 104 #define ERROR_ELEM_SIZE (7 * sizeof(u32)) 105 106 static bool iwl_fwrt_if_errorid_other_cpu(u32 err_id) 107 { 108 err_id &= 0xFF; 109 110 if ((err_id >= FW_ASSERT_LMAC_FATAL && 111 err_id <= RT_NMI_INTERRUPT_OTHER_LMAC_FATAL) || 112 err_id == FW_ASSERT_NMI_UNKNOWN) 113 return true; 114 return false; 115 } 116 117 static void iwl_fwrt_dump_umac_error_log(struct iwl_fw_runtime *fwrt) 118 { 119 struct iwl_trans *trans = fwrt->trans; 120 struct iwl_umac_error_event_table table = {}; 121 u32 base = fwrt->trans->dbg.umac_error_event_table; 122 char pnvm_name[MAX_PNVM_NAME]; 123 124 if (!base && 125 !(fwrt->trans->dbg.error_event_table_tlv_status & 126 IWL_ERROR_EVENT_TABLE_UMAC)) 127 return; 128 129 iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table)); 130 131 if (table.valid) 132 fwrt->dump.umac_err_id = table.error_id; 133 134 if (!iwl_fwrt_if_errorid_other_cpu(fwrt->dump.umac_err_id) && 135 !fwrt->trans->dbg.dump_file_name_ext_valid) { 136 fwrt->trans->dbg.dump_file_name_ext_valid = true; 137 snprintf(fwrt->trans->dbg.dump_file_name_ext, IWL_FW_INI_MAX_NAME, 138 "0x%x", fwrt->dump.umac_err_id); 139 } 140 141 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { 142 IWL_ERR(trans, "Start IWL Error Log Dump:\n"); 143 IWL_ERR(trans, "Transport status: 0x%08lX, valid: %d\n", 144 fwrt->trans->status, table.valid); 145 } 146 147 if ((table.error_id & ~FW_SYSASSERT_CPU_MASK) == 148 FW_SYSASSERT_PNVM_MISSING) { 149 iwl_pnvm_get_fs_name(trans, pnvm_name, sizeof(pnvm_name)); 150 IWL_ERR(fwrt, "PNVM data is missing, please install %s\n", 151 pnvm_name); 152 } 153 154 IWL_ERR(fwrt, "0x%08X | %s\n", table.error_id, 155 iwl_fw_lookup_assert_desc(table.error_id)); 156 IWL_ERR(fwrt, "0x%08X | umac branchlink1\n", table.blink1); 157 IWL_ERR(fwrt, "0x%08X | umac branchlink2\n", table.blink2); 158 IWL_ERR(fwrt, "0x%08X | umac interruptlink1\n", table.ilink1); 159 IWL_ERR(fwrt, "0x%08X | umac interruptlink2\n", table.ilink2); 160 IWL_ERR(fwrt, "0x%08X | umac data1\n", table.data1); 161 IWL_ERR(fwrt, "0x%08X | umac data2\n", table.data2); 162 IWL_ERR(fwrt, "0x%08X | umac data3\n", table.data3); 163 IWL_ERR(fwrt, "0x%08X | umac major\n", table.umac_major); 164 IWL_ERR(fwrt, "0x%08X | umac minor\n", table.umac_minor); 165 IWL_ERR(fwrt, "0x%08X | frame pointer\n", table.frame_pointer); 166 IWL_ERR(fwrt, "0x%08X | stack pointer\n", table.stack_pointer); 167 IWL_ERR(fwrt, "0x%08X | last host cmd\n", table.cmd_header); 168 IWL_ERR(fwrt, "0x%08X | isr status reg\n", table.nic_isr_pref); 169 } 170 171 static void iwl_fwrt_dump_lmac_error_log(struct iwl_fw_runtime *fwrt, u8 lmac_num) 172 { 173 struct iwl_trans *trans = fwrt->trans; 174 struct iwl_error_event_table table = {}; 175 u32 val, base = fwrt->trans->dbg.lmac_error_event_table[lmac_num]; 176 177 if (fwrt->cur_fw_img == IWL_UCODE_INIT) { 178 if (!base) 179 base = fwrt->fw->init_errlog_ptr; 180 } else { 181 if (!base) 182 base = fwrt->fw->inst_errlog_ptr; 183 } 184 185 if (!base) { 186 IWL_ERR(fwrt, 187 "Not valid error log pointer 0x%08X for %s uCode\n", 188 base, 189 (fwrt->cur_fw_img == IWL_UCODE_INIT) 190 ? "Init" : "RT"); 191 return; 192 } 193 194 /* check if there is a HW error */ 195 val = iwl_trans_read_mem32(trans, base); 196 if (iwl_trans_is_hw_error_value(val)) { 197 int err; 198 199 IWL_ERR(trans, "HW error, resetting before reading\n"); 200 201 /* reset the device */ 202 err = iwl_trans_sw_reset(trans, true); 203 if (err) 204 return; 205 206 err = iwl_finish_nic_init(trans); 207 if (err) 208 return; 209 } 210 211 iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table)); 212 213 if (table.valid) 214 fwrt->dump.lmac_err_id[lmac_num] = table.error_id; 215 216 if (!iwl_fwrt_if_errorid_other_cpu(fwrt->dump.lmac_err_id[lmac_num]) && 217 !fwrt->trans->dbg.dump_file_name_ext_valid) { 218 fwrt->trans->dbg.dump_file_name_ext_valid = true; 219 snprintf(fwrt->trans->dbg.dump_file_name_ext, IWL_FW_INI_MAX_NAME, 220 "0x%x", fwrt->dump.lmac_err_id[lmac_num]); 221 } 222 223 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { 224 IWL_ERR(trans, "Start IWL Error Log Dump:\n"); 225 IWL_ERR(trans, "Transport status: 0x%08lX, valid: %d\n", 226 fwrt->trans->status, table.valid); 227 } 228 229 /* Do not change this output - scripts rely on it */ 230 231 IWL_ERR(fwrt, "Loaded firmware version: %s\n", fwrt->fw->fw_version); 232 233 IWL_ERR(fwrt, "0x%08X | %-28s\n", table.error_id, 234 iwl_fw_lookup_assert_desc(table.error_id)); 235 IWL_ERR(fwrt, "0x%08X | trm_hw_status0\n", table.trm_hw_status0); 236 IWL_ERR(fwrt, "0x%08X | trm_hw_status1\n", table.trm_hw_status1); 237 IWL_ERR(fwrt, "0x%08X | branchlink2\n", table.blink2); 238 IWL_ERR(fwrt, "0x%08X | interruptlink1\n", table.ilink1); 239 IWL_ERR(fwrt, "0x%08X | interruptlink2\n", table.ilink2); 240 IWL_ERR(fwrt, "0x%08X | data1\n", table.data1); 241 IWL_ERR(fwrt, "0x%08X | data2\n", table.data2); 242 IWL_ERR(fwrt, "0x%08X | data3\n", table.data3); 243 IWL_ERR(fwrt, "0x%08X | beacon time\n", table.bcon_time); 244 IWL_ERR(fwrt, "0x%08X | tsf low\n", table.tsf_low); 245 IWL_ERR(fwrt, "0x%08X | tsf hi\n", table.tsf_hi); 246 IWL_ERR(fwrt, "0x%08X | time gp1\n", table.gp1); 247 IWL_ERR(fwrt, "0x%08X | time gp2\n", table.gp2); 248 IWL_ERR(fwrt, "0x%08X | uCode revision type\n", table.fw_rev_type); 249 IWL_ERR(fwrt, "0x%08X | uCode version major\n", table.major); 250 IWL_ERR(fwrt, "0x%08X | uCode version minor\n", table.minor); 251 IWL_ERR(fwrt, "0x%08X | hw version\n", table.hw_ver); 252 IWL_ERR(fwrt, "0x%08X | board version\n", table.brd_ver); 253 IWL_ERR(fwrt, "0x%08X | hcmd\n", table.hcmd); 254 IWL_ERR(fwrt, "0x%08X | isr0\n", table.isr0); 255 IWL_ERR(fwrt, "0x%08X | isr1\n", table.isr1); 256 IWL_ERR(fwrt, "0x%08X | isr2\n", table.isr2); 257 IWL_ERR(fwrt, "0x%08X | isr3\n", table.isr3); 258 IWL_ERR(fwrt, "0x%08X | isr4\n", table.isr4); 259 IWL_ERR(fwrt, "0x%08X | last cmd Id\n", table.last_cmd_id); 260 IWL_ERR(fwrt, "0x%08X | wait_event\n", table.wait_event); 261 IWL_ERR(fwrt, "0x%08X | l2p_control\n", table.l2p_control); 262 IWL_ERR(fwrt, "0x%08X | l2p_duration\n", table.l2p_duration); 263 IWL_ERR(fwrt, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid); 264 IWL_ERR(fwrt, "0x%08X | l2p_addr_match\n", table.l2p_addr_match); 265 IWL_ERR(fwrt, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel); 266 IWL_ERR(fwrt, "0x%08X | timestamp\n", table.u_timestamp); 267 IWL_ERR(fwrt, "0x%08X | flow_handler\n", table.flow_handler); 268 } 269 270 /* 271 * TCM error struct. 272 * Note: This structure is read from the device with IO accesses, 273 * and the reading already does the endian conversion. As it is 274 * read with u32-sized accesses, any members with a different size 275 * need to be ordered correctly though! 276 */ 277 struct iwl_tcm_error_event_table { 278 u32 valid; 279 u32 error_id; 280 u32 blink2; 281 u32 ilink1; 282 u32 ilink2; 283 u32 data1, data2, data3; 284 u32 logpc; 285 u32 frame_pointer; 286 u32 stack_pointer; 287 u32 msgid; 288 u32 isr; 289 u32 hw_status[5]; 290 u32 sw_status[1]; 291 u32 reserved[4]; 292 } __packed; /* TCM_LOG_ERROR_TABLE_API_S_VER_1 */ 293 294 static void iwl_fwrt_dump_tcm_error_log(struct iwl_fw_runtime *fwrt, int idx) 295 { 296 struct iwl_trans *trans = fwrt->trans; 297 struct iwl_tcm_error_event_table table = {}; 298 u32 base = fwrt->trans->dbg.tcm_error_event_table[idx]; 299 int i; 300 u32 flag = idx ? IWL_ERROR_EVENT_TABLE_TCM2 : 301 IWL_ERROR_EVENT_TABLE_TCM1; 302 303 if (!base || !(fwrt->trans->dbg.error_event_table_tlv_status & flag)) 304 return; 305 306 iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table)); 307 308 if (table.valid) 309 fwrt->dump.tcm_err_id[idx] = table.error_id; 310 311 if (!iwl_fwrt_if_errorid_other_cpu(fwrt->dump.tcm_err_id[idx]) && 312 !fwrt->trans->dbg.dump_file_name_ext_valid) { 313 fwrt->trans->dbg.dump_file_name_ext_valid = true; 314 snprintf(fwrt->trans->dbg.dump_file_name_ext, IWL_FW_INI_MAX_NAME, 315 "0x%x", fwrt->dump.tcm_err_id[idx]); 316 } 317 318 IWL_ERR(fwrt, "TCM%d status:\n", idx + 1); 319 IWL_ERR(fwrt, "0x%08X | error ID\n", table.error_id); 320 IWL_ERR(fwrt, "0x%08X | tcm branchlink2\n", table.blink2); 321 IWL_ERR(fwrt, "0x%08X | tcm interruptlink1\n", table.ilink1); 322 IWL_ERR(fwrt, "0x%08X | tcm interruptlink2\n", table.ilink2); 323 IWL_ERR(fwrt, "0x%08X | tcm data1\n", table.data1); 324 IWL_ERR(fwrt, "0x%08X | tcm data2\n", table.data2); 325 IWL_ERR(fwrt, "0x%08X | tcm data3\n", table.data3); 326 IWL_ERR(fwrt, "0x%08X | tcm log PC\n", table.logpc); 327 IWL_ERR(fwrt, "0x%08X | tcm frame pointer\n", table.frame_pointer); 328 IWL_ERR(fwrt, "0x%08X | tcm stack pointer\n", table.stack_pointer); 329 IWL_ERR(fwrt, "0x%08X | tcm msg ID\n", table.msgid); 330 IWL_ERR(fwrt, "0x%08X | tcm ISR status\n", table.isr); 331 for (i = 0; i < ARRAY_SIZE(table.hw_status); i++) 332 IWL_ERR(fwrt, "0x%08X | tcm HW status[%d]\n", 333 table.hw_status[i], i); 334 for (i = 0; i < ARRAY_SIZE(table.sw_status); i++) 335 IWL_ERR(fwrt, "0x%08X | tcm SW status[%d]\n", 336 table.sw_status[i], i); 337 } 338 339 /* 340 * RCM error struct. 341 * Note: This structure is read from the device with IO accesses, 342 * and the reading already does the endian conversion. As it is 343 * read with u32-sized accesses, any members with a different size 344 * need to be ordered correctly though! 345 */ 346 struct iwl_rcm_error_event_table { 347 u32 valid; 348 u32 error_id; 349 u32 blink2; 350 u32 ilink1; 351 u32 ilink2; 352 u32 data1, data2, data3; 353 u32 logpc; 354 u32 frame_pointer; 355 u32 stack_pointer; 356 u32 msgid; 357 u32 isr; 358 u32 frame_hw_status; 359 u32 mbx_lmac_to_rcm_req; 360 u32 mbx_rcm_to_lmac_req; 361 u32 mh_ctl; 362 u32 mh_addr1_lo; 363 u32 mh_info; 364 u32 mh_err; 365 u32 reserved[3]; 366 } __packed; /* RCM_LOG_ERROR_TABLE_API_S_VER_1 */ 367 368 static void iwl_fwrt_dump_rcm_error_log(struct iwl_fw_runtime *fwrt, int idx) 369 { 370 struct iwl_trans *trans = fwrt->trans; 371 struct iwl_rcm_error_event_table table = {}; 372 u32 base = fwrt->trans->dbg.rcm_error_event_table[idx]; 373 u32 flag = idx ? IWL_ERROR_EVENT_TABLE_RCM2 : 374 IWL_ERROR_EVENT_TABLE_RCM1; 375 376 if (!base || !(fwrt->trans->dbg.error_event_table_tlv_status & flag)) 377 return; 378 379 iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table)); 380 381 if (table.valid) 382 fwrt->dump.rcm_err_id[idx] = table.error_id; 383 384 if (!iwl_fwrt_if_errorid_other_cpu(fwrt->dump.rcm_err_id[idx]) && 385 !fwrt->trans->dbg.dump_file_name_ext_valid) { 386 fwrt->trans->dbg.dump_file_name_ext_valid = true; 387 snprintf(fwrt->trans->dbg.dump_file_name_ext, IWL_FW_INI_MAX_NAME, 388 "0x%x", fwrt->dump.rcm_err_id[idx]); 389 } 390 391 IWL_ERR(fwrt, "RCM%d status:\n", idx + 1); 392 IWL_ERR(fwrt, "0x%08X | error ID\n", table.error_id); 393 IWL_ERR(fwrt, "0x%08X | rcm branchlink2\n", table.blink2); 394 IWL_ERR(fwrt, "0x%08X | rcm interruptlink1\n", table.ilink1); 395 IWL_ERR(fwrt, "0x%08X | rcm interruptlink2\n", table.ilink2); 396 IWL_ERR(fwrt, "0x%08X | rcm data1\n", table.data1); 397 IWL_ERR(fwrt, "0x%08X | rcm data2\n", table.data2); 398 IWL_ERR(fwrt, "0x%08X | rcm data3\n", table.data3); 399 IWL_ERR(fwrt, "0x%08X | rcm log PC\n", table.logpc); 400 IWL_ERR(fwrt, "0x%08X | rcm frame pointer\n", table.frame_pointer); 401 IWL_ERR(fwrt, "0x%08X | rcm stack pointer\n", table.stack_pointer); 402 IWL_ERR(fwrt, "0x%08X | rcm msg ID\n", table.msgid); 403 IWL_ERR(fwrt, "0x%08X | rcm ISR status\n", table.isr); 404 IWL_ERR(fwrt, "0x%08X | frame HW status\n", table.frame_hw_status); 405 IWL_ERR(fwrt, "0x%08X | LMAC-to-RCM request mbox\n", 406 table.mbx_lmac_to_rcm_req); 407 IWL_ERR(fwrt, "0x%08X | RCM-to-LMAC request mbox\n", 408 table.mbx_rcm_to_lmac_req); 409 IWL_ERR(fwrt, "0x%08X | MAC header control\n", table.mh_ctl); 410 IWL_ERR(fwrt, "0x%08X | MAC header addr1 low\n", table.mh_addr1_lo); 411 IWL_ERR(fwrt, "0x%08X | MAC header info\n", table.mh_info); 412 IWL_ERR(fwrt, "0x%08X | MAC header error\n", table.mh_err); 413 } 414 415 static void iwl_fwrt_dump_iml_error_log(struct iwl_fw_runtime *fwrt) 416 { 417 struct iwl_trans *trans = fwrt->trans; 418 u32 error, data1; 419 420 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) { 421 error = UMAG_SB_CPU_2_STATUS; 422 data1 = UMAG_SB_CPU_1_STATUS; 423 } else if (fwrt->trans->trans_cfg->device_family >= 424 IWL_DEVICE_FAMILY_8000) { 425 error = SB_CPU_2_STATUS; 426 data1 = SB_CPU_1_STATUS; 427 } else { 428 return; 429 } 430 431 error = iwl_read_umac_prph(trans, error); 432 433 IWL_ERR(trans, "IML/ROM dump:\n"); 434 435 if (error & 0xFFFF0000) 436 IWL_ERR(trans, "0x%04X | IML/ROM SYSASSERT\n", error >> 16); 437 438 IWL_ERR(fwrt, "0x%08X | IML/ROM error/state\n", error); 439 IWL_ERR(fwrt, "0x%08X | IML/ROM data1\n", 440 iwl_read_umac_prph(trans, data1)); 441 442 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) 443 IWL_ERR(fwrt, "0x%08X | IML/ROM WFPM_AUTH_KEY_0\n", 444 iwl_read_umac_prph(trans, SB_MODIFY_CFG_FLAG)); 445 } 446 447 #define FSEQ_REG(x) { .addr = (x), .str = #x, } 448 449 static void iwl_fwrt_dump_fseq_regs(struct iwl_fw_runtime *fwrt) 450 { 451 struct iwl_trans *trans = fwrt->trans; 452 int i; 453 struct { 454 u32 addr; 455 const char *str; 456 } fseq_regs[] = { 457 FSEQ_REG(FSEQ_ERROR_CODE), 458 FSEQ_REG(FSEQ_TOP_INIT_VERSION), 459 FSEQ_REG(FSEQ_CNVIO_INIT_VERSION), 460 FSEQ_REG(FSEQ_OTP_VERSION), 461 FSEQ_REG(FSEQ_TOP_CONTENT_VERSION), 462 FSEQ_REG(FSEQ_ALIVE_TOKEN), 463 FSEQ_REG(FSEQ_CNVI_ID), 464 FSEQ_REG(FSEQ_CNVR_ID), 465 FSEQ_REG(CNVI_AUX_MISC_CHIP), 466 FSEQ_REG(CNVR_AUX_MISC_CHIP), 467 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM), 468 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR), 469 FSEQ_REG(FSEQ_PREV_CNVIO_INIT_VERSION), 470 FSEQ_REG(FSEQ_WIFI_FSEQ_VERSION), 471 FSEQ_REG(FSEQ_BT_FSEQ_VERSION), 472 FSEQ_REG(FSEQ_CLASS_TP_VERSION), 473 }; 474 475 if (!iwl_trans_grab_nic_access(trans)) 476 return; 477 478 IWL_ERR(fwrt, "Fseq Registers:\n"); 479 480 for (i = 0; i < ARRAY_SIZE(fseq_regs); i++) 481 IWL_ERR(fwrt, "0x%08X | %s\n", 482 iwl_read_prph_no_grab(trans, fseq_regs[i].addr), 483 fseq_regs[i].str); 484 485 iwl_trans_release_nic_access(trans); 486 } 487 488 void iwl_fwrt_dump_error_logs(struct iwl_fw_runtime *fwrt) 489 { 490 struct iwl_pc_data *pc_data; 491 u8 count; 492 493 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) { 494 IWL_ERR(fwrt, 495 "DEVICE_ENABLED bit is not set. Aborting dump.\n"); 496 return; 497 } 498 499 iwl_fwrt_dump_lmac_error_log(fwrt, 0); 500 if (fwrt->trans->dbg.lmac_error_event_table[1]) 501 iwl_fwrt_dump_lmac_error_log(fwrt, 1); 502 iwl_fwrt_dump_umac_error_log(fwrt); 503 iwl_fwrt_dump_tcm_error_log(fwrt, 0); 504 iwl_fwrt_dump_rcm_error_log(fwrt, 0); 505 if (fwrt->trans->dbg.tcm_error_event_table[1]) 506 iwl_fwrt_dump_tcm_error_log(fwrt, 1); 507 if (fwrt->trans->dbg.rcm_error_event_table[1]) 508 iwl_fwrt_dump_rcm_error_log(fwrt, 1); 509 iwl_fwrt_dump_iml_error_log(fwrt); 510 iwl_fwrt_dump_fseq_regs(fwrt); 511 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) { 512 pc_data = fwrt->trans->dbg.pc_data; 513 514 if (!iwl_trans_grab_nic_access(fwrt->trans)) 515 return; 516 for (count = 0; count < fwrt->trans->dbg.num_pc; 517 count++, pc_data++) 518 IWL_ERR(fwrt, "%s: 0x%x\n", 519 pc_data->pc_name, 520 iwl_read_prph_no_grab(fwrt->trans, 521 pc_data->pc_address)); 522 iwl_trans_release_nic_access(fwrt->trans); 523 } 524 525 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 526 u32 scratch = iwl_read32(fwrt->trans, CSR_FUNC_SCRATCH); 527 528 IWL_ERR(fwrt, "Function Scratch status:\n"); 529 IWL_ERR(fwrt, "0x%08X | Func Scratch\n", scratch); 530 } 531 } 532 IWL_EXPORT_SYMBOL(iwl_fwrt_dump_error_logs); 533