1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/devcoredump.h> 8 #include "iwl-drv.h" 9 #include "runtime.h" 10 #include "dbg.h" 11 #include "debugfs.h" 12 #include "iwl-io.h" 13 #include "iwl-prph.h" 14 #include "iwl-csr.h" 15 16 /** 17 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 18 * 19 * @fwrt_ptr: pointer to the buffer coming from fwrt 20 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 21 * transport's data. 22 * @trans_len: length of the valid data in trans_ptr 23 * @fwrt_len: length of the valid data in fwrt_ptr 24 */ 25 struct iwl_fw_dump_ptrs { 26 struct iwl_trans_dump_data *trans_ptr; 27 void *fwrt_ptr; 28 u32 fwrt_len; 29 }; 30 31 #define RADIO_REG_MAX_READ 0x2ad 32 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 33 struct iwl_fw_error_dump_data **dump_data) 34 { 35 u8 *pos = (void *)(*dump_data)->data; 36 int i; 37 38 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 39 40 if (!iwl_trans_grab_nic_access(fwrt->trans)) 41 return; 42 43 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 44 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 45 46 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 47 u32 rd_cmd = RADIO_RSP_RD_CMD; 48 49 rd_cmd |= i << RADIO_RSP_ADDR_POS; 50 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 51 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 52 53 pos++; 54 } 55 56 *dump_data = iwl_fw_error_next_data(*dump_data); 57 58 iwl_trans_release_nic_access(fwrt->trans); 59 } 60 61 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 62 struct iwl_fw_error_dump_data **dump_data, 63 int size, u32 offset, int fifo_num) 64 { 65 struct iwl_fw_error_dump_fifo *fifo_hdr; 66 u32 *fifo_data; 67 u32 fifo_len; 68 int i; 69 70 fifo_hdr = (void *)(*dump_data)->data; 71 fifo_data = (void *)fifo_hdr->data; 72 fifo_len = size; 73 74 /* No need to try to read the data if the length is 0 */ 75 if (fifo_len == 0) 76 return; 77 78 /* Add a TLV for the RXF */ 79 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 80 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 81 82 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 83 fifo_hdr->available_bytes = 84 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 85 RXF_RD_D_SPACE + offset)); 86 fifo_hdr->wr_ptr = 87 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 88 RXF_RD_WR_PTR + offset)); 89 fifo_hdr->rd_ptr = 90 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 91 RXF_RD_RD_PTR + offset)); 92 fifo_hdr->fence_ptr = 93 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 94 RXF_RD_FENCE_PTR + offset)); 95 fifo_hdr->fence_mode = 96 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 97 RXF_SET_FENCE_MODE + offset)); 98 99 /* Lock fence */ 100 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 101 /* Set fence pointer to the same place like WR pointer */ 102 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 103 /* Set fence offset */ 104 iwl_trans_write_prph(fwrt->trans, 105 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 106 107 /* Read FIFO */ 108 fifo_len /= sizeof(u32); /* Size in DWORDS */ 109 for (i = 0; i < fifo_len; i++) 110 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 111 RXF_FIFO_RD_FENCE_INC + 112 offset); 113 *dump_data = iwl_fw_error_next_data(*dump_data); 114 } 115 116 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 117 struct iwl_fw_error_dump_data **dump_data, 118 int size, u32 offset, int fifo_num) 119 { 120 struct iwl_fw_error_dump_fifo *fifo_hdr; 121 u32 *fifo_data; 122 u32 fifo_len; 123 int i; 124 125 fifo_hdr = (void *)(*dump_data)->data; 126 fifo_data = (void *)fifo_hdr->data; 127 fifo_len = size; 128 129 /* No need to try to read the data if the length is 0 */ 130 if (fifo_len == 0) 131 return; 132 133 /* Add a TLV for the FIFO */ 134 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 135 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 136 137 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 138 fifo_hdr->available_bytes = 139 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 140 TXF_FIFO_ITEM_CNT + offset)); 141 fifo_hdr->wr_ptr = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 TXF_WR_PTR + offset)); 144 fifo_hdr->rd_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 TXF_RD_PTR + offset)); 147 fifo_hdr->fence_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 TXF_FENCE_PTR + offset)); 150 fifo_hdr->fence_mode = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 TXF_LOCK_FENCE + offset)); 153 154 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 155 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 156 TXF_WR_PTR + offset); 157 158 /* Dummy-read to advance the read pointer to the head */ 159 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 160 161 /* Read FIFO */ 162 for (i = 0; i < fifo_len / sizeof(u32); i++) 163 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 164 TXF_READ_MODIFY_DATA + 165 offset); 166 167 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 168 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 169 fifo_data, fifo_len); 170 171 *dump_data = iwl_fw_error_next_data(*dump_data); 172 } 173 174 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 175 struct iwl_fw_error_dump_data **dump_data) 176 { 177 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 178 179 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 180 181 if (!iwl_trans_grab_nic_access(fwrt->trans)) 182 return; 183 184 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 185 /* Pull RXF1 */ 186 iwl_fwrt_dump_rxf(fwrt, dump_data, 187 cfg->lmac[0].rxfifo1_size, 0, 0); 188 /* Pull RXF2 */ 189 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 190 RXF_DIFF_FROM_PREV + 191 fwrt->trans->trans_cfg->umac_prph_offset, 1); 192 /* Pull LMAC2 RXF1 */ 193 if (fwrt->smem_cfg.num_lmacs > 1) 194 iwl_fwrt_dump_rxf(fwrt, dump_data, 195 cfg->lmac[1].rxfifo1_size, 196 LMAC2_PRPH_OFFSET, 2); 197 } 198 199 iwl_trans_release_nic_access(fwrt->trans); 200 } 201 202 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 203 struct iwl_fw_error_dump_data **dump_data) 204 { 205 struct iwl_fw_error_dump_fifo *fifo_hdr; 206 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 207 u32 *fifo_data; 208 u32 fifo_len; 209 int i, j; 210 211 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 212 213 if (!iwl_trans_grab_nic_access(fwrt->trans)) 214 return; 215 216 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 217 /* Pull TXF data from LMAC1 */ 218 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 219 /* Mark the number of TXF we're pulling now */ 220 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 221 iwl_fwrt_dump_txf(fwrt, dump_data, 222 cfg->lmac[0].txfifo_size[i], 0, i); 223 } 224 225 /* Pull TXF data from LMAC2 */ 226 if (fwrt->smem_cfg.num_lmacs > 1) { 227 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 228 i++) { 229 /* Mark the number of TXF we're pulling now */ 230 iwl_trans_write_prph(fwrt->trans, 231 TXF_LARC_NUM + 232 LMAC2_PRPH_OFFSET, i); 233 iwl_fwrt_dump_txf(fwrt, dump_data, 234 cfg->lmac[1].txfifo_size[i], 235 LMAC2_PRPH_OFFSET, 236 i + cfg->num_txfifo_entries); 237 } 238 } 239 } 240 241 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 242 fw_has_capa(&fwrt->fw->ucode_capa, 243 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 244 /* Pull UMAC internal TXF data from all TXFs */ 245 for (i = 0; 246 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 247 i++) { 248 fifo_hdr = (void *)(*dump_data)->data; 249 fifo_data = (void *)fifo_hdr->data; 250 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 251 252 /* No need to try to read the data if the length is 0 */ 253 if (fifo_len == 0) 254 continue; 255 256 /* Add a TLV for the internal FIFOs */ 257 (*dump_data)->type = 258 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 259 (*dump_data)->len = 260 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 261 262 fifo_hdr->fifo_num = cpu_to_le32(i); 263 264 /* Mark the number of TXF we're pulling now */ 265 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 266 fwrt->smem_cfg.num_txfifo_entries); 267 268 fifo_hdr->available_bytes = 269 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 270 TXF_CPU2_FIFO_ITEM_CNT)); 271 fifo_hdr->wr_ptr = 272 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 273 TXF_CPU2_WR_PTR)); 274 fifo_hdr->rd_ptr = 275 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 276 TXF_CPU2_RD_PTR)); 277 fifo_hdr->fence_ptr = 278 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 279 TXF_CPU2_FENCE_PTR)); 280 fifo_hdr->fence_mode = 281 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 282 TXF_CPU2_LOCK_FENCE)); 283 284 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 285 iwl_trans_write_prph(fwrt->trans, 286 TXF_CPU2_READ_MODIFY_ADDR, 287 TXF_CPU2_WR_PTR); 288 289 /* Dummy-read to advance the read pointer to head */ 290 iwl_trans_read_prph(fwrt->trans, 291 TXF_CPU2_READ_MODIFY_DATA); 292 293 /* Read FIFO */ 294 fifo_len /= sizeof(u32); /* Size in DWORDS */ 295 for (j = 0; j < fifo_len; j++) 296 fifo_data[j] = 297 iwl_trans_read_prph(fwrt->trans, 298 TXF_CPU2_READ_MODIFY_DATA); 299 *dump_data = iwl_fw_error_next_data(*dump_data); 300 } 301 } 302 303 iwl_trans_release_nic_access(fwrt->trans); 304 } 305 306 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ 307 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ 308 309 struct iwl_prph_range { 310 u32 start, end; 311 }; 312 313 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 314 { .start = 0x00a00000, .end = 0x00a00000 }, 315 { .start = 0x00a0000c, .end = 0x00a00024 }, 316 { .start = 0x00a0002c, .end = 0x00a0003c }, 317 { .start = 0x00a00410, .end = 0x00a00418 }, 318 { .start = 0x00a00420, .end = 0x00a00420 }, 319 { .start = 0x00a00428, .end = 0x00a00428 }, 320 { .start = 0x00a00430, .end = 0x00a0043c }, 321 { .start = 0x00a00444, .end = 0x00a00444 }, 322 { .start = 0x00a004c0, .end = 0x00a004cc }, 323 { .start = 0x00a004d8, .end = 0x00a004d8 }, 324 { .start = 0x00a004e0, .end = 0x00a004f0 }, 325 { .start = 0x00a00840, .end = 0x00a00840 }, 326 { .start = 0x00a00850, .end = 0x00a00858 }, 327 { .start = 0x00a01004, .end = 0x00a01008 }, 328 { .start = 0x00a01010, .end = 0x00a01010 }, 329 { .start = 0x00a01018, .end = 0x00a01018 }, 330 { .start = 0x00a01024, .end = 0x00a01024 }, 331 { .start = 0x00a0102c, .end = 0x00a01034 }, 332 { .start = 0x00a0103c, .end = 0x00a01040 }, 333 { .start = 0x00a01048, .end = 0x00a01094 }, 334 { .start = 0x00a01c00, .end = 0x00a01c20 }, 335 { .start = 0x00a01c58, .end = 0x00a01c58 }, 336 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 337 { .start = 0x00a01c28, .end = 0x00a01c54 }, 338 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 339 { .start = 0x00a01c60, .end = 0x00a01cdc }, 340 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 341 { .start = 0x00a01d18, .end = 0x00a01d20 }, 342 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 343 { .start = 0x00a01d40, .end = 0x00a01d5c }, 344 { .start = 0x00a01d80, .end = 0x00a01d80 }, 345 { .start = 0x00a01d98, .end = 0x00a01d9c }, 346 { .start = 0x00a01da8, .end = 0x00a01da8 }, 347 { .start = 0x00a01db8, .end = 0x00a01df4 }, 348 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 349 { .start = 0x00a01e00, .end = 0x00a01e2c }, 350 { .start = 0x00a01e40, .end = 0x00a01e60 }, 351 { .start = 0x00a01e68, .end = 0x00a01e6c }, 352 { .start = 0x00a01e74, .end = 0x00a01e74 }, 353 { .start = 0x00a01e84, .end = 0x00a01e90 }, 354 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 355 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 356 { .start = 0x00a01f00, .end = 0x00a01f1c }, 357 { .start = 0x00a01f44, .end = 0x00a01ffc }, 358 { .start = 0x00a02000, .end = 0x00a02048 }, 359 { .start = 0x00a02068, .end = 0x00a020f0 }, 360 { .start = 0x00a02100, .end = 0x00a02118 }, 361 { .start = 0x00a02140, .end = 0x00a0214c }, 362 { .start = 0x00a02168, .end = 0x00a0218c }, 363 { .start = 0x00a021c0, .end = 0x00a021c0 }, 364 { .start = 0x00a02400, .end = 0x00a02410 }, 365 { .start = 0x00a02418, .end = 0x00a02420 }, 366 { .start = 0x00a02428, .end = 0x00a0242c }, 367 { .start = 0x00a02434, .end = 0x00a02434 }, 368 { .start = 0x00a02440, .end = 0x00a02460 }, 369 { .start = 0x00a02468, .end = 0x00a024b0 }, 370 { .start = 0x00a024c8, .end = 0x00a024cc }, 371 { .start = 0x00a02500, .end = 0x00a02504 }, 372 { .start = 0x00a0250c, .end = 0x00a02510 }, 373 { .start = 0x00a02540, .end = 0x00a02554 }, 374 { .start = 0x00a02580, .end = 0x00a025f4 }, 375 { .start = 0x00a02600, .end = 0x00a0260c }, 376 { .start = 0x00a02648, .end = 0x00a02650 }, 377 { .start = 0x00a02680, .end = 0x00a02680 }, 378 { .start = 0x00a026c0, .end = 0x00a026d0 }, 379 { .start = 0x00a02700, .end = 0x00a0270c }, 380 { .start = 0x00a02804, .end = 0x00a02804 }, 381 { .start = 0x00a02818, .end = 0x00a0281c }, 382 { .start = 0x00a02c00, .end = 0x00a02db4 }, 383 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 384 { .start = 0x00a03000, .end = 0x00a03014 }, 385 { .start = 0x00a0301c, .end = 0x00a0302c }, 386 { .start = 0x00a03034, .end = 0x00a03038 }, 387 { .start = 0x00a03040, .end = 0x00a03048 }, 388 { .start = 0x00a03060, .end = 0x00a03068 }, 389 { .start = 0x00a03070, .end = 0x00a03074 }, 390 { .start = 0x00a0307c, .end = 0x00a0307c }, 391 { .start = 0x00a03080, .end = 0x00a03084 }, 392 { .start = 0x00a0308c, .end = 0x00a03090 }, 393 { .start = 0x00a03098, .end = 0x00a03098 }, 394 { .start = 0x00a030a0, .end = 0x00a030a0 }, 395 { .start = 0x00a030a8, .end = 0x00a030b4 }, 396 { .start = 0x00a030bc, .end = 0x00a030bc }, 397 { .start = 0x00a030c0, .end = 0x00a0312c }, 398 { .start = 0x00a03c00, .end = 0x00a03c5c }, 399 { .start = 0x00a04400, .end = 0x00a04454 }, 400 { .start = 0x00a04460, .end = 0x00a04474 }, 401 { .start = 0x00a044c0, .end = 0x00a044ec }, 402 { .start = 0x00a04500, .end = 0x00a04504 }, 403 { .start = 0x00a04510, .end = 0x00a04538 }, 404 { .start = 0x00a04540, .end = 0x00a04548 }, 405 { .start = 0x00a04560, .end = 0x00a0457c }, 406 { .start = 0x00a04590, .end = 0x00a04598 }, 407 { .start = 0x00a045c0, .end = 0x00a045f4 }, 408 }; 409 410 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 411 { .start = 0x00a05c00, .end = 0x00a05c18 }, 412 { .start = 0x00a05400, .end = 0x00a056e8 }, 413 { .start = 0x00a08000, .end = 0x00a098bc }, 414 { .start = 0x00a02400, .end = 0x00a02758 }, 415 { .start = 0x00a04764, .end = 0x00a0476c }, 416 { .start = 0x00a04770, .end = 0x00a04774 }, 417 { .start = 0x00a04620, .end = 0x00a04624 }, 418 }; 419 420 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 421 { .start = 0x00a00000, .end = 0x00a00000 }, 422 { .start = 0x00a0000c, .end = 0x00a00024 }, 423 { .start = 0x00a0002c, .end = 0x00a00034 }, 424 { .start = 0x00a0003c, .end = 0x00a0003c }, 425 { .start = 0x00a00410, .end = 0x00a00418 }, 426 { .start = 0x00a00420, .end = 0x00a00420 }, 427 { .start = 0x00a00428, .end = 0x00a00428 }, 428 { .start = 0x00a00430, .end = 0x00a0043c }, 429 { .start = 0x00a00444, .end = 0x00a00444 }, 430 { .start = 0x00a00840, .end = 0x00a00840 }, 431 { .start = 0x00a00850, .end = 0x00a00858 }, 432 { .start = 0x00a01004, .end = 0x00a01008 }, 433 { .start = 0x00a01010, .end = 0x00a01010 }, 434 { .start = 0x00a01018, .end = 0x00a01018 }, 435 { .start = 0x00a01024, .end = 0x00a01024 }, 436 { .start = 0x00a0102c, .end = 0x00a01034 }, 437 { .start = 0x00a0103c, .end = 0x00a01040 }, 438 { .start = 0x00a01048, .end = 0x00a01050 }, 439 { .start = 0x00a01058, .end = 0x00a01058 }, 440 { .start = 0x00a01060, .end = 0x00a01070 }, 441 { .start = 0x00a0108c, .end = 0x00a0108c }, 442 { .start = 0x00a01c20, .end = 0x00a01c28 }, 443 { .start = 0x00a01d10, .end = 0x00a01d10 }, 444 { .start = 0x00a01e28, .end = 0x00a01e2c }, 445 { .start = 0x00a01e60, .end = 0x00a01e60 }, 446 { .start = 0x00a01e80, .end = 0x00a01e80 }, 447 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 448 { .start = 0x00a02000, .end = 0x00a0201c }, 449 { .start = 0x00a02024, .end = 0x00a02024 }, 450 { .start = 0x00a02040, .end = 0x00a02048 }, 451 { .start = 0x00a020c0, .end = 0x00a020e0 }, 452 { .start = 0x00a02400, .end = 0x00a02404 }, 453 { .start = 0x00a0240c, .end = 0x00a02414 }, 454 { .start = 0x00a0241c, .end = 0x00a0243c }, 455 { .start = 0x00a02448, .end = 0x00a024bc }, 456 { .start = 0x00a024c4, .end = 0x00a024cc }, 457 { .start = 0x00a02508, .end = 0x00a02508 }, 458 { .start = 0x00a02510, .end = 0x00a02514 }, 459 { .start = 0x00a0251c, .end = 0x00a0251c }, 460 { .start = 0x00a0252c, .end = 0x00a0255c }, 461 { .start = 0x00a02564, .end = 0x00a025a0 }, 462 { .start = 0x00a025a8, .end = 0x00a025b4 }, 463 { .start = 0x00a025c0, .end = 0x00a025c0 }, 464 { .start = 0x00a025e8, .end = 0x00a025f4 }, 465 { .start = 0x00a02c08, .end = 0x00a02c18 }, 466 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 467 { .start = 0x00a02c68, .end = 0x00a02c78 }, 468 { .start = 0x00a03000, .end = 0x00a03000 }, 469 { .start = 0x00a03010, .end = 0x00a03014 }, 470 { .start = 0x00a0301c, .end = 0x00a0302c }, 471 { .start = 0x00a03034, .end = 0x00a03038 }, 472 { .start = 0x00a03040, .end = 0x00a03044 }, 473 { .start = 0x00a03060, .end = 0x00a03068 }, 474 { .start = 0x00a03070, .end = 0x00a03070 }, 475 { .start = 0x00a0307c, .end = 0x00a03084 }, 476 { .start = 0x00a0308c, .end = 0x00a03090 }, 477 { .start = 0x00a03098, .end = 0x00a03098 }, 478 { .start = 0x00a030a0, .end = 0x00a030a0 }, 479 { .start = 0x00a030a8, .end = 0x00a030b4 }, 480 { .start = 0x00a030bc, .end = 0x00a030c0 }, 481 { .start = 0x00a030c8, .end = 0x00a030f4 }, 482 { .start = 0x00a03100, .end = 0x00a0312c }, 483 { .start = 0x00a03c00, .end = 0x00a03c5c }, 484 { .start = 0x00a04400, .end = 0x00a04454 }, 485 { .start = 0x00a04460, .end = 0x00a04474 }, 486 { .start = 0x00a044c0, .end = 0x00a044ec }, 487 { .start = 0x00a04500, .end = 0x00a04504 }, 488 { .start = 0x00a04510, .end = 0x00a04538 }, 489 { .start = 0x00a04540, .end = 0x00a04548 }, 490 { .start = 0x00a04560, .end = 0x00a04560 }, 491 { .start = 0x00a04570, .end = 0x00a0457c }, 492 { .start = 0x00a04590, .end = 0x00a04590 }, 493 { .start = 0x00a04598, .end = 0x00a04598 }, 494 { .start = 0x00a045c0, .end = 0x00a045f4 }, 495 { .start = 0x00a05c18, .end = 0x00a05c1c }, 496 { .start = 0x00a0c000, .end = 0x00a0c018 }, 497 { .start = 0x00a0c020, .end = 0x00a0c028 }, 498 { .start = 0x00a0c038, .end = 0x00a0c094 }, 499 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 500 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 501 { .start = 0x00a0c150, .end = 0x00a0c174 }, 502 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 503 { .start = 0x00a0c190, .end = 0x00a0c198 }, 504 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 505 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 506 }; 507 508 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 509 { .start = 0x00d03c00, .end = 0x00d03c64 }, 510 { .start = 0x00d05c18, .end = 0x00d05c1c }, 511 { .start = 0x00d0c000, .end = 0x00d0c174 }, 512 }; 513 514 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 515 u32 len_bytes, __le32 *data) 516 { 517 u32 i; 518 519 for (i = 0; i < len_bytes; i += 4) 520 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 521 } 522 523 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 524 const struct iwl_prph_range *iwl_prph_dump_addr, 525 u32 range_len, void *ptr) 526 { 527 struct iwl_fw_error_dump_prph *prph; 528 struct iwl_trans *trans = fwrt->trans; 529 struct iwl_fw_error_dump_data **data = 530 (struct iwl_fw_error_dump_data **)ptr; 531 u32 i; 532 533 if (!data) 534 return; 535 536 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 537 538 if (!iwl_trans_grab_nic_access(trans)) 539 return; 540 541 for (i = 0; i < range_len; i++) { 542 /* The range includes both boundaries */ 543 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 544 iwl_prph_dump_addr[i].start + 4; 545 546 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 547 (*data)->len = cpu_to_le32(sizeof(*prph) + 548 num_bytes_in_chunk); 549 prph = (void *)(*data)->data; 550 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 551 552 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 553 /* our range is inclusive, hence + 4 */ 554 iwl_prph_dump_addr[i].end - 555 iwl_prph_dump_addr[i].start + 4, 556 (void *)prph->data); 557 558 *data = iwl_fw_error_next_data(*data); 559 } 560 561 iwl_trans_release_nic_access(trans); 562 } 563 564 /* 565 * alloc_sgtable - allocates scallerlist table in the given size, 566 * fills it with pages and returns it 567 * @size: the size (in bytes) of the table 568 */ 569 static struct scatterlist *alloc_sgtable(int size) 570 { 571 int alloc_size, nents, i; 572 struct page *new_page; 573 struct scatterlist *iter; 574 struct scatterlist *table; 575 576 nents = DIV_ROUND_UP(size, PAGE_SIZE); 577 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 578 if (!table) 579 return NULL; 580 sg_init_table(table, nents); 581 iter = table; 582 for_each_sg(table, iter, sg_nents(table), i) { 583 new_page = alloc_page(GFP_KERNEL); 584 if (!new_page) { 585 /* release all previous allocated pages in the table */ 586 iter = table; 587 for_each_sg(table, iter, sg_nents(table), i) { 588 new_page = sg_page(iter); 589 if (new_page) 590 __free_page(new_page); 591 } 592 kfree(table); 593 return NULL; 594 } 595 alloc_size = min_t(int, size, PAGE_SIZE); 596 size -= PAGE_SIZE; 597 sg_set_page(iter, new_page, alloc_size, 0); 598 } 599 return table; 600 } 601 602 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 603 const struct iwl_prph_range *iwl_prph_dump_addr, 604 u32 range_len, void *ptr) 605 { 606 u32 *prph_len = (u32 *)ptr; 607 int i, num_bytes_in_chunk; 608 609 if (!prph_len) 610 return; 611 612 for (i = 0; i < range_len; i++) { 613 /* The range includes both boundaries */ 614 num_bytes_in_chunk = 615 iwl_prph_dump_addr[i].end - 616 iwl_prph_dump_addr[i].start + 4; 617 618 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 619 sizeof(struct iwl_fw_error_dump_prph) + 620 num_bytes_in_chunk; 621 } 622 } 623 624 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 625 void (*handler)(struct iwl_fw_runtime *, 626 const struct iwl_prph_range *, 627 u32, void *)) 628 { 629 u32 range_len; 630 631 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 632 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 633 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 634 } else if (fwrt->trans->trans_cfg->device_family >= 635 IWL_DEVICE_FAMILY_22000) { 636 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 637 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 638 } else { 639 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 640 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 641 642 if (fwrt->trans->trans_cfg->mq_rx_supported) { 643 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 644 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 645 } 646 } 647 } 648 649 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 650 struct iwl_fw_error_dump_data **dump_data, 651 u32 len, u32 ofs, u32 type) 652 { 653 struct iwl_fw_error_dump_mem *dump_mem; 654 655 if (!len) 656 return; 657 658 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 659 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 660 dump_mem = (void *)(*dump_data)->data; 661 dump_mem->type = cpu_to_le32(type); 662 dump_mem->offset = cpu_to_le32(ofs); 663 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 664 *dump_data = iwl_fw_error_next_data(*dump_data); 665 666 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 667 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs, 668 dump_mem->data, len); 669 670 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 671 } 672 673 #define ADD_LEN(len, item_len, const_len) \ 674 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 675 while (0) 676 677 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 678 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 679 { 680 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 681 sizeof(struct iwl_fw_error_dump_fifo); 682 u32 fifo_len = 0; 683 int i; 684 685 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 686 return 0; 687 688 /* Count RXF2 size */ 689 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 690 691 /* Count RXF1 sizes */ 692 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 693 mem_cfg->num_lmacs = MAX_NUM_LMAC; 694 695 for (i = 0; i < mem_cfg->num_lmacs; i++) 696 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 697 698 return fifo_len; 699 } 700 701 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 702 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 703 { 704 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 705 sizeof(struct iwl_fw_error_dump_fifo); 706 u32 fifo_len = 0; 707 int i; 708 709 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 710 goto dump_internal_txf; 711 712 /* Count TXF sizes */ 713 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 714 mem_cfg->num_lmacs = MAX_NUM_LMAC; 715 716 for (i = 0; i < mem_cfg->num_lmacs; i++) { 717 int j; 718 719 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 720 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 721 hdr_len); 722 } 723 724 dump_internal_txf: 725 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 726 fw_has_capa(&fwrt->fw->ucode_capa, 727 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 728 goto out; 729 730 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 731 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 732 733 out: 734 return fifo_len; 735 } 736 737 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 738 struct iwl_fw_error_dump_data **data) 739 { 740 int i; 741 742 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 743 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 744 struct iwl_fw_error_dump_paging *paging; 745 struct page *pages = 746 fwrt->fw_paging_db[i].fw_paging_block; 747 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 748 749 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 750 (*data)->len = cpu_to_le32(sizeof(*paging) + 751 PAGING_BLOCK_SIZE); 752 paging = (void *)(*data)->data; 753 paging->index = cpu_to_le32(i); 754 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 755 PAGING_BLOCK_SIZE, 756 DMA_BIDIRECTIONAL); 757 memcpy(paging->data, page_address(pages), 758 PAGING_BLOCK_SIZE); 759 dma_sync_single_for_device(fwrt->trans->dev, addr, 760 PAGING_BLOCK_SIZE, 761 DMA_BIDIRECTIONAL); 762 (*data) = iwl_fw_error_next_data(*data); 763 764 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 765 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 766 fwrt->fw_paging_db[i].fw_offs, 767 paging->data, 768 PAGING_BLOCK_SIZE); 769 } 770 } 771 772 static struct iwl_fw_error_dump_file * 773 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 774 struct iwl_fw_dump_ptrs *fw_error_dump, 775 struct iwl_fwrt_dump_data *data) 776 { 777 struct iwl_fw_error_dump_file *dump_file; 778 struct iwl_fw_error_dump_data *dump_data; 779 struct iwl_fw_error_dump_info *dump_info; 780 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 781 struct iwl_fw_error_dump_trigger_desc *dump_trig; 782 u32 sram_len, sram_ofs; 783 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 784 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 785 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 786 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 787 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 788 0 : fwrt->trans->cfg->dccm2_len; 789 int i; 790 791 /* SRAM - include stack CCM if driver knows the values for it */ 792 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 793 const struct fw_img *img; 794 795 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 796 return NULL; 797 img = &fwrt->fw->img[fwrt->cur_fw_img]; 798 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 799 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 800 } else { 801 sram_ofs = fwrt->trans->cfg->dccm_offset; 802 sram_len = fwrt->trans->cfg->dccm_len; 803 } 804 805 /* reading RXF/TXF sizes */ 806 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 807 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 808 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 809 810 /* Make room for PRPH registers */ 811 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 812 iwl_fw_prph_handler(fwrt, &prph_len, 813 iwl_fw_get_prph_len); 814 815 if (fwrt->trans->trans_cfg->device_family == 816 IWL_DEVICE_FAMILY_7000 && 817 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 818 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 819 } 820 821 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 822 823 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 824 file_len += sizeof(*dump_data) + sizeof(*dump_info); 825 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 826 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 827 828 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 829 size_t hdr_len = sizeof(*dump_data) + 830 sizeof(struct iwl_fw_error_dump_mem); 831 832 /* Dump SRAM only if no mem_tlvs */ 833 if (!fwrt->fw->dbg.n_mem_tlv) 834 ADD_LEN(file_len, sram_len, hdr_len); 835 836 /* Make room for all mem types that exist */ 837 ADD_LEN(file_len, smem_len, hdr_len); 838 ADD_LEN(file_len, sram2_len, hdr_len); 839 840 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 841 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 842 } 843 844 /* Make room for fw's virtual image pages, if it exists */ 845 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 846 file_len += fwrt->num_of_paging_blk * 847 (sizeof(*dump_data) + 848 sizeof(struct iwl_fw_error_dump_paging) + 849 PAGING_BLOCK_SIZE); 850 851 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 852 file_len += sizeof(*dump_data) + 853 fwrt->trans->cfg->d3_debug_data_length * 2; 854 } 855 856 /* If we only want a monitor dump, reset the file length */ 857 if (data->monitor_only) { 858 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 859 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 860 } 861 862 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 863 data->desc) 864 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 865 data->desc->len; 866 867 dump_file = vzalloc(file_len); 868 if (!dump_file) 869 return NULL; 870 871 fw_error_dump->fwrt_ptr = dump_file; 872 873 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 874 dump_data = (void *)dump_file->data; 875 876 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 877 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 878 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 879 dump_info = (void *)dump_data->data; 880 dump_info->hw_type = 881 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 882 dump_info->hw_step = 883 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 884 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 885 sizeof(dump_info->fw_human_readable)); 886 strncpy(dump_info->dev_human_readable, fwrt->trans->name, 887 sizeof(dump_info->dev_human_readable) - 1); 888 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 889 sizeof(dump_info->bus_human_readable) - 1); 890 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 891 dump_info->lmac_err_id[0] = 892 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 893 if (fwrt->smem_cfg.num_lmacs > 1) 894 dump_info->lmac_err_id[1] = 895 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 896 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 897 898 dump_data = iwl_fw_error_next_data(dump_data); 899 } 900 901 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 902 /* Dump shared memory configuration */ 903 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 904 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 905 dump_smem_cfg = (void *)dump_data->data; 906 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 907 dump_smem_cfg->num_txfifo_entries = 908 cpu_to_le32(mem_cfg->num_txfifo_entries); 909 for (i = 0; i < MAX_NUM_LMAC; i++) { 910 int j; 911 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 912 913 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 914 dump_smem_cfg->lmac[i].txfifo_size[j] = 915 cpu_to_le32(txf_size[j]); 916 dump_smem_cfg->lmac[i].rxfifo1_size = 917 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 918 } 919 dump_smem_cfg->rxfifo2_size = 920 cpu_to_le32(mem_cfg->rxfifo2_size); 921 dump_smem_cfg->internal_txfifo_addr = 922 cpu_to_le32(mem_cfg->internal_txfifo_addr); 923 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 924 dump_smem_cfg->internal_txfifo_size[i] = 925 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 926 } 927 928 dump_data = iwl_fw_error_next_data(dump_data); 929 } 930 931 /* We only dump the FIFOs if the FW is in error state */ 932 if (fifo_len) { 933 iwl_fw_dump_rxf(fwrt, &dump_data); 934 iwl_fw_dump_txf(fwrt, &dump_data); 935 } 936 937 if (radio_len) 938 iwl_read_radio_regs(fwrt, &dump_data); 939 940 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 941 data->desc) { 942 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 943 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 944 data->desc->len); 945 dump_trig = (void *)dump_data->data; 946 memcpy(dump_trig, &data->desc->trig_desc, 947 sizeof(*dump_trig) + data->desc->len); 948 949 dump_data = iwl_fw_error_next_data(dump_data); 950 } 951 952 /* In case we only want monitor dump, skip to dump trasport data */ 953 if (data->monitor_only) 954 goto out; 955 956 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 957 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 958 fwrt->fw->dbg.mem_tlv; 959 960 if (!fwrt->fw->dbg.n_mem_tlv) 961 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 962 IWL_FW_ERROR_DUMP_MEM_SRAM); 963 964 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 965 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 966 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 967 968 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 969 le32_to_cpu(fw_dbg_mem[i].data_type)); 970 } 971 972 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 973 fwrt->trans->cfg->smem_offset, 974 IWL_FW_ERROR_DUMP_MEM_SMEM); 975 976 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 977 fwrt->trans->cfg->dccm2_offset, 978 IWL_FW_ERROR_DUMP_MEM_SRAM); 979 } 980 981 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 982 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 983 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 984 985 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 986 dump_data->len = cpu_to_le32(data_size * 2); 987 988 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 989 990 kfree(fwrt->dump.d3_debug_data); 991 fwrt->dump.d3_debug_data = NULL; 992 993 iwl_trans_read_mem_bytes(fwrt->trans, addr, 994 dump_data->data + data_size, 995 data_size); 996 997 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 998 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr, 999 dump_data->data + data_size, 1000 data_size); 1001 1002 dump_data = iwl_fw_error_next_data(dump_data); 1003 } 1004 1005 /* Dump fw's virtual image */ 1006 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1007 iwl_dump_paging(fwrt, &dump_data); 1008 1009 if (prph_len) 1010 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1011 1012 out: 1013 dump_file->file_len = cpu_to_le32(file_len); 1014 return dump_file; 1015 } 1016 1017 /** 1018 * struct iwl_dump_ini_region_data - region data 1019 * @reg_tlv: region TLV 1020 * @dump_data: dump data 1021 */ 1022 struct iwl_dump_ini_region_data { 1023 struct iwl_ucode_tlv *reg_tlv; 1024 struct iwl_fwrt_dump_data *dump_data; 1025 }; 1026 1027 static int 1028 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt, 1029 struct iwl_dump_ini_region_data *reg_data, 1030 void *range_ptr, int idx) 1031 { 1032 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1033 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1034 __le32 *val = range->data; 1035 u32 prph_val; 1036 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1037 le32_to_cpu(reg->dev_addr.offset); 1038 int i; 1039 1040 range->internal_base_addr = cpu_to_le32(addr); 1041 range->range_data_size = reg->dev_addr.size; 1042 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1043 prph_val = iwl_read_prph(fwrt->trans, addr + i); 1044 if (prph_val == 0x5a5a5a5a) 1045 return -EBUSY; 1046 *val++ = cpu_to_le32(prph_val); 1047 } 1048 1049 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1050 } 1051 1052 static int 1053 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt, 1054 struct iwl_dump_ini_region_data *reg_data, 1055 void *range_ptr, int idx) 1056 { 1057 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1058 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1059 __le32 *val = range->data; 1060 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1; 1061 u32 indirect_rd_addr = WMAL_MRSPF_1; 1062 u32 prph_val; 1063 u32 addr = le32_to_cpu(reg->addrs[idx]); 1064 u32 dphy_state; 1065 u32 dphy_addr; 1066 int i; 1067 1068 range->internal_base_addr = cpu_to_le32(addr); 1069 range->range_data_size = reg->dev_addr.size; 1070 1071 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 1072 indirect_wr_addr = WMAL_INDRCT_CMD1; 1073 1074 indirect_wr_addr += le32_to_cpu(reg->dev_addr.offset); 1075 indirect_rd_addr += le32_to_cpu(reg->dev_addr.offset); 1076 1077 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1078 return -EBUSY; 1079 1080 dphy_addr = (reg->dev_addr.offset) ? WFPM_LMAC2_PS_CTL_RW : 1081 WFPM_LMAC1_PS_CTL_RW; 1082 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1083 1084 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1085 if (dphy_state == HBUS_TIMEOUT || 1086 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1087 WFPM_PHYRF_STATE_ON) { 1088 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1089 continue; 1090 } 1091 1092 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr, 1093 WMAL_INDRCT_CMD(addr + i)); 1094 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1095 indirect_rd_addr); 1096 *val++ = cpu_to_le32(prph_val); 1097 } 1098 1099 iwl_trans_release_nic_access(fwrt->trans); 1100 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1101 } 1102 1103 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1104 struct iwl_dump_ini_region_data *reg_data, 1105 void *range_ptr, int idx) 1106 { 1107 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1108 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1109 __le32 *val = range->data; 1110 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1111 le32_to_cpu(reg->dev_addr.offset); 1112 int i; 1113 1114 range->internal_base_addr = cpu_to_le32(addr); 1115 range->range_data_size = reg->dev_addr.size; 1116 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) 1117 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1118 1119 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1120 } 1121 1122 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt, 1123 struct iwl_dump_ini_region_data *reg_data, 1124 void *range_ptr, int idx) 1125 { 1126 struct iwl_trans *trans = fwrt->trans; 1127 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1128 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1129 __le32 *val = range->data; 1130 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1131 le32_to_cpu(reg->dev_addr.offset); 1132 int i; 1133 1134 /* we shouldn't get here if the trans doesn't have read_config32 */ 1135 if (WARN_ON_ONCE(!trans->ops->read_config32)) 1136 return -EOPNOTSUPP; 1137 1138 range->internal_base_addr = cpu_to_le32(addr); 1139 range->range_data_size = reg->dev_addr.size; 1140 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1141 int ret; 1142 u32 tmp; 1143 1144 ret = trans->ops->read_config32(trans, addr + i, &tmp); 1145 if (ret < 0) 1146 return ret; 1147 1148 *val++ = cpu_to_le32(tmp); 1149 } 1150 1151 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1152 } 1153 1154 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1155 struct iwl_dump_ini_region_data *reg_data, 1156 void *range_ptr, int idx) 1157 { 1158 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1159 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1160 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1161 le32_to_cpu(reg->dev_addr.offset); 1162 1163 range->internal_base_addr = cpu_to_le32(addr); 1164 range->range_data_size = reg->dev_addr.size; 1165 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1166 le32_to_cpu(reg->dev_addr.size)); 1167 1168 if ((le32_to_cpu(reg->id) & IWL_FW_INI_REGION_V2_MASK) == 1169 IWL_FW_INI_HW_SMEM_REGION_ID && 1170 fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1171 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1172 range->data, 1173 le32_to_cpu(reg->dev_addr.size)); 1174 1175 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1176 } 1177 1178 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1179 void *range_ptr, int idx) 1180 { 1181 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block; 1182 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1183 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1184 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1185 1186 range->page_num = cpu_to_le32(idx); 1187 range->range_data_size = cpu_to_le32(page_size); 1188 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1189 DMA_BIDIRECTIONAL); 1190 memcpy(range->data, page_address(page), page_size); 1191 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1192 DMA_BIDIRECTIONAL); 1193 1194 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1195 } 1196 1197 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1198 struct iwl_dump_ini_region_data *reg_data, 1199 void *range_ptr, int idx) 1200 { 1201 struct iwl_fw_ini_error_dump_range *range; 1202 u32 page_size; 1203 1204 /* all paged index start from 1 to skip CSS section */ 1205 idx++; 1206 1207 if (!fwrt->trans->trans_cfg->gen2) 1208 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, idx); 1209 1210 range = range_ptr; 1211 page_size = fwrt->trans->init_dram.paging[idx].size; 1212 1213 range->page_num = cpu_to_le32(idx); 1214 range->range_data_size = cpu_to_le32(page_size); 1215 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1216 page_size); 1217 1218 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1219 } 1220 1221 static int 1222 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1223 struct iwl_dump_ini_region_data *reg_data, 1224 void *range_ptr, int idx) 1225 { 1226 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1227 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1228 struct iwl_dram_data *frag; 1229 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1230 1231 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx]; 1232 1233 range->dram_base_addr = cpu_to_le64(frag->physical); 1234 range->range_data_size = cpu_to_le32(frag->size); 1235 1236 memcpy(range->data, frag->block, frag->size); 1237 1238 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1239 } 1240 1241 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt, 1242 struct iwl_dump_ini_region_data *reg_data, 1243 void *range_ptr, int idx) 1244 { 1245 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1246 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1247 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr); 1248 1249 range->internal_base_addr = cpu_to_le32(addr); 1250 range->range_data_size = reg->internal_buffer.size; 1251 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1252 le32_to_cpu(reg->internal_buffer.size)); 1253 1254 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1255 } 1256 1257 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1258 struct iwl_dump_ini_region_data *reg_data, int idx) 1259 { 1260 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1261 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1262 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1263 int txf_num = cfg->num_txfifo_entries; 1264 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1265 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]); 1266 1267 if (!idx) { 1268 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) { 1269 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n", 1270 le32_to_cpu(reg->fifos.offset)); 1271 return false; 1272 } 1273 1274 iter->internal_txf = 0; 1275 iter->fifo_size = 0; 1276 iter->fifo = -1; 1277 if (le32_to_cpu(reg->fifos.offset)) 1278 iter->lmac = 1; 1279 else 1280 iter->lmac = 0; 1281 } 1282 1283 if (!iter->internal_txf) { 1284 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1285 iter->fifo_size = 1286 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1287 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1288 return true; 1289 } 1290 iter->fifo--; 1291 } 1292 1293 iter->internal_txf = 1; 1294 1295 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1296 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1297 return false; 1298 1299 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1300 iter->fifo_size = 1301 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1302 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1303 return true; 1304 } 1305 1306 return false; 1307 } 1308 1309 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1310 struct iwl_dump_ini_region_data *reg_data, 1311 void *range_ptr, int idx) 1312 { 1313 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1314 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1315 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1316 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1317 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1318 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1319 u32 registers_size = registers_num * sizeof(*reg_dump); 1320 __le32 *data; 1321 int i; 1322 1323 if (!iwl_ini_txf_iter(fwrt, reg_data, idx)) 1324 return -EIO; 1325 1326 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1327 return -EBUSY; 1328 1329 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1330 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1331 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1332 1333 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1334 1335 /* 1336 * read txf registers. for each register, write to the dump the 1337 * register address and its value 1338 */ 1339 for (i = 0; i < registers_num; i++) { 1340 addr = le32_to_cpu(reg->addrs[i]) + offs; 1341 1342 reg_dump->addr = cpu_to_le32(addr); 1343 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1344 addr)); 1345 1346 reg_dump++; 1347 } 1348 1349 if (reg->fifos.hdr_only) { 1350 range->range_data_size = cpu_to_le32(registers_size); 1351 goto out; 1352 } 1353 1354 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1355 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1356 TXF_WR_PTR + offs); 1357 1358 /* Dummy-read to advance the read pointer to the head */ 1359 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1360 1361 /* Read FIFO */ 1362 addr = TXF_READ_MODIFY_DATA + offs; 1363 data = (void *)reg_dump; 1364 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1365 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1366 1367 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1368 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1369 reg_dump, iter->fifo_size); 1370 1371 out: 1372 iwl_trans_release_nic_access(fwrt->trans); 1373 1374 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1375 } 1376 1377 struct iwl_ini_rxf_data { 1378 u32 fifo_num; 1379 u32 size; 1380 u32 offset; 1381 }; 1382 1383 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1384 struct iwl_dump_ini_region_data *reg_data, 1385 struct iwl_ini_rxf_data *data) 1386 { 1387 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1388 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]); 1389 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]); 1390 u8 fifo_idx; 1391 1392 if (!data) 1393 return; 1394 1395 /* make sure only one bit is set in only one fid */ 1396 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1, 1397 "fid1=%x, fid2=%x\n", fid1, fid2)) 1398 return; 1399 1400 memset(data, 0, sizeof(*data)); 1401 1402 if (fid1) { 1403 fifo_idx = ffs(fid1) - 1; 1404 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n", 1405 fifo_idx)) 1406 return; 1407 1408 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1409 data->fifo_num = fifo_idx; 1410 } else { 1411 u8 max_idx; 1412 1413 fifo_idx = ffs(fid2) - 1; 1414 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP, 1415 SHARED_MEM_CFG_CMD, 0) <= 3) 1416 max_idx = 0; 1417 else 1418 max_idx = 1; 1419 1420 if (WARN_ONCE(fifo_idx > max_idx, 1421 "invalid umac fifo idx %d", fifo_idx)) 1422 return; 1423 1424 /* use bit 31 to distinguish between umac and lmac rxf while 1425 * parsing the dump 1426 */ 1427 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1428 1429 switch (fifo_idx) { 1430 case 0: 1431 data->size = fwrt->smem_cfg.rxfifo2_size; 1432 data->offset = iwl_umac_prph(fwrt->trans, 1433 RXF_DIFF_FROM_PREV); 1434 break; 1435 case 1: 1436 data->size = fwrt->smem_cfg.rxfifo2_control_size; 1437 data->offset = iwl_umac_prph(fwrt->trans, 1438 RXF2C_DIFF_FROM_PREV); 1439 break; 1440 } 1441 } 1442 } 1443 1444 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1445 struct iwl_dump_ini_region_data *reg_data, 1446 void *range_ptr, int idx) 1447 { 1448 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1449 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1450 struct iwl_ini_rxf_data rxf_data; 1451 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1452 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1453 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1454 u32 registers_size = registers_num * sizeof(*reg_dump); 1455 __le32 *data; 1456 int i; 1457 1458 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data); 1459 if (!rxf_data.size) 1460 return -EIO; 1461 1462 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1463 return -EBUSY; 1464 1465 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1466 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1467 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1468 1469 /* 1470 * read rxf registers. for each register, write to the dump the 1471 * register address and its value 1472 */ 1473 for (i = 0; i < registers_num; i++) { 1474 addr = le32_to_cpu(reg->addrs[i]) + offs; 1475 1476 reg_dump->addr = cpu_to_le32(addr); 1477 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1478 addr)); 1479 1480 reg_dump++; 1481 } 1482 1483 if (reg->fifos.hdr_only) { 1484 range->range_data_size = cpu_to_le32(registers_size); 1485 goto out; 1486 } 1487 1488 offs = rxf_data.offset; 1489 1490 /* Lock fence */ 1491 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1492 /* Set fence pointer to the same place like WR pointer */ 1493 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1494 /* Set fence offset */ 1495 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1496 0x0); 1497 1498 /* Read FIFO */ 1499 addr = RXF_FIFO_RD_FENCE_INC + offs; 1500 data = (void *)reg_dump; 1501 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1502 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1503 1504 out: 1505 iwl_trans_release_nic_access(fwrt->trans); 1506 1507 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1508 } 1509 1510 static int 1511 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt, 1512 struct iwl_dump_ini_region_data *reg_data, 1513 void *range_ptr, int idx) 1514 { 1515 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1516 struct iwl_fw_ini_region_err_table *err_table = ®->err_table; 1517 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1518 u32 addr = le32_to_cpu(err_table->base_addr) + 1519 le32_to_cpu(err_table->offset); 1520 1521 range->internal_base_addr = cpu_to_le32(addr); 1522 range->range_data_size = err_table->size; 1523 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1524 le32_to_cpu(err_table->size)); 1525 1526 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1527 } 1528 1529 static int 1530 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt, 1531 struct iwl_dump_ini_region_data *reg_data, 1532 void *range_ptr, int idx) 1533 { 1534 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1535 struct iwl_fw_ini_region_special_device_memory *special_mem = 1536 ®->special_mem; 1537 1538 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1539 u32 addr = le32_to_cpu(special_mem->base_addr) + 1540 le32_to_cpu(special_mem->offset); 1541 1542 range->internal_base_addr = cpu_to_le32(addr); 1543 range->range_data_size = special_mem->size; 1544 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1545 le32_to_cpu(special_mem->size)); 1546 1547 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1548 } 1549 1550 static int 1551 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt, 1552 struct iwl_dump_ini_region_data *reg_data, 1553 void *range_ptr, int idx) 1554 { 1555 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1556 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1557 __le32 *val = range->data; 1558 u32 prph_data; 1559 int i; 1560 1561 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1562 return -EBUSY; 1563 1564 range->range_data_size = reg->dev_addr.size; 1565 iwl_write_prph_no_grab(fwrt->trans, DBGI_SRAM_TARGET_ACCESS_CFG, 1566 DBGI_SRAM_TARGET_ACCESS_CFG_RESET_ADDRESS_MSK); 1567 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) { 1568 prph_data = iwl_read_prph(fwrt->trans, (i % 2) ? 1569 DBGI_SRAM_TARGET_ACCESS_RDATA_MSB : 1570 DBGI_SRAM_TARGET_ACCESS_RDATA_LSB); 1571 if (prph_data == 0x5a5a5a5a) { 1572 iwl_trans_release_nic_access(fwrt->trans); 1573 return -EBUSY; 1574 } 1575 *val++ = cpu_to_le32(prph_data); 1576 } 1577 iwl_trans_release_nic_access(fwrt->trans); 1578 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1579 } 1580 1581 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt, 1582 struct iwl_dump_ini_region_data *reg_data, 1583 void *range_ptr, int idx) 1584 { 1585 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1586 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt; 1587 u32 pkt_len; 1588 1589 if (!pkt) 1590 return -EIO; 1591 1592 pkt_len = iwl_rx_packet_payload_len(pkt); 1593 1594 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr)); 1595 range->range_data_size = cpu_to_le32(pkt_len); 1596 1597 memcpy(range->data, pkt->data, pkt_len); 1598 1599 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1600 } 1601 1602 static void * 1603 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1604 struct iwl_dump_ini_region_data *reg_data, 1605 void *data) 1606 { 1607 struct iwl_fw_ini_error_dump *dump = data; 1608 1609 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1610 1611 return dump->data; 1612 } 1613 1614 /** 1615 * mask_apply_and_normalize - applies mask on val and normalize the result 1616 * 1617 * The normalization is based on the first set bit in the mask 1618 * 1619 * @val: value 1620 * @mask: mask to apply and to normalize with 1621 */ 1622 static u32 mask_apply_and_normalize(u32 val, u32 mask) 1623 { 1624 return (val & mask) >> (ffs(mask) - 1); 1625 } 1626 1627 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1628 const struct iwl_fw_mon_reg *reg_info) 1629 { 1630 u32 val, offs; 1631 1632 /* The header addresses of DBGCi is calculate as follows: 1633 * DBGC1 address + (0x100 * i) 1634 */ 1635 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100; 1636 1637 if (!reg_info || !reg_info->addr || !reg_info->mask) 1638 return 0; 1639 1640 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs); 1641 1642 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask)); 1643 } 1644 1645 static void * 1646 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, 1647 struct iwl_dump_ini_region_data *reg_data, 1648 struct iwl_fw_ini_monitor_dump *data, 1649 const struct iwl_fw_mon_regs *addrs) 1650 { 1651 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1652 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1653 1654 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 1655 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1656 return NULL; 1657 } 1658 1659 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id, 1660 &addrs->write_ptr); 1661 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1662 u32 wrt_ptr = le32_to_cpu(data->write_ptr); 1663 1664 data->write_ptr = cpu_to_le32(wrt_ptr >> 2); 1665 } 1666 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id, 1667 &addrs->cycle_cnt); 1668 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id, 1669 &addrs->cur_frag); 1670 1671 iwl_trans_release_nic_access(fwrt->trans); 1672 1673 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1674 1675 return data->data; 1676 } 1677 1678 static void * 1679 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1680 struct iwl_dump_ini_region_data *reg_data, 1681 void *data) 1682 { 1683 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1684 1685 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump, 1686 &fwrt->trans->cfg->mon_dram_regs); 1687 } 1688 1689 static void * 1690 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1691 struct iwl_dump_ini_region_data *reg_data, 1692 void *data) 1693 { 1694 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1695 1696 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump, 1697 &fwrt->trans->cfg->mon_smem_regs); 1698 } 1699 1700 static void * 1701 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt, 1702 struct iwl_dump_ini_region_data *reg_data, 1703 void *data) 1704 { 1705 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1706 struct iwl_fw_ini_err_table_dump *dump = data; 1707 1708 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1709 dump->version = reg->err_table.version; 1710 1711 return dump->data; 1712 } 1713 1714 static void * 1715 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt, 1716 struct iwl_dump_ini_region_data *reg_data, 1717 void *data) 1718 { 1719 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1720 struct iwl_fw_ini_special_device_memory *dump = data; 1721 1722 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1723 dump->type = reg->special_mem.type; 1724 dump->version = reg->special_mem.version; 1725 1726 return dump->data; 1727 } 1728 1729 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1730 struct iwl_dump_ini_region_data *reg_data) 1731 { 1732 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1733 1734 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1735 } 1736 1737 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1738 struct iwl_dump_ini_region_data *reg_data) 1739 { 1740 if (fwrt->trans->trans_cfg->gen2) { 1741 if (fwrt->trans->init_dram.paging_cnt) 1742 return fwrt->trans->init_dram.paging_cnt - 1; 1743 else 1744 return 0; 1745 } 1746 1747 return fwrt->num_of_paging_blk; 1748 } 1749 1750 static u32 1751 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1752 struct iwl_dump_ini_region_data *reg_data) 1753 { 1754 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1755 struct iwl_fw_mon *fw_mon; 1756 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1757 int i; 1758 1759 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1760 1761 for (i = 0; i < fw_mon->num_frags; i++) { 1762 if (!fw_mon->frags[i].size) 1763 break; 1764 1765 ranges++; 1766 } 1767 1768 return ranges; 1769 } 1770 1771 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1772 struct iwl_dump_ini_region_data *reg_data) 1773 { 1774 u32 num_of_fifos = 0; 1775 1776 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos)) 1777 num_of_fifos++; 1778 1779 return num_of_fifos; 1780 } 1781 1782 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt, 1783 struct iwl_dump_ini_region_data *reg_data) 1784 { 1785 return 1; 1786 } 1787 1788 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1789 struct iwl_dump_ini_region_data *reg_data) 1790 { 1791 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1792 u32 size = le32_to_cpu(reg->dev_addr.size); 1793 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1794 1795 if (!size || !ranges) 1796 return 0; 1797 1798 return sizeof(struct iwl_fw_ini_error_dump) + ranges * 1799 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1800 } 1801 1802 static u32 1803 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1804 struct iwl_dump_ini_region_data *reg_data) 1805 { 1806 int i; 1807 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1808 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1809 1810 /* start from 1 to skip CSS section */ 1811 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) { 1812 size += range_header_len; 1813 if (fwrt->trans->trans_cfg->gen2) 1814 size += fwrt->trans->init_dram.paging[i].size; 1815 else 1816 size += fwrt->fw_paging_db[i].fw_paging_size; 1817 } 1818 1819 return size; 1820 } 1821 1822 static u32 1823 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 1824 struct iwl_dump_ini_region_data *reg_data) 1825 { 1826 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1827 struct iwl_fw_mon *fw_mon; 1828 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1829 int i; 1830 1831 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1832 1833 for (i = 0; i < fw_mon->num_frags; i++) { 1834 struct iwl_dram_data *frag = &fw_mon->frags[i]; 1835 1836 if (!frag->size) 1837 break; 1838 1839 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size; 1840 } 1841 1842 if (size) 1843 size += sizeof(struct iwl_fw_ini_monitor_dump); 1844 1845 return size; 1846 } 1847 1848 static u32 1849 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 1850 struct iwl_dump_ini_region_data *reg_data) 1851 { 1852 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1853 u32 size; 1854 1855 size = le32_to_cpu(reg->internal_buffer.size); 1856 if (!size) 1857 return 0; 1858 1859 size += sizeof(struct iwl_fw_ini_monitor_dump) + 1860 sizeof(struct iwl_fw_ini_error_dump_range); 1861 1862 return size; 1863 } 1864 1865 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 1866 struct iwl_dump_ini_region_data *reg_data) 1867 { 1868 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1869 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1870 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1871 u32 size = 0; 1872 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 1873 registers_num * 1874 sizeof(struct iwl_fw_ini_error_dump_register); 1875 1876 while (iwl_ini_txf_iter(fwrt, reg_data, size)) { 1877 size += fifo_hdr; 1878 if (!reg->fifos.hdr_only) 1879 size += iter->fifo_size; 1880 } 1881 1882 if (!size) 1883 return 0; 1884 1885 return size + sizeof(struct iwl_fw_ini_error_dump); 1886 } 1887 1888 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 1889 struct iwl_dump_ini_region_data *reg_data) 1890 { 1891 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1892 struct iwl_ini_rxf_data rx_data; 1893 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1894 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 1895 sizeof(struct iwl_fw_ini_error_dump_range) + 1896 registers_num * sizeof(struct iwl_fw_ini_error_dump_register); 1897 1898 if (reg->fifos.hdr_only) 1899 return size; 1900 1901 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data); 1902 size += rx_data.size; 1903 1904 return size; 1905 } 1906 1907 static u32 1908 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt, 1909 struct iwl_dump_ini_region_data *reg_data) 1910 { 1911 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1912 u32 size = le32_to_cpu(reg->err_table.size); 1913 1914 if (size) 1915 size += sizeof(struct iwl_fw_ini_err_table_dump) + 1916 sizeof(struct iwl_fw_ini_error_dump_range); 1917 1918 return size; 1919 } 1920 1921 static u32 1922 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt, 1923 struct iwl_dump_ini_region_data *reg_data) 1924 { 1925 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1926 u32 size = le32_to_cpu(reg->special_mem.size); 1927 1928 if (size) 1929 size += sizeof(struct iwl_fw_ini_special_device_memory) + 1930 sizeof(struct iwl_fw_ini_error_dump_range); 1931 1932 return size; 1933 } 1934 1935 static u32 1936 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt, 1937 struct iwl_dump_ini_region_data *reg_data) 1938 { 1939 u32 size = 0; 1940 1941 if (!reg_data->dump_data->fw_pkt) 1942 return 0; 1943 1944 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt); 1945 if (size) 1946 size += sizeof(struct iwl_fw_ini_error_dump) + 1947 sizeof(struct iwl_fw_ini_error_dump_range); 1948 1949 return size; 1950 } 1951 1952 /** 1953 * struct iwl_dump_ini_mem_ops - ini memory dump operations 1954 * @get_num_of_ranges: returns the number of memory ranges in the region. 1955 * @get_size: returns the total size of the region. 1956 * @fill_mem_hdr: fills region type specific headers and returns pointer to 1957 * the first range or NULL if failed to fill headers. 1958 * @fill_range: copies a given memory range into the dump. 1959 * Returns the size of the range or negative error value otherwise. 1960 */ 1961 struct iwl_dump_ini_mem_ops { 1962 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 1963 struct iwl_dump_ini_region_data *reg_data); 1964 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 1965 struct iwl_dump_ini_region_data *reg_data); 1966 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 1967 struct iwl_dump_ini_region_data *reg_data, 1968 void *data); 1969 int (*fill_range)(struct iwl_fw_runtime *fwrt, 1970 struct iwl_dump_ini_region_data *reg_data, 1971 void *range, int idx); 1972 }; 1973 1974 /** 1975 * iwl_dump_ini_mem 1976 * 1977 * Creates a dump tlv and copy a memory region into it. 1978 * Returns the size of the current dump tlv or 0 if failed 1979 * 1980 * @fwrt: fw runtime struct 1981 * @list: list to add the dump tlv to 1982 * @reg_data: memory region 1983 * @ops: memory dump operations 1984 */ 1985 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 1986 struct iwl_dump_ini_region_data *reg_data, 1987 const struct iwl_dump_ini_mem_ops *ops) 1988 { 1989 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1990 struct iwl_fw_ini_dump_entry *entry; 1991 struct iwl_fw_error_dump_data *tlv; 1992 struct iwl_fw_ini_error_dump_header *header; 1993 u32 type = le32_to_cpu(reg->type), id = le32_to_cpu(reg->id); 1994 u32 num_of_ranges, i, size; 1995 void *range; 1996 1997 /* 1998 * The higher part of the ID in version 2 is irrelevant for 1999 * us, so mask it out. 2000 */ 2001 if (le32_to_cpu(reg->hdr.version) == 2) 2002 id &= IWL_FW_INI_REGION_V2_MASK; 2003 2004 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 2005 !ops->fill_range) 2006 return 0; 2007 2008 size = ops->get_size(fwrt, reg_data); 2009 if (!size) 2010 return 0; 2011 2012 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size); 2013 if (!entry) 2014 return 0; 2015 2016 entry->size = sizeof(*tlv) + size; 2017 2018 tlv = (void *)entry->data; 2019 tlv->type = reg->type; 2020 tlv->len = cpu_to_le32(size); 2021 2022 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: id=%d, type=%d\n", id, 2023 type); 2024 2025 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data); 2026 2027 header = (void *)tlv->data; 2028 header->region_id = cpu_to_le32(id); 2029 header->num_of_ranges = cpu_to_le32(num_of_ranges); 2030 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME); 2031 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME); 2032 2033 range = ops->fill_mem_hdr(fwrt, reg_data, header); 2034 if (!range) { 2035 IWL_ERR(fwrt, 2036 "WRT: Failed to fill region header: id=%d, type=%d\n", 2037 id, type); 2038 goto out_err; 2039 } 2040 2041 for (i = 0; i < num_of_ranges; i++) { 2042 int range_size = ops->fill_range(fwrt, reg_data, range, i); 2043 2044 if (range_size < 0) { 2045 IWL_ERR(fwrt, 2046 "WRT: Failed to dump region: id=%d, type=%d\n", 2047 id, type); 2048 goto out_err; 2049 } 2050 range = range + range_size; 2051 } 2052 2053 list_add_tail(&entry->list, list); 2054 2055 return entry->size; 2056 2057 out_err: 2058 vfree(entry); 2059 2060 return 0; 2061 } 2062 2063 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 2064 struct iwl_fw_ini_trigger_tlv *trigger, 2065 struct list_head *list) 2066 { 2067 struct iwl_fw_ini_dump_entry *entry; 2068 struct iwl_fw_error_dump_data *tlv; 2069 struct iwl_fw_ini_dump_info *dump; 2070 struct iwl_dbg_tlv_node *node; 2071 struct iwl_fw_ini_dump_cfg_name *cfg_name; 2072 u32 size = sizeof(*tlv) + sizeof(*dump); 2073 u32 num_of_cfg_names = 0; 2074 u32 hw_type; 2075 2076 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2077 size += sizeof(*cfg_name); 2078 num_of_cfg_names++; 2079 } 2080 2081 entry = vzalloc(sizeof(*entry) + size); 2082 if (!entry) 2083 return 0; 2084 2085 entry->size = size; 2086 2087 tlv = (void *)entry->data; 2088 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 2089 tlv->len = cpu_to_le32(size - sizeof(*tlv)); 2090 2091 dump = (void *)tlv->data; 2092 2093 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 2094 dump->time_point = trigger->time_point; 2095 dump->trigger_reason = trigger->trigger_reason; 2096 dump->external_cfg_state = 2097 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 2098 2099 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 2100 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 2101 2102 dump->hw_step = cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 2103 2104 /* 2105 * Several HWs all have type == 0x42, so we'll override this value 2106 * according to the detected HW 2107 */ 2108 hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev); 2109 if (hw_type == IWL_AX210_HW_TYPE) { 2110 u32 prph_val = iwl_read_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR_GEN2); 2111 u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT); 2112 u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT); 2113 u32 masked_bits = is_jacket | (is_cdb << 1); 2114 2115 /* 2116 * The HW type depends on certain bits in this case, so add 2117 * these bits to the HW type. We won't have collisions since we 2118 * add these bits after the highest possible bit in the mask. 2119 */ 2120 hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT; 2121 } 2122 dump->hw_type = cpu_to_le32(hw_type); 2123 2124 dump->rf_id_flavor = 2125 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id)); 2126 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id)); 2127 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id)); 2128 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id)); 2129 2130 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 2131 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 2132 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 2133 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 2134 2135 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest); 2136 dump->regions_mask = trigger->regions_mask & 2137 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk); 2138 2139 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 2140 memcpy(dump->build_tag, fwrt->fw->human_readable, 2141 sizeof(dump->build_tag)); 2142 2143 cfg_name = dump->cfg_names; 2144 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names); 2145 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2146 struct iwl_fw_ini_debug_info_tlv *debug_info = 2147 (void *)node->tlv.data; 2148 2149 cfg_name->image_type = debug_info->image_type; 2150 cfg_name->cfg_name_len = 2151 cpu_to_le32(IWL_FW_INI_MAX_CFG_NAME); 2152 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name, 2153 sizeof(cfg_name->cfg_name)); 2154 cfg_name++; 2155 } 2156 2157 /* add dump info TLV to the beginning of the list since it needs to be 2158 * the first TLV in the dump 2159 */ 2160 list_add(&entry->list, list); 2161 2162 return entry->size; 2163 } 2164 2165 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 2166 [IWL_FW_INI_REGION_INVALID] = {}, 2167 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 2168 .get_num_of_ranges = iwl_dump_ini_single_range, 2169 .get_size = iwl_dump_ini_mon_smem_get_size, 2170 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 2171 .fill_range = iwl_dump_ini_mon_smem_iter, 2172 }, 2173 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 2174 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 2175 .get_size = iwl_dump_ini_mon_dram_get_size, 2176 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 2177 .fill_range = iwl_dump_ini_mon_dram_iter, 2178 }, 2179 [IWL_FW_INI_REGION_TXF] = { 2180 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 2181 .get_size = iwl_dump_ini_txf_get_size, 2182 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2183 .fill_range = iwl_dump_ini_txf_iter, 2184 }, 2185 [IWL_FW_INI_REGION_RXF] = { 2186 .get_num_of_ranges = iwl_dump_ini_single_range, 2187 .get_size = iwl_dump_ini_rxf_get_size, 2188 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2189 .fill_range = iwl_dump_ini_rxf_iter, 2190 }, 2191 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 2192 .get_num_of_ranges = iwl_dump_ini_single_range, 2193 .get_size = iwl_dump_ini_err_table_get_size, 2194 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2195 .fill_range = iwl_dump_ini_err_table_iter, 2196 }, 2197 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 2198 .get_num_of_ranges = iwl_dump_ini_single_range, 2199 .get_size = iwl_dump_ini_err_table_get_size, 2200 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2201 .fill_range = iwl_dump_ini_err_table_iter, 2202 }, 2203 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = { 2204 .get_num_of_ranges = iwl_dump_ini_single_range, 2205 .get_size = iwl_dump_ini_fw_pkt_get_size, 2206 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2207 .fill_range = iwl_dump_ini_fw_pkt_iter, 2208 }, 2209 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 2210 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2211 .get_size = iwl_dump_ini_mem_get_size, 2212 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2213 .fill_range = iwl_dump_ini_dev_mem_iter, 2214 }, 2215 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 2216 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2217 .get_size = iwl_dump_ini_mem_get_size, 2218 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2219 .fill_range = iwl_dump_ini_prph_mac_iter, 2220 }, 2221 [IWL_FW_INI_REGION_PERIPHERY_PHY] = { 2222 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2223 .get_size = iwl_dump_ini_mem_get_size, 2224 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2225 .fill_range = iwl_dump_ini_prph_phy_iter, 2226 }, 2227 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 2228 [IWL_FW_INI_REGION_PAGING] = { 2229 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2230 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 2231 .get_size = iwl_dump_ini_paging_get_size, 2232 .fill_range = iwl_dump_ini_paging_iter, 2233 }, 2234 [IWL_FW_INI_REGION_CSR] = { 2235 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2236 .get_size = iwl_dump_ini_mem_get_size, 2237 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2238 .fill_range = iwl_dump_ini_csr_iter, 2239 }, 2240 [IWL_FW_INI_REGION_DRAM_IMR] = {}, 2241 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = { 2242 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2243 .get_size = iwl_dump_ini_mem_get_size, 2244 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2245 .fill_range = iwl_dump_ini_config_iter, 2246 }, 2247 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = { 2248 .get_num_of_ranges = iwl_dump_ini_single_range, 2249 .get_size = iwl_dump_ini_special_mem_get_size, 2250 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header, 2251 .fill_range = iwl_dump_ini_special_mem_iter, 2252 }, 2253 [IWL_FW_INI_REGION_DBGI_SRAM] = { 2254 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2255 .get_size = iwl_dump_ini_mem_get_size, 2256 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2257 .fill_range = iwl_dump_ini_dbgi_sram_iter, 2258 }, 2259 }; 2260 2261 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 2262 struct iwl_fwrt_dump_data *dump_data, 2263 struct list_head *list) 2264 { 2265 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2266 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point); 2267 struct iwl_dump_ini_region_data reg_data = { 2268 .dump_data = dump_data, 2269 }; 2270 int i; 2271 u32 size = 0; 2272 u64 regions_mask = le64_to_cpu(trigger->regions_mask) & 2273 ~(fwrt->trans->dbg.unsupported_region_msk); 2274 2275 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask)); 2276 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) < 2277 ARRAY_SIZE(fwrt->trans->dbg.active_regions)); 2278 2279 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) { 2280 u32 reg_type; 2281 struct iwl_fw_ini_region_tlv *reg; 2282 2283 if (!(BIT_ULL(i) & regions_mask)) 2284 continue; 2285 2286 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2287 if (!reg_data.reg_tlv) { 2288 IWL_WARN(fwrt, 2289 "WRT: Unassigned region id %d, skipping\n", i); 2290 continue; 2291 } 2292 2293 reg = (void *)reg_data.reg_tlv->data; 2294 reg_type = le32_to_cpu(reg->type); 2295 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 2296 continue; 2297 2298 if (reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY && 2299 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) { 2300 IWL_WARN(fwrt, 2301 "WRT: trying to collect phy prph at time point: %d, skipping\n", 2302 tp_id); 2303 continue; 2304 } 2305 2306 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2307 &iwl_dump_ini_region_ops[reg_type]); 2308 } 2309 2310 if (size) 2311 size += iwl_dump_ini_info(fwrt, trigger, list); 2312 2313 return size; 2314 } 2315 2316 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt, 2317 struct iwl_fw_ini_trigger_tlv *trig) 2318 { 2319 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2320 u32 usec = le32_to_cpu(trig->ignore_consec); 2321 2322 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 2323 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 2324 tp_id >= IWL_FW_INI_TIME_POINT_NUM || 2325 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec)) 2326 return false; 2327 2328 return true; 2329 } 2330 2331 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 2332 struct iwl_fwrt_dump_data *dump_data, 2333 struct list_head *list) 2334 { 2335 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2336 struct iwl_fw_ini_dump_entry *entry; 2337 struct iwl_fw_ini_dump_file_hdr *hdr; 2338 u32 size; 2339 2340 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) || 2341 !le64_to_cpu(trigger->regions_mask)) 2342 return 0; 2343 2344 entry = vzalloc(sizeof(*entry) + sizeof(*hdr)); 2345 if (!entry) 2346 return 0; 2347 2348 entry->size = sizeof(*hdr); 2349 2350 size = iwl_dump_ini_trigger(fwrt, dump_data, list); 2351 if (!size) { 2352 vfree(entry); 2353 return 0; 2354 } 2355 2356 hdr = (void *)entry->data; 2357 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 2358 hdr->file_len = cpu_to_le32(size + entry->size); 2359 2360 list_add(&entry->list, list); 2361 2362 return le32_to_cpu(hdr->file_len); 2363 } 2364 2365 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt, 2366 const struct iwl_fw_dump_desc *desc) 2367 { 2368 if (desc && desc != &iwl_dump_desc_assert) 2369 kfree(desc); 2370 2371 fwrt->dump.lmac_err_id[0] = 0; 2372 if (fwrt->smem_cfg.num_lmacs > 1) 2373 fwrt->dump.lmac_err_id[1] = 0; 2374 fwrt->dump.umac_err_id = 0; 2375 } 2376 2377 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt, 2378 struct iwl_fwrt_dump_data *dump_data) 2379 { 2380 struct iwl_fw_dump_ptrs fw_error_dump = {}; 2381 struct iwl_fw_error_dump_file *dump_file; 2382 struct scatterlist *sg_dump_data; 2383 u32 file_len; 2384 u32 dump_mask = fwrt->fw->dbg.dump_mask; 2385 2386 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data); 2387 if (!dump_file) 2388 return; 2389 2390 if (dump_data->monitor_only) 2391 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR); 2392 2393 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask, 2394 fwrt->sanitize_ops, 2395 fwrt->sanitize_ctx); 2396 file_len = le32_to_cpu(dump_file->file_len); 2397 fw_error_dump.fwrt_len = file_len; 2398 2399 if (fw_error_dump.trans_ptr) { 2400 file_len += fw_error_dump.trans_ptr->len; 2401 dump_file->file_len = cpu_to_le32(file_len); 2402 } 2403 2404 sg_dump_data = alloc_sgtable(file_len); 2405 if (sg_dump_data) { 2406 sg_pcopy_from_buffer(sg_dump_data, 2407 sg_nents(sg_dump_data), 2408 fw_error_dump.fwrt_ptr, 2409 fw_error_dump.fwrt_len, 0); 2410 if (fw_error_dump.trans_ptr) 2411 sg_pcopy_from_buffer(sg_dump_data, 2412 sg_nents(sg_dump_data), 2413 fw_error_dump.trans_ptr->data, 2414 fw_error_dump.trans_ptr->len, 2415 fw_error_dump.fwrt_len); 2416 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2417 GFP_KERNEL); 2418 } 2419 vfree(fw_error_dump.fwrt_ptr); 2420 vfree(fw_error_dump.trans_ptr); 2421 } 2422 2423 static void iwl_dump_ini_list_free(struct list_head *list) 2424 { 2425 while (!list_empty(list)) { 2426 struct iwl_fw_ini_dump_entry *entry = 2427 list_entry(list->next, typeof(*entry), list); 2428 2429 list_del(&entry->list); 2430 vfree(entry); 2431 } 2432 } 2433 2434 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data) 2435 { 2436 dump_data->trig = NULL; 2437 kfree(dump_data->fw_pkt); 2438 dump_data->fw_pkt = NULL; 2439 } 2440 2441 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, 2442 struct iwl_fwrt_dump_data *dump_data) 2443 { 2444 struct list_head dump_list = LIST_HEAD_INIT(dump_list); 2445 struct scatterlist *sg_dump_data; 2446 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list); 2447 2448 if (!file_len) 2449 return; 2450 2451 sg_dump_data = alloc_sgtable(file_len); 2452 if (sg_dump_data) { 2453 struct iwl_fw_ini_dump_entry *entry; 2454 int sg_entries = sg_nents(sg_dump_data); 2455 u32 offs = 0; 2456 2457 list_for_each_entry(entry, &dump_list, list) { 2458 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2459 entry->data, entry->size, offs); 2460 offs += entry->size; 2461 } 2462 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2463 GFP_KERNEL); 2464 } 2465 iwl_dump_ini_list_free(&dump_list); 2466 } 2467 2468 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2469 .trig_desc = { 2470 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2471 }, 2472 }; 2473 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2474 2475 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2476 const struct iwl_fw_dump_desc *desc, 2477 bool monitor_only, 2478 unsigned int delay) 2479 { 2480 struct iwl_fwrt_wk_data *wk_data; 2481 unsigned long idx; 2482 2483 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2484 iwl_fw_free_dump_desc(fwrt, desc); 2485 return 0; 2486 } 2487 2488 /* 2489 * Check there is an available worker. 2490 * ffz return value is undefined if no zero exists, 2491 * so check against ~0UL first. 2492 */ 2493 if (fwrt->dump.active_wks == ~0UL) 2494 return -EBUSY; 2495 2496 idx = ffz(fwrt->dump.active_wks); 2497 2498 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2499 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2500 return -EBUSY; 2501 2502 wk_data = &fwrt->dump.wks[idx]; 2503 2504 if (WARN_ON(wk_data->dump_data.desc)) 2505 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc); 2506 2507 wk_data->dump_data.desc = desc; 2508 wk_data->dump_data.monitor_only = monitor_only; 2509 2510 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2511 le32_to_cpu(desc->trig_desc.type)); 2512 2513 schedule_delayed_work(&wk_data->wk, usecs_to_jiffies(delay)); 2514 2515 return 0; 2516 } 2517 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2518 2519 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2520 enum iwl_fw_dbg_trigger trig_type) 2521 { 2522 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2523 return -EIO; 2524 2525 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2526 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT && 2527 trig_type != FW_DBG_TRIGGER_DRIVER) 2528 return -EIO; 2529 2530 iwl_dbg_tlv_time_point(fwrt, 2531 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT, 2532 NULL); 2533 } else { 2534 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2535 int ret; 2536 2537 iwl_dump_error_desc = 2538 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2539 2540 if (!iwl_dump_error_desc) 2541 return -ENOMEM; 2542 2543 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2544 iwl_dump_error_desc->len = 0; 2545 2546 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, 2547 false, 0); 2548 if (ret) { 2549 kfree(iwl_dump_error_desc); 2550 return ret; 2551 } 2552 } 2553 2554 iwl_trans_sync_nmi(fwrt->trans); 2555 2556 return 0; 2557 } 2558 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2559 2560 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2561 enum iwl_fw_dbg_trigger trig, 2562 const char *str, size_t len, 2563 struct iwl_fw_dbg_trigger_tlv *trigger) 2564 { 2565 struct iwl_fw_dump_desc *desc; 2566 unsigned int delay = 0; 2567 bool monitor_only = false; 2568 2569 if (trigger) { 2570 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2571 2572 if (!le16_to_cpu(trigger->occurrences)) 2573 return 0; 2574 2575 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2576 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2577 trig); 2578 iwl_force_nmi(fwrt->trans); 2579 return 0; 2580 } 2581 2582 trigger->occurrences = cpu_to_le16(occurrences); 2583 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2584 2585 /* convert msec to usec */ 2586 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2587 } 2588 2589 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 2590 if (!desc) 2591 return -ENOMEM; 2592 2593 2594 desc->len = len; 2595 desc->trig_desc.type = cpu_to_le32(trig); 2596 memcpy(desc->trig_desc.data, str, len); 2597 2598 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2599 } 2600 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2601 2602 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2603 struct iwl_fw_dbg_trigger_tlv *trigger, 2604 const char *fmt, ...) 2605 { 2606 int ret, len = 0; 2607 char buf[64]; 2608 2609 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2610 return 0; 2611 2612 if (fmt) { 2613 va_list ap; 2614 2615 buf[sizeof(buf) - 1] = '\0'; 2616 2617 va_start(ap, fmt); 2618 vsnprintf(buf, sizeof(buf), fmt, ap); 2619 va_end(ap); 2620 2621 /* check for truncation */ 2622 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2623 buf[sizeof(buf) - 1] = '\0'; 2624 2625 len = strlen(buf) + 1; 2626 } 2627 2628 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2629 trigger); 2630 2631 if (ret) 2632 return ret; 2633 2634 return 0; 2635 } 2636 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2637 2638 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2639 { 2640 u8 *ptr; 2641 int ret; 2642 int i; 2643 2644 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 2645 "Invalid configuration %d\n", conf_id)) 2646 return -EINVAL; 2647 2648 /* EARLY START - firmware's configuration is hard coded */ 2649 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 2650 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 2651 conf_id == FW_DBG_START_FROM_ALIVE) 2652 return 0; 2653 2654 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 2655 return -EINVAL; 2656 2657 if (fwrt->dump.conf != FW_DBG_INVALID) 2658 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n", 2659 fwrt->dump.conf); 2660 2661 /* Send all HCMDs for configuring the FW debug */ 2662 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 2663 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 2664 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 2665 struct iwl_host_cmd hcmd = { 2666 .id = cmd->id, 2667 .len = { le16_to_cpu(cmd->len), }, 2668 .data = { cmd->data, }, 2669 }; 2670 2671 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 2672 if (ret) 2673 return ret; 2674 2675 ptr += sizeof(*cmd); 2676 ptr += le16_to_cpu(cmd->len); 2677 } 2678 2679 fwrt->dump.conf = conf_id; 2680 2681 return 0; 2682 } 2683 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 2684 2685 /* this function assumes dump_start was called beforehand and dump_end will be 2686 * called afterwards 2687 */ 2688 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 2689 { 2690 struct iwl_fw_dbg_params params = {0}; 2691 struct iwl_fwrt_dump_data *dump_data = 2692 &fwrt->dump.wks[wk_idx].dump_data; 2693 2694 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 2695 return; 2696 2697 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) { 2698 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n"); 2699 goto out; 2700 } 2701 2702 /* there's no point in fw dump if the bus is dead */ 2703 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 2704 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 2705 goto out; 2706 } 2707 2708 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true); 2709 2710 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 2711 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2712 iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 2713 else 2714 iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 2715 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 2716 2717 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 2718 2719 out: 2720 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2721 iwl_fw_error_dump_data_free(dump_data); 2722 } else { 2723 iwl_fw_free_dump_desc(fwrt, dump_data->desc); 2724 dump_data->desc = NULL; 2725 } 2726 2727 clear_bit(wk_idx, &fwrt->dump.active_wks); 2728 } 2729 2730 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 2731 struct iwl_fwrt_dump_data *dump_data, 2732 bool sync) 2733 { 2734 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig; 2735 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2736 u32 occur, delay; 2737 unsigned long idx; 2738 2739 if (!iwl_fw_ini_trigger_on(fwrt, trig)) { 2740 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 2741 tp_id); 2742 return -EINVAL; 2743 } 2744 2745 delay = le32_to_cpu(trig->dump_delay); 2746 occur = le32_to_cpu(trig->occurrences); 2747 if (!occur) 2748 return 0; 2749 2750 trig->occurrences = cpu_to_le32(--occur); 2751 2752 /* Check there is an available worker. 2753 * ffz return value is undefined if no zero exists, 2754 * so check against ~0UL first. 2755 */ 2756 if (fwrt->dump.active_wks == ~0UL) 2757 return -EBUSY; 2758 2759 idx = ffz(fwrt->dump.active_wks); 2760 2761 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2762 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2763 return -EBUSY; 2764 2765 fwrt->dump.wks[idx].dump_data = *dump_data; 2766 2767 if (sync) 2768 delay = 0; 2769 2770 IWL_WARN(fwrt, 2771 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n", 2772 tp_id, (u32)(delay / USEC_PER_MSEC)); 2773 2774 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay)); 2775 2776 if (sync) 2777 iwl_fw_dbg_collect_sync(fwrt, idx); 2778 2779 return 0; 2780 } 2781 2782 void iwl_fw_error_dump_wk(struct work_struct *work) 2783 { 2784 struct iwl_fwrt_wk_data *wks = 2785 container_of(work, typeof(*wks), wk.work); 2786 struct iwl_fw_runtime *fwrt = 2787 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]); 2788 2789 /* assumes the op mode mutex is locked in dump_start since 2790 * iwl_fw_dbg_collect_sync can't run in parallel 2791 */ 2792 if (fwrt->ops && fwrt->ops->dump_start && 2793 fwrt->ops->dump_start(fwrt->ops_ctx)) 2794 return; 2795 2796 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 2797 2798 if (fwrt->ops && fwrt->ops->dump_end) 2799 fwrt->ops->dump_end(fwrt->ops_ctx); 2800 } 2801 2802 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 2803 { 2804 const struct iwl_cfg *cfg = fwrt->trans->cfg; 2805 2806 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 2807 return; 2808 2809 if (!fwrt->dump.d3_debug_data) { 2810 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 2811 GFP_KERNEL); 2812 if (!fwrt->dump.d3_debug_data) { 2813 IWL_ERR(fwrt, 2814 "failed to allocate memory for D3 debug data\n"); 2815 return; 2816 } 2817 } 2818 2819 /* if the buffer holds previous debug data it is overwritten */ 2820 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 2821 fwrt->dump.d3_debug_data, 2822 cfg->d3_debug_data_length); 2823 2824 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 2825 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 2826 cfg->d3_debug_data_base_addr, 2827 fwrt->dump.d3_debug_data, 2828 cfg->d3_debug_data_length); 2829 } 2830 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 2831 2832 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 2833 { 2834 int i; 2835 2836 iwl_dbg_tlv_del_timers(fwrt->trans); 2837 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 2838 iwl_fw_dbg_collect_sync(fwrt, i); 2839 2840 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 2841 } 2842 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 2843 2844 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 2845 { 2846 struct iwl_dbg_suspend_resume_cmd cmd = { 2847 .operation = suspend ? 2848 cpu_to_le32(DBGC_SUSPEND_CMD) : 2849 cpu_to_le32(DBGC_RESUME_CMD), 2850 }; 2851 struct iwl_host_cmd hcmd = { 2852 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 2853 .data[0] = &cmd, 2854 .len[0] = sizeof(cmd), 2855 }; 2856 2857 return iwl_trans_send_cmd(trans, &hcmd); 2858 } 2859 2860 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 2861 struct iwl_fw_dbg_params *params) 2862 { 2863 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 2864 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 2865 return; 2866 } 2867 2868 if (params) { 2869 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 2870 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 2871 } 2872 2873 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 2874 /* wait for the DBGC to finish writing the internal buffer to DRAM to 2875 * avoid halting the HW while writing 2876 */ 2877 usleep_range(700, 1000); 2878 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 2879 } 2880 2881 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 2882 struct iwl_fw_dbg_params *params) 2883 { 2884 if (!params) 2885 return -EIO; 2886 2887 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 2888 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 2889 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 2890 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 2891 } else { 2892 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 2893 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 2894 } 2895 2896 return 0; 2897 } 2898 2899 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 2900 struct iwl_fw_dbg_params *params, 2901 bool stop) 2902 { 2903 int ret __maybe_unused = 0; 2904 2905 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 2906 return; 2907 2908 if (fw_has_capa(&fwrt->fw->ucode_capa, 2909 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) 2910 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 2911 else if (stop) 2912 iwl_fw_dbg_stop_recording(fwrt->trans, params); 2913 else 2914 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 2915 #ifdef CONFIG_IWLWIFI_DEBUGFS 2916 if (!ret) { 2917 if (stop) 2918 fwrt->trans->dbg.rec_on = false; 2919 else 2920 iwl_fw_set_dbg_rec_on(fwrt); 2921 } 2922 #endif 2923 } 2924 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 2925