1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/devcoredump.h> 8 #include "iwl-drv.h" 9 #include "runtime.h" 10 #include "dbg.h" 11 #include "debugfs.h" 12 #include "iwl-io.h" 13 #include "iwl-prph.h" 14 #include "iwl-csr.h" 15 #include "iwl-fh.h" 16 /** 17 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 18 * 19 * @fwrt_ptr: pointer to the buffer coming from fwrt 20 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 21 * transport's data. 22 * @trans_len: length of the valid data in trans_ptr 23 * @fwrt_len: length of the valid data in fwrt_ptr 24 */ 25 struct iwl_fw_dump_ptrs { 26 struct iwl_trans_dump_data *trans_ptr; 27 void *fwrt_ptr; 28 u32 fwrt_len; 29 }; 30 31 #define RADIO_REG_MAX_READ 0x2ad 32 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 33 struct iwl_fw_error_dump_data **dump_data) 34 { 35 u8 *pos = (void *)(*dump_data)->data; 36 int i; 37 38 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 39 40 if (!iwl_trans_grab_nic_access(fwrt->trans)) 41 return; 42 43 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 44 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 45 46 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 47 u32 rd_cmd = RADIO_RSP_RD_CMD; 48 49 rd_cmd |= i << RADIO_RSP_ADDR_POS; 50 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 51 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 52 53 pos++; 54 } 55 56 *dump_data = iwl_fw_error_next_data(*dump_data); 57 58 iwl_trans_release_nic_access(fwrt->trans); 59 } 60 61 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 62 struct iwl_fw_error_dump_data **dump_data, 63 int size, u32 offset, int fifo_num) 64 { 65 struct iwl_fw_error_dump_fifo *fifo_hdr; 66 u32 *fifo_data; 67 u32 fifo_len; 68 int i; 69 70 fifo_hdr = (void *)(*dump_data)->data; 71 fifo_data = (void *)fifo_hdr->data; 72 fifo_len = size; 73 74 /* No need to try to read the data if the length is 0 */ 75 if (fifo_len == 0) 76 return; 77 78 /* Add a TLV for the RXF */ 79 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 80 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 81 82 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 83 fifo_hdr->available_bytes = 84 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 85 RXF_RD_D_SPACE + offset)); 86 fifo_hdr->wr_ptr = 87 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 88 RXF_RD_WR_PTR + offset)); 89 fifo_hdr->rd_ptr = 90 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 91 RXF_RD_RD_PTR + offset)); 92 fifo_hdr->fence_ptr = 93 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 94 RXF_RD_FENCE_PTR + offset)); 95 fifo_hdr->fence_mode = 96 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 97 RXF_SET_FENCE_MODE + offset)); 98 99 /* Lock fence */ 100 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 101 /* Set fence pointer to the same place like WR pointer */ 102 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 103 /* Set fence offset */ 104 iwl_trans_write_prph(fwrt->trans, 105 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 106 107 /* Read FIFO */ 108 fifo_len /= sizeof(u32); /* Size in DWORDS */ 109 for (i = 0; i < fifo_len; i++) 110 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 111 RXF_FIFO_RD_FENCE_INC + 112 offset); 113 *dump_data = iwl_fw_error_next_data(*dump_data); 114 } 115 116 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 117 struct iwl_fw_error_dump_data **dump_data, 118 int size, u32 offset, int fifo_num) 119 { 120 struct iwl_fw_error_dump_fifo *fifo_hdr; 121 u32 *fifo_data; 122 u32 fifo_len; 123 int i; 124 125 fifo_hdr = (void *)(*dump_data)->data; 126 fifo_data = (void *)fifo_hdr->data; 127 fifo_len = size; 128 129 /* No need to try to read the data if the length is 0 */ 130 if (fifo_len == 0) 131 return; 132 133 /* Add a TLV for the FIFO */ 134 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 135 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 136 137 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 138 fifo_hdr->available_bytes = 139 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 140 TXF_FIFO_ITEM_CNT + offset)); 141 fifo_hdr->wr_ptr = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 TXF_WR_PTR + offset)); 144 fifo_hdr->rd_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 TXF_RD_PTR + offset)); 147 fifo_hdr->fence_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 TXF_FENCE_PTR + offset)); 150 fifo_hdr->fence_mode = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 TXF_LOCK_FENCE + offset)); 153 154 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 155 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 156 TXF_WR_PTR + offset); 157 158 /* Dummy-read to advance the read pointer to the head */ 159 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 160 161 /* Read FIFO */ 162 for (i = 0; i < fifo_len / sizeof(u32); i++) 163 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 164 TXF_READ_MODIFY_DATA + 165 offset); 166 167 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 168 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 169 fifo_data, fifo_len); 170 171 *dump_data = iwl_fw_error_next_data(*dump_data); 172 } 173 174 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 175 struct iwl_fw_error_dump_data **dump_data) 176 { 177 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 178 179 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 180 181 if (!iwl_trans_grab_nic_access(fwrt->trans)) 182 return; 183 184 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 185 /* Pull RXF1 */ 186 iwl_fwrt_dump_rxf(fwrt, dump_data, 187 cfg->lmac[0].rxfifo1_size, 0, 0); 188 /* Pull RXF2 */ 189 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 190 RXF_DIFF_FROM_PREV + 191 fwrt->trans->trans_cfg->umac_prph_offset, 1); 192 /* Pull LMAC2 RXF1 */ 193 if (fwrt->smem_cfg.num_lmacs > 1) 194 iwl_fwrt_dump_rxf(fwrt, dump_data, 195 cfg->lmac[1].rxfifo1_size, 196 LMAC2_PRPH_OFFSET, 2); 197 } 198 199 iwl_trans_release_nic_access(fwrt->trans); 200 } 201 202 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 203 struct iwl_fw_error_dump_data **dump_data) 204 { 205 struct iwl_fw_error_dump_fifo *fifo_hdr; 206 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 207 u32 *fifo_data; 208 u32 fifo_len; 209 int i, j; 210 211 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 212 213 if (!iwl_trans_grab_nic_access(fwrt->trans)) 214 return; 215 216 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 217 /* Pull TXF data from LMAC1 */ 218 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 219 /* Mark the number of TXF we're pulling now */ 220 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 221 iwl_fwrt_dump_txf(fwrt, dump_data, 222 cfg->lmac[0].txfifo_size[i], 0, i); 223 } 224 225 /* Pull TXF data from LMAC2 */ 226 if (fwrt->smem_cfg.num_lmacs > 1) { 227 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 228 i++) { 229 /* Mark the number of TXF we're pulling now */ 230 iwl_trans_write_prph(fwrt->trans, 231 TXF_LARC_NUM + 232 LMAC2_PRPH_OFFSET, i); 233 iwl_fwrt_dump_txf(fwrt, dump_data, 234 cfg->lmac[1].txfifo_size[i], 235 LMAC2_PRPH_OFFSET, 236 i + cfg->num_txfifo_entries); 237 } 238 } 239 } 240 241 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 242 fw_has_capa(&fwrt->fw->ucode_capa, 243 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 244 /* Pull UMAC internal TXF data from all TXFs */ 245 for (i = 0; 246 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 247 i++) { 248 fifo_hdr = (void *)(*dump_data)->data; 249 fifo_data = (void *)fifo_hdr->data; 250 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 251 252 /* No need to try to read the data if the length is 0 */ 253 if (fifo_len == 0) 254 continue; 255 256 /* Add a TLV for the internal FIFOs */ 257 (*dump_data)->type = 258 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 259 (*dump_data)->len = 260 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 261 262 fifo_hdr->fifo_num = cpu_to_le32(i); 263 264 /* Mark the number of TXF we're pulling now */ 265 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 266 fwrt->smem_cfg.num_txfifo_entries); 267 268 fifo_hdr->available_bytes = 269 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 270 TXF_CPU2_FIFO_ITEM_CNT)); 271 fifo_hdr->wr_ptr = 272 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 273 TXF_CPU2_WR_PTR)); 274 fifo_hdr->rd_ptr = 275 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 276 TXF_CPU2_RD_PTR)); 277 fifo_hdr->fence_ptr = 278 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 279 TXF_CPU2_FENCE_PTR)); 280 fifo_hdr->fence_mode = 281 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 282 TXF_CPU2_LOCK_FENCE)); 283 284 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 285 iwl_trans_write_prph(fwrt->trans, 286 TXF_CPU2_READ_MODIFY_ADDR, 287 TXF_CPU2_WR_PTR); 288 289 /* Dummy-read to advance the read pointer to head */ 290 iwl_trans_read_prph(fwrt->trans, 291 TXF_CPU2_READ_MODIFY_DATA); 292 293 /* Read FIFO */ 294 fifo_len /= sizeof(u32); /* Size in DWORDS */ 295 for (j = 0; j < fifo_len; j++) 296 fifo_data[j] = 297 iwl_trans_read_prph(fwrt->trans, 298 TXF_CPU2_READ_MODIFY_DATA); 299 *dump_data = iwl_fw_error_next_data(*dump_data); 300 } 301 } 302 303 iwl_trans_release_nic_access(fwrt->trans); 304 } 305 306 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ 307 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ 308 309 struct iwl_prph_range { 310 u32 start, end; 311 }; 312 313 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 314 { .start = 0x00a00000, .end = 0x00a00000 }, 315 { .start = 0x00a0000c, .end = 0x00a00024 }, 316 { .start = 0x00a0002c, .end = 0x00a0003c }, 317 { .start = 0x00a00410, .end = 0x00a00418 }, 318 { .start = 0x00a00420, .end = 0x00a00420 }, 319 { .start = 0x00a00428, .end = 0x00a00428 }, 320 { .start = 0x00a00430, .end = 0x00a0043c }, 321 { .start = 0x00a00444, .end = 0x00a00444 }, 322 { .start = 0x00a004c0, .end = 0x00a004cc }, 323 { .start = 0x00a004d8, .end = 0x00a004d8 }, 324 { .start = 0x00a004e0, .end = 0x00a004f0 }, 325 { .start = 0x00a00840, .end = 0x00a00840 }, 326 { .start = 0x00a00850, .end = 0x00a00858 }, 327 { .start = 0x00a01004, .end = 0x00a01008 }, 328 { .start = 0x00a01010, .end = 0x00a01010 }, 329 { .start = 0x00a01018, .end = 0x00a01018 }, 330 { .start = 0x00a01024, .end = 0x00a01024 }, 331 { .start = 0x00a0102c, .end = 0x00a01034 }, 332 { .start = 0x00a0103c, .end = 0x00a01040 }, 333 { .start = 0x00a01048, .end = 0x00a01094 }, 334 { .start = 0x00a01c00, .end = 0x00a01c20 }, 335 { .start = 0x00a01c58, .end = 0x00a01c58 }, 336 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 337 { .start = 0x00a01c28, .end = 0x00a01c54 }, 338 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 339 { .start = 0x00a01c60, .end = 0x00a01cdc }, 340 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 341 { .start = 0x00a01d18, .end = 0x00a01d20 }, 342 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 343 { .start = 0x00a01d40, .end = 0x00a01d5c }, 344 { .start = 0x00a01d80, .end = 0x00a01d80 }, 345 { .start = 0x00a01d98, .end = 0x00a01d9c }, 346 { .start = 0x00a01da8, .end = 0x00a01da8 }, 347 { .start = 0x00a01db8, .end = 0x00a01df4 }, 348 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 349 { .start = 0x00a01e00, .end = 0x00a01e2c }, 350 { .start = 0x00a01e40, .end = 0x00a01e60 }, 351 { .start = 0x00a01e68, .end = 0x00a01e6c }, 352 { .start = 0x00a01e74, .end = 0x00a01e74 }, 353 { .start = 0x00a01e84, .end = 0x00a01e90 }, 354 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 355 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 356 { .start = 0x00a01f00, .end = 0x00a01f1c }, 357 { .start = 0x00a01f44, .end = 0x00a01ffc }, 358 { .start = 0x00a02000, .end = 0x00a02048 }, 359 { .start = 0x00a02068, .end = 0x00a020f0 }, 360 { .start = 0x00a02100, .end = 0x00a02118 }, 361 { .start = 0x00a02140, .end = 0x00a0214c }, 362 { .start = 0x00a02168, .end = 0x00a0218c }, 363 { .start = 0x00a021c0, .end = 0x00a021c0 }, 364 { .start = 0x00a02400, .end = 0x00a02410 }, 365 { .start = 0x00a02418, .end = 0x00a02420 }, 366 { .start = 0x00a02428, .end = 0x00a0242c }, 367 { .start = 0x00a02434, .end = 0x00a02434 }, 368 { .start = 0x00a02440, .end = 0x00a02460 }, 369 { .start = 0x00a02468, .end = 0x00a024b0 }, 370 { .start = 0x00a024c8, .end = 0x00a024cc }, 371 { .start = 0x00a02500, .end = 0x00a02504 }, 372 { .start = 0x00a0250c, .end = 0x00a02510 }, 373 { .start = 0x00a02540, .end = 0x00a02554 }, 374 { .start = 0x00a02580, .end = 0x00a025f4 }, 375 { .start = 0x00a02600, .end = 0x00a0260c }, 376 { .start = 0x00a02648, .end = 0x00a02650 }, 377 { .start = 0x00a02680, .end = 0x00a02680 }, 378 { .start = 0x00a026c0, .end = 0x00a026d0 }, 379 { .start = 0x00a02700, .end = 0x00a0270c }, 380 { .start = 0x00a02804, .end = 0x00a02804 }, 381 { .start = 0x00a02818, .end = 0x00a0281c }, 382 { .start = 0x00a02c00, .end = 0x00a02db4 }, 383 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 384 { .start = 0x00a03000, .end = 0x00a03014 }, 385 { .start = 0x00a0301c, .end = 0x00a0302c }, 386 { .start = 0x00a03034, .end = 0x00a03038 }, 387 { .start = 0x00a03040, .end = 0x00a03048 }, 388 { .start = 0x00a03060, .end = 0x00a03068 }, 389 { .start = 0x00a03070, .end = 0x00a03074 }, 390 { .start = 0x00a0307c, .end = 0x00a0307c }, 391 { .start = 0x00a03080, .end = 0x00a03084 }, 392 { .start = 0x00a0308c, .end = 0x00a03090 }, 393 { .start = 0x00a03098, .end = 0x00a03098 }, 394 { .start = 0x00a030a0, .end = 0x00a030a0 }, 395 { .start = 0x00a030a8, .end = 0x00a030b4 }, 396 { .start = 0x00a030bc, .end = 0x00a030bc }, 397 { .start = 0x00a030c0, .end = 0x00a0312c }, 398 { .start = 0x00a03c00, .end = 0x00a03c5c }, 399 { .start = 0x00a04400, .end = 0x00a04454 }, 400 { .start = 0x00a04460, .end = 0x00a04474 }, 401 { .start = 0x00a044c0, .end = 0x00a044ec }, 402 { .start = 0x00a04500, .end = 0x00a04504 }, 403 { .start = 0x00a04510, .end = 0x00a04538 }, 404 { .start = 0x00a04540, .end = 0x00a04548 }, 405 { .start = 0x00a04560, .end = 0x00a0457c }, 406 { .start = 0x00a04590, .end = 0x00a04598 }, 407 { .start = 0x00a045c0, .end = 0x00a045f4 }, 408 }; 409 410 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 411 { .start = 0x00a05c00, .end = 0x00a05c18 }, 412 { .start = 0x00a05400, .end = 0x00a056e8 }, 413 { .start = 0x00a08000, .end = 0x00a098bc }, 414 { .start = 0x00a02400, .end = 0x00a02758 }, 415 { .start = 0x00a04764, .end = 0x00a0476c }, 416 { .start = 0x00a04770, .end = 0x00a04774 }, 417 { .start = 0x00a04620, .end = 0x00a04624 }, 418 }; 419 420 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 421 { .start = 0x00a00000, .end = 0x00a00000 }, 422 { .start = 0x00a0000c, .end = 0x00a00024 }, 423 { .start = 0x00a0002c, .end = 0x00a00034 }, 424 { .start = 0x00a0003c, .end = 0x00a0003c }, 425 { .start = 0x00a00410, .end = 0x00a00418 }, 426 { .start = 0x00a00420, .end = 0x00a00420 }, 427 { .start = 0x00a00428, .end = 0x00a00428 }, 428 { .start = 0x00a00430, .end = 0x00a0043c }, 429 { .start = 0x00a00444, .end = 0x00a00444 }, 430 { .start = 0x00a00840, .end = 0x00a00840 }, 431 { .start = 0x00a00850, .end = 0x00a00858 }, 432 { .start = 0x00a01004, .end = 0x00a01008 }, 433 { .start = 0x00a01010, .end = 0x00a01010 }, 434 { .start = 0x00a01018, .end = 0x00a01018 }, 435 { .start = 0x00a01024, .end = 0x00a01024 }, 436 { .start = 0x00a0102c, .end = 0x00a01034 }, 437 { .start = 0x00a0103c, .end = 0x00a01040 }, 438 { .start = 0x00a01048, .end = 0x00a01050 }, 439 { .start = 0x00a01058, .end = 0x00a01058 }, 440 { .start = 0x00a01060, .end = 0x00a01070 }, 441 { .start = 0x00a0108c, .end = 0x00a0108c }, 442 { .start = 0x00a01c20, .end = 0x00a01c28 }, 443 { .start = 0x00a01d10, .end = 0x00a01d10 }, 444 { .start = 0x00a01e28, .end = 0x00a01e2c }, 445 { .start = 0x00a01e60, .end = 0x00a01e60 }, 446 { .start = 0x00a01e80, .end = 0x00a01e80 }, 447 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 448 { .start = 0x00a02000, .end = 0x00a0201c }, 449 { .start = 0x00a02024, .end = 0x00a02024 }, 450 { .start = 0x00a02040, .end = 0x00a02048 }, 451 { .start = 0x00a020c0, .end = 0x00a020e0 }, 452 { .start = 0x00a02400, .end = 0x00a02404 }, 453 { .start = 0x00a0240c, .end = 0x00a02414 }, 454 { .start = 0x00a0241c, .end = 0x00a0243c }, 455 { .start = 0x00a02448, .end = 0x00a024bc }, 456 { .start = 0x00a024c4, .end = 0x00a024cc }, 457 { .start = 0x00a02508, .end = 0x00a02508 }, 458 { .start = 0x00a02510, .end = 0x00a02514 }, 459 { .start = 0x00a0251c, .end = 0x00a0251c }, 460 { .start = 0x00a0252c, .end = 0x00a0255c }, 461 { .start = 0x00a02564, .end = 0x00a025a0 }, 462 { .start = 0x00a025a8, .end = 0x00a025b4 }, 463 { .start = 0x00a025c0, .end = 0x00a025c0 }, 464 { .start = 0x00a025e8, .end = 0x00a025f4 }, 465 { .start = 0x00a02c08, .end = 0x00a02c18 }, 466 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 467 { .start = 0x00a02c68, .end = 0x00a02c78 }, 468 { .start = 0x00a03000, .end = 0x00a03000 }, 469 { .start = 0x00a03010, .end = 0x00a03014 }, 470 { .start = 0x00a0301c, .end = 0x00a0302c }, 471 { .start = 0x00a03034, .end = 0x00a03038 }, 472 { .start = 0x00a03040, .end = 0x00a03044 }, 473 { .start = 0x00a03060, .end = 0x00a03068 }, 474 { .start = 0x00a03070, .end = 0x00a03070 }, 475 { .start = 0x00a0307c, .end = 0x00a03084 }, 476 { .start = 0x00a0308c, .end = 0x00a03090 }, 477 { .start = 0x00a03098, .end = 0x00a03098 }, 478 { .start = 0x00a030a0, .end = 0x00a030a0 }, 479 { .start = 0x00a030a8, .end = 0x00a030b4 }, 480 { .start = 0x00a030bc, .end = 0x00a030c0 }, 481 { .start = 0x00a030c8, .end = 0x00a030f4 }, 482 { .start = 0x00a03100, .end = 0x00a0312c }, 483 { .start = 0x00a03c00, .end = 0x00a03c5c }, 484 { .start = 0x00a04400, .end = 0x00a04454 }, 485 { .start = 0x00a04460, .end = 0x00a04474 }, 486 { .start = 0x00a044c0, .end = 0x00a044ec }, 487 { .start = 0x00a04500, .end = 0x00a04504 }, 488 { .start = 0x00a04510, .end = 0x00a04538 }, 489 { .start = 0x00a04540, .end = 0x00a04548 }, 490 { .start = 0x00a04560, .end = 0x00a04560 }, 491 { .start = 0x00a04570, .end = 0x00a0457c }, 492 { .start = 0x00a04590, .end = 0x00a04590 }, 493 { .start = 0x00a04598, .end = 0x00a04598 }, 494 { .start = 0x00a045c0, .end = 0x00a045f4 }, 495 { .start = 0x00a05c18, .end = 0x00a05c1c }, 496 { .start = 0x00a0c000, .end = 0x00a0c018 }, 497 { .start = 0x00a0c020, .end = 0x00a0c028 }, 498 { .start = 0x00a0c038, .end = 0x00a0c094 }, 499 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 500 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 501 { .start = 0x00a0c150, .end = 0x00a0c174 }, 502 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 503 { .start = 0x00a0c190, .end = 0x00a0c198 }, 504 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 505 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 506 }; 507 508 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 509 { .start = 0x00d03c00, .end = 0x00d03c64 }, 510 { .start = 0x00d05c18, .end = 0x00d05c1c }, 511 { .start = 0x00d0c000, .end = 0x00d0c174 }, 512 }; 513 514 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 515 u32 len_bytes, __le32 *data) 516 { 517 u32 i; 518 519 for (i = 0; i < len_bytes; i += 4) 520 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 521 } 522 523 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 524 const struct iwl_prph_range *iwl_prph_dump_addr, 525 u32 range_len, void *ptr) 526 { 527 struct iwl_fw_error_dump_prph *prph; 528 struct iwl_trans *trans = fwrt->trans; 529 struct iwl_fw_error_dump_data **data = 530 (struct iwl_fw_error_dump_data **)ptr; 531 u32 i; 532 533 if (!data) 534 return; 535 536 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 537 538 if (!iwl_trans_grab_nic_access(trans)) 539 return; 540 541 for (i = 0; i < range_len; i++) { 542 /* The range includes both boundaries */ 543 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 544 iwl_prph_dump_addr[i].start + 4; 545 546 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 547 (*data)->len = cpu_to_le32(sizeof(*prph) + 548 num_bytes_in_chunk); 549 prph = (void *)(*data)->data; 550 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 551 552 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 553 /* our range is inclusive, hence + 4 */ 554 iwl_prph_dump_addr[i].end - 555 iwl_prph_dump_addr[i].start + 4, 556 (void *)prph->data); 557 558 *data = iwl_fw_error_next_data(*data); 559 } 560 561 iwl_trans_release_nic_access(trans); 562 } 563 564 /* 565 * alloc_sgtable - allocates scallerlist table in the given size, 566 * fills it with pages and returns it 567 * @size: the size (in bytes) of the table 568 */ 569 static struct scatterlist *alloc_sgtable(int size) 570 { 571 int alloc_size, nents, i; 572 struct page *new_page; 573 struct scatterlist *iter; 574 struct scatterlist *table; 575 576 nents = DIV_ROUND_UP(size, PAGE_SIZE); 577 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 578 if (!table) 579 return NULL; 580 sg_init_table(table, nents); 581 iter = table; 582 for_each_sg(table, iter, sg_nents(table), i) { 583 new_page = alloc_page(GFP_KERNEL); 584 if (!new_page) { 585 /* release all previous allocated pages in the table */ 586 iter = table; 587 for_each_sg(table, iter, sg_nents(table), i) { 588 new_page = sg_page(iter); 589 if (new_page) 590 __free_page(new_page); 591 } 592 kfree(table); 593 return NULL; 594 } 595 alloc_size = min_t(int, size, PAGE_SIZE); 596 size -= PAGE_SIZE; 597 sg_set_page(iter, new_page, alloc_size, 0); 598 } 599 return table; 600 } 601 602 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 603 const struct iwl_prph_range *iwl_prph_dump_addr, 604 u32 range_len, void *ptr) 605 { 606 u32 *prph_len = (u32 *)ptr; 607 int i, num_bytes_in_chunk; 608 609 if (!prph_len) 610 return; 611 612 for (i = 0; i < range_len; i++) { 613 /* The range includes both boundaries */ 614 num_bytes_in_chunk = 615 iwl_prph_dump_addr[i].end - 616 iwl_prph_dump_addr[i].start + 4; 617 618 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 619 sizeof(struct iwl_fw_error_dump_prph) + 620 num_bytes_in_chunk; 621 } 622 } 623 624 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 625 void (*handler)(struct iwl_fw_runtime *, 626 const struct iwl_prph_range *, 627 u32, void *)) 628 { 629 u32 range_len; 630 631 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 632 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 633 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 634 } else if (fwrt->trans->trans_cfg->device_family >= 635 IWL_DEVICE_FAMILY_22000) { 636 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 637 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 638 } else { 639 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 640 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 641 642 if (fwrt->trans->trans_cfg->mq_rx_supported) { 643 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 644 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 645 } 646 } 647 } 648 649 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 650 struct iwl_fw_error_dump_data **dump_data, 651 u32 len, u32 ofs, u32 type) 652 { 653 struct iwl_fw_error_dump_mem *dump_mem; 654 655 if (!len) 656 return; 657 658 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 659 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 660 dump_mem = (void *)(*dump_data)->data; 661 dump_mem->type = cpu_to_le32(type); 662 dump_mem->offset = cpu_to_le32(ofs); 663 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 664 *dump_data = iwl_fw_error_next_data(*dump_data); 665 666 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 667 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs, 668 dump_mem->data, len); 669 670 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 671 } 672 673 #define ADD_LEN(len, item_len, const_len) \ 674 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 675 while (0) 676 677 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 678 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 679 { 680 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 681 sizeof(struct iwl_fw_error_dump_fifo); 682 u32 fifo_len = 0; 683 int i; 684 685 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 686 return 0; 687 688 /* Count RXF2 size */ 689 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 690 691 /* Count RXF1 sizes */ 692 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 693 mem_cfg->num_lmacs = MAX_NUM_LMAC; 694 695 for (i = 0; i < mem_cfg->num_lmacs; i++) 696 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 697 698 return fifo_len; 699 } 700 701 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 702 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 703 { 704 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 705 sizeof(struct iwl_fw_error_dump_fifo); 706 u32 fifo_len = 0; 707 int i; 708 709 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 710 goto dump_internal_txf; 711 712 /* Count TXF sizes */ 713 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 714 mem_cfg->num_lmacs = MAX_NUM_LMAC; 715 716 for (i = 0; i < mem_cfg->num_lmacs; i++) { 717 int j; 718 719 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 720 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 721 hdr_len); 722 } 723 724 dump_internal_txf: 725 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 726 fw_has_capa(&fwrt->fw->ucode_capa, 727 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 728 goto out; 729 730 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 731 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 732 733 out: 734 return fifo_len; 735 } 736 737 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 738 struct iwl_fw_error_dump_data **data) 739 { 740 int i; 741 742 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 743 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 744 struct iwl_fw_error_dump_paging *paging; 745 struct page *pages = 746 fwrt->fw_paging_db[i].fw_paging_block; 747 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 748 749 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 750 (*data)->len = cpu_to_le32(sizeof(*paging) + 751 PAGING_BLOCK_SIZE); 752 paging = (void *)(*data)->data; 753 paging->index = cpu_to_le32(i); 754 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 755 PAGING_BLOCK_SIZE, 756 DMA_BIDIRECTIONAL); 757 memcpy(paging->data, page_address(pages), 758 PAGING_BLOCK_SIZE); 759 dma_sync_single_for_device(fwrt->trans->dev, addr, 760 PAGING_BLOCK_SIZE, 761 DMA_BIDIRECTIONAL); 762 (*data) = iwl_fw_error_next_data(*data); 763 764 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 765 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 766 fwrt->fw_paging_db[i].fw_offs, 767 paging->data, 768 PAGING_BLOCK_SIZE); 769 } 770 } 771 772 static struct iwl_fw_error_dump_file * 773 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 774 struct iwl_fw_dump_ptrs *fw_error_dump, 775 struct iwl_fwrt_dump_data *data) 776 { 777 struct iwl_fw_error_dump_file *dump_file; 778 struct iwl_fw_error_dump_data *dump_data; 779 struct iwl_fw_error_dump_info *dump_info; 780 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 781 struct iwl_fw_error_dump_trigger_desc *dump_trig; 782 u32 sram_len, sram_ofs; 783 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 784 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 785 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 786 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 787 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 788 0 : fwrt->trans->cfg->dccm2_len; 789 int i; 790 791 /* SRAM - include stack CCM if driver knows the values for it */ 792 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 793 const struct fw_img *img; 794 795 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 796 return NULL; 797 img = &fwrt->fw->img[fwrt->cur_fw_img]; 798 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 799 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 800 } else { 801 sram_ofs = fwrt->trans->cfg->dccm_offset; 802 sram_len = fwrt->trans->cfg->dccm_len; 803 } 804 805 /* reading RXF/TXF sizes */ 806 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 807 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 808 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 809 810 /* Make room for PRPH registers */ 811 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 812 iwl_fw_prph_handler(fwrt, &prph_len, 813 iwl_fw_get_prph_len); 814 815 if (fwrt->trans->trans_cfg->device_family == 816 IWL_DEVICE_FAMILY_7000 && 817 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 818 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 819 } 820 821 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 822 823 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 824 file_len += sizeof(*dump_data) + sizeof(*dump_info); 825 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 826 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 827 828 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 829 size_t hdr_len = sizeof(*dump_data) + 830 sizeof(struct iwl_fw_error_dump_mem); 831 832 /* Dump SRAM only if no mem_tlvs */ 833 if (!fwrt->fw->dbg.n_mem_tlv) 834 ADD_LEN(file_len, sram_len, hdr_len); 835 836 /* Make room for all mem types that exist */ 837 ADD_LEN(file_len, smem_len, hdr_len); 838 ADD_LEN(file_len, sram2_len, hdr_len); 839 840 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 841 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 842 } 843 844 /* Make room for fw's virtual image pages, if it exists */ 845 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 846 file_len += fwrt->num_of_paging_blk * 847 (sizeof(*dump_data) + 848 sizeof(struct iwl_fw_error_dump_paging) + 849 PAGING_BLOCK_SIZE); 850 851 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 852 file_len += sizeof(*dump_data) + 853 fwrt->trans->cfg->d3_debug_data_length * 2; 854 } 855 856 /* If we only want a monitor dump, reset the file length */ 857 if (data->monitor_only) { 858 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 859 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 860 } 861 862 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 863 data->desc) 864 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 865 data->desc->len; 866 867 dump_file = vzalloc(file_len); 868 if (!dump_file) 869 return NULL; 870 871 fw_error_dump->fwrt_ptr = dump_file; 872 873 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 874 dump_data = (void *)dump_file->data; 875 876 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 877 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 878 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 879 dump_info = (void *)dump_data->data; 880 dump_info->hw_type = 881 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 882 dump_info->hw_step = 883 cpu_to_le32(fwrt->trans->hw_rev_step); 884 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 885 sizeof(dump_info->fw_human_readable)); 886 strncpy(dump_info->dev_human_readable, fwrt->trans->name, 887 sizeof(dump_info->dev_human_readable) - 1); 888 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 889 sizeof(dump_info->bus_human_readable) - 1); 890 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 891 dump_info->lmac_err_id[0] = 892 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 893 if (fwrt->smem_cfg.num_lmacs > 1) 894 dump_info->lmac_err_id[1] = 895 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 896 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 897 898 dump_data = iwl_fw_error_next_data(dump_data); 899 } 900 901 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 902 /* Dump shared memory configuration */ 903 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 904 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 905 dump_smem_cfg = (void *)dump_data->data; 906 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 907 dump_smem_cfg->num_txfifo_entries = 908 cpu_to_le32(mem_cfg->num_txfifo_entries); 909 for (i = 0; i < MAX_NUM_LMAC; i++) { 910 int j; 911 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 912 913 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 914 dump_smem_cfg->lmac[i].txfifo_size[j] = 915 cpu_to_le32(txf_size[j]); 916 dump_smem_cfg->lmac[i].rxfifo1_size = 917 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 918 } 919 dump_smem_cfg->rxfifo2_size = 920 cpu_to_le32(mem_cfg->rxfifo2_size); 921 dump_smem_cfg->internal_txfifo_addr = 922 cpu_to_le32(mem_cfg->internal_txfifo_addr); 923 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 924 dump_smem_cfg->internal_txfifo_size[i] = 925 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 926 } 927 928 dump_data = iwl_fw_error_next_data(dump_data); 929 } 930 931 /* We only dump the FIFOs if the FW is in error state */ 932 if (fifo_len) { 933 iwl_fw_dump_rxf(fwrt, &dump_data); 934 iwl_fw_dump_txf(fwrt, &dump_data); 935 } 936 937 if (radio_len) 938 iwl_read_radio_regs(fwrt, &dump_data); 939 940 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 941 data->desc) { 942 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 943 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 944 data->desc->len); 945 dump_trig = (void *)dump_data->data; 946 memcpy(dump_trig, &data->desc->trig_desc, 947 sizeof(*dump_trig) + data->desc->len); 948 949 dump_data = iwl_fw_error_next_data(dump_data); 950 } 951 952 /* In case we only want monitor dump, skip to dump trasport data */ 953 if (data->monitor_only) 954 goto out; 955 956 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 957 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 958 fwrt->fw->dbg.mem_tlv; 959 960 if (!fwrt->fw->dbg.n_mem_tlv) 961 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 962 IWL_FW_ERROR_DUMP_MEM_SRAM); 963 964 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 965 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 966 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 967 968 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 969 le32_to_cpu(fw_dbg_mem[i].data_type)); 970 } 971 972 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 973 fwrt->trans->cfg->smem_offset, 974 IWL_FW_ERROR_DUMP_MEM_SMEM); 975 976 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 977 fwrt->trans->cfg->dccm2_offset, 978 IWL_FW_ERROR_DUMP_MEM_SRAM); 979 } 980 981 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 982 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 983 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 984 985 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 986 dump_data->len = cpu_to_le32(data_size * 2); 987 988 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 989 990 kfree(fwrt->dump.d3_debug_data); 991 fwrt->dump.d3_debug_data = NULL; 992 993 iwl_trans_read_mem_bytes(fwrt->trans, addr, 994 dump_data->data + data_size, 995 data_size); 996 997 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 998 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr, 999 dump_data->data + data_size, 1000 data_size); 1001 1002 dump_data = iwl_fw_error_next_data(dump_data); 1003 } 1004 1005 /* Dump fw's virtual image */ 1006 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1007 iwl_dump_paging(fwrt, &dump_data); 1008 1009 if (prph_len) 1010 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1011 1012 out: 1013 dump_file->file_len = cpu_to_le32(file_len); 1014 return dump_file; 1015 } 1016 1017 /** 1018 * struct iwl_dump_ini_region_data - region data 1019 * @reg_tlv: region TLV 1020 * @dump_data: dump data 1021 */ 1022 struct iwl_dump_ini_region_data { 1023 struct iwl_ucode_tlv *reg_tlv; 1024 struct iwl_fwrt_dump_data *dump_data; 1025 }; 1026 1027 static int 1028 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt, 1029 struct iwl_dump_ini_region_data *reg_data, 1030 void *range_ptr, u32 range_len, int idx) 1031 { 1032 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1033 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1034 __le32 *val = range->data; 1035 u32 prph_val; 1036 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1037 le32_to_cpu(reg->dev_addr.offset); 1038 int i; 1039 1040 range->internal_base_addr = cpu_to_le32(addr); 1041 range->range_data_size = reg->dev_addr.size; 1042 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1043 prph_val = iwl_read_prph(fwrt->trans, addr + i); 1044 if (prph_val == 0x5a5a5a5a) 1045 return -EBUSY; 1046 *val++ = cpu_to_le32(prph_val); 1047 } 1048 1049 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1050 } 1051 1052 static int 1053 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt, 1054 struct iwl_dump_ini_region_data *reg_data, 1055 void *range_ptr, u32 range_len, int idx) 1056 { 1057 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1058 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1059 __le32 *val = range->data; 1060 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1; 1061 u32 indirect_rd_addr = WMAL_MRSPF_1; 1062 u32 prph_val; 1063 u32 addr = le32_to_cpu(reg->addrs[idx]); 1064 u32 dphy_state; 1065 u32 dphy_addr; 1066 int i; 1067 1068 range->internal_base_addr = cpu_to_le32(addr); 1069 range->range_data_size = reg->dev_addr.size; 1070 1071 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 1072 indirect_wr_addr = WMAL_INDRCT_CMD1; 1073 1074 indirect_wr_addr += le32_to_cpu(reg->dev_addr.offset); 1075 indirect_rd_addr += le32_to_cpu(reg->dev_addr.offset); 1076 1077 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1078 return -EBUSY; 1079 1080 dphy_addr = (reg->dev_addr.offset) ? WFPM_LMAC2_PS_CTL_RW : 1081 WFPM_LMAC1_PS_CTL_RW; 1082 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1083 1084 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1085 if (dphy_state == HBUS_TIMEOUT || 1086 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1087 WFPM_PHYRF_STATE_ON) { 1088 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1089 continue; 1090 } 1091 1092 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr, 1093 WMAL_INDRCT_CMD(addr + i)); 1094 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1095 indirect_rd_addr); 1096 *val++ = cpu_to_le32(prph_val); 1097 } 1098 1099 iwl_trans_release_nic_access(fwrt->trans); 1100 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1101 } 1102 1103 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1104 struct iwl_dump_ini_region_data *reg_data, 1105 void *range_ptr, u32 range_len, int idx) 1106 { 1107 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1108 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1109 __le32 *val = range->data; 1110 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1111 le32_to_cpu(reg->dev_addr.offset); 1112 int i; 1113 1114 range->internal_base_addr = cpu_to_le32(addr); 1115 range->range_data_size = reg->dev_addr.size; 1116 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) 1117 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1118 1119 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1120 } 1121 1122 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt, 1123 struct iwl_dump_ini_region_data *reg_data, 1124 void *range_ptr, u32 range_len, int idx) 1125 { 1126 struct iwl_trans *trans = fwrt->trans; 1127 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1128 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1129 __le32 *val = range->data; 1130 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1131 le32_to_cpu(reg->dev_addr.offset); 1132 int i; 1133 1134 /* we shouldn't get here if the trans doesn't have read_config32 */ 1135 if (WARN_ON_ONCE(!trans->ops->read_config32)) 1136 return -EOPNOTSUPP; 1137 1138 range->internal_base_addr = cpu_to_le32(addr); 1139 range->range_data_size = reg->dev_addr.size; 1140 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1141 int ret; 1142 u32 tmp; 1143 1144 ret = trans->ops->read_config32(trans, addr + i, &tmp); 1145 if (ret < 0) 1146 return ret; 1147 1148 *val++ = cpu_to_le32(tmp); 1149 } 1150 1151 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1152 } 1153 1154 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1155 struct iwl_dump_ini_region_data *reg_data, 1156 void *range_ptr, u32 range_len, int idx) 1157 { 1158 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1159 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1160 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1161 le32_to_cpu(reg->dev_addr.offset); 1162 1163 range->internal_base_addr = cpu_to_le32(addr); 1164 range->range_data_size = reg->dev_addr.size; 1165 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1166 le32_to_cpu(reg->dev_addr.size)); 1167 1168 if (reg->sub_type == IWL_FW_INI_REGION_DEVICE_MEMORY_SUBTYPE_HW_SMEM && 1169 fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1170 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1171 range->data, 1172 le32_to_cpu(reg->dev_addr.size)); 1173 1174 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1175 } 1176 1177 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1178 void *range_ptr, u32 range_len, int idx) 1179 { 1180 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block; 1181 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1182 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1183 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1184 1185 range->page_num = cpu_to_le32(idx); 1186 range->range_data_size = cpu_to_le32(page_size); 1187 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1188 DMA_BIDIRECTIONAL); 1189 memcpy(range->data, page_address(page), page_size); 1190 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1191 DMA_BIDIRECTIONAL); 1192 1193 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1194 } 1195 1196 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1197 struct iwl_dump_ini_region_data *reg_data, 1198 void *range_ptr, u32 range_len, int idx) 1199 { 1200 struct iwl_fw_ini_error_dump_range *range; 1201 u32 page_size; 1202 1203 /* all paged index start from 1 to skip CSS section */ 1204 idx++; 1205 1206 if (!fwrt->trans->trans_cfg->gen2) 1207 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, range_len, idx); 1208 1209 range = range_ptr; 1210 page_size = fwrt->trans->init_dram.paging[idx].size; 1211 1212 range->page_num = cpu_to_le32(idx); 1213 range->range_data_size = cpu_to_le32(page_size); 1214 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1215 page_size); 1216 1217 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1218 } 1219 1220 static int 1221 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1222 struct iwl_dump_ini_region_data *reg_data, 1223 void *range_ptr, u32 range_len, int idx) 1224 { 1225 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1226 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1227 struct iwl_dram_data *frag; 1228 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1229 1230 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx]; 1231 1232 range->dram_base_addr = cpu_to_le64(frag->physical); 1233 range->range_data_size = cpu_to_le32(frag->size); 1234 1235 memcpy(range->data, frag->block, frag->size); 1236 1237 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1238 } 1239 1240 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt, 1241 struct iwl_dump_ini_region_data *reg_data, 1242 void *range_ptr, u32 range_len, int idx) 1243 { 1244 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1245 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1246 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr); 1247 1248 range->internal_base_addr = cpu_to_le32(addr); 1249 range->range_data_size = reg->internal_buffer.size; 1250 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1251 le32_to_cpu(reg->internal_buffer.size)); 1252 1253 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1254 } 1255 1256 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1257 struct iwl_dump_ini_region_data *reg_data, int idx) 1258 { 1259 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1260 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1261 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1262 int txf_num = cfg->num_txfifo_entries; 1263 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1264 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]); 1265 1266 if (!idx) { 1267 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) { 1268 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n", 1269 le32_to_cpu(reg->fifos.offset)); 1270 return false; 1271 } 1272 1273 iter->internal_txf = 0; 1274 iter->fifo_size = 0; 1275 iter->fifo = -1; 1276 if (le32_to_cpu(reg->fifos.offset)) 1277 iter->lmac = 1; 1278 else 1279 iter->lmac = 0; 1280 } 1281 1282 if (!iter->internal_txf) { 1283 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1284 iter->fifo_size = 1285 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1286 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1287 return true; 1288 } 1289 iter->fifo--; 1290 } 1291 1292 iter->internal_txf = 1; 1293 1294 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1295 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1296 return false; 1297 1298 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1299 iter->fifo_size = 1300 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1301 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1302 return true; 1303 } 1304 1305 return false; 1306 } 1307 1308 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1309 struct iwl_dump_ini_region_data *reg_data, 1310 void *range_ptr, u32 range_len, int idx) 1311 { 1312 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1313 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1314 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1315 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1316 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1317 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1318 u32 registers_size = registers_num * sizeof(*reg_dump); 1319 __le32 *data; 1320 int i; 1321 1322 if (!iwl_ini_txf_iter(fwrt, reg_data, idx)) 1323 return -EIO; 1324 1325 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1326 return -EBUSY; 1327 1328 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1329 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1330 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1331 1332 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1333 1334 /* 1335 * read txf registers. for each register, write to the dump the 1336 * register address and its value 1337 */ 1338 for (i = 0; i < registers_num; i++) { 1339 addr = le32_to_cpu(reg->addrs[i]) + offs; 1340 1341 reg_dump->addr = cpu_to_le32(addr); 1342 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1343 addr)); 1344 1345 reg_dump++; 1346 } 1347 1348 if (reg->fifos.hdr_only) { 1349 range->range_data_size = cpu_to_le32(registers_size); 1350 goto out; 1351 } 1352 1353 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1354 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1355 TXF_WR_PTR + offs); 1356 1357 /* Dummy-read to advance the read pointer to the head */ 1358 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1359 1360 /* Read FIFO */ 1361 addr = TXF_READ_MODIFY_DATA + offs; 1362 data = (void *)reg_dump; 1363 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1364 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1365 1366 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1367 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1368 reg_dump, iter->fifo_size); 1369 1370 out: 1371 iwl_trans_release_nic_access(fwrt->trans); 1372 1373 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1374 } 1375 1376 struct iwl_ini_rxf_data { 1377 u32 fifo_num; 1378 u32 size; 1379 u32 offset; 1380 }; 1381 1382 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1383 struct iwl_dump_ini_region_data *reg_data, 1384 struct iwl_ini_rxf_data *data) 1385 { 1386 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1387 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]); 1388 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]); 1389 u8 fifo_idx; 1390 1391 if (!data) 1392 return; 1393 1394 /* make sure only one bit is set in only one fid */ 1395 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1, 1396 "fid1=%x, fid2=%x\n", fid1, fid2)) 1397 return; 1398 1399 memset(data, 0, sizeof(*data)); 1400 1401 if (fid1) { 1402 fifo_idx = ffs(fid1) - 1; 1403 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n", 1404 fifo_idx)) 1405 return; 1406 1407 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1408 data->fifo_num = fifo_idx; 1409 } else { 1410 u8 max_idx; 1411 1412 fifo_idx = ffs(fid2) - 1; 1413 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP, 1414 SHARED_MEM_CFG_CMD, 0) <= 3) 1415 max_idx = 0; 1416 else 1417 max_idx = 1; 1418 1419 if (WARN_ONCE(fifo_idx > max_idx, 1420 "invalid umac fifo idx %d", fifo_idx)) 1421 return; 1422 1423 /* use bit 31 to distinguish between umac and lmac rxf while 1424 * parsing the dump 1425 */ 1426 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1427 1428 switch (fifo_idx) { 1429 case 0: 1430 data->size = fwrt->smem_cfg.rxfifo2_size; 1431 data->offset = iwl_umac_prph(fwrt->trans, 1432 RXF_DIFF_FROM_PREV); 1433 break; 1434 case 1: 1435 data->size = fwrt->smem_cfg.rxfifo2_control_size; 1436 data->offset = iwl_umac_prph(fwrt->trans, 1437 RXF2C_DIFF_FROM_PREV); 1438 break; 1439 } 1440 } 1441 } 1442 1443 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1444 struct iwl_dump_ini_region_data *reg_data, 1445 void *range_ptr, u32 range_len, int idx) 1446 { 1447 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1448 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1449 struct iwl_ini_rxf_data rxf_data; 1450 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1451 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1452 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1453 u32 registers_size = registers_num * sizeof(*reg_dump); 1454 __le32 *data; 1455 int i; 1456 1457 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data); 1458 if (!rxf_data.size) 1459 return -EIO; 1460 1461 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1462 return -EBUSY; 1463 1464 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1465 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1466 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1467 1468 /* 1469 * read rxf registers. for each register, write to the dump the 1470 * register address and its value 1471 */ 1472 for (i = 0; i < registers_num; i++) { 1473 addr = le32_to_cpu(reg->addrs[i]) + offs; 1474 1475 reg_dump->addr = cpu_to_le32(addr); 1476 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1477 addr)); 1478 1479 reg_dump++; 1480 } 1481 1482 if (reg->fifos.hdr_only) { 1483 range->range_data_size = cpu_to_le32(registers_size); 1484 goto out; 1485 } 1486 1487 offs = rxf_data.offset; 1488 1489 /* Lock fence */ 1490 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1491 /* Set fence pointer to the same place like WR pointer */ 1492 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1493 /* Set fence offset */ 1494 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1495 0x0); 1496 1497 /* Read FIFO */ 1498 addr = RXF_FIFO_RD_FENCE_INC + offs; 1499 data = (void *)reg_dump; 1500 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1501 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1502 1503 out: 1504 iwl_trans_release_nic_access(fwrt->trans); 1505 1506 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1507 } 1508 1509 static int 1510 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt, 1511 struct iwl_dump_ini_region_data *reg_data, 1512 void *range_ptr, u32 range_len, int idx) 1513 { 1514 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1515 struct iwl_fw_ini_region_err_table *err_table = ®->err_table; 1516 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1517 u32 addr = le32_to_cpu(err_table->base_addr) + 1518 le32_to_cpu(err_table->offset); 1519 1520 range->internal_base_addr = cpu_to_le32(addr); 1521 range->range_data_size = err_table->size; 1522 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1523 le32_to_cpu(err_table->size)); 1524 1525 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1526 } 1527 1528 static int 1529 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt, 1530 struct iwl_dump_ini_region_data *reg_data, 1531 void *range_ptr, u32 range_len, int idx) 1532 { 1533 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1534 struct iwl_fw_ini_region_special_device_memory *special_mem = 1535 ®->special_mem; 1536 1537 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1538 u32 addr = le32_to_cpu(special_mem->base_addr) + 1539 le32_to_cpu(special_mem->offset); 1540 1541 range->internal_base_addr = cpu_to_le32(addr); 1542 range->range_data_size = special_mem->size; 1543 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1544 le32_to_cpu(special_mem->size)); 1545 1546 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1547 } 1548 1549 static int 1550 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt, 1551 struct iwl_dump_ini_region_data *reg_data, 1552 void *range_ptr, u32 range_len, int idx) 1553 { 1554 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1555 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1556 __le32 *val = range->data; 1557 u32 prph_data; 1558 int i; 1559 1560 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1561 return -EBUSY; 1562 1563 range->range_data_size = reg->dev_addr.size; 1564 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) { 1565 prph_data = iwl_read_prph_no_grab(fwrt->trans, (i % 2) ? 1566 DBGI_SRAM_TARGET_ACCESS_RDATA_MSB : 1567 DBGI_SRAM_TARGET_ACCESS_RDATA_LSB); 1568 if (prph_data == 0x5a5a5a5a) { 1569 iwl_trans_release_nic_access(fwrt->trans); 1570 return -EBUSY; 1571 } 1572 *val++ = cpu_to_le32(prph_data); 1573 } 1574 iwl_trans_release_nic_access(fwrt->trans); 1575 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1576 } 1577 1578 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt, 1579 struct iwl_dump_ini_region_data *reg_data, 1580 void *range_ptr, u32 range_len, int idx) 1581 { 1582 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1583 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt; 1584 u32 pkt_len; 1585 1586 if (!pkt) 1587 return -EIO; 1588 1589 pkt_len = iwl_rx_packet_payload_len(pkt); 1590 1591 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr)); 1592 range->range_data_size = cpu_to_le32(pkt_len); 1593 1594 memcpy(range->data, pkt->data, pkt_len); 1595 1596 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1597 } 1598 1599 static int iwl_dump_ini_imr_iter(struct iwl_fw_runtime *fwrt, 1600 struct iwl_dump_ini_region_data *reg_data, 1601 void *range_ptr, u32 range_len, int idx) 1602 { 1603 /* read the IMR memory and DMA it to SRAM */ 1604 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1605 u64 imr_curr_addr = fwrt->trans->dbg.imr_data.imr_curr_addr; 1606 u32 imr_rem_bytes = fwrt->trans->dbg.imr_data.imr2sram_remainbyte; 1607 u32 sram_addr = fwrt->trans->dbg.imr_data.sram_addr; 1608 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1609 u32 size_to_dump = (imr_rem_bytes > sram_size) ? sram_size : imr_rem_bytes; 1610 1611 range->range_data_size = cpu_to_le32(size_to_dump); 1612 if (iwl_trans_write_imr_mem(fwrt->trans, sram_addr, 1613 imr_curr_addr, size_to_dump)) { 1614 IWL_ERR(fwrt, "WRT_DEBUG: IMR Memory transfer failed\n"); 1615 return -1; 1616 } 1617 1618 fwrt->trans->dbg.imr_data.imr_curr_addr = imr_curr_addr + size_to_dump; 1619 fwrt->trans->dbg.imr_data.imr2sram_remainbyte -= size_to_dump; 1620 1621 iwl_trans_read_mem_bytes(fwrt->trans, sram_addr, range->data, 1622 size_to_dump); 1623 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1624 } 1625 1626 static void * 1627 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1628 struct iwl_dump_ini_region_data *reg_data, 1629 void *data, u32 data_len) 1630 { 1631 struct iwl_fw_ini_error_dump *dump = data; 1632 1633 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1634 1635 return dump->data; 1636 } 1637 1638 /** 1639 * mask_apply_and_normalize - applies mask on val and normalize the result 1640 * 1641 * The normalization is based on the first set bit in the mask 1642 * 1643 * @val: value 1644 * @mask: mask to apply and to normalize with 1645 */ 1646 static u32 mask_apply_and_normalize(u32 val, u32 mask) 1647 { 1648 return (val & mask) >> (ffs(mask) - 1); 1649 } 1650 1651 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1652 const struct iwl_fw_mon_reg *reg_info) 1653 { 1654 u32 val, offs; 1655 1656 /* The header addresses of DBGCi is calculate as follows: 1657 * DBGC1 address + (0x100 * i) 1658 */ 1659 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100; 1660 1661 if (!reg_info || !reg_info->addr || !reg_info->mask) 1662 return 0; 1663 1664 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs); 1665 1666 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask)); 1667 } 1668 1669 static void * 1670 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, 1671 struct iwl_dump_ini_region_data *reg_data, 1672 struct iwl_fw_ini_monitor_dump *data, 1673 const struct iwl_fw_mon_regs *addrs) 1674 { 1675 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1676 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1677 1678 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 1679 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1680 return NULL; 1681 } 1682 1683 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id, 1684 &addrs->write_ptr); 1685 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1686 u32 wrt_ptr = le32_to_cpu(data->write_ptr); 1687 1688 data->write_ptr = cpu_to_le32(wrt_ptr >> 2); 1689 } 1690 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id, 1691 &addrs->cycle_cnt); 1692 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id, 1693 &addrs->cur_frag); 1694 1695 iwl_trans_release_nic_access(fwrt->trans); 1696 1697 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1698 1699 return data->data; 1700 } 1701 1702 static void * 1703 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1704 struct iwl_dump_ini_region_data *reg_data, 1705 void *data, u32 data_len) 1706 { 1707 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1708 1709 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump, 1710 &fwrt->trans->cfg->mon_dram_regs); 1711 } 1712 1713 static void * 1714 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1715 struct iwl_dump_ini_region_data *reg_data, 1716 void *data, u32 data_len) 1717 { 1718 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1719 1720 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump, 1721 &fwrt->trans->cfg->mon_smem_regs); 1722 } 1723 1724 static void * 1725 iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime *fwrt, 1726 struct iwl_dump_ini_region_data *reg_data, 1727 void *data, u32 data_len) 1728 { 1729 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1730 1731 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump, 1732 &fwrt->trans->cfg->mon_dbgi_regs); 1733 } 1734 1735 static void * 1736 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt, 1737 struct iwl_dump_ini_region_data *reg_data, 1738 void *data, u32 data_len) 1739 { 1740 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1741 struct iwl_fw_ini_err_table_dump *dump = data; 1742 1743 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1744 dump->version = reg->err_table.version; 1745 1746 return dump->data; 1747 } 1748 1749 static void * 1750 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt, 1751 struct iwl_dump_ini_region_data *reg_data, 1752 void *data, u32 data_len) 1753 { 1754 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1755 struct iwl_fw_ini_special_device_memory *dump = data; 1756 1757 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1758 dump->type = reg->special_mem.type; 1759 dump->version = reg->special_mem.version; 1760 1761 return dump->data; 1762 } 1763 1764 static void * 1765 iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime *fwrt, 1766 struct iwl_dump_ini_region_data *reg_data, 1767 void *data, u32 data_len) 1768 { 1769 struct iwl_fw_ini_error_dump *dump = data; 1770 1771 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1772 1773 return dump->data; 1774 } 1775 1776 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1777 struct iwl_dump_ini_region_data *reg_data) 1778 { 1779 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1780 1781 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1782 } 1783 1784 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1785 struct iwl_dump_ini_region_data *reg_data) 1786 { 1787 if (fwrt->trans->trans_cfg->gen2) { 1788 if (fwrt->trans->init_dram.paging_cnt) 1789 return fwrt->trans->init_dram.paging_cnt - 1; 1790 else 1791 return 0; 1792 } 1793 1794 return fwrt->num_of_paging_blk; 1795 } 1796 1797 static u32 1798 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1799 struct iwl_dump_ini_region_data *reg_data) 1800 { 1801 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1802 struct iwl_fw_mon *fw_mon; 1803 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1804 int i; 1805 1806 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1807 1808 for (i = 0; i < fw_mon->num_frags; i++) { 1809 if (!fw_mon->frags[i].size) 1810 break; 1811 1812 ranges++; 1813 } 1814 1815 return ranges; 1816 } 1817 1818 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1819 struct iwl_dump_ini_region_data *reg_data) 1820 { 1821 u32 num_of_fifos = 0; 1822 1823 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos)) 1824 num_of_fifos++; 1825 1826 return num_of_fifos; 1827 } 1828 1829 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt, 1830 struct iwl_dump_ini_region_data *reg_data) 1831 { 1832 return 1; 1833 } 1834 1835 static u32 iwl_dump_ini_imr_ranges(struct iwl_fw_runtime *fwrt, 1836 struct iwl_dump_ini_region_data *reg_data) 1837 { 1838 /* range is total number of pages need to copied from 1839 *IMR memory to SRAM and later from SRAM to DRAM 1840 */ 1841 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 1842 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 1843 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1844 1845 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 1846 IWL_DEBUG_INFO(fwrt, 1847 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 1848 imr_enable, imr_size, sram_size); 1849 return 0; 1850 } 1851 1852 return((imr_size % sram_size) ? (imr_size / sram_size + 1) : (imr_size / sram_size)); 1853 } 1854 1855 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1856 struct iwl_dump_ini_region_data *reg_data) 1857 { 1858 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1859 u32 size = le32_to_cpu(reg->dev_addr.size); 1860 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1861 1862 if (!size || !ranges) 1863 return 0; 1864 1865 return sizeof(struct iwl_fw_ini_error_dump) + ranges * 1866 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1867 } 1868 1869 static u32 1870 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1871 struct iwl_dump_ini_region_data *reg_data) 1872 { 1873 int i; 1874 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1875 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1876 1877 /* start from 1 to skip CSS section */ 1878 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) { 1879 size += range_header_len; 1880 if (fwrt->trans->trans_cfg->gen2) 1881 size += fwrt->trans->init_dram.paging[i].size; 1882 else 1883 size += fwrt->fw_paging_db[i].fw_paging_size; 1884 } 1885 1886 return size; 1887 } 1888 1889 static u32 1890 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 1891 struct iwl_dump_ini_region_data *reg_data) 1892 { 1893 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1894 struct iwl_fw_mon *fw_mon; 1895 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1896 int i; 1897 1898 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1899 1900 for (i = 0; i < fw_mon->num_frags; i++) { 1901 struct iwl_dram_data *frag = &fw_mon->frags[i]; 1902 1903 if (!frag->size) 1904 break; 1905 1906 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size; 1907 } 1908 1909 if (size) 1910 size += sizeof(struct iwl_fw_ini_monitor_dump); 1911 1912 return size; 1913 } 1914 1915 static u32 1916 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 1917 struct iwl_dump_ini_region_data *reg_data) 1918 { 1919 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1920 u32 size; 1921 1922 size = le32_to_cpu(reg->internal_buffer.size); 1923 if (!size) 1924 return 0; 1925 1926 size += sizeof(struct iwl_fw_ini_monitor_dump) + 1927 sizeof(struct iwl_fw_ini_error_dump_range); 1928 1929 return size; 1930 } 1931 1932 static u32 iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime *fwrt, 1933 struct iwl_dump_ini_region_data *reg_data) 1934 { 1935 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1936 u32 size = le32_to_cpu(reg->dev_addr.size); 1937 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1938 1939 if (!size || !ranges) 1940 return 0; 1941 1942 return sizeof(struct iwl_fw_ini_monitor_dump) + ranges * 1943 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1944 } 1945 1946 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 1947 struct iwl_dump_ini_region_data *reg_data) 1948 { 1949 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1950 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1951 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1952 u32 size = 0; 1953 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 1954 registers_num * 1955 sizeof(struct iwl_fw_ini_error_dump_register); 1956 1957 while (iwl_ini_txf_iter(fwrt, reg_data, size)) { 1958 size += fifo_hdr; 1959 if (!reg->fifos.hdr_only) 1960 size += iter->fifo_size; 1961 } 1962 1963 if (!size) 1964 return 0; 1965 1966 return size + sizeof(struct iwl_fw_ini_error_dump); 1967 } 1968 1969 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 1970 struct iwl_dump_ini_region_data *reg_data) 1971 { 1972 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1973 struct iwl_ini_rxf_data rx_data; 1974 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1975 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 1976 sizeof(struct iwl_fw_ini_error_dump_range) + 1977 registers_num * sizeof(struct iwl_fw_ini_error_dump_register); 1978 1979 if (reg->fifos.hdr_only) 1980 return size; 1981 1982 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data); 1983 size += rx_data.size; 1984 1985 return size; 1986 } 1987 1988 static u32 1989 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt, 1990 struct iwl_dump_ini_region_data *reg_data) 1991 { 1992 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1993 u32 size = le32_to_cpu(reg->err_table.size); 1994 1995 if (size) 1996 size += sizeof(struct iwl_fw_ini_err_table_dump) + 1997 sizeof(struct iwl_fw_ini_error_dump_range); 1998 1999 return size; 2000 } 2001 2002 static u32 2003 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt, 2004 struct iwl_dump_ini_region_data *reg_data) 2005 { 2006 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2007 u32 size = le32_to_cpu(reg->special_mem.size); 2008 2009 if (size) 2010 size += sizeof(struct iwl_fw_ini_special_device_memory) + 2011 sizeof(struct iwl_fw_ini_error_dump_range); 2012 2013 return size; 2014 } 2015 2016 static u32 2017 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt, 2018 struct iwl_dump_ini_region_data *reg_data) 2019 { 2020 u32 size = 0; 2021 2022 if (!reg_data->dump_data->fw_pkt) 2023 return 0; 2024 2025 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt); 2026 if (size) 2027 size += sizeof(struct iwl_fw_ini_error_dump) + 2028 sizeof(struct iwl_fw_ini_error_dump_range); 2029 2030 return size; 2031 } 2032 2033 static u32 2034 iwl_dump_ini_imr_get_size(struct iwl_fw_runtime *fwrt, 2035 struct iwl_dump_ini_region_data *reg_data) 2036 { 2037 u32 size = 0; 2038 u32 ranges = 0; 2039 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 2040 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 2041 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 2042 2043 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 2044 IWL_DEBUG_INFO(fwrt, 2045 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 2046 imr_enable, imr_size, sram_size); 2047 return size; 2048 } 2049 size = imr_size; 2050 ranges = iwl_dump_ini_imr_ranges(fwrt, reg_data); 2051 if (!size && !ranges) { 2052 IWL_ERR(fwrt, "WRT: imr_size :=%d, ranges :=%d\n", size, ranges); 2053 return 0; 2054 } 2055 size += sizeof(struct iwl_fw_ini_error_dump) + 2056 ranges * sizeof(struct iwl_fw_ini_error_dump_range); 2057 return size; 2058 } 2059 2060 /** 2061 * struct iwl_dump_ini_mem_ops - ini memory dump operations 2062 * @get_num_of_ranges: returns the number of memory ranges in the region. 2063 * @get_size: returns the total size of the region. 2064 * @fill_mem_hdr: fills region type specific headers and returns pointer to 2065 * the first range or NULL if failed to fill headers. 2066 * @fill_range: copies a given memory range into the dump. 2067 * Returns the size of the range or negative error value otherwise. 2068 */ 2069 struct iwl_dump_ini_mem_ops { 2070 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 2071 struct iwl_dump_ini_region_data *reg_data); 2072 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 2073 struct iwl_dump_ini_region_data *reg_data); 2074 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 2075 struct iwl_dump_ini_region_data *reg_data, 2076 void *data, u32 data_len); 2077 int (*fill_range)(struct iwl_fw_runtime *fwrt, 2078 struct iwl_dump_ini_region_data *reg_data, 2079 void *range, u32 range_len, int idx); 2080 }; 2081 2082 /** 2083 * iwl_dump_ini_mem 2084 * 2085 * Creates a dump tlv and copy a memory region into it. 2086 * Returns the size of the current dump tlv or 0 if failed 2087 * 2088 * @fwrt: fw runtime struct 2089 * @list: list to add the dump tlv to 2090 * @reg_data: memory region 2091 * @ops: memory dump operations 2092 */ 2093 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 2094 struct iwl_dump_ini_region_data *reg_data, 2095 const struct iwl_dump_ini_mem_ops *ops) 2096 { 2097 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2098 struct iwl_fw_ini_dump_entry *entry; 2099 struct iwl_fw_ini_error_dump_data *tlv; 2100 struct iwl_fw_ini_error_dump_header *header; 2101 u32 type = reg->type; 2102 u32 id = le32_to_cpu(reg->id); 2103 u32 num_of_ranges, i, size; 2104 u8 *range; 2105 u32 free_size; 2106 u64 header_size; 2107 2108 /* 2109 * The higher part of the ID from 2 is irrelevant for 2110 * us, so mask it out. 2111 */ 2112 if (le32_to_cpu(reg->hdr.version) >= 2) 2113 id &= IWL_FW_INI_REGION_V2_MASK; 2114 2115 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: id=%d, type=%d\n", id, 2116 type); 2117 2118 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 2119 !ops->fill_range) { 2120 IWL_DEBUG_FW(fwrt, "WRT: no ops for collecting data\n"); 2121 return 0; 2122 } 2123 2124 size = ops->get_size(fwrt, reg_data); 2125 2126 if (size < sizeof(*header)) { 2127 IWL_DEBUG_FW(fwrt, "WRT: size didn't include space for header\n"); 2128 return 0; 2129 } 2130 2131 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size); 2132 if (!entry) 2133 return 0; 2134 2135 entry->size = sizeof(*tlv) + size; 2136 2137 tlv = (void *)entry->data; 2138 tlv->type = reg->type; 2139 tlv->sub_type = reg->sub_type; 2140 tlv->sub_type_ver = reg->sub_type_ver; 2141 tlv->reserved = reg->reserved; 2142 tlv->len = cpu_to_le32(size); 2143 2144 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data); 2145 2146 header = (void *)tlv->data; 2147 header->region_id = cpu_to_le32(id); 2148 header->num_of_ranges = cpu_to_le32(num_of_ranges); 2149 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME); 2150 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME); 2151 2152 free_size = size; 2153 range = ops->fill_mem_hdr(fwrt, reg_data, header, free_size); 2154 if (!range) { 2155 IWL_ERR(fwrt, 2156 "WRT: Failed to fill region header: id=%d, type=%d\n", 2157 id, type); 2158 goto out_err; 2159 } 2160 2161 header_size = range - (u8 *)header; 2162 2163 if (WARN(header_size > free_size, 2164 "header size %llu > free_size %d", 2165 header_size, free_size)) { 2166 IWL_ERR(fwrt, 2167 "WRT: fill_mem_hdr used more than given free_size\n"); 2168 goto out_err; 2169 } 2170 2171 free_size -= header_size; 2172 2173 for (i = 0; i < num_of_ranges; i++) { 2174 int range_size = ops->fill_range(fwrt, reg_data, range, 2175 free_size, i); 2176 2177 if (range_size < 0) { 2178 IWL_ERR(fwrt, 2179 "WRT: Failed to dump region: id=%d, type=%d\n", 2180 id, type); 2181 goto out_err; 2182 } 2183 2184 if (WARN(range_size > free_size, "range_size %d > free_size %d", 2185 range_size, free_size)) { 2186 IWL_ERR(fwrt, 2187 "WRT: fill_raged used more than given free_size\n"); 2188 goto out_err; 2189 } 2190 2191 free_size -= range_size; 2192 range = range + range_size; 2193 } 2194 2195 list_add_tail(&entry->list, list); 2196 2197 return entry->size; 2198 2199 out_err: 2200 vfree(entry); 2201 2202 return 0; 2203 } 2204 2205 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 2206 struct iwl_fw_ini_trigger_tlv *trigger, 2207 struct list_head *list) 2208 { 2209 struct iwl_fw_ini_dump_entry *entry; 2210 struct iwl_fw_error_dump_data *tlv; 2211 struct iwl_fw_ini_dump_info *dump; 2212 struct iwl_dbg_tlv_node *node; 2213 struct iwl_fw_ini_dump_cfg_name *cfg_name; 2214 u32 size = sizeof(*tlv) + sizeof(*dump); 2215 u32 num_of_cfg_names = 0; 2216 u32 hw_type; 2217 2218 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2219 size += sizeof(*cfg_name); 2220 num_of_cfg_names++; 2221 } 2222 2223 entry = vzalloc(sizeof(*entry) + size); 2224 if (!entry) 2225 return 0; 2226 2227 entry->size = size; 2228 2229 tlv = (void *)entry->data; 2230 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 2231 tlv->len = cpu_to_le32(size - sizeof(*tlv)); 2232 2233 dump = (void *)tlv->data; 2234 2235 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 2236 dump->time_point = trigger->time_point; 2237 dump->trigger_reason = trigger->trigger_reason; 2238 dump->external_cfg_state = 2239 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 2240 2241 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 2242 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 2243 2244 dump->hw_step = cpu_to_le32(fwrt->trans->hw_rev_step); 2245 2246 /* 2247 * Several HWs all have type == 0x42, so we'll override this value 2248 * according to the detected HW 2249 */ 2250 hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev); 2251 if (hw_type == IWL_AX210_HW_TYPE) { 2252 u32 prph_val = iwl_read_umac_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR); 2253 u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT); 2254 u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT); 2255 u32 masked_bits = is_jacket | (is_cdb << 1); 2256 2257 /* 2258 * The HW type depends on certain bits in this case, so add 2259 * these bits to the HW type. We won't have collisions since we 2260 * add these bits after the highest possible bit in the mask. 2261 */ 2262 hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT; 2263 } 2264 dump->hw_type = cpu_to_le32(hw_type); 2265 2266 dump->rf_id_flavor = 2267 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id)); 2268 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id)); 2269 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id)); 2270 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id)); 2271 2272 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 2273 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 2274 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 2275 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 2276 2277 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest); 2278 dump->regions_mask = trigger->regions_mask & 2279 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk); 2280 2281 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 2282 memcpy(dump->build_tag, fwrt->fw->human_readable, 2283 sizeof(dump->build_tag)); 2284 2285 cfg_name = dump->cfg_names; 2286 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names); 2287 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2288 struct iwl_fw_ini_debug_info_tlv *debug_info = 2289 (void *)node->tlv.data; 2290 2291 cfg_name->image_type = debug_info->image_type; 2292 cfg_name->cfg_name_len = 2293 cpu_to_le32(IWL_FW_INI_MAX_CFG_NAME); 2294 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name, 2295 sizeof(cfg_name->cfg_name)); 2296 cfg_name++; 2297 } 2298 2299 /* add dump info TLV to the beginning of the list since it needs to be 2300 * the first TLV in the dump 2301 */ 2302 list_add(&entry->list, list); 2303 2304 return entry->size; 2305 } 2306 2307 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 2308 [IWL_FW_INI_REGION_INVALID] = {}, 2309 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 2310 .get_num_of_ranges = iwl_dump_ini_single_range, 2311 .get_size = iwl_dump_ini_mon_smem_get_size, 2312 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 2313 .fill_range = iwl_dump_ini_mon_smem_iter, 2314 }, 2315 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 2316 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 2317 .get_size = iwl_dump_ini_mon_dram_get_size, 2318 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 2319 .fill_range = iwl_dump_ini_mon_dram_iter, 2320 }, 2321 [IWL_FW_INI_REGION_TXF] = { 2322 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 2323 .get_size = iwl_dump_ini_txf_get_size, 2324 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2325 .fill_range = iwl_dump_ini_txf_iter, 2326 }, 2327 [IWL_FW_INI_REGION_RXF] = { 2328 .get_num_of_ranges = iwl_dump_ini_single_range, 2329 .get_size = iwl_dump_ini_rxf_get_size, 2330 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2331 .fill_range = iwl_dump_ini_rxf_iter, 2332 }, 2333 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 2334 .get_num_of_ranges = iwl_dump_ini_single_range, 2335 .get_size = iwl_dump_ini_err_table_get_size, 2336 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2337 .fill_range = iwl_dump_ini_err_table_iter, 2338 }, 2339 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 2340 .get_num_of_ranges = iwl_dump_ini_single_range, 2341 .get_size = iwl_dump_ini_err_table_get_size, 2342 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2343 .fill_range = iwl_dump_ini_err_table_iter, 2344 }, 2345 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = { 2346 .get_num_of_ranges = iwl_dump_ini_single_range, 2347 .get_size = iwl_dump_ini_fw_pkt_get_size, 2348 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2349 .fill_range = iwl_dump_ini_fw_pkt_iter, 2350 }, 2351 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 2352 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2353 .get_size = iwl_dump_ini_mem_get_size, 2354 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2355 .fill_range = iwl_dump_ini_dev_mem_iter, 2356 }, 2357 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 2358 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2359 .get_size = iwl_dump_ini_mem_get_size, 2360 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2361 .fill_range = iwl_dump_ini_prph_mac_iter, 2362 }, 2363 [IWL_FW_INI_REGION_PERIPHERY_PHY] = { 2364 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2365 .get_size = iwl_dump_ini_mem_get_size, 2366 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2367 .fill_range = iwl_dump_ini_prph_phy_iter, 2368 }, 2369 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 2370 [IWL_FW_INI_REGION_PAGING] = { 2371 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2372 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 2373 .get_size = iwl_dump_ini_paging_get_size, 2374 .fill_range = iwl_dump_ini_paging_iter, 2375 }, 2376 [IWL_FW_INI_REGION_CSR] = { 2377 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2378 .get_size = iwl_dump_ini_mem_get_size, 2379 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2380 .fill_range = iwl_dump_ini_csr_iter, 2381 }, 2382 [IWL_FW_INI_REGION_DRAM_IMR] = { 2383 .get_num_of_ranges = iwl_dump_ini_imr_ranges, 2384 .get_size = iwl_dump_ini_imr_get_size, 2385 .fill_mem_hdr = iwl_dump_ini_imr_fill_header, 2386 .fill_range = iwl_dump_ini_imr_iter, 2387 }, 2388 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = { 2389 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2390 .get_size = iwl_dump_ini_mem_get_size, 2391 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2392 .fill_range = iwl_dump_ini_config_iter, 2393 }, 2394 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = { 2395 .get_num_of_ranges = iwl_dump_ini_single_range, 2396 .get_size = iwl_dump_ini_special_mem_get_size, 2397 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header, 2398 .fill_range = iwl_dump_ini_special_mem_iter, 2399 }, 2400 [IWL_FW_INI_REGION_DBGI_SRAM] = { 2401 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2402 .get_size = iwl_dump_ini_mon_dbgi_get_size, 2403 .fill_mem_hdr = iwl_dump_ini_mon_dbgi_fill_header, 2404 .fill_range = iwl_dump_ini_dbgi_sram_iter, 2405 }, 2406 }; 2407 2408 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 2409 struct iwl_fwrt_dump_data *dump_data, 2410 struct list_head *list) 2411 { 2412 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2413 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point); 2414 struct iwl_dump_ini_region_data reg_data = { 2415 .dump_data = dump_data, 2416 }; 2417 int i; 2418 u32 size = 0; 2419 u64 regions_mask = le64_to_cpu(trigger->regions_mask) & 2420 ~(fwrt->trans->dbg.unsupported_region_msk); 2421 2422 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask)); 2423 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) < 2424 ARRAY_SIZE(fwrt->trans->dbg.active_regions)); 2425 2426 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) { 2427 u32 reg_type; 2428 struct iwl_fw_ini_region_tlv *reg; 2429 2430 if (!(BIT_ULL(i) & regions_mask)) 2431 continue; 2432 2433 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2434 if (!reg_data.reg_tlv) { 2435 IWL_WARN(fwrt, 2436 "WRT: Unassigned region id %d, skipping\n", i); 2437 continue; 2438 } 2439 2440 reg = (void *)reg_data.reg_tlv->data; 2441 reg_type = reg->type; 2442 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 2443 continue; 2444 2445 if (reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY && 2446 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) { 2447 IWL_WARN(fwrt, 2448 "WRT: trying to collect phy prph at time point: %d, skipping\n", 2449 tp_id); 2450 continue; 2451 } 2452 2453 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2454 &iwl_dump_ini_region_ops[reg_type]); 2455 } 2456 2457 if (size) 2458 size += iwl_dump_ini_info(fwrt, trigger, list); 2459 2460 return size; 2461 } 2462 2463 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt, 2464 struct iwl_fw_ini_trigger_tlv *trig) 2465 { 2466 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2467 u32 usec = le32_to_cpu(trig->ignore_consec); 2468 2469 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 2470 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 2471 tp_id >= IWL_FW_INI_TIME_POINT_NUM || 2472 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec)) 2473 return false; 2474 2475 return true; 2476 } 2477 2478 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 2479 struct iwl_fwrt_dump_data *dump_data, 2480 struct list_head *list) 2481 { 2482 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2483 struct iwl_fw_ini_dump_entry *entry; 2484 struct iwl_fw_ini_dump_file_hdr *hdr; 2485 u32 size; 2486 2487 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) || 2488 !le64_to_cpu(trigger->regions_mask)) 2489 return 0; 2490 2491 entry = vzalloc(sizeof(*entry) + sizeof(*hdr)); 2492 if (!entry) 2493 return 0; 2494 2495 entry->size = sizeof(*hdr); 2496 2497 size = iwl_dump_ini_trigger(fwrt, dump_data, list); 2498 if (!size) { 2499 vfree(entry); 2500 return 0; 2501 } 2502 2503 hdr = (void *)entry->data; 2504 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 2505 hdr->file_len = cpu_to_le32(size + entry->size); 2506 2507 list_add(&entry->list, list); 2508 2509 return le32_to_cpu(hdr->file_len); 2510 } 2511 2512 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt, 2513 const struct iwl_fw_dump_desc *desc) 2514 { 2515 if (desc && desc != &iwl_dump_desc_assert) 2516 kfree(desc); 2517 2518 fwrt->dump.lmac_err_id[0] = 0; 2519 if (fwrt->smem_cfg.num_lmacs > 1) 2520 fwrt->dump.lmac_err_id[1] = 0; 2521 fwrt->dump.umac_err_id = 0; 2522 } 2523 2524 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt, 2525 struct iwl_fwrt_dump_data *dump_data) 2526 { 2527 struct iwl_fw_dump_ptrs fw_error_dump = {}; 2528 struct iwl_fw_error_dump_file *dump_file; 2529 struct scatterlist *sg_dump_data; 2530 u32 file_len; 2531 u32 dump_mask = fwrt->fw->dbg.dump_mask; 2532 2533 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data); 2534 if (!dump_file) 2535 return; 2536 2537 if (dump_data->monitor_only) 2538 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR); 2539 2540 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask, 2541 fwrt->sanitize_ops, 2542 fwrt->sanitize_ctx); 2543 file_len = le32_to_cpu(dump_file->file_len); 2544 fw_error_dump.fwrt_len = file_len; 2545 2546 if (fw_error_dump.trans_ptr) { 2547 file_len += fw_error_dump.trans_ptr->len; 2548 dump_file->file_len = cpu_to_le32(file_len); 2549 } 2550 2551 sg_dump_data = alloc_sgtable(file_len); 2552 if (sg_dump_data) { 2553 sg_pcopy_from_buffer(sg_dump_data, 2554 sg_nents(sg_dump_data), 2555 fw_error_dump.fwrt_ptr, 2556 fw_error_dump.fwrt_len, 0); 2557 if (fw_error_dump.trans_ptr) 2558 sg_pcopy_from_buffer(sg_dump_data, 2559 sg_nents(sg_dump_data), 2560 fw_error_dump.trans_ptr->data, 2561 fw_error_dump.trans_ptr->len, 2562 fw_error_dump.fwrt_len); 2563 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2564 GFP_KERNEL); 2565 } 2566 vfree(fw_error_dump.fwrt_ptr); 2567 vfree(fw_error_dump.trans_ptr); 2568 } 2569 2570 static void iwl_dump_ini_list_free(struct list_head *list) 2571 { 2572 while (!list_empty(list)) { 2573 struct iwl_fw_ini_dump_entry *entry = 2574 list_entry(list->next, typeof(*entry), list); 2575 2576 list_del(&entry->list); 2577 vfree(entry); 2578 } 2579 } 2580 2581 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data) 2582 { 2583 dump_data->trig = NULL; 2584 kfree(dump_data->fw_pkt); 2585 dump_data->fw_pkt = NULL; 2586 } 2587 2588 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, 2589 struct iwl_fwrt_dump_data *dump_data) 2590 { 2591 struct list_head dump_list = LIST_HEAD_INIT(dump_list); 2592 struct scatterlist *sg_dump_data; 2593 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list); 2594 2595 if (!file_len) 2596 return; 2597 2598 sg_dump_data = alloc_sgtable(file_len); 2599 if (sg_dump_data) { 2600 struct iwl_fw_ini_dump_entry *entry; 2601 int sg_entries = sg_nents(sg_dump_data); 2602 u32 offs = 0; 2603 2604 list_for_each_entry(entry, &dump_list, list) { 2605 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2606 entry->data, entry->size, offs); 2607 offs += entry->size; 2608 } 2609 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2610 GFP_KERNEL); 2611 } 2612 iwl_dump_ini_list_free(&dump_list); 2613 } 2614 2615 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2616 .trig_desc = { 2617 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2618 }, 2619 }; 2620 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2621 2622 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2623 const struct iwl_fw_dump_desc *desc, 2624 bool monitor_only, 2625 unsigned int delay) 2626 { 2627 struct iwl_fwrt_wk_data *wk_data; 2628 unsigned long idx; 2629 2630 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2631 iwl_fw_free_dump_desc(fwrt, desc); 2632 return 0; 2633 } 2634 2635 /* 2636 * Check there is an available worker. 2637 * ffz return value is undefined if no zero exists, 2638 * so check against ~0UL first. 2639 */ 2640 if (fwrt->dump.active_wks == ~0UL) 2641 return -EBUSY; 2642 2643 idx = ffz(fwrt->dump.active_wks); 2644 2645 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2646 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2647 return -EBUSY; 2648 2649 wk_data = &fwrt->dump.wks[idx]; 2650 2651 if (WARN_ON(wk_data->dump_data.desc)) 2652 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc); 2653 2654 wk_data->dump_data.desc = desc; 2655 wk_data->dump_data.monitor_only = monitor_only; 2656 2657 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2658 le32_to_cpu(desc->trig_desc.type)); 2659 2660 schedule_delayed_work(&wk_data->wk, usecs_to_jiffies(delay)); 2661 2662 return 0; 2663 } 2664 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2665 2666 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2667 enum iwl_fw_dbg_trigger trig_type) 2668 { 2669 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2670 return -EIO; 2671 2672 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2673 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT && 2674 trig_type != FW_DBG_TRIGGER_DRIVER) 2675 return -EIO; 2676 2677 iwl_dbg_tlv_time_point(fwrt, 2678 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT, 2679 NULL); 2680 } else { 2681 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2682 int ret; 2683 2684 iwl_dump_error_desc = 2685 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2686 2687 if (!iwl_dump_error_desc) 2688 return -ENOMEM; 2689 2690 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2691 iwl_dump_error_desc->len = 0; 2692 2693 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, 2694 false, 0); 2695 if (ret) { 2696 kfree(iwl_dump_error_desc); 2697 return ret; 2698 } 2699 } 2700 2701 iwl_trans_sync_nmi(fwrt->trans); 2702 2703 return 0; 2704 } 2705 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2706 2707 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2708 enum iwl_fw_dbg_trigger trig, 2709 const char *str, size_t len, 2710 struct iwl_fw_dbg_trigger_tlv *trigger) 2711 { 2712 struct iwl_fw_dump_desc *desc; 2713 unsigned int delay = 0; 2714 bool monitor_only = false; 2715 2716 if (trigger) { 2717 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2718 2719 if (!le16_to_cpu(trigger->occurrences)) 2720 return 0; 2721 2722 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2723 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2724 trig); 2725 iwl_force_nmi(fwrt->trans); 2726 return 0; 2727 } 2728 2729 trigger->occurrences = cpu_to_le16(occurrences); 2730 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2731 2732 /* convert msec to usec */ 2733 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2734 } 2735 2736 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 2737 if (!desc) 2738 return -ENOMEM; 2739 2740 2741 desc->len = len; 2742 desc->trig_desc.type = cpu_to_le32(trig); 2743 memcpy(desc->trig_desc.data, str, len); 2744 2745 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2746 } 2747 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2748 2749 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2750 struct iwl_fw_dbg_trigger_tlv *trigger, 2751 const char *fmt, ...) 2752 { 2753 int ret, len = 0; 2754 char buf[64]; 2755 2756 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2757 return 0; 2758 2759 if (fmt) { 2760 va_list ap; 2761 2762 buf[sizeof(buf) - 1] = '\0'; 2763 2764 va_start(ap, fmt); 2765 vsnprintf(buf, sizeof(buf), fmt, ap); 2766 va_end(ap); 2767 2768 /* check for truncation */ 2769 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2770 buf[sizeof(buf) - 1] = '\0'; 2771 2772 len = strlen(buf) + 1; 2773 } 2774 2775 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2776 trigger); 2777 2778 if (ret) 2779 return ret; 2780 2781 return 0; 2782 } 2783 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2784 2785 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2786 { 2787 u8 *ptr; 2788 int ret; 2789 int i; 2790 2791 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 2792 "Invalid configuration %d\n", conf_id)) 2793 return -EINVAL; 2794 2795 /* EARLY START - firmware's configuration is hard coded */ 2796 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 2797 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 2798 conf_id == FW_DBG_START_FROM_ALIVE) 2799 return 0; 2800 2801 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 2802 return -EINVAL; 2803 2804 if (fwrt->dump.conf != FW_DBG_INVALID) 2805 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n", 2806 fwrt->dump.conf); 2807 2808 /* Send all HCMDs for configuring the FW debug */ 2809 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 2810 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 2811 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 2812 struct iwl_host_cmd hcmd = { 2813 .id = cmd->id, 2814 .len = { le16_to_cpu(cmd->len), }, 2815 .data = { cmd->data, }, 2816 }; 2817 2818 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 2819 if (ret) 2820 return ret; 2821 2822 ptr += sizeof(*cmd); 2823 ptr += le16_to_cpu(cmd->len); 2824 } 2825 2826 fwrt->dump.conf = conf_id; 2827 2828 return 0; 2829 } 2830 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 2831 2832 /* this function assumes dump_start was called beforehand and dump_end will be 2833 * called afterwards 2834 */ 2835 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 2836 { 2837 struct iwl_fw_dbg_params params = {0}; 2838 struct iwl_fwrt_dump_data *dump_data = 2839 &fwrt->dump.wks[wk_idx].dump_data; 2840 2841 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 2842 return; 2843 2844 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) { 2845 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n"); 2846 goto out; 2847 } 2848 2849 /* there's no point in fw dump if the bus is dead */ 2850 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 2851 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 2852 goto out; 2853 } 2854 2855 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true); 2856 2857 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 2858 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2859 iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 2860 else 2861 iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 2862 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 2863 2864 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 2865 2866 if (fwrt->trans->dbg.last_tp_resetfw == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) 2867 iwl_force_nmi(fwrt->trans); 2868 2869 out: 2870 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2871 iwl_fw_error_dump_data_free(dump_data); 2872 } else { 2873 iwl_fw_free_dump_desc(fwrt, dump_data->desc); 2874 dump_data->desc = NULL; 2875 } 2876 2877 clear_bit(wk_idx, &fwrt->dump.active_wks); 2878 } 2879 2880 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 2881 struct iwl_fwrt_dump_data *dump_data, 2882 bool sync) 2883 { 2884 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig; 2885 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2886 u32 occur, delay; 2887 unsigned long idx; 2888 2889 if (!iwl_fw_ini_trigger_on(fwrt, trig)) { 2890 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 2891 tp_id); 2892 return -EINVAL; 2893 } 2894 2895 delay = le32_to_cpu(trig->dump_delay); 2896 occur = le32_to_cpu(trig->occurrences); 2897 if (!occur) 2898 return 0; 2899 2900 trig->occurrences = cpu_to_le32(--occur); 2901 2902 /* Check there is an available worker. 2903 * ffz return value is undefined if no zero exists, 2904 * so check against ~0UL first. 2905 */ 2906 if (fwrt->dump.active_wks == ~0UL) 2907 return -EBUSY; 2908 2909 idx = ffz(fwrt->dump.active_wks); 2910 2911 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2912 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2913 return -EBUSY; 2914 2915 fwrt->dump.wks[idx].dump_data = *dump_data; 2916 2917 if (sync) 2918 delay = 0; 2919 2920 IWL_WARN(fwrt, 2921 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n", 2922 tp_id, (u32)(delay / USEC_PER_MSEC)); 2923 2924 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay)); 2925 2926 if (sync) 2927 iwl_fw_dbg_collect_sync(fwrt, idx); 2928 2929 return 0; 2930 } 2931 2932 void iwl_fw_error_dump_wk(struct work_struct *work) 2933 { 2934 struct iwl_fwrt_wk_data *wks = 2935 container_of(work, typeof(*wks), wk.work); 2936 struct iwl_fw_runtime *fwrt = 2937 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]); 2938 2939 /* assumes the op mode mutex is locked in dump_start since 2940 * iwl_fw_dbg_collect_sync can't run in parallel 2941 */ 2942 if (fwrt->ops && fwrt->ops->dump_start && 2943 fwrt->ops->dump_start(fwrt->ops_ctx)) 2944 return; 2945 2946 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 2947 2948 if (fwrt->ops && fwrt->ops->dump_end) 2949 fwrt->ops->dump_end(fwrt->ops_ctx); 2950 } 2951 2952 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 2953 { 2954 const struct iwl_cfg *cfg = fwrt->trans->cfg; 2955 2956 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 2957 return; 2958 2959 if (!fwrt->dump.d3_debug_data) { 2960 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 2961 GFP_KERNEL); 2962 if (!fwrt->dump.d3_debug_data) { 2963 IWL_ERR(fwrt, 2964 "failed to allocate memory for D3 debug data\n"); 2965 return; 2966 } 2967 } 2968 2969 /* if the buffer holds previous debug data it is overwritten */ 2970 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 2971 fwrt->dump.d3_debug_data, 2972 cfg->d3_debug_data_length); 2973 2974 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 2975 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 2976 cfg->d3_debug_data_base_addr, 2977 fwrt->dump.d3_debug_data, 2978 cfg->d3_debug_data_length); 2979 } 2980 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 2981 2982 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 2983 { 2984 int i; 2985 2986 iwl_dbg_tlv_del_timers(fwrt->trans); 2987 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 2988 iwl_fw_dbg_collect_sync(fwrt, i); 2989 2990 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 2991 } 2992 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 2993 2994 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 2995 { 2996 struct iwl_dbg_suspend_resume_cmd cmd = { 2997 .operation = suspend ? 2998 cpu_to_le32(DBGC_SUSPEND_CMD) : 2999 cpu_to_le32(DBGC_RESUME_CMD), 3000 }; 3001 struct iwl_host_cmd hcmd = { 3002 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 3003 .data[0] = &cmd, 3004 .len[0] = sizeof(cmd), 3005 }; 3006 3007 return iwl_trans_send_cmd(trans, &hcmd); 3008 } 3009 3010 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 3011 struct iwl_fw_dbg_params *params) 3012 { 3013 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3014 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3015 return; 3016 } 3017 3018 if (params) { 3019 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 3020 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 3021 } 3022 3023 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 3024 /* wait for the DBGC to finish writing the internal buffer to DRAM to 3025 * avoid halting the HW while writing 3026 */ 3027 usleep_range(700, 1000); 3028 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 3029 } 3030 3031 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 3032 struct iwl_fw_dbg_params *params) 3033 { 3034 if (!params) 3035 return -EIO; 3036 3037 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3038 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3039 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3040 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3041 } else { 3042 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 3043 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 3044 } 3045 3046 return 0; 3047 } 3048 3049 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 3050 struct iwl_fw_dbg_params *params, 3051 bool stop) 3052 { 3053 int ret __maybe_unused = 0; 3054 3055 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 3056 return; 3057 3058 if (fw_has_capa(&fwrt->fw->ucode_capa, 3059 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) 3060 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 3061 else if (stop) 3062 iwl_fw_dbg_stop_recording(fwrt->trans, params); 3063 else 3064 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 3065 #ifdef CONFIG_IWLWIFI_DEBUGFS 3066 if (!ret) { 3067 if (stop) 3068 fwrt->trans->dbg.rec_on = false; 3069 else 3070 iwl_fw_set_dbg_rec_on(fwrt); 3071 } 3072 #endif 3073 } 3074 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 3075