1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #include <linux/devcoredump.h> 65 #include "iwl-drv.h" 66 #include "runtime.h" 67 #include "dbg.h" 68 #include "debugfs.h" 69 #include "iwl-io.h" 70 #include "iwl-prph.h" 71 #include "iwl-csr.h" 72 73 /** 74 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 75 * 76 * @fwrt_ptr: pointer to the buffer coming from fwrt 77 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 78 * transport's data. 79 * @trans_len: length of the valid data in trans_ptr 80 * @fwrt_len: length of the valid data in fwrt_ptr 81 */ 82 struct iwl_fw_dump_ptrs { 83 struct iwl_trans_dump_data *trans_ptr; 84 void *fwrt_ptr; 85 u32 fwrt_len; 86 }; 87 88 #define RADIO_REG_MAX_READ 0x2ad 89 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 90 struct iwl_fw_error_dump_data **dump_data) 91 { 92 u8 *pos = (void *)(*dump_data)->data; 93 unsigned long flags; 94 int i; 95 96 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 97 98 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 99 return; 100 101 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 102 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 103 104 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 105 u32 rd_cmd = RADIO_RSP_RD_CMD; 106 107 rd_cmd |= i << RADIO_RSP_ADDR_POS; 108 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 109 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 110 111 pos++; 112 } 113 114 *dump_data = iwl_fw_error_next_data(*dump_data); 115 116 iwl_trans_release_nic_access(fwrt->trans, &flags); 117 } 118 119 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 120 struct iwl_fw_error_dump_data **dump_data, 121 int size, u32 offset, int fifo_num) 122 { 123 struct iwl_fw_error_dump_fifo *fifo_hdr; 124 u32 *fifo_data; 125 u32 fifo_len; 126 int i; 127 128 fifo_hdr = (void *)(*dump_data)->data; 129 fifo_data = (void *)fifo_hdr->data; 130 fifo_len = size; 131 132 /* No need to try to read the data if the length is 0 */ 133 if (fifo_len == 0) 134 return; 135 136 /* Add a TLV for the RXF */ 137 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 138 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 139 140 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 141 fifo_hdr->available_bytes = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 RXF_RD_D_SPACE + offset)); 144 fifo_hdr->wr_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 RXF_RD_WR_PTR + offset)); 147 fifo_hdr->rd_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 RXF_RD_RD_PTR + offset)); 150 fifo_hdr->fence_ptr = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 RXF_RD_FENCE_PTR + offset)); 153 fifo_hdr->fence_mode = 154 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 155 RXF_SET_FENCE_MODE + offset)); 156 157 /* Lock fence */ 158 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 159 /* Set fence pointer to the same place like WR pointer */ 160 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 161 /* Set fence offset */ 162 iwl_trans_write_prph(fwrt->trans, 163 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 164 165 /* Read FIFO */ 166 fifo_len /= sizeof(u32); /* Size in DWORDS */ 167 for (i = 0; i < fifo_len; i++) 168 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 169 RXF_FIFO_RD_FENCE_INC + 170 offset); 171 *dump_data = iwl_fw_error_next_data(*dump_data); 172 } 173 174 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 175 struct iwl_fw_error_dump_data **dump_data, 176 int size, u32 offset, int fifo_num) 177 { 178 struct iwl_fw_error_dump_fifo *fifo_hdr; 179 u32 *fifo_data; 180 u32 fifo_len; 181 int i; 182 183 fifo_hdr = (void *)(*dump_data)->data; 184 fifo_data = (void *)fifo_hdr->data; 185 fifo_len = size; 186 187 /* No need to try to read the data if the length is 0 */ 188 if (fifo_len == 0) 189 return; 190 191 /* Add a TLV for the FIFO */ 192 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 193 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 194 195 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 196 fifo_hdr->available_bytes = 197 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 198 TXF_FIFO_ITEM_CNT + offset)); 199 fifo_hdr->wr_ptr = 200 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 201 TXF_WR_PTR + offset)); 202 fifo_hdr->rd_ptr = 203 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 204 TXF_RD_PTR + offset)); 205 fifo_hdr->fence_ptr = 206 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 207 TXF_FENCE_PTR + offset)); 208 fifo_hdr->fence_mode = 209 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 210 TXF_LOCK_FENCE + offset)); 211 212 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 213 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 214 TXF_WR_PTR + offset); 215 216 /* Dummy-read to advance the read pointer to the head */ 217 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 218 219 /* Read FIFO */ 220 fifo_len /= sizeof(u32); /* Size in DWORDS */ 221 for (i = 0; i < fifo_len; i++) 222 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 223 TXF_READ_MODIFY_DATA + 224 offset); 225 *dump_data = iwl_fw_error_next_data(*dump_data); 226 } 227 228 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 229 struct iwl_fw_error_dump_data **dump_data) 230 { 231 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 232 unsigned long flags; 233 234 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 235 236 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 237 return; 238 239 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 240 /* Pull RXF1 */ 241 iwl_fwrt_dump_rxf(fwrt, dump_data, 242 cfg->lmac[0].rxfifo1_size, 0, 0); 243 /* Pull RXF2 */ 244 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 245 RXF_DIFF_FROM_PREV + 246 fwrt->trans->trans_cfg->umac_prph_offset, 1); 247 /* Pull LMAC2 RXF1 */ 248 if (fwrt->smem_cfg.num_lmacs > 1) 249 iwl_fwrt_dump_rxf(fwrt, dump_data, 250 cfg->lmac[1].rxfifo1_size, 251 LMAC2_PRPH_OFFSET, 2); 252 } 253 254 iwl_trans_release_nic_access(fwrt->trans, &flags); 255 } 256 257 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 258 struct iwl_fw_error_dump_data **dump_data) 259 { 260 struct iwl_fw_error_dump_fifo *fifo_hdr; 261 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 262 u32 *fifo_data; 263 u32 fifo_len; 264 unsigned long flags; 265 int i, j; 266 267 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 268 269 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 270 return; 271 272 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 273 /* Pull TXF data from LMAC1 */ 274 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 275 /* Mark the number of TXF we're pulling now */ 276 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 277 iwl_fwrt_dump_txf(fwrt, dump_data, 278 cfg->lmac[0].txfifo_size[i], 0, i); 279 } 280 281 /* Pull TXF data from LMAC2 */ 282 if (fwrt->smem_cfg.num_lmacs > 1) { 283 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 284 i++) { 285 /* Mark the number of TXF we're pulling now */ 286 iwl_trans_write_prph(fwrt->trans, 287 TXF_LARC_NUM + 288 LMAC2_PRPH_OFFSET, i); 289 iwl_fwrt_dump_txf(fwrt, dump_data, 290 cfg->lmac[1].txfifo_size[i], 291 LMAC2_PRPH_OFFSET, 292 i + cfg->num_txfifo_entries); 293 } 294 } 295 } 296 297 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 298 fw_has_capa(&fwrt->fw->ucode_capa, 299 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 300 /* Pull UMAC internal TXF data from all TXFs */ 301 for (i = 0; 302 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 303 i++) { 304 fifo_hdr = (void *)(*dump_data)->data; 305 fifo_data = (void *)fifo_hdr->data; 306 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 307 308 /* No need to try to read the data if the length is 0 */ 309 if (fifo_len == 0) 310 continue; 311 312 /* Add a TLV for the internal FIFOs */ 313 (*dump_data)->type = 314 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 315 (*dump_data)->len = 316 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 317 318 fifo_hdr->fifo_num = cpu_to_le32(i); 319 320 /* Mark the number of TXF we're pulling now */ 321 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 322 fwrt->smem_cfg.num_txfifo_entries); 323 324 fifo_hdr->available_bytes = 325 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 326 TXF_CPU2_FIFO_ITEM_CNT)); 327 fifo_hdr->wr_ptr = 328 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 329 TXF_CPU2_WR_PTR)); 330 fifo_hdr->rd_ptr = 331 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 332 TXF_CPU2_RD_PTR)); 333 fifo_hdr->fence_ptr = 334 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 335 TXF_CPU2_FENCE_PTR)); 336 fifo_hdr->fence_mode = 337 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 338 TXF_CPU2_LOCK_FENCE)); 339 340 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 341 iwl_trans_write_prph(fwrt->trans, 342 TXF_CPU2_READ_MODIFY_ADDR, 343 TXF_CPU2_WR_PTR); 344 345 /* Dummy-read to advance the read pointer to head */ 346 iwl_trans_read_prph(fwrt->trans, 347 TXF_CPU2_READ_MODIFY_DATA); 348 349 /* Read FIFO */ 350 fifo_len /= sizeof(u32); /* Size in DWORDS */ 351 for (j = 0; j < fifo_len; j++) 352 fifo_data[j] = 353 iwl_trans_read_prph(fwrt->trans, 354 TXF_CPU2_READ_MODIFY_DATA); 355 *dump_data = iwl_fw_error_next_data(*dump_data); 356 } 357 } 358 359 iwl_trans_release_nic_access(fwrt->trans, &flags); 360 } 361 362 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ 363 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ 364 365 struct iwl_prph_range { 366 u32 start, end; 367 }; 368 369 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 370 { .start = 0x00a00000, .end = 0x00a00000 }, 371 { .start = 0x00a0000c, .end = 0x00a00024 }, 372 { .start = 0x00a0002c, .end = 0x00a0003c }, 373 { .start = 0x00a00410, .end = 0x00a00418 }, 374 { .start = 0x00a00420, .end = 0x00a00420 }, 375 { .start = 0x00a00428, .end = 0x00a00428 }, 376 { .start = 0x00a00430, .end = 0x00a0043c }, 377 { .start = 0x00a00444, .end = 0x00a00444 }, 378 { .start = 0x00a004c0, .end = 0x00a004cc }, 379 { .start = 0x00a004d8, .end = 0x00a004d8 }, 380 { .start = 0x00a004e0, .end = 0x00a004f0 }, 381 { .start = 0x00a00840, .end = 0x00a00840 }, 382 { .start = 0x00a00850, .end = 0x00a00858 }, 383 { .start = 0x00a01004, .end = 0x00a01008 }, 384 { .start = 0x00a01010, .end = 0x00a01010 }, 385 { .start = 0x00a01018, .end = 0x00a01018 }, 386 { .start = 0x00a01024, .end = 0x00a01024 }, 387 { .start = 0x00a0102c, .end = 0x00a01034 }, 388 { .start = 0x00a0103c, .end = 0x00a01040 }, 389 { .start = 0x00a01048, .end = 0x00a01094 }, 390 { .start = 0x00a01c00, .end = 0x00a01c20 }, 391 { .start = 0x00a01c58, .end = 0x00a01c58 }, 392 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 393 { .start = 0x00a01c28, .end = 0x00a01c54 }, 394 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 395 { .start = 0x00a01c60, .end = 0x00a01cdc }, 396 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 397 { .start = 0x00a01d18, .end = 0x00a01d20 }, 398 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 399 { .start = 0x00a01d40, .end = 0x00a01d5c }, 400 { .start = 0x00a01d80, .end = 0x00a01d80 }, 401 { .start = 0x00a01d98, .end = 0x00a01d9c }, 402 { .start = 0x00a01da8, .end = 0x00a01da8 }, 403 { .start = 0x00a01db8, .end = 0x00a01df4 }, 404 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 405 { .start = 0x00a01e00, .end = 0x00a01e2c }, 406 { .start = 0x00a01e40, .end = 0x00a01e60 }, 407 { .start = 0x00a01e68, .end = 0x00a01e6c }, 408 { .start = 0x00a01e74, .end = 0x00a01e74 }, 409 { .start = 0x00a01e84, .end = 0x00a01e90 }, 410 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 411 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 412 { .start = 0x00a01f00, .end = 0x00a01f1c }, 413 { .start = 0x00a01f44, .end = 0x00a01ffc }, 414 { .start = 0x00a02000, .end = 0x00a02048 }, 415 { .start = 0x00a02068, .end = 0x00a020f0 }, 416 { .start = 0x00a02100, .end = 0x00a02118 }, 417 { .start = 0x00a02140, .end = 0x00a0214c }, 418 { .start = 0x00a02168, .end = 0x00a0218c }, 419 { .start = 0x00a021c0, .end = 0x00a021c0 }, 420 { .start = 0x00a02400, .end = 0x00a02410 }, 421 { .start = 0x00a02418, .end = 0x00a02420 }, 422 { .start = 0x00a02428, .end = 0x00a0242c }, 423 { .start = 0x00a02434, .end = 0x00a02434 }, 424 { .start = 0x00a02440, .end = 0x00a02460 }, 425 { .start = 0x00a02468, .end = 0x00a024b0 }, 426 { .start = 0x00a024c8, .end = 0x00a024cc }, 427 { .start = 0x00a02500, .end = 0x00a02504 }, 428 { .start = 0x00a0250c, .end = 0x00a02510 }, 429 { .start = 0x00a02540, .end = 0x00a02554 }, 430 { .start = 0x00a02580, .end = 0x00a025f4 }, 431 { .start = 0x00a02600, .end = 0x00a0260c }, 432 { .start = 0x00a02648, .end = 0x00a02650 }, 433 { .start = 0x00a02680, .end = 0x00a02680 }, 434 { .start = 0x00a026c0, .end = 0x00a026d0 }, 435 { .start = 0x00a02700, .end = 0x00a0270c }, 436 { .start = 0x00a02804, .end = 0x00a02804 }, 437 { .start = 0x00a02818, .end = 0x00a0281c }, 438 { .start = 0x00a02c00, .end = 0x00a02db4 }, 439 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 440 { .start = 0x00a03000, .end = 0x00a03014 }, 441 { .start = 0x00a0301c, .end = 0x00a0302c }, 442 { .start = 0x00a03034, .end = 0x00a03038 }, 443 { .start = 0x00a03040, .end = 0x00a03048 }, 444 { .start = 0x00a03060, .end = 0x00a03068 }, 445 { .start = 0x00a03070, .end = 0x00a03074 }, 446 { .start = 0x00a0307c, .end = 0x00a0307c }, 447 { .start = 0x00a03080, .end = 0x00a03084 }, 448 { .start = 0x00a0308c, .end = 0x00a03090 }, 449 { .start = 0x00a03098, .end = 0x00a03098 }, 450 { .start = 0x00a030a0, .end = 0x00a030a0 }, 451 { .start = 0x00a030a8, .end = 0x00a030b4 }, 452 { .start = 0x00a030bc, .end = 0x00a030bc }, 453 { .start = 0x00a030c0, .end = 0x00a0312c }, 454 { .start = 0x00a03c00, .end = 0x00a03c5c }, 455 { .start = 0x00a04400, .end = 0x00a04454 }, 456 { .start = 0x00a04460, .end = 0x00a04474 }, 457 { .start = 0x00a044c0, .end = 0x00a044ec }, 458 { .start = 0x00a04500, .end = 0x00a04504 }, 459 { .start = 0x00a04510, .end = 0x00a04538 }, 460 { .start = 0x00a04540, .end = 0x00a04548 }, 461 { .start = 0x00a04560, .end = 0x00a0457c }, 462 { .start = 0x00a04590, .end = 0x00a04598 }, 463 { .start = 0x00a045c0, .end = 0x00a045f4 }, 464 }; 465 466 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 467 { .start = 0x00a05c00, .end = 0x00a05c18 }, 468 { .start = 0x00a05400, .end = 0x00a056e8 }, 469 { .start = 0x00a08000, .end = 0x00a098bc }, 470 { .start = 0x00a02400, .end = 0x00a02758 }, 471 { .start = 0x00a04764, .end = 0x00a0476c }, 472 { .start = 0x00a04770, .end = 0x00a04774 }, 473 { .start = 0x00a04620, .end = 0x00a04624 }, 474 }; 475 476 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 477 { .start = 0x00a00000, .end = 0x00a00000 }, 478 { .start = 0x00a0000c, .end = 0x00a00024 }, 479 { .start = 0x00a0002c, .end = 0x00a00034 }, 480 { .start = 0x00a0003c, .end = 0x00a0003c }, 481 { .start = 0x00a00410, .end = 0x00a00418 }, 482 { .start = 0x00a00420, .end = 0x00a00420 }, 483 { .start = 0x00a00428, .end = 0x00a00428 }, 484 { .start = 0x00a00430, .end = 0x00a0043c }, 485 { .start = 0x00a00444, .end = 0x00a00444 }, 486 { .start = 0x00a00840, .end = 0x00a00840 }, 487 { .start = 0x00a00850, .end = 0x00a00858 }, 488 { .start = 0x00a01004, .end = 0x00a01008 }, 489 { .start = 0x00a01010, .end = 0x00a01010 }, 490 { .start = 0x00a01018, .end = 0x00a01018 }, 491 { .start = 0x00a01024, .end = 0x00a01024 }, 492 { .start = 0x00a0102c, .end = 0x00a01034 }, 493 { .start = 0x00a0103c, .end = 0x00a01040 }, 494 { .start = 0x00a01048, .end = 0x00a01050 }, 495 { .start = 0x00a01058, .end = 0x00a01058 }, 496 { .start = 0x00a01060, .end = 0x00a01070 }, 497 { .start = 0x00a0108c, .end = 0x00a0108c }, 498 { .start = 0x00a01c20, .end = 0x00a01c28 }, 499 { .start = 0x00a01d10, .end = 0x00a01d10 }, 500 { .start = 0x00a01e28, .end = 0x00a01e2c }, 501 { .start = 0x00a01e60, .end = 0x00a01e60 }, 502 { .start = 0x00a01e80, .end = 0x00a01e80 }, 503 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 504 { .start = 0x00a02000, .end = 0x00a0201c }, 505 { .start = 0x00a02024, .end = 0x00a02024 }, 506 { .start = 0x00a02040, .end = 0x00a02048 }, 507 { .start = 0x00a020c0, .end = 0x00a020e0 }, 508 { .start = 0x00a02400, .end = 0x00a02404 }, 509 { .start = 0x00a0240c, .end = 0x00a02414 }, 510 { .start = 0x00a0241c, .end = 0x00a0243c }, 511 { .start = 0x00a02448, .end = 0x00a024bc }, 512 { .start = 0x00a024c4, .end = 0x00a024cc }, 513 { .start = 0x00a02508, .end = 0x00a02508 }, 514 { .start = 0x00a02510, .end = 0x00a02514 }, 515 { .start = 0x00a0251c, .end = 0x00a0251c }, 516 { .start = 0x00a0252c, .end = 0x00a0255c }, 517 { .start = 0x00a02564, .end = 0x00a025a0 }, 518 { .start = 0x00a025a8, .end = 0x00a025b4 }, 519 { .start = 0x00a025c0, .end = 0x00a025c0 }, 520 { .start = 0x00a025e8, .end = 0x00a025f4 }, 521 { .start = 0x00a02c08, .end = 0x00a02c18 }, 522 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 523 { .start = 0x00a02c68, .end = 0x00a02c78 }, 524 { .start = 0x00a03000, .end = 0x00a03000 }, 525 { .start = 0x00a03010, .end = 0x00a03014 }, 526 { .start = 0x00a0301c, .end = 0x00a0302c }, 527 { .start = 0x00a03034, .end = 0x00a03038 }, 528 { .start = 0x00a03040, .end = 0x00a03044 }, 529 { .start = 0x00a03060, .end = 0x00a03068 }, 530 { .start = 0x00a03070, .end = 0x00a03070 }, 531 { .start = 0x00a0307c, .end = 0x00a03084 }, 532 { .start = 0x00a0308c, .end = 0x00a03090 }, 533 { .start = 0x00a03098, .end = 0x00a03098 }, 534 { .start = 0x00a030a0, .end = 0x00a030a0 }, 535 { .start = 0x00a030a8, .end = 0x00a030b4 }, 536 { .start = 0x00a030bc, .end = 0x00a030c0 }, 537 { .start = 0x00a030c8, .end = 0x00a030f4 }, 538 { .start = 0x00a03100, .end = 0x00a0312c }, 539 { .start = 0x00a03c00, .end = 0x00a03c5c }, 540 { .start = 0x00a04400, .end = 0x00a04454 }, 541 { .start = 0x00a04460, .end = 0x00a04474 }, 542 { .start = 0x00a044c0, .end = 0x00a044ec }, 543 { .start = 0x00a04500, .end = 0x00a04504 }, 544 { .start = 0x00a04510, .end = 0x00a04538 }, 545 { .start = 0x00a04540, .end = 0x00a04548 }, 546 { .start = 0x00a04560, .end = 0x00a04560 }, 547 { .start = 0x00a04570, .end = 0x00a0457c }, 548 { .start = 0x00a04590, .end = 0x00a04590 }, 549 { .start = 0x00a04598, .end = 0x00a04598 }, 550 { .start = 0x00a045c0, .end = 0x00a045f4 }, 551 { .start = 0x00a05c18, .end = 0x00a05c1c }, 552 { .start = 0x00a0c000, .end = 0x00a0c018 }, 553 { .start = 0x00a0c020, .end = 0x00a0c028 }, 554 { .start = 0x00a0c038, .end = 0x00a0c094 }, 555 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 556 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 557 { .start = 0x00a0c150, .end = 0x00a0c174 }, 558 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 559 { .start = 0x00a0c190, .end = 0x00a0c198 }, 560 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 561 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 562 }; 563 564 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 565 { .start = 0x00d03c00, .end = 0x00d03c64 }, 566 { .start = 0x00d05c18, .end = 0x00d05c1c }, 567 { .start = 0x00d0c000, .end = 0x00d0c174 }, 568 }; 569 570 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 571 u32 len_bytes, __le32 *data) 572 { 573 u32 i; 574 575 for (i = 0; i < len_bytes; i += 4) 576 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 577 } 578 579 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 580 const struct iwl_prph_range *iwl_prph_dump_addr, 581 u32 range_len, void *ptr) 582 { 583 struct iwl_fw_error_dump_prph *prph; 584 struct iwl_trans *trans = fwrt->trans; 585 struct iwl_fw_error_dump_data **data = 586 (struct iwl_fw_error_dump_data **)ptr; 587 unsigned long flags; 588 u32 i; 589 590 if (!data) 591 return; 592 593 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 594 595 if (!iwl_trans_grab_nic_access(trans, &flags)) 596 return; 597 598 for (i = 0; i < range_len; i++) { 599 /* The range includes both boundaries */ 600 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 601 iwl_prph_dump_addr[i].start + 4; 602 603 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 604 (*data)->len = cpu_to_le32(sizeof(*prph) + 605 num_bytes_in_chunk); 606 prph = (void *)(*data)->data; 607 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 608 609 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 610 /* our range is inclusive, hence + 4 */ 611 iwl_prph_dump_addr[i].end - 612 iwl_prph_dump_addr[i].start + 4, 613 (void *)prph->data); 614 615 *data = iwl_fw_error_next_data(*data); 616 } 617 618 iwl_trans_release_nic_access(trans, &flags); 619 } 620 621 /* 622 * alloc_sgtable - allocates scallerlist table in the given size, 623 * fills it with pages and returns it 624 * @size: the size (in bytes) of the table 625 */ 626 static struct scatterlist *alloc_sgtable(int size) 627 { 628 int alloc_size, nents, i; 629 struct page *new_page; 630 struct scatterlist *iter; 631 struct scatterlist *table; 632 633 nents = DIV_ROUND_UP(size, PAGE_SIZE); 634 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 635 if (!table) 636 return NULL; 637 sg_init_table(table, nents); 638 iter = table; 639 for_each_sg(table, iter, sg_nents(table), i) { 640 new_page = alloc_page(GFP_KERNEL); 641 if (!new_page) { 642 /* release all previous allocated pages in the table */ 643 iter = table; 644 for_each_sg(table, iter, sg_nents(table), i) { 645 new_page = sg_page(iter); 646 if (new_page) 647 __free_page(new_page); 648 } 649 kfree(table); 650 return NULL; 651 } 652 alloc_size = min_t(int, size, PAGE_SIZE); 653 size -= PAGE_SIZE; 654 sg_set_page(iter, new_page, alloc_size, 0); 655 } 656 return table; 657 } 658 659 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 660 const struct iwl_prph_range *iwl_prph_dump_addr, 661 u32 range_len, void *ptr) 662 { 663 u32 *prph_len = (u32 *)ptr; 664 int i, num_bytes_in_chunk; 665 666 if (!prph_len) 667 return; 668 669 for (i = 0; i < range_len; i++) { 670 /* The range includes both boundaries */ 671 num_bytes_in_chunk = 672 iwl_prph_dump_addr[i].end - 673 iwl_prph_dump_addr[i].start + 4; 674 675 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 676 sizeof(struct iwl_fw_error_dump_prph) + 677 num_bytes_in_chunk; 678 } 679 } 680 681 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 682 void (*handler)(struct iwl_fw_runtime *, 683 const struct iwl_prph_range *, 684 u32, void *)) 685 { 686 u32 range_len; 687 688 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 689 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 690 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 691 } else if (fwrt->trans->trans_cfg->device_family >= 692 IWL_DEVICE_FAMILY_22000) { 693 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 694 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 695 } else { 696 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 697 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 698 699 if (fwrt->trans->trans_cfg->mq_rx_supported) { 700 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 701 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 702 } 703 } 704 } 705 706 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 707 struct iwl_fw_error_dump_data **dump_data, 708 u32 len, u32 ofs, u32 type) 709 { 710 struct iwl_fw_error_dump_mem *dump_mem; 711 712 if (!len) 713 return; 714 715 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 716 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 717 dump_mem = (void *)(*dump_data)->data; 718 dump_mem->type = cpu_to_le32(type); 719 dump_mem->offset = cpu_to_le32(ofs); 720 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 721 *dump_data = iwl_fw_error_next_data(*dump_data); 722 723 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 724 } 725 726 #define ADD_LEN(len, item_len, const_len) \ 727 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 728 while (0) 729 730 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 731 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 732 { 733 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 734 sizeof(struct iwl_fw_error_dump_fifo); 735 u32 fifo_len = 0; 736 int i; 737 738 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 739 return 0; 740 741 /* Count RXF2 size */ 742 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 743 744 /* Count RXF1 sizes */ 745 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 746 mem_cfg->num_lmacs = MAX_NUM_LMAC; 747 748 for (i = 0; i < mem_cfg->num_lmacs; i++) 749 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 750 751 return fifo_len; 752 } 753 754 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 755 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 756 { 757 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 758 sizeof(struct iwl_fw_error_dump_fifo); 759 u32 fifo_len = 0; 760 int i; 761 762 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 763 goto dump_internal_txf; 764 765 /* Count TXF sizes */ 766 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 767 mem_cfg->num_lmacs = MAX_NUM_LMAC; 768 769 for (i = 0; i < mem_cfg->num_lmacs; i++) { 770 int j; 771 772 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 773 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 774 hdr_len); 775 } 776 777 dump_internal_txf: 778 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 779 fw_has_capa(&fwrt->fw->ucode_capa, 780 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 781 goto out; 782 783 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 784 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 785 786 out: 787 return fifo_len; 788 } 789 790 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 791 struct iwl_fw_error_dump_data **data) 792 { 793 int i; 794 795 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 796 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 797 struct iwl_fw_error_dump_paging *paging; 798 struct page *pages = 799 fwrt->fw_paging_db[i].fw_paging_block; 800 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 801 802 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 803 (*data)->len = cpu_to_le32(sizeof(*paging) + 804 PAGING_BLOCK_SIZE); 805 paging = (void *)(*data)->data; 806 paging->index = cpu_to_le32(i); 807 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 808 PAGING_BLOCK_SIZE, 809 DMA_BIDIRECTIONAL); 810 memcpy(paging->data, page_address(pages), 811 PAGING_BLOCK_SIZE); 812 dma_sync_single_for_device(fwrt->trans->dev, addr, 813 PAGING_BLOCK_SIZE, 814 DMA_BIDIRECTIONAL); 815 (*data) = iwl_fw_error_next_data(*data); 816 } 817 } 818 819 static struct iwl_fw_error_dump_file * 820 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 821 struct iwl_fw_dump_ptrs *fw_error_dump) 822 { 823 struct iwl_fw_error_dump_file *dump_file; 824 struct iwl_fw_error_dump_data *dump_data; 825 struct iwl_fw_error_dump_info *dump_info; 826 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 827 struct iwl_fw_error_dump_trigger_desc *dump_trig; 828 u32 sram_len, sram_ofs; 829 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 830 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 831 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 832 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 833 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 834 0 : fwrt->trans->cfg->dccm2_len; 835 int i; 836 837 /* SRAM - include stack CCM if driver knows the values for it */ 838 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 839 const struct fw_img *img; 840 841 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 842 return NULL; 843 img = &fwrt->fw->img[fwrt->cur_fw_img]; 844 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 845 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 846 } else { 847 sram_ofs = fwrt->trans->cfg->dccm_offset; 848 sram_len = fwrt->trans->cfg->dccm_len; 849 } 850 851 /* reading RXF/TXF sizes */ 852 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 853 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 854 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 855 856 /* Make room for PRPH registers */ 857 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 858 iwl_fw_prph_handler(fwrt, &prph_len, 859 iwl_fw_get_prph_len); 860 861 if (fwrt->trans->trans_cfg->device_family == 862 IWL_DEVICE_FAMILY_7000 && 863 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 864 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 865 } 866 867 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 868 869 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 870 file_len += sizeof(*dump_data) + sizeof(*dump_info); 871 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 872 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 873 874 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 875 size_t hdr_len = sizeof(*dump_data) + 876 sizeof(struct iwl_fw_error_dump_mem); 877 878 /* Dump SRAM only if no mem_tlvs */ 879 if (!fwrt->fw->dbg.n_mem_tlv) 880 ADD_LEN(file_len, sram_len, hdr_len); 881 882 /* Make room for all mem types that exist */ 883 ADD_LEN(file_len, smem_len, hdr_len); 884 ADD_LEN(file_len, sram2_len, hdr_len); 885 886 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 887 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 888 } 889 890 /* Make room for fw's virtual image pages, if it exists */ 891 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 892 file_len += fwrt->num_of_paging_blk * 893 (sizeof(*dump_data) + 894 sizeof(struct iwl_fw_error_dump_paging) + 895 PAGING_BLOCK_SIZE); 896 897 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 898 file_len += sizeof(*dump_data) + 899 fwrt->trans->cfg->d3_debug_data_length * 2; 900 } 901 902 /* If we only want a monitor dump, reset the file length */ 903 if (fwrt->dump.monitor_only) { 904 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 905 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 906 } 907 908 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 909 fwrt->dump.desc) 910 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 911 fwrt->dump.desc->len; 912 913 dump_file = vzalloc(file_len); 914 if (!dump_file) 915 return NULL; 916 917 fw_error_dump->fwrt_ptr = dump_file; 918 919 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 920 dump_data = (void *)dump_file->data; 921 922 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 923 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 924 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 925 dump_info = (void *)dump_data->data; 926 dump_info->hw_type = 927 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 928 dump_info->hw_step = 929 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 930 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 931 sizeof(dump_info->fw_human_readable)); 932 strncpy(dump_info->dev_human_readable, fwrt->trans->cfg->name, 933 sizeof(dump_info->dev_human_readable) - 1); 934 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 935 sizeof(dump_info->bus_human_readable) - 1); 936 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 937 dump_info->lmac_err_id[0] = 938 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 939 if (fwrt->smem_cfg.num_lmacs > 1) 940 dump_info->lmac_err_id[1] = 941 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 942 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 943 944 dump_data = iwl_fw_error_next_data(dump_data); 945 } 946 947 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 948 /* Dump shared memory configuration */ 949 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 950 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 951 dump_smem_cfg = (void *)dump_data->data; 952 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 953 dump_smem_cfg->num_txfifo_entries = 954 cpu_to_le32(mem_cfg->num_txfifo_entries); 955 for (i = 0; i < MAX_NUM_LMAC; i++) { 956 int j; 957 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 958 959 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 960 dump_smem_cfg->lmac[i].txfifo_size[j] = 961 cpu_to_le32(txf_size[j]); 962 dump_smem_cfg->lmac[i].rxfifo1_size = 963 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 964 } 965 dump_smem_cfg->rxfifo2_size = 966 cpu_to_le32(mem_cfg->rxfifo2_size); 967 dump_smem_cfg->internal_txfifo_addr = 968 cpu_to_le32(mem_cfg->internal_txfifo_addr); 969 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 970 dump_smem_cfg->internal_txfifo_size[i] = 971 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 972 } 973 974 dump_data = iwl_fw_error_next_data(dump_data); 975 } 976 977 /* We only dump the FIFOs if the FW is in error state */ 978 if (fifo_len) { 979 iwl_fw_dump_rxf(fwrt, &dump_data); 980 iwl_fw_dump_txf(fwrt, &dump_data); 981 } 982 983 if (radio_len) 984 iwl_read_radio_regs(fwrt, &dump_data); 985 986 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 987 fwrt->dump.desc) { 988 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 989 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 990 fwrt->dump.desc->len); 991 dump_trig = (void *)dump_data->data; 992 memcpy(dump_trig, &fwrt->dump.desc->trig_desc, 993 sizeof(*dump_trig) + fwrt->dump.desc->len); 994 995 dump_data = iwl_fw_error_next_data(dump_data); 996 } 997 998 /* In case we only want monitor dump, skip to dump trasport data */ 999 if (fwrt->dump.monitor_only) 1000 goto out; 1001 1002 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 1003 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 1004 fwrt->fw->dbg.mem_tlv; 1005 1006 if (!fwrt->fw->dbg.n_mem_tlv) 1007 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 1008 IWL_FW_ERROR_DUMP_MEM_SRAM); 1009 1010 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 1011 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 1012 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 1013 1014 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 1015 le32_to_cpu(fw_dbg_mem[i].data_type)); 1016 } 1017 1018 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 1019 fwrt->trans->cfg->smem_offset, 1020 IWL_FW_ERROR_DUMP_MEM_SMEM); 1021 1022 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 1023 fwrt->trans->cfg->dccm2_offset, 1024 IWL_FW_ERROR_DUMP_MEM_SRAM); 1025 } 1026 1027 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 1028 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 1029 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 1030 1031 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 1032 dump_data->len = cpu_to_le32(data_size * 2); 1033 1034 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 1035 1036 kfree(fwrt->dump.d3_debug_data); 1037 fwrt->dump.d3_debug_data = NULL; 1038 1039 iwl_trans_read_mem_bytes(fwrt->trans, addr, 1040 dump_data->data + data_size, 1041 data_size); 1042 1043 dump_data = iwl_fw_error_next_data(dump_data); 1044 } 1045 1046 /* Dump fw's virtual image */ 1047 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1048 iwl_dump_paging(fwrt, &dump_data); 1049 1050 if (prph_len) 1051 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1052 1053 out: 1054 dump_file->file_len = cpu_to_le32(file_len); 1055 return dump_file; 1056 } 1057 1058 static int iwl_dump_ini_prph_iter(struct iwl_fw_runtime *fwrt, 1059 struct iwl_fw_ini_region_cfg *reg, 1060 void *range_ptr, int idx) 1061 { 1062 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1063 __le32 *val = range->data; 1064 u32 prph_val; 1065 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1066 int i; 1067 1068 range->internal_base_addr = cpu_to_le32(addr); 1069 range->range_data_size = reg->internal.range_data_size; 1070 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) { 1071 prph_val = iwl_read_prph(fwrt->trans, addr + i); 1072 if (prph_val == 0x5a5a5a5a) 1073 return -EBUSY; 1074 *val++ = cpu_to_le32(prph_val); 1075 } 1076 1077 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1078 } 1079 1080 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1081 struct iwl_fw_ini_region_cfg *reg, 1082 void *range_ptr, int idx) 1083 { 1084 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1085 __le32 *val = range->data; 1086 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1087 int i; 1088 1089 range->internal_base_addr = cpu_to_le32(addr); 1090 range->range_data_size = reg->internal.range_data_size; 1091 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) 1092 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1093 1094 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1095 } 1096 1097 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1098 struct iwl_fw_ini_region_cfg *reg, 1099 void *range_ptr, int idx) 1100 { 1101 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1102 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1103 1104 range->internal_base_addr = cpu_to_le32(addr); 1105 range->range_data_size = reg->internal.range_data_size; 1106 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1107 le32_to_cpu(reg->internal.range_data_size)); 1108 1109 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1110 } 1111 1112 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1113 struct iwl_fw_ini_region_cfg *reg, 1114 void *range_ptr, int idx) 1115 { 1116 /* increase idx by 1 since the pages are from 1 to 1117 * fwrt->num_of_paging_blk + 1 1118 */ 1119 struct page *page = fwrt->fw_paging_db[++idx].fw_paging_block; 1120 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1121 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1122 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1123 1124 range->page_num = cpu_to_le32(idx); 1125 range->range_data_size = cpu_to_le32(page_size); 1126 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1127 DMA_BIDIRECTIONAL); 1128 memcpy(range->data, page_address(page), page_size); 1129 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1130 DMA_BIDIRECTIONAL); 1131 1132 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1133 } 1134 1135 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1136 struct iwl_fw_ini_region_cfg *reg, 1137 void *range_ptr, int idx) 1138 { 1139 struct iwl_fw_ini_error_dump_range *range; 1140 u32 page_size; 1141 1142 if (!fwrt->trans->trans_cfg->gen2) 1143 return _iwl_dump_ini_paging_iter(fwrt, reg, range_ptr, idx); 1144 1145 range = range_ptr; 1146 page_size = fwrt->trans->init_dram.paging[idx].size; 1147 1148 range->page_num = cpu_to_le32(idx); 1149 range->range_data_size = cpu_to_le32(page_size); 1150 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1151 page_size); 1152 1153 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1154 } 1155 1156 static int 1157 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1158 struct iwl_fw_ini_region_cfg *reg, void *range_ptr, 1159 int idx) 1160 { 1161 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1162 u32 start_addr = iwl_read_umac_prph(fwrt->trans, 1163 MON_BUFF_BASE_ADDR_VER2); 1164 1165 if (start_addr == 0x5a5a5a5a) 1166 return -EBUSY; 1167 1168 range->dram_base_addr = cpu_to_le64(start_addr); 1169 range->range_data_size = cpu_to_le32(fwrt->trans->dbg.fw_mon[idx].size); 1170 1171 memcpy(range->data, fwrt->trans->dbg.fw_mon[idx].block, 1172 fwrt->trans->dbg.fw_mon[idx].size); 1173 1174 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1175 } 1176 1177 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1178 struct iwl_fw_ini_region_cfg *reg, int idx) 1179 { 1180 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1181 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1182 int txf_num = cfg->num_txfifo_entries; 1183 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1184 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid1); 1185 1186 if (!idx) { 1187 if (le32_to_cpu(reg->offset) && 1188 WARN_ONCE(cfg->num_lmacs == 1, 1189 "Invalid lmac offset: 0x%x\n", 1190 le32_to_cpu(reg->offset))) 1191 return false; 1192 1193 iter->internal_txf = 0; 1194 iter->fifo_size = 0; 1195 iter->fifo = -1; 1196 if (le32_to_cpu(reg->offset)) 1197 iter->lmac = 1; 1198 else 1199 iter->lmac = 0; 1200 } 1201 1202 if (!iter->internal_txf) 1203 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1204 iter->fifo_size = 1205 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1206 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1207 return true; 1208 } 1209 1210 iter->internal_txf = 1; 1211 1212 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1213 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1214 return false; 1215 1216 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1217 iter->fifo_size = 1218 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1219 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1220 return true; 1221 } 1222 1223 return false; 1224 } 1225 1226 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1227 struct iwl_fw_ini_region_cfg *reg, 1228 void *range_ptr, int idx) 1229 { 1230 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1231 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1232 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1233 u32 offs = le32_to_cpu(reg->offset), addr; 1234 u32 registers_size = 1235 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump); 1236 __le32 *data; 1237 unsigned long flags; 1238 int i; 1239 1240 if (!iwl_ini_txf_iter(fwrt, reg, idx)) 1241 return -EIO; 1242 1243 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1244 return -EBUSY; 1245 1246 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1247 range->fifo_hdr.num_of_registers = reg->fifos.num_of_registers; 1248 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1249 1250 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1251 1252 /* 1253 * read txf registers. for each register, write to the dump the 1254 * register address and its value 1255 */ 1256 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { 1257 addr = le32_to_cpu(reg->start_addr[i]) + offs; 1258 1259 reg_dump->addr = cpu_to_le32(addr); 1260 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1261 addr)); 1262 1263 reg_dump++; 1264 } 1265 1266 if (reg->fifos.header_only) { 1267 range->range_data_size = cpu_to_le32(registers_size); 1268 goto out; 1269 } 1270 1271 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1272 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1273 TXF_WR_PTR + offs); 1274 1275 /* Dummy-read to advance the read pointer to the head */ 1276 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1277 1278 /* Read FIFO */ 1279 addr = TXF_READ_MODIFY_DATA + offs; 1280 data = (void *)reg_dump; 1281 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1282 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1283 1284 out: 1285 iwl_trans_release_nic_access(fwrt->trans, &flags); 1286 1287 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1288 } 1289 1290 struct iwl_ini_rxf_data { 1291 u32 fifo_num; 1292 u32 size; 1293 u32 offset; 1294 }; 1295 1296 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1297 struct iwl_fw_ini_region_cfg *reg, 1298 struct iwl_ini_rxf_data *data) 1299 { 1300 u32 fid1 = le32_to_cpu(reg->fifos.fid1); 1301 u32 fid2 = le32_to_cpu(reg->fifos.fid2); 1302 u32 fifo_idx; 1303 1304 if (!data) 1305 return; 1306 1307 memset(data, 0, sizeof(*data)); 1308 1309 if (WARN_ON_ONCE((fid1 && fid2) || (!fid1 && !fid2))) 1310 return; 1311 1312 fifo_idx = ffs(fid1) - 1; 1313 if (fid1 && !WARN_ON_ONCE((~BIT(fifo_idx) & fid1) || 1314 fifo_idx >= MAX_NUM_LMAC)) { 1315 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1316 data->fifo_num = fifo_idx; 1317 return; 1318 } 1319 1320 fifo_idx = ffs(fid2) - 1; 1321 if (fid2 && !WARN_ON_ONCE(fifo_idx != 0)) { 1322 data->size = fwrt->smem_cfg.rxfifo2_size; 1323 data->offset = RXF_DIFF_FROM_PREV; 1324 /* use bit 31 to distinguish between umac and lmac rxf while 1325 * parsing the dump 1326 */ 1327 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1328 return; 1329 } 1330 } 1331 1332 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1333 struct iwl_fw_ini_region_cfg *reg, 1334 void *range_ptr, int idx) 1335 { 1336 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1337 struct iwl_ini_rxf_data rxf_data; 1338 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1339 u32 offs = le32_to_cpu(reg->offset), addr; 1340 u32 registers_size = 1341 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump); 1342 __le32 *data; 1343 unsigned long flags; 1344 int i; 1345 1346 iwl_ini_get_rxf_data(fwrt, reg, &rxf_data); 1347 if (!rxf_data.size) 1348 return -EIO; 1349 1350 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1351 return -EBUSY; 1352 1353 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1354 range->fifo_hdr.num_of_registers = reg->fifos.num_of_registers; 1355 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1356 1357 /* 1358 * read rxf registers. for each register, write to the dump the 1359 * register address and its value 1360 */ 1361 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { 1362 addr = le32_to_cpu(reg->start_addr[i]) + offs; 1363 1364 reg_dump->addr = cpu_to_le32(addr); 1365 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1366 addr)); 1367 1368 reg_dump++; 1369 } 1370 1371 if (reg->fifos.header_only) { 1372 range->range_data_size = cpu_to_le32(registers_size); 1373 goto out; 1374 } 1375 1376 /* 1377 * region register have absolute value so apply rxf offset after 1378 * reading the registers 1379 */ 1380 offs += rxf_data.offset; 1381 1382 /* Lock fence */ 1383 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1384 /* Set fence pointer to the same place like WR pointer */ 1385 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1386 /* Set fence offset */ 1387 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1388 0x0); 1389 1390 /* Read FIFO */ 1391 addr = RXF_FIFO_RD_FENCE_INC + offs; 1392 data = (void *)reg_dump; 1393 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1394 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1395 1396 out: 1397 iwl_trans_release_nic_access(fwrt->trans, &flags); 1398 1399 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1400 } 1401 1402 static void *iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1403 struct iwl_fw_ini_region_cfg *reg, 1404 void *data) 1405 { 1406 struct iwl_fw_ini_error_dump *dump = data; 1407 1408 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1409 1410 return dump->ranges; 1411 } 1412 1413 static void 1414 *iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, 1415 struct iwl_fw_ini_region_cfg *reg, 1416 struct iwl_fw_ini_monitor_dump *data, 1417 u32 write_ptr_addr, u32 write_ptr_msk, 1418 u32 cycle_cnt_addr, u32 cycle_cnt_msk) 1419 { 1420 u32 write_ptr, cycle_cnt; 1421 unsigned long flags; 1422 1423 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) { 1424 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1425 return NULL; 1426 } 1427 1428 write_ptr = iwl_read_prph_no_grab(fwrt->trans, write_ptr_addr); 1429 cycle_cnt = iwl_read_prph_no_grab(fwrt->trans, cycle_cnt_addr); 1430 1431 iwl_trans_release_nic_access(fwrt->trans, &flags); 1432 1433 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1434 data->write_ptr = cpu_to_le32(write_ptr & write_ptr_msk); 1435 data->cycle_cnt = cpu_to_le32(cycle_cnt & cycle_cnt_msk); 1436 1437 return data->ranges; 1438 } 1439 1440 static void 1441 *iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1442 struct iwl_fw_ini_region_cfg *reg, 1443 void *data) 1444 { 1445 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1446 u32 write_ptr_addr, write_ptr_msk, cycle_cnt_addr, cycle_cnt_msk; 1447 1448 switch (fwrt->trans->trans_cfg->device_family) { 1449 case IWL_DEVICE_FAMILY_9000: 1450 case IWL_DEVICE_FAMILY_22000: 1451 write_ptr_addr = MON_BUFF_WRPTR_VER2; 1452 write_ptr_msk = -1; 1453 cycle_cnt_addr = MON_BUFF_CYCLE_CNT_VER2; 1454 cycle_cnt_msk = -1; 1455 break; 1456 default: 1457 IWL_ERR(fwrt, "Unsupported device family %d\n", 1458 fwrt->trans->trans_cfg->device_family); 1459 return NULL; 1460 } 1461 1462 return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, write_ptr_addr, 1463 write_ptr_msk, cycle_cnt_addr, 1464 cycle_cnt_msk); 1465 } 1466 1467 static void 1468 *iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1469 struct iwl_fw_ini_region_cfg *reg, 1470 void *data) 1471 { 1472 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1473 const struct iwl_cfg *cfg = fwrt->trans->cfg; 1474 1475 if (fwrt->trans->trans_cfg->device_family != IWL_DEVICE_FAMILY_9000 && 1476 fwrt->trans->trans_cfg->device_family != IWL_DEVICE_FAMILY_22000) { 1477 IWL_ERR(fwrt, "Unsupported device family %d\n", 1478 fwrt->trans->trans_cfg->device_family); 1479 return NULL; 1480 } 1481 1482 return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, 1483 cfg->fw_mon_smem_write_ptr_addr, 1484 cfg->fw_mon_smem_write_ptr_msk, 1485 cfg->fw_mon_smem_cycle_cnt_ptr_addr, 1486 cfg->fw_mon_smem_cycle_cnt_ptr_msk); 1487 1488 } 1489 1490 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1491 struct iwl_fw_ini_region_cfg *reg) 1492 { 1493 return le32_to_cpu(reg->internal.num_of_ranges); 1494 } 1495 1496 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1497 struct iwl_fw_ini_region_cfg *reg) 1498 { 1499 if (fwrt->trans->trans_cfg->gen2) 1500 return fwrt->trans->init_dram.paging_cnt; 1501 1502 return fwrt->num_of_paging_blk; 1503 } 1504 1505 static u32 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1506 struct iwl_fw_ini_region_cfg *reg) 1507 { 1508 return 1; 1509 } 1510 1511 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1512 struct iwl_fw_ini_region_cfg *reg) 1513 { 1514 u32 num_of_fifos = 0; 1515 1516 while (iwl_ini_txf_iter(fwrt, reg, num_of_fifos)) 1517 num_of_fifos++; 1518 1519 return num_of_fifos; 1520 } 1521 1522 static u32 iwl_dump_ini_rxf_ranges(struct iwl_fw_runtime *fwrt, 1523 struct iwl_fw_ini_region_cfg *reg) 1524 { 1525 /* Each Rx fifo needs a different offset and therefore, it's 1526 * region can contain only one fifo, i.e. 1 memory range. 1527 */ 1528 return 1; 1529 } 1530 1531 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1532 struct iwl_fw_ini_region_cfg *reg) 1533 { 1534 return sizeof(struct iwl_fw_ini_error_dump) + 1535 iwl_dump_ini_mem_ranges(fwrt, reg) * 1536 (sizeof(struct iwl_fw_ini_error_dump_range) + 1537 le32_to_cpu(reg->internal.range_data_size)); 1538 } 1539 1540 static u32 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1541 struct iwl_fw_ini_region_cfg *reg) 1542 { 1543 int i; 1544 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1545 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1546 1547 if (fwrt->trans->trans_cfg->gen2) { 1548 for (i = 0; i < iwl_dump_ini_paging_ranges(fwrt, reg); i++) 1549 size += range_header_len + 1550 fwrt->trans->init_dram.paging[i].size; 1551 } else { 1552 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg); i++) 1553 size += range_header_len + 1554 fwrt->fw_paging_db[i].fw_paging_size; 1555 } 1556 1557 return size; 1558 } 1559 1560 static u32 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 1561 struct iwl_fw_ini_region_cfg *reg) 1562 { 1563 u32 size = sizeof(struct iwl_fw_ini_monitor_dump) + 1564 sizeof(struct iwl_fw_ini_error_dump_range); 1565 1566 if (fwrt->trans->dbg.num_blocks) 1567 size += fwrt->trans->dbg.fw_mon[0].size; 1568 1569 return size; 1570 } 1571 1572 static u32 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 1573 struct iwl_fw_ini_region_cfg *reg) 1574 { 1575 return sizeof(struct iwl_fw_ini_monitor_dump) + 1576 iwl_dump_ini_mem_ranges(fwrt, reg) * 1577 (sizeof(struct iwl_fw_ini_error_dump_range) + 1578 le32_to_cpu(reg->internal.range_data_size)); 1579 } 1580 1581 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 1582 struct iwl_fw_ini_region_cfg *reg) 1583 { 1584 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1585 u32 size = 0; 1586 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 1587 le32_to_cpu(reg->fifos.num_of_registers) * 1588 sizeof(struct iwl_fw_ini_error_dump_register); 1589 1590 while (iwl_ini_txf_iter(fwrt, reg, size)) { 1591 size += fifo_hdr; 1592 if (!reg->fifos.header_only) 1593 size += iter->fifo_size; 1594 } 1595 1596 if (size) 1597 size += sizeof(struct iwl_fw_ini_error_dump); 1598 1599 return size; 1600 } 1601 1602 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 1603 struct iwl_fw_ini_region_cfg *reg) 1604 { 1605 struct iwl_ini_rxf_data rx_data; 1606 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 1607 sizeof(struct iwl_fw_ini_error_dump_range) + 1608 le32_to_cpu(reg->fifos.num_of_registers) * 1609 sizeof(struct iwl_fw_ini_error_dump_register); 1610 1611 if (reg->fifos.header_only) 1612 return size; 1613 1614 iwl_ini_get_rxf_data(fwrt, reg, &rx_data); 1615 size += rx_data.size; 1616 1617 return size; 1618 } 1619 1620 /** 1621 * struct iwl_dump_ini_mem_ops - ini memory dump operations 1622 * @get_num_of_ranges: returns the number of memory ranges in the region. 1623 * @get_size: returns the total size of the region. 1624 * @fill_mem_hdr: fills region type specific headers and returns pointer to 1625 * the first range or NULL if failed to fill headers. 1626 * @fill_range: copies a given memory range into the dump. 1627 * Returns the size of the range or negative error value otherwise. 1628 */ 1629 struct iwl_dump_ini_mem_ops { 1630 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 1631 struct iwl_fw_ini_region_cfg *reg); 1632 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 1633 struct iwl_fw_ini_region_cfg *reg); 1634 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 1635 struct iwl_fw_ini_region_cfg *reg, void *data); 1636 int (*fill_range)(struct iwl_fw_runtime *fwrt, 1637 struct iwl_fw_ini_region_cfg *reg, void *range, 1638 int idx); 1639 }; 1640 1641 /** 1642 * iwl_dump_ini_mem 1643 * 1644 * Creates a dump tlv and copy a memory region into it. 1645 * Returns the size of the current dump tlv or 0 if failed 1646 * 1647 * @fwrt: fw runtime struct 1648 * @list: list to add the dump tlv to 1649 * @reg: memory region 1650 * @ops: memory dump operations 1651 */ 1652 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 1653 struct iwl_fw_ini_region_cfg *reg, 1654 const struct iwl_dump_ini_mem_ops *ops) 1655 { 1656 struct iwl_fw_ini_dump_entry *entry; 1657 struct iwl_fw_error_dump_data *tlv; 1658 struct iwl_fw_ini_error_dump_header *header; 1659 u32 num_of_ranges, i, type = le32_to_cpu(reg->region_type), size; 1660 void *range; 1661 1662 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 1663 !ops->fill_range) 1664 return 0; 1665 1666 size = ops->get_size(fwrt, reg); 1667 if (!size) 1668 return 0; 1669 1670 entry = kmalloc(sizeof(*entry) + sizeof(*tlv) + size, GFP_KERNEL); 1671 if (!entry) 1672 return 0; 1673 1674 entry->size = sizeof(*tlv) + size; 1675 1676 tlv = (void *)entry->data; 1677 tlv->type = cpu_to_le32(type); 1678 tlv->len = cpu_to_le32(size); 1679 1680 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: id=%d, type=%d\n", 1681 le32_to_cpu(reg->region_id), type); 1682 1683 num_of_ranges = ops->get_num_of_ranges(fwrt, reg); 1684 1685 header = (void *)tlv->data; 1686 header->region_id = reg->region_id; 1687 header->num_of_ranges = cpu_to_le32(num_of_ranges); 1688 header->name_len = cpu_to_le32(min_t(int, IWL_FW_INI_MAX_NAME, 1689 le32_to_cpu(reg->name_len))); 1690 memcpy(header->name, reg->name, le32_to_cpu(header->name_len)); 1691 1692 range = ops->fill_mem_hdr(fwrt, reg, header); 1693 if (!range) { 1694 IWL_ERR(fwrt, 1695 "WRT: Failed to fill region header: id=%d, type=%d\n", 1696 le32_to_cpu(reg->region_id), type); 1697 goto out_err; 1698 } 1699 1700 for (i = 0; i < num_of_ranges; i++) { 1701 int range_size = ops->fill_range(fwrt, reg, range, i); 1702 1703 if (range_size < 0) { 1704 IWL_ERR(fwrt, 1705 "WRT: Failed to dump region: id=%d, type=%d\n", 1706 le32_to_cpu(reg->region_id), type); 1707 goto out_err; 1708 } 1709 range = range + range_size; 1710 } 1711 1712 list_add_tail(&entry->list, list); 1713 1714 return entry->size; 1715 1716 out_err: 1717 kfree(entry); 1718 1719 return 0; 1720 } 1721 1722 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 1723 struct iwl_fw_ini_trigger *trigger, 1724 struct list_head *list) 1725 { 1726 struct iwl_fw_ini_dump_entry *entry; 1727 struct iwl_fw_error_dump_data *tlv; 1728 struct iwl_fw_ini_dump_info *dump; 1729 u32 reg_ids_size = le32_to_cpu(trigger->num_regions) * sizeof(__le32); 1730 u32 size = sizeof(*tlv) + sizeof(*dump) + reg_ids_size; 1731 1732 entry = kmalloc(sizeof(*entry) + size, GFP_KERNEL); 1733 if (!entry) 1734 return 0; 1735 1736 entry->size = size; 1737 1738 tlv = (void *)entry->data; 1739 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 1740 tlv->len = cpu_to_le32(sizeof(*dump) + reg_ids_size); 1741 1742 dump = (void *)tlv->data; 1743 1744 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 1745 dump->trigger_id = trigger->trigger_id; 1746 dump->is_external_cfg = 1747 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 1748 1749 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 1750 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 1751 1752 dump->hw_step = cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 1753 dump->hw_type = cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 1754 1755 dump->rf_id_flavor = 1756 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id)); 1757 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id)); 1758 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id)); 1759 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id)); 1760 1761 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 1762 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 1763 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 1764 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 1765 1766 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 1767 memcpy(dump->build_tag, fwrt->fw->human_readable, 1768 sizeof(dump->build_tag)); 1769 1770 dump->img_name_len = cpu_to_le32(sizeof(dump->img_name)); 1771 memcpy(dump->img_name, fwrt->dump.img_name, sizeof(dump->img_name)); 1772 1773 dump->internal_dbg_cfg_name_len = 1774 cpu_to_le32(sizeof(dump->internal_dbg_cfg_name)); 1775 memcpy(dump->internal_dbg_cfg_name, fwrt->dump.internal_dbg_cfg_name, 1776 sizeof(dump->internal_dbg_cfg_name)); 1777 1778 dump->external_dbg_cfg_name_len = 1779 cpu_to_le32(sizeof(dump->external_dbg_cfg_name)); 1780 1781 memcpy(dump->external_dbg_cfg_name, fwrt->dump.external_dbg_cfg_name, 1782 sizeof(dump->external_dbg_cfg_name)); 1783 1784 dump->regions_num = trigger->num_regions; 1785 memcpy(dump->region_ids, trigger->data, reg_ids_size); 1786 1787 /* add dump info TLV to the beginning of the list since it needs to be 1788 * the first TLV in the dump 1789 */ 1790 list_add(&entry->list, list); 1791 1792 return entry->size; 1793 } 1794 1795 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 1796 [IWL_FW_INI_REGION_INVALID] = {}, 1797 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 1798 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 1799 .get_size = iwl_dump_ini_mem_get_size, 1800 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1801 .fill_range = iwl_dump_ini_dev_mem_iter, 1802 }, 1803 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 1804 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 1805 .get_size = iwl_dump_ini_mem_get_size, 1806 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1807 .fill_range = iwl_dump_ini_prph_iter, 1808 }, 1809 [IWL_FW_INI_REGION_PERIPHERY_PHY] = {}, 1810 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 1811 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 1812 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 1813 .get_size = iwl_dump_ini_mon_dram_get_size, 1814 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 1815 .fill_range = iwl_dump_ini_mon_dram_iter, 1816 }, 1817 [IWL_FW_INI_REGION_DRAM_IMR] = {}, 1818 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 1819 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 1820 .get_size = iwl_dump_ini_mon_smem_get_size, 1821 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 1822 .fill_range = iwl_dump_ini_dev_mem_iter, 1823 }, 1824 [IWL_FW_INI_REGION_TXF] = { 1825 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 1826 .get_size = iwl_dump_ini_txf_get_size, 1827 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1828 .fill_range = iwl_dump_ini_txf_iter, 1829 }, 1830 [IWL_FW_INI_REGION_RXF] = { 1831 .get_num_of_ranges = iwl_dump_ini_rxf_ranges, 1832 .get_size = iwl_dump_ini_rxf_get_size, 1833 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1834 .fill_range = iwl_dump_ini_rxf_iter, 1835 }, 1836 [IWL_FW_INI_REGION_PAGING] = { 1837 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1838 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 1839 .get_size = iwl_dump_ini_paging_get_size, 1840 .fill_range = iwl_dump_ini_paging_iter, 1841 }, 1842 [IWL_FW_INI_REGION_CSR] = { 1843 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 1844 .get_size = iwl_dump_ini_mem_get_size, 1845 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1846 .fill_range = iwl_dump_ini_csr_iter, 1847 }, 1848 [IWL_FW_INI_REGION_NOTIFICATION] = {}, 1849 [IWL_FW_INI_REGION_DHC] = {}, 1850 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 1851 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 1852 .get_size = iwl_dump_ini_mem_get_size, 1853 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1854 .fill_range = iwl_dump_ini_dev_mem_iter, 1855 }, 1856 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 1857 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 1858 .get_size = iwl_dump_ini_mem_get_size, 1859 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1860 .fill_range = iwl_dump_ini_dev_mem_iter, 1861 }, 1862 }; 1863 1864 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 1865 struct iwl_fw_ini_trigger *trigger, 1866 struct list_head *list) 1867 { 1868 int i; 1869 u32 size = 0; 1870 1871 for (i = 0; i < le32_to_cpu(trigger->num_regions); i++) { 1872 u32 reg_id = le32_to_cpu(trigger->data[i]), reg_type; 1873 struct iwl_fw_ini_region_cfg *reg; 1874 1875 if (WARN_ON(reg_id >= ARRAY_SIZE(fwrt->dump.active_regs))) 1876 continue; 1877 1878 reg = fwrt->dump.active_regs[reg_id]; 1879 if (!reg) { 1880 IWL_WARN(fwrt, 1881 "WRT: Unassigned region id %d, skipping\n", 1882 reg_id); 1883 continue; 1884 } 1885 1886 /* currently the driver supports always on domain only */ 1887 if (le32_to_cpu(reg->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON) 1888 continue; 1889 1890 reg_type = le32_to_cpu(reg->region_type); 1891 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 1892 continue; 1893 1894 size += iwl_dump_ini_mem(fwrt, list, reg, 1895 &iwl_dump_ini_region_ops[reg_type]); 1896 } 1897 1898 if (size) 1899 size += iwl_dump_ini_info(fwrt, trigger, list); 1900 1901 return size; 1902 } 1903 1904 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 1905 enum iwl_fw_ini_trigger_id trig_id, 1906 struct list_head *list) 1907 { 1908 struct iwl_fw_ini_dump_entry *entry; 1909 struct iwl_fw_ini_dump_file_hdr *hdr; 1910 struct iwl_fw_ini_trigger *trigger; 1911 u32 size; 1912 1913 if (!iwl_fw_ini_trigger_on(fwrt, trig_id)) 1914 return 0; 1915 1916 trigger = fwrt->dump.active_trigs[trig_id].trig; 1917 if (!trigger || !le32_to_cpu(trigger->num_regions)) 1918 return 0; 1919 1920 entry = kmalloc(sizeof(*entry) + sizeof(*hdr), GFP_KERNEL); 1921 if (!entry) 1922 return 0; 1923 1924 entry->size = sizeof(*hdr); 1925 1926 size = iwl_dump_ini_trigger(fwrt, trigger, list); 1927 if (!size) { 1928 kfree(entry); 1929 return 0; 1930 } 1931 1932 hdr = (void *)entry->data; 1933 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 1934 hdr->file_len = cpu_to_le32(size + entry->size); 1935 1936 list_add(&entry->list, list); 1937 1938 return le32_to_cpu(hdr->file_len); 1939 } 1940 1941 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt) 1942 { 1943 struct iwl_fw_dump_ptrs fw_error_dump = {}; 1944 struct iwl_fw_error_dump_file *dump_file; 1945 struct scatterlist *sg_dump_data; 1946 u32 file_len; 1947 u32 dump_mask = fwrt->fw->dbg.dump_mask; 1948 1949 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump); 1950 if (!dump_file) 1951 goto out; 1952 1953 if (fwrt->dump.monitor_only) 1954 dump_mask &= IWL_FW_ERROR_DUMP_FW_MONITOR; 1955 1956 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask); 1957 file_len = le32_to_cpu(dump_file->file_len); 1958 fw_error_dump.fwrt_len = file_len; 1959 1960 if (fw_error_dump.trans_ptr) { 1961 file_len += fw_error_dump.trans_ptr->len; 1962 dump_file->file_len = cpu_to_le32(file_len); 1963 } 1964 1965 sg_dump_data = alloc_sgtable(file_len); 1966 if (sg_dump_data) { 1967 sg_pcopy_from_buffer(sg_dump_data, 1968 sg_nents(sg_dump_data), 1969 fw_error_dump.fwrt_ptr, 1970 fw_error_dump.fwrt_len, 0); 1971 if (fw_error_dump.trans_ptr) 1972 sg_pcopy_from_buffer(sg_dump_data, 1973 sg_nents(sg_dump_data), 1974 fw_error_dump.trans_ptr->data, 1975 fw_error_dump.trans_ptr->len, 1976 fw_error_dump.fwrt_len); 1977 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 1978 GFP_KERNEL); 1979 } 1980 vfree(fw_error_dump.fwrt_ptr); 1981 vfree(fw_error_dump.trans_ptr); 1982 1983 out: 1984 iwl_fw_free_dump_desc(fwrt); 1985 } 1986 1987 static void iwl_dump_ini_list_free(struct list_head *list) 1988 { 1989 while (!list_empty(list)) { 1990 struct iwl_fw_ini_dump_entry *entry = 1991 list_entry(list->next, typeof(*entry), list); 1992 1993 list_del(&entry->list); 1994 kfree(entry); 1995 } 1996 } 1997 1998 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, u8 wk_idx) 1999 { 2000 enum iwl_fw_ini_trigger_id trig_id = fwrt->dump.wks[wk_idx].ini_trig_id; 2001 struct list_head dump_list = LIST_HEAD_INIT(dump_list); 2002 struct scatterlist *sg_dump_data; 2003 u32 file_len; 2004 2005 file_len = iwl_dump_ini_file_gen(fwrt, trig_id, &dump_list); 2006 if (!file_len) 2007 goto out; 2008 2009 sg_dump_data = alloc_sgtable(file_len); 2010 if (sg_dump_data) { 2011 struct iwl_fw_ini_dump_entry *entry; 2012 int sg_entries = sg_nents(sg_dump_data); 2013 u32 offs = 0; 2014 2015 list_for_each_entry(entry, &dump_list, list) { 2016 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2017 entry->data, entry->size, offs); 2018 offs += entry->size; 2019 } 2020 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2021 GFP_KERNEL); 2022 } 2023 iwl_dump_ini_list_free(&dump_list); 2024 2025 out: 2026 fwrt->dump.wks[wk_idx].ini_trig_id = IWL_FW_TRIGGER_ID_INVALID; 2027 } 2028 2029 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2030 .trig_desc = { 2031 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2032 }, 2033 }; 2034 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2035 2036 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2037 const struct iwl_fw_dump_desc *desc, 2038 bool monitor_only, 2039 unsigned int delay) 2040 { 2041 u32 trig_type = le32_to_cpu(desc->trig_desc.type); 2042 int ret; 2043 2044 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2045 ret = iwl_fw_dbg_ini_collect(fwrt, trig_type); 2046 if (!ret) 2047 iwl_fw_free_dump_desc(fwrt); 2048 2049 return ret; 2050 } 2051 2052 /* use wks[0] since dump flow prior to ini does not need to support 2053 * consecutive triggers collection 2054 */ 2055 if (test_and_set_bit(fwrt->dump.wks[0].idx, &fwrt->dump.active_wks)) 2056 return -EBUSY; 2057 2058 if (WARN_ON(fwrt->dump.desc)) 2059 iwl_fw_free_dump_desc(fwrt); 2060 2061 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2062 le32_to_cpu(desc->trig_desc.type)); 2063 2064 fwrt->dump.desc = desc; 2065 fwrt->dump.monitor_only = monitor_only; 2066 2067 schedule_delayed_work(&fwrt->dump.wks[0].wk, usecs_to_jiffies(delay)); 2068 2069 return 0; 2070 } 2071 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2072 2073 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2074 enum iwl_fw_dbg_trigger trig_type) 2075 { 2076 int ret; 2077 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2078 2079 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2080 return -EIO; 2081 2082 iwl_dump_error_desc = kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2083 if (!iwl_dump_error_desc) 2084 return -ENOMEM; 2085 2086 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2087 iwl_dump_error_desc->len = 0; 2088 2089 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, false, 0); 2090 if (ret) 2091 kfree(iwl_dump_error_desc); 2092 else 2093 iwl_trans_sync_nmi(fwrt->trans); 2094 2095 return ret; 2096 } 2097 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2098 2099 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2100 enum iwl_fw_dbg_trigger trig, 2101 const char *str, size_t len, 2102 struct iwl_fw_dbg_trigger_tlv *trigger) 2103 { 2104 struct iwl_fw_dump_desc *desc; 2105 unsigned int delay = 0; 2106 bool monitor_only = false; 2107 2108 if (trigger) { 2109 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2110 2111 if (!le16_to_cpu(trigger->occurrences)) 2112 return 0; 2113 2114 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2115 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2116 trig); 2117 iwl_force_nmi(fwrt->trans); 2118 return 0; 2119 } 2120 2121 trigger->occurrences = cpu_to_le16(occurrences); 2122 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2123 2124 /* convert msec to usec */ 2125 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2126 } 2127 2128 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 2129 if (!desc) 2130 return -ENOMEM; 2131 2132 2133 desc->len = len; 2134 desc->trig_desc.type = cpu_to_le32(trig); 2135 memcpy(desc->trig_desc.data, str, len); 2136 2137 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2138 } 2139 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2140 2141 int _iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 2142 enum iwl_fw_ini_trigger_id id) 2143 { 2144 struct iwl_fw_ini_active_triggers *active; 2145 u32 occur, delay; 2146 unsigned long idx; 2147 2148 if (WARN_ON(!iwl_fw_ini_trigger_on(fwrt, id))) 2149 return -EINVAL; 2150 2151 if (!iwl_fw_ini_trigger_on(fwrt, id)) { 2152 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 2153 id); 2154 return -EINVAL; 2155 } 2156 2157 active = &fwrt->dump.active_trigs[id]; 2158 delay = le32_to_cpu(active->trig->dump_delay); 2159 occur = le32_to_cpu(active->trig->occurrences); 2160 if (!occur) 2161 return 0; 2162 2163 active->trig->occurrences = cpu_to_le32(--occur); 2164 2165 if (le32_to_cpu(active->trig->force_restart)) { 2166 IWL_WARN(fwrt, "WRT: Force restart: trigger %d fired.\n", id); 2167 iwl_force_nmi(fwrt->trans); 2168 return 0; 2169 } 2170 2171 /* Check there is an available worker. 2172 * ffz return value is undefined if no zero exists, 2173 * so check against ~0UL first. 2174 */ 2175 if (fwrt->dump.active_wks == ~0UL) 2176 return -EBUSY; 2177 2178 idx = ffz(fwrt->dump.active_wks); 2179 2180 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2181 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2182 return -EBUSY; 2183 2184 fwrt->dump.wks[idx].ini_trig_id = id; 2185 2186 IWL_WARN(fwrt, "WRT: Collecting data: ini trigger %d fired.\n", id); 2187 2188 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay)); 2189 2190 return 0; 2191 } 2192 IWL_EXPORT_SYMBOL(_iwl_fw_dbg_ini_collect); 2193 2194 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, u32 legacy_trigger_id) 2195 { 2196 int id; 2197 2198 switch (legacy_trigger_id) { 2199 case FW_DBG_TRIGGER_FW_ASSERT: 2200 case FW_DBG_TRIGGER_ALIVE_TIMEOUT: 2201 case FW_DBG_TRIGGER_DRIVER: 2202 id = IWL_FW_TRIGGER_ID_FW_ASSERT; 2203 break; 2204 case FW_DBG_TRIGGER_USER: 2205 id = IWL_FW_TRIGGER_ID_USER_TRIGGER; 2206 break; 2207 default: 2208 return -EIO; 2209 } 2210 2211 return _iwl_fw_dbg_ini_collect(fwrt, id); 2212 } 2213 IWL_EXPORT_SYMBOL(iwl_fw_dbg_ini_collect); 2214 2215 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2216 struct iwl_fw_dbg_trigger_tlv *trigger, 2217 const char *fmt, ...) 2218 { 2219 int ret, len = 0; 2220 char buf[64]; 2221 2222 if (fmt) { 2223 va_list ap; 2224 2225 buf[sizeof(buf) - 1] = '\0'; 2226 2227 va_start(ap, fmt); 2228 vsnprintf(buf, sizeof(buf), fmt, ap); 2229 va_end(ap); 2230 2231 /* check for truncation */ 2232 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2233 buf[sizeof(buf) - 1] = '\0'; 2234 2235 len = strlen(buf) + 1; 2236 } 2237 2238 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2239 trigger); 2240 2241 if (ret) 2242 return ret; 2243 2244 return 0; 2245 } 2246 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2247 2248 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2249 { 2250 u8 *ptr; 2251 int ret; 2252 int i; 2253 2254 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 2255 "Invalid configuration %d\n", conf_id)) 2256 return -EINVAL; 2257 2258 /* EARLY START - firmware's configuration is hard coded */ 2259 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 2260 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 2261 conf_id == FW_DBG_START_FROM_ALIVE) 2262 return 0; 2263 2264 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 2265 return -EINVAL; 2266 2267 if (fwrt->dump.conf != FW_DBG_INVALID) 2268 IWL_WARN(fwrt, "FW already configured (%d) - re-configuring\n", 2269 fwrt->dump.conf); 2270 2271 /* Send all HCMDs for configuring the FW debug */ 2272 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 2273 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 2274 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 2275 struct iwl_host_cmd hcmd = { 2276 .id = cmd->id, 2277 .len = { le16_to_cpu(cmd->len), }, 2278 .data = { cmd->data, }, 2279 }; 2280 2281 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 2282 if (ret) 2283 return ret; 2284 2285 ptr += sizeof(*cmd); 2286 ptr += le16_to_cpu(cmd->len); 2287 } 2288 2289 fwrt->dump.conf = conf_id; 2290 2291 return 0; 2292 } 2293 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 2294 2295 /* this function assumes dump_start was called beforehand and dump_end will be 2296 * called afterwards 2297 */ 2298 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 2299 { 2300 struct iwl_fw_dbg_params params = {0}; 2301 2302 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 2303 return; 2304 2305 if (fwrt->ops && fwrt->ops->fw_running && 2306 !fwrt->ops->fw_running(fwrt->ops_ctx)) { 2307 IWL_ERR(fwrt, "Firmware not running - cannot dump error\n"); 2308 iwl_fw_free_dump_desc(fwrt); 2309 goto out; 2310 } 2311 2312 /* there's no point in fw dump if the bus is dead */ 2313 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 2314 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 2315 goto out; 2316 } 2317 2318 if (iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true)) { 2319 IWL_ERR(fwrt, "Failed to stop DBGC recording, aborting dump\n"); 2320 goto out; 2321 } 2322 2323 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 2324 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2325 iwl_fw_error_ini_dump(fwrt, wk_idx); 2326 else 2327 iwl_fw_error_dump(fwrt); 2328 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 2329 2330 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 2331 2332 out: 2333 clear_bit(wk_idx, &fwrt->dump.active_wks); 2334 } 2335 2336 void iwl_fw_error_dump_wk(struct work_struct *work) 2337 { 2338 struct iwl_fw_runtime *fwrt; 2339 typeof(fwrt->dump.wks[0]) *wks; 2340 2341 wks = container_of(work, typeof(fwrt->dump.wks[0]), wk.work); 2342 fwrt = container_of(wks, struct iwl_fw_runtime, dump.wks[wks->idx]); 2343 2344 /* assumes the op mode mutex is locked in dump_start since 2345 * iwl_fw_dbg_collect_sync can't run in parallel 2346 */ 2347 if (fwrt->ops && fwrt->ops->dump_start && 2348 fwrt->ops->dump_start(fwrt->ops_ctx)) 2349 return; 2350 2351 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 2352 2353 if (fwrt->ops && fwrt->ops->dump_end) 2354 fwrt->ops->dump_end(fwrt->ops_ctx); 2355 } 2356 2357 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 2358 { 2359 const struct iwl_cfg *cfg = fwrt->trans->cfg; 2360 2361 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 2362 return; 2363 2364 if (!fwrt->dump.d3_debug_data) { 2365 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 2366 GFP_KERNEL); 2367 if (!fwrt->dump.d3_debug_data) { 2368 IWL_ERR(fwrt, 2369 "failed to allocate memory for D3 debug data\n"); 2370 return; 2371 } 2372 } 2373 2374 /* if the buffer holds previous debug data it is overwritten */ 2375 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 2376 fwrt->dump.d3_debug_data, 2377 cfg->d3_debug_data_length); 2378 } 2379 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 2380 2381 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 2382 { 2383 int i; 2384 2385 iwl_dbg_tlv_del_timers(fwrt->trans); 2386 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 2387 iwl_fw_dbg_collect_sync(fwrt, i); 2388 2389 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 2390 } 2391 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 2392 2393 #define FSEQ_REG(x) { .addr = (x), .str = #x, } 2394 2395 void iwl_fw_error_print_fseq_regs(struct iwl_fw_runtime *fwrt) 2396 { 2397 struct iwl_trans *trans = fwrt->trans; 2398 unsigned long flags; 2399 int i; 2400 struct { 2401 u32 addr; 2402 const char *str; 2403 } fseq_regs[] = { 2404 FSEQ_REG(FSEQ_ERROR_CODE), 2405 FSEQ_REG(FSEQ_TOP_INIT_VERSION), 2406 FSEQ_REG(FSEQ_CNVIO_INIT_VERSION), 2407 FSEQ_REG(FSEQ_OTP_VERSION), 2408 FSEQ_REG(FSEQ_TOP_CONTENT_VERSION), 2409 FSEQ_REG(FSEQ_ALIVE_TOKEN), 2410 FSEQ_REG(FSEQ_CNVI_ID), 2411 FSEQ_REG(FSEQ_CNVR_ID), 2412 FSEQ_REG(CNVI_AUX_MISC_CHIP), 2413 FSEQ_REG(CNVR_AUX_MISC_CHIP), 2414 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM), 2415 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR), 2416 }; 2417 2418 if (!iwl_trans_grab_nic_access(trans, &flags)) 2419 return; 2420 2421 IWL_ERR(fwrt, "Fseq Registers:\n"); 2422 2423 for (i = 0; i < ARRAY_SIZE(fseq_regs); i++) 2424 IWL_ERR(fwrt, "0x%08X | %s\n", 2425 iwl_read_prph_no_grab(trans, fseq_regs[i].addr), 2426 fseq_regs[i].str); 2427 2428 iwl_trans_release_nic_access(trans, &flags); 2429 } 2430 IWL_EXPORT_SYMBOL(iwl_fw_error_print_fseq_regs); 2431 2432 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 2433 { 2434 struct iwl_dbg_suspend_resume_cmd cmd = { 2435 .operation = suspend ? 2436 cpu_to_le32(DBGC_SUSPEND_CMD) : 2437 cpu_to_le32(DBGC_RESUME_CMD), 2438 }; 2439 struct iwl_host_cmd hcmd = { 2440 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 2441 .data[0] = &cmd, 2442 .len[0] = sizeof(cmd), 2443 }; 2444 2445 return iwl_trans_send_cmd(trans, &hcmd); 2446 } 2447 2448 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 2449 struct iwl_fw_dbg_params *params) 2450 { 2451 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 2452 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 2453 return; 2454 } 2455 2456 if (params) { 2457 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 2458 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 2459 } 2460 2461 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 2462 /* wait for the DBGC to finish writing the internal buffer to DRAM to 2463 * avoid halting the HW while writing 2464 */ 2465 usleep_range(700, 1000); 2466 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 2467 } 2468 2469 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 2470 struct iwl_fw_dbg_params *params) 2471 { 2472 if (!params) 2473 return -EIO; 2474 2475 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 2476 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 2477 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 2478 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 2479 } else { 2480 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 2481 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 2482 } 2483 2484 return 0; 2485 } 2486 2487 int iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 2488 struct iwl_fw_dbg_params *params, 2489 bool stop) 2490 { 2491 int ret = 0; 2492 2493 /* if the FW crashed or not debug monitor cfg was given, there is 2494 * no point in changing the recording state 2495 */ 2496 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status) || 2497 (!fwrt->trans->dbg.dest_tlv && 2498 fwrt->trans->dbg.ini_dest == IWL_FW_INI_LOCATION_INVALID)) 2499 return 0; 2500 2501 if (fw_has_capa(&fwrt->fw->ucode_capa, 2502 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) 2503 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 2504 else if (stop) 2505 iwl_fw_dbg_stop_recording(fwrt->trans, params); 2506 else 2507 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 2508 #ifdef CONFIG_IWLWIFI_DEBUGFS 2509 if (!ret) { 2510 if (stop) 2511 fwrt->trans->dbg.rec_on = false; 2512 else 2513 iwl_fw_set_dbg_rec_on(fwrt); 2514 } 2515 #endif 2516 2517 return ret; 2518 } 2519 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 2520