1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; 24 * 25 * The full GNU General Public License is included in this distribution 26 * in the file called COPYING. 27 * 28 * Contact Information: 29 * Intel Linux Wireless <linuxwifi@intel.com> 30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 31 * 32 * BSD LICENSE 33 * 34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 35 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 36 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 37 * Copyright(c) 2018 Intel Corporation 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 44 * * Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * * Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in 48 * the documentation and/or other materials provided with the 49 * distribution. 50 * * Neither the name Intel Corporation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 *****************************************************************************/ 67 #include <linux/devcoredump.h> 68 #include "iwl-drv.h" 69 #include "runtime.h" 70 #include "dbg.h" 71 #include "debugfs.h" 72 #include "iwl-io.h" 73 #include "iwl-prph.h" 74 #include "iwl-csr.h" 75 76 /** 77 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 78 * 79 * @fwrt_ptr: pointer to the buffer coming from fwrt 80 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 81 * transport's data. 82 * @trans_len: length of the valid data in trans_ptr 83 * @fwrt_len: length of the valid data in fwrt_ptr 84 */ 85 struct iwl_fw_dump_ptrs { 86 struct iwl_trans_dump_data *trans_ptr; 87 void *fwrt_ptr; 88 u32 fwrt_len; 89 }; 90 91 #define RADIO_REG_MAX_READ 0x2ad 92 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 93 struct iwl_fw_error_dump_data **dump_data) 94 { 95 u8 *pos = (void *)(*dump_data)->data; 96 unsigned long flags; 97 int i; 98 99 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 100 101 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 102 return; 103 104 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 105 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 106 107 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 108 u32 rd_cmd = RADIO_RSP_RD_CMD; 109 110 rd_cmd |= i << RADIO_RSP_ADDR_POS; 111 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 112 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 113 114 pos++; 115 } 116 117 *dump_data = iwl_fw_error_next_data(*dump_data); 118 119 iwl_trans_release_nic_access(fwrt->trans, &flags); 120 } 121 122 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 123 struct iwl_fw_error_dump_data **dump_data, 124 int size, u32 offset, int fifo_num) 125 { 126 struct iwl_fw_error_dump_fifo *fifo_hdr; 127 u32 *fifo_data; 128 u32 fifo_len; 129 int i; 130 131 fifo_hdr = (void *)(*dump_data)->data; 132 fifo_data = (void *)fifo_hdr->data; 133 fifo_len = size; 134 135 /* No need to try to read the data if the length is 0 */ 136 if (fifo_len == 0) 137 return; 138 139 /* Add a TLV for the RXF */ 140 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 141 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 142 143 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 144 fifo_hdr->available_bytes = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 RXF_RD_D_SPACE + offset)); 147 fifo_hdr->wr_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 RXF_RD_WR_PTR + offset)); 150 fifo_hdr->rd_ptr = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 RXF_RD_RD_PTR + offset)); 153 fifo_hdr->fence_ptr = 154 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 155 RXF_RD_FENCE_PTR + offset)); 156 fifo_hdr->fence_mode = 157 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 158 RXF_SET_FENCE_MODE + offset)); 159 160 /* Lock fence */ 161 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 162 /* Set fence pointer to the same place like WR pointer */ 163 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 164 /* Set fence offset */ 165 iwl_trans_write_prph(fwrt->trans, 166 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 167 168 /* Read FIFO */ 169 fifo_len /= sizeof(u32); /* Size in DWORDS */ 170 for (i = 0; i < fifo_len; i++) 171 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 172 RXF_FIFO_RD_FENCE_INC + 173 offset); 174 *dump_data = iwl_fw_error_next_data(*dump_data); 175 } 176 177 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 178 struct iwl_fw_error_dump_data **dump_data, 179 int size, u32 offset, int fifo_num) 180 { 181 struct iwl_fw_error_dump_fifo *fifo_hdr; 182 u32 *fifo_data; 183 u32 fifo_len; 184 int i; 185 186 fifo_hdr = (void *)(*dump_data)->data; 187 fifo_data = (void *)fifo_hdr->data; 188 fifo_len = size; 189 190 /* No need to try to read the data if the length is 0 */ 191 if (fifo_len == 0) 192 return; 193 194 /* Add a TLV for the FIFO */ 195 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 196 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 197 198 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 199 fifo_hdr->available_bytes = 200 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 201 TXF_FIFO_ITEM_CNT + offset)); 202 fifo_hdr->wr_ptr = 203 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 204 TXF_WR_PTR + offset)); 205 fifo_hdr->rd_ptr = 206 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 207 TXF_RD_PTR + offset)); 208 fifo_hdr->fence_ptr = 209 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 210 TXF_FENCE_PTR + offset)); 211 fifo_hdr->fence_mode = 212 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 213 TXF_LOCK_FENCE + offset)); 214 215 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 216 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 217 TXF_WR_PTR + offset); 218 219 /* Dummy-read to advance the read pointer to the head */ 220 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 221 222 /* Read FIFO */ 223 fifo_len /= sizeof(u32); /* Size in DWORDS */ 224 for (i = 0; i < fifo_len; i++) 225 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 226 TXF_READ_MODIFY_DATA + 227 offset); 228 *dump_data = iwl_fw_error_next_data(*dump_data); 229 } 230 231 static void iwl_fw_dump_fifos(struct iwl_fw_runtime *fwrt, 232 struct iwl_fw_error_dump_data **dump_data) 233 { 234 struct iwl_fw_error_dump_fifo *fifo_hdr; 235 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 236 u32 *fifo_data; 237 u32 fifo_len; 238 unsigned long flags; 239 int i, j; 240 241 IWL_DEBUG_INFO(fwrt, "WRT FIFO dump\n"); 242 243 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 244 return; 245 246 /* Pull RXF1 */ 247 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->lmac[0].rxfifo1_size, 0, 0); 248 /* Pull RXF2 */ 249 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 250 RXF_DIFF_FROM_PREV, 1); 251 /* Pull LMAC2 RXF1 */ 252 if (fwrt->smem_cfg.num_lmacs > 1) 253 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->lmac[1].rxfifo1_size, 254 LMAC2_PRPH_OFFSET, 2); 255 256 /* Pull TXF data from LMAC1 */ 257 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 258 /* Mark the number of TXF we're pulling now */ 259 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 260 iwl_fwrt_dump_txf(fwrt, dump_data, cfg->lmac[0].txfifo_size[i], 261 0, i); 262 } 263 264 /* Pull TXF data from LMAC2 */ 265 if (fwrt->smem_cfg.num_lmacs > 1) { 266 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 267 /* Mark the number of TXF we're pulling now */ 268 iwl_trans_write_prph(fwrt->trans, 269 TXF_LARC_NUM + LMAC2_PRPH_OFFSET, 270 i); 271 iwl_fwrt_dump_txf(fwrt, dump_data, 272 cfg->lmac[1].txfifo_size[i], 273 LMAC2_PRPH_OFFSET, 274 i + cfg->num_txfifo_entries); 275 } 276 } 277 278 if (fw_has_capa(&fwrt->fw->ucode_capa, 279 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 280 /* Pull UMAC internal TXF data from all TXFs */ 281 for (i = 0; 282 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 283 i++) { 284 fifo_hdr = (void *)(*dump_data)->data; 285 fifo_data = (void *)fifo_hdr->data; 286 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 287 288 /* No need to try to read the data if the length is 0 */ 289 if (fifo_len == 0) 290 continue; 291 292 /* Add a TLV for the internal FIFOs */ 293 (*dump_data)->type = 294 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 295 (*dump_data)->len = 296 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 297 298 fifo_hdr->fifo_num = cpu_to_le32(i); 299 300 /* Mark the number of TXF we're pulling now */ 301 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 302 fwrt->smem_cfg.num_txfifo_entries); 303 304 fifo_hdr->available_bytes = 305 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 306 TXF_CPU2_FIFO_ITEM_CNT)); 307 fifo_hdr->wr_ptr = 308 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 309 TXF_CPU2_WR_PTR)); 310 fifo_hdr->rd_ptr = 311 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 312 TXF_CPU2_RD_PTR)); 313 fifo_hdr->fence_ptr = 314 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 315 TXF_CPU2_FENCE_PTR)); 316 fifo_hdr->fence_mode = 317 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 318 TXF_CPU2_LOCK_FENCE)); 319 320 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 321 iwl_trans_write_prph(fwrt->trans, 322 TXF_CPU2_READ_MODIFY_ADDR, 323 TXF_CPU2_WR_PTR); 324 325 /* Dummy-read to advance the read pointer to head */ 326 iwl_trans_read_prph(fwrt->trans, 327 TXF_CPU2_READ_MODIFY_DATA); 328 329 /* Read FIFO */ 330 fifo_len /= sizeof(u32); /* Size in DWORDS */ 331 for (j = 0; j < fifo_len; j++) 332 fifo_data[j] = 333 iwl_trans_read_prph(fwrt->trans, 334 TXF_CPU2_READ_MODIFY_DATA); 335 *dump_data = iwl_fw_error_next_data(*dump_data); 336 } 337 } 338 339 iwl_trans_release_nic_access(fwrt->trans, &flags); 340 } 341 342 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ 343 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ 344 345 struct iwl_prph_range { 346 u32 start, end; 347 }; 348 349 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 350 { .start = 0x00a00000, .end = 0x00a00000 }, 351 { .start = 0x00a0000c, .end = 0x00a00024 }, 352 { .start = 0x00a0002c, .end = 0x00a0003c }, 353 { .start = 0x00a00410, .end = 0x00a00418 }, 354 { .start = 0x00a00420, .end = 0x00a00420 }, 355 { .start = 0x00a00428, .end = 0x00a00428 }, 356 { .start = 0x00a00430, .end = 0x00a0043c }, 357 { .start = 0x00a00444, .end = 0x00a00444 }, 358 { .start = 0x00a004c0, .end = 0x00a004cc }, 359 { .start = 0x00a004d8, .end = 0x00a004d8 }, 360 { .start = 0x00a004e0, .end = 0x00a004f0 }, 361 { .start = 0x00a00840, .end = 0x00a00840 }, 362 { .start = 0x00a00850, .end = 0x00a00858 }, 363 { .start = 0x00a01004, .end = 0x00a01008 }, 364 { .start = 0x00a01010, .end = 0x00a01010 }, 365 { .start = 0x00a01018, .end = 0x00a01018 }, 366 { .start = 0x00a01024, .end = 0x00a01024 }, 367 { .start = 0x00a0102c, .end = 0x00a01034 }, 368 { .start = 0x00a0103c, .end = 0x00a01040 }, 369 { .start = 0x00a01048, .end = 0x00a01094 }, 370 { .start = 0x00a01c00, .end = 0x00a01c20 }, 371 { .start = 0x00a01c58, .end = 0x00a01c58 }, 372 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 373 { .start = 0x00a01c28, .end = 0x00a01c54 }, 374 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 375 { .start = 0x00a01c60, .end = 0x00a01cdc }, 376 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 377 { .start = 0x00a01d18, .end = 0x00a01d20 }, 378 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 379 { .start = 0x00a01d40, .end = 0x00a01d5c }, 380 { .start = 0x00a01d80, .end = 0x00a01d80 }, 381 { .start = 0x00a01d98, .end = 0x00a01d9c }, 382 { .start = 0x00a01da8, .end = 0x00a01da8 }, 383 { .start = 0x00a01db8, .end = 0x00a01df4 }, 384 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 385 { .start = 0x00a01e00, .end = 0x00a01e2c }, 386 { .start = 0x00a01e40, .end = 0x00a01e60 }, 387 { .start = 0x00a01e68, .end = 0x00a01e6c }, 388 { .start = 0x00a01e74, .end = 0x00a01e74 }, 389 { .start = 0x00a01e84, .end = 0x00a01e90 }, 390 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 391 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 392 { .start = 0x00a01f00, .end = 0x00a01f1c }, 393 { .start = 0x00a01f44, .end = 0x00a01ffc }, 394 { .start = 0x00a02000, .end = 0x00a02048 }, 395 { .start = 0x00a02068, .end = 0x00a020f0 }, 396 { .start = 0x00a02100, .end = 0x00a02118 }, 397 { .start = 0x00a02140, .end = 0x00a0214c }, 398 { .start = 0x00a02168, .end = 0x00a0218c }, 399 { .start = 0x00a021c0, .end = 0x00a021c0 }, 400 { .start = 0x00a02400, .end = 0x00a02410 }, 401 { .start = 0x00a02418, .end = 0x00a02420 }, 402 { .start = 0x00a02428, .end = 0x00a0242c }, 403 { .start = 0x00a02434, .end = 0x00a02434 }, 404 { .start = 0x00a02440, .end = 0x00a02460 }, 405 { .start = 0x00a02468, .end = 0x00a024b0 }, 406 { .start = 0x00a024c8, .end = 0x00a024cc }, 407 { .start = 0x00a02500, .end = 0x00a02504 }, 408 { .start = 0x00a0250c, .end = 0x00a02510 }, 409 { .start = 0x00a02540, .end = 0x00a02554 }, 410 { .start = 0x00a02580, .end = 0x00a025f4 }, 411 { .start = 0x00a02600, .end = 0x00a0260c }, 412 { .start = 0x00a02648, .end = 0x00a02650 }, 413 { .start = 0x00a02680, .end = 0x00a02680 }, 414 { .start = 0x00a026c0, .end = 0x00a026d0 }, 415 { .start = 0x00a02700, .end = 0x00a0270c }, 416 { .start = 0x00a02804, .end = 0x00a02804 }, 417 { .start = 0x00a02818, .end = 0x00a0281c }, 418 { .start = 0x00a02c00, .end = 0x00a02db4 }, 419 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 420 { .start = 0x00a03000, .end = 0x00a03014 }, 421 { .start = 0x00a0301c, .end = 0x00a0302c }, 422 { .start = 0x00a03034, .end = 0x00a03038 }, 423 { .start = 0x00a03040, .end = 0x00a03048 }, 424 { .start = 0x00a03060, .end = 0x00a03068 }, 425 { .start = 0x00a03070, .end = 0x00a03074 }, 426 { .start = 0x00a0307c, .end = 0x00a0307c }, 427 { .start = 0x00a03080, .end = 0x00a03084 }, 428 { .start = 0x00a0308c, .end = 0x00a03090 }, 429 { .start = 0x00a03098, .end = 0x00a03098 }, 430 { .start = 0x00a030a0, .end = 0x00a030a0 }, 431 { .start = 0x00a030a8, .end = 0x00a030b4 }, 432 { .start = 0x00a030bc, .end = 0x00a030bc }, 433 { .start = 0x00a030c0, .end = 0x00a0312c }, 434 { .start = 0x00a03c00, .end = 0x00a03c5c }, 435 { .start = 0x00a04400, .end = 0x00a04454 }, 436 { .start = 0x00a04460, .end = 0x00a04474 }, 437 { .start = 0x00a044c0, .end = 0x00a044ec }, 438 { .start = 0x00a04500, .end = 0x00a04504 }, 439 { .start = 0x00a04510, .end = 0x00a04538 }, 440 { .start = 0x00a04540, .end = 0x00a04548 }, 441 { .start = 0x00a04560, .end = 0x00a0457c }, 442 { .start = 0x00a04590, .end = 0x00a04598 }, 443 { .start = 0x00a045c0, .end = 0x00a045f4 }, 444 }; 445 446 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 447 { .start = 0x00a05c00, .end = 0x00a05c18 }, 448 { .start = 0x00a05400, .end = 0x00a056e8 }, 449 { .start = 0x00a08000, .end = 0x00a098bc }, 450 { .start = 0x00a02400, .end = 0x00a02758 }, 451 }; 452 453 static void _iwl_read_prph_block(struct iwl_trans *trans, u32 start, 454 u32 len_bytes, __le32 *data) 455 { 456 u32 i; 457 458 for (i = 0; i < len_bytes; i += 4) 459 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 460 } 461 462 static bool iwl_read_prph_block(struct iwl_trans *trans, u32 start, 463 u32 len_bytes, __le32 *data) 464 { 465 unsigned long flags; 466 bool success = false; 467 468 if (iwl_trans_grab_nic_access(trans, &flags)) { 469 success = true; 470 _iwl_read_prph_block(trans, start, len_bytes, data); 471 iwl_trans_release_nic_access(trans, &flags); 472 } 473 474 return success; 475 } 476 477 static void iwl_dump_prph(struct iwl_trans *trans, 478 struct iwl_fw_error_dump_data **data, 479 const struct iwl_prph_range *iwl_prph_dump_addr, 480 u32 range_len) 481 { 482 struct iwl_fw_error_dump_prph *prph; 483 unsigned long flags; 484 u32 i; 485 486 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 487 488 if (!iwl_trans_grab_nic_access(trans, &flags)) 489 return; 490 491 for (i = 0; i < range_len; i++) { 492 /* The range includes both boundaries */ 493 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 494 iwl_prph_dump_addr[i].start + 4; 495 496 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 497 (*data)->len = cpu_to_le32(sizeof(*prph) + 498 num_bytes_in_chunk); 499 prph = (void *)(*data)->data; 500 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 501 502 _iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 503 /* our range is inclusive, hence + 4 */ 504 iwl_prph_dump_addr[i].end - 505 iwl_prph_dump_addr[i].start + 4, 506 (void *)prph->data); 507 508 *data = iwl_fw_error_next_data(*data); 509 } 510 511 iwl_trans_release_nic_access(trans, &flags); 512 } 513 514 /* 515 * alloc_sgtable - allocates scallerlist table in the given size, 516 * fills it with pages and returns it 517 * @size: the size (in bytes) of the table 518 */ 519 static struct scatterlist *alloc_sgtable(int size) 520 { 521 int alloc_size, nents, i; 522 struct page *new_page; 523 struct scatterlist *iter; 524 struct scatterlist *table; 525 526 nents = DIV_ROUND_UP(size, PAGE_SIZE); 527 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 528 if (!table) 529 return NULL; 530 sg_init_table(table, nents); 531 iter = table; 532 for_each_sg(table, iter, sg_nents(table), i) { 533 new_page = alloc_page(GFP_KERNEL); 534 if (!new_page) { 535 /* release all previous allocated pages in the table */ 536 iter = table; 537 for_each_sg(table, iter, sg_nents(table), i) { 538 new_page = sg_page(iter); 539 if (new_page) 540 __free_page(new_page); 541 } 542 return NULL; 543 } 544 alloc_size = min_t(int, size, PAGE_SIZE); 545 size -= PAGE_SIZE; 546 sg_set_page(iter, new_page, alloc_size, 0); 547 } 548 return table; 549 } 550 551 void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt) 552 { 553 struct iwl_fw_error_dump_file *dump_file; 554 struct iwl_fw_error_dump_data *dump_data; 555 struct iwl_fw_error_dump_info *dump_info; 556 struct iwl_fw_error_dump_mem *dump_mem; 557 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 558 struct iwl_fw_error_dump_trigger_desc *dump_trig; 559 struct iwl_fw_dump_ptrs *fw_error_dump; 560 struct scatterlist *sg_dump_data; 561 u32 sram_len, sram_ofs; 562 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = fwrt->fw->dbg_mem_tlv; 563 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 564 u32 file_len, fifo_data_len = 0, prph_len = 0, radio_len = 0; 565 u32 smem_len = fwrt->fw->n_dbg_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 566 u32 sram2_len = fwrt->fw->n_dbg_mem_tlv ? 567 0 : fwrt->trans->cfg->dccm2_len; 568 bool monitor_dump_only = false; 569 int i; 570 571 IWL_DEBUG_INFO(fwrt, "WRT dump start\n"); 572 573 /* there's no point in fw dump if the bus is dead */ 574 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 575 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 576 goto out; 577 } 578 579 if (fwrt->dump.trig && 580 fwrt->dump.trig->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY) 581 monitor_dump_only = true; 582 583 fw_error_dump = kzalloc(sizeof(*fw_error_dump), GFP_KERNEL); 584 if (!fw_error_dump) 585 goto out; 586 587 /* SRAM - include stack CCM if driver knows the values for it */ 588 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 589 const struct fw_img *img; 590 591 img = &fwrt->fw->img[fwrt->cur_fw_img]; 592 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 593 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 594 } else { 595 sram_ofs = fwrt->trans->cfg->dccm_offset; 596 sram_len = fwrt->trans->cfg->dccm_len; 597 } 598 599 /* reading RXF/TXF sizes */ 600 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 601 fifo_data_len = 0; 602 603 /* Count RXF2 size */ 604 if (mem_cfg->rxfifo2_size) { 605 /* Add header info */ 606 fifo_data_len += mem_cfg->rxfifo2_size + 607 sizeof(*dump_data) + 608 sizeof(struct iwl_fw_error_dump_fifo); 609 } 610 611 /* Count RXF1 sizes */ 612 for (i = 0; i < mem_cfg->num_lmacs; i++) { 613 if (!mem_cfg->lmac[i].rxfifo1_size) 614 continue; 615 616 /* Add header info */ 617 fifo_data_len += mem_cfg->lmac[i].rxfifo1_size + 618 sizeof(*dump_data) + 619 sizeof(struct iwl_fw_error_dump_fifo); 620 } 621 622 /* Count TXF sizes */ 623 for (i = 0; i < mem_cfg->num_lmacs; i++) { 624 int j; 625 626 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) { 627 if (!mem_cfg->lmac[i].txfifo_size[j]) 628 continue; 629 630 /* Add header info */ 631 fifo_data_len += 632 mem_cfg->lmac[i].txfifo_size[j] + 633 sizeof(*dump_data) + 634 sizeof(struct iwl_fw_error_dump_fifo); 635 } 636 } 637 638 if (fw_has_capa(&fwrt->fw->ucode_capa, 639 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 640 for (i = 0; 641 i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); 642 i++) { 643 if (!mem_cfg->internal_txfifo_size[i]) 644 continue; 645 646 /* Add header info */ 647 fifo_data_len += 648 mem_cfg->internal_txfifo_size[i] + 649 sizeof(*dump_data) + 650 sizeof(struct iwl_fw_error_dump_fifo); 651 } 652 } 653 654 /* Make room for PRPH registers */ 655 if (!fwrt->trans->cfg->gen2) { 656 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr_comm); 657 i++) { 658 /* The range includes both boundaries */ 659 int num_bytes_in_chunk = 660 iwl_prph_dump_addr_comm[i].end - 661 iwl_prph_dump_addr_comm[i].start + 4; 662 663 prph_len += sizeof(*dump_data) + 664 sizeof(struct iwl_fw_error_dump_prph) + 665 num_bytes_in_chunk; 666 } 667 } 668 669 if (!fwrt->trans->cfg->gen2 && 670 fwrt->trans->cfg->mq_rx_supported) { 671 for (i = 0; i < 672 ARRAY_SIZE(iwl_prph_dump_addr_9000); i++) { 673 /* The range includes both boundaries */ 674 int num_bytes_in_chunk = 675 iwl_prph_dump_addr_9000[i].end - 676 iwl_prph_dump_addr_9000[i].start + 4; 677 678 prph_len += sizeof(*dump_data) + 679 sizeof(struct iwl_fw_error_dump_prph) + 680 num_bytes_in_chunk; 681 } 682 } 683 684 if (fwrt->trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 685 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 686 } 687 688 file_len = sizeof(*dump_file) + 689 sizeof(*dump_data) * 3 + 690 sizeof(*dump_smem_cfg) + 691 fifo_data_len + 692 prph_len + 693 radio_len + 694 sizeof(*dump_info); 695 696 /* Make room for the SMEM, if it exists */ 697 if (smem_len) 698 file_len += sizeof(*dump_data) + sizeof(*dump_mem) + smem_len; 699 700 /* Make room for the secondary SRAM, if it exists */ 701 if (sram2_len) 702 file_len += sizeof(*dump_data) + sizeof(*dump_mem) + sram2_len; 703 704 /* Make room for MEM segments */ 705 for (i = 0; i < fwrt->fw->n_dbg_mem_tlv; i++) { 706 file_len += sizeof(*dump_data) + sizeof(*dump_mem) + 707 le32_to_cpu(fw_dbg_mem[i].len); 708 } 709 710 /* Make room for fw's virtual image pages, if it exists */ 711 if (!fwrt->trans->cfg->gen2 && 712 fwrt->fw->img[fwrt->cur_fw_img].paging_mem_size && 713 fwrt->fw_paging_db[0].fw_paging_block) 714 file_len += fwrt->num_of_paging_blk * 715 (sizeof(*dump_data) + 716 sizeof(struct iwl_fw_error_dump_paging) + 717 PAGING_BLOCK_SIZE); 718 719 /* If we only want a monitor dump, reset the file length */ 720 if (monitor_dump_only) { 721 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 722 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 723 } 724 725 if (fwrt->dump.desc) 726 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 727 fwrt->dump.desc->len; 728 729 if (!fwrt->fw->n_dbg_mem_tlv) 730 file_len += sram_len + sizeof(*dump_mem); 731 732 dump_file = vzalloc(file_len); 733 if (!dump_file) { 734 kfree(fw_error_dump); 735 goto out; 736 } 737 738 fw_error_dump->fwrt_ptr = dump_file; 739 740 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 741 dump_data = (void *)dump_file->data; 742 743 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 744 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 745 dump_info = (void *)dump_data->data; 746 dump_info->device_family = 747 fwrt->trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 ? 748 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_7) : 749 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_8); 750 dump_info->hw_step = cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 751 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 752 sizeof(dump_info->fw_human_readable)); 753 strncpy(dump_info->dev_human_readable, fwrt->trans->cfg->name, 754 sizeof(dump_info->dev_human_readable)); 755 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 756 sizeof(dump_info->bus_human_readable)); 757 758 dump_data = iwl_fw_error_next_data(dump_data); 759 760 /* Dump shared memory configuration */ 761 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 762 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 763 dump_smem_cfg = (void *)dump_data->data; 764 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 765 dump_smem_cfg->num_txfifo_entries = 766 cpu_to_le32(mem_cfg->num_txfifo_entries); 767 for (i = 0; i < MAX_NUM_LMAC; i++) { 768 int j; 769 770 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 771 dump_smem_cfg->lmac[i].txfifo_size[j] = 772 cpu_to_le32(mem_cfg->lmac[i].txfifo_size[j]); 773 dump_smem_cfg->lmac[i].rxfifo1_size = 774 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 775 } 776 dump_smem_cfg->rxfifo2_size = cpu_to_le32(mem_cfg->rxfifo2_size); 777 dump_smem_cfg->internal_txfifo_addr = 778 cpu_to_le32(mem_cfg->internal_txfifo_addr); 779 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 780 dump_smem_cfg->internal_txfifo_size[i] = 781 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 782 } 783 784 dump_data = iwl_fw_error_next_data(dump_data); 785 786 /* We only dump the FIFOs if the FW is in error state */ 787 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 788 iwl_fw_dump_fifos(fwrt, &dump_data); 789 if (radio_len) 790 iwl_read_radio_regs(fwrt, &dump_data); 791 } 792 793 if (fwrt->dump.desc) { 794 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 795 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 796 fwrt->dump.desc->len); 797 dump_trig = (void *)dump_data->data; 798 memcpy(dump_trig, &fwrt->dump.desc->trig_desc, 799 sizeof(*dump_trig) + fwrt->dump.desc->len); 800 801 dump_data = iwl_fw_error_next_data(dump_data); 802 } 803 804 /* In case we only want monitor dump, skip to dump trasport data */ 805 if (monitor_dump_only) 806 goto dump_trans_data; 807 808 if (!fwrt->fw->n_dbg_mem_tlv) { 809 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 810 dump_data->len = cpu_to_le32(sram_len + sizeof(*dump_mem)); 811 dump_mem = (void *)dump_data->data; 812 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM); 813 dump_mem->offset = cpu_to_le32(sram_ofs); 814 iwl_trans_read_mem_bytes(fwrt->trans, sram_ofs, dump_mem->data, 815 sram_len); 816 dump_data = iwl_fw_error_next_data(dump_data); 817 } 818 819 for (i = 0; i < fwrt->fw->n_dbg_mem_tlv; i++) { 820 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 821 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 822 bool success; 823 824 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 825 dump_data->len = cpu_to_le32(len + sizeof(*dump_mem)); 826 dump_mem = (void *)dump_data->data; 827 dump_mem->type = fw_dbg_mem[i].data_type; 828 dump_mem->offset = cpu_to_le32(ofs); 829 830 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", 831 dump_mem->type); 832 833 switch (dump_mem->type & cpu_to_le32(FW_DBG_MEM_TYPE_MASK)) { 834 case cpu_to_le32(FW_DBG_MEM_TYPE_REGULAR): 835 iwl_trans_read_mem_bytes(fwrt->trans, ofs, 836 dump_mem->data, 837 len); 838 success = true; 839 break; 840 case cpu_to_le32(FW_DBG_MEM_TYPE_PRPH): 841 success = iwl_read_prph_block(fwrt->trans, ofs, len, 842 (void *)dump_mem->data); 843 break; 844 default: 845 /* 846 * shouldn't get here, we ignored this kind 847 * of TLV earlier during the TLV parsing?! 848 */ 849 WARN_ON(1); 850 success = false; 851 } 852 853 if (success) 854 dump_data = iwl_fw_error_next_data(dump_data); 855 } 856 857 if (smem_len) { 858 IWL_DEBUG_INFO(fwrt, "WRT SMEM dump\n"); 859 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 860 dump_data->len = cpu_to_le32(smem_len + sizeof(*dump_mem)); 861 dump_mem = (void *)dump_data->data; 862 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SMEM); 863 dump_mem->offset = cpu_to_le32(fwrt->trans->cfg->smem_offset); 864 iwl_trans_read_mem_bytes(fwrt->trans, 865 fwrt->trans->cfg->smem_offset, 866 dump_mem->data, smem_len); 867 dump_data = iwl_fw_error_next_data(dump_data); 868 } 869 870 if (sram2_len) { 871 IWL_DEBUG_INFO(fwrt, "WRT SRAM dump\n"); 872 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 873 dump_data->len = cpu_to_le32(sram2_len + sizeof(*dump_mem)); 874 dump_mem = (void *)dump_data->data; 875 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM); 876 dump_mem->offset = cpu_to_le32(fwrt->trans->cfg->dccm2_offset); 877 iwl_trans_read_mem_bytes(fwrt->trans, 878 fwrt->trans->cfg->dccm2_offset, 879 dump_mem->data, sram2_len); 880 dump_data = iwl_fw_error_next_data(dump_data); 881 } 882 883 /* Dump fw's virtual image */ 884 if (!fwrt->trans->cfg->gen2 && 885 fwrt->fw->img[fwrt->cur_fw_img].paging_mem_size && 886 fwrt->fw_paging_db[0].fw_paging_block) { 887 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 888 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 889 struct iwl_fw_error_dump_paging *paging; 890 struct page *pages = 891 fwrt->fw_paging_db[i].fw_paging_block; 892 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 893 894 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 895 dump_data->len = cpu_to_le32(sizeof(*paging) + 896 PAGING_BLOCK_SIZE); 897 paging = (void *)dump_data->data; 898 paging->index = cpu_to_le32(i); 899 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 900 PAGING_BLOCK_SIZE, 901 DMA_BIDIRECTIONAL); 902 memcpy(paging->data, page_address(pages), 903 PAGING_BLOCK_SIZE); 904 dump_data = iwl_fw_error_next_data(dump_data); 905 } 906 } 907 908 if (prph_len) { 909 iwl_dump_prph(fwrt->trans, &dump_data, 910 iwl_prph_dump_addr_comm, 911 ARRAY_SIZE(iwl_prph_dump_addr_comm)); 912 913 if (fwrt->trans->cfg->mq_rx_supported) 914 iwl_dump_prph(fwrt->trans, &dump_data, 915 iwl_prph_dump_addr_9000, 916 ARRAY_SIZE(iwl_prph_dump_addr_9000)); 917 } 918 919 dump_trans_data: 920 fw_error_dump->trans_ptr = iwl_trans_dump_data(fwrt->trans, 921 fwrt->dump.trig); 922 fw_error_dump->fwrt_len = file_len; 923 if (fw_error_dump->trans_ptr) 924 file_len += fw_error_dump->trans_ptr->len; 925 dump_file->file_len = cpu_to_le32(file_len); 926 927 sg_dump_data = alloc_sgtable(file_len); 928 if (sg_dump_data) { 929 sg_pcopy_from_buffer(sg_dump_data, 930 sg_nents(sg_dump_data), 931 fw_error_dump->fwrt_ptr, 932 fw_error_dump->fwrt_len, 0); 933 if (fw_error_dump->trans_ptr) 934 sg_pcopy_from_buffer(sg_dump_data, 935 sg_nents(sg_dump_data), 936 fw_error_dump->trans_ptr->data, 937 fw_error_dump->trans_ptr->len, 938 fw_error_dump->fwrt_len); 939 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 940 GFP_KERNEL); 941 } 942 vfree(fw_error_dump->fwrt_ptr); 943 vfree(fw_error_dump->trans_ptr); 944 kfree(fw_error_dump); 945 946 out: 947 iwl_fw_free_dump_desc(fwrt); 948 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 949 IWL_DEBUG_INFO(fwrt, "WRT dump done\n"); 950 } 951 IWL_EXPORT_SYMBOL(iwl_fw_error_dump); 952 953 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 954 .trig_desc = { 955 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 956 }, 957 }; 958 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 959 960 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 961 const struct iwl_fw_dump_desc *desc, 962 const struct iwl_fw_dbg_trigger_tlv *trigger) 963 { 964 unsigned int delay = 0; 965 966 if (trigger) 967 delay = msecs_to_jiffies(le32_to_cpu(trigger->stop_delay)); 968 969 /* 970 * If the loading of the FW completed successfully, the next step is to 971 * get the SMEM config data. Thus, if fwrt->smem_cfg.num_lmacs is non 972 * zero, the FW was already loaded successully. If the state is "NO_FW" 973 * in such a case - WARN and exit, since FW may be dead. Otherwise, we 974 * can try to collect the data, since FW might just not be fully 975 * loaded (no "ALIVE" yet), and the debug data is accessible. 976 * 977 * Corner case: got the FW alive but crashed before getting the SMEM 978 * config. In such a case, due to HW access problems, we might 979 * collect garbage. 980 */ 981 if (WARN((fwrt->trans->state == IWL_TRANS_NO_FW) && 982 fwrt->smem_cfg.num_lmacs, 983 "Can't collect dbg data when FW isn't alive\n")) 984 return -EIO; 985 986 if (test_and_set_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 987 return -EBUSY; 988 989 if (WARN_ON(fwrt->dump.desc)) 990 iwl_fw_free_dump_desc(fwrt); 991 992 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 993 le32_to_cpu(desc->trig_desc.type)); 994 995 fwrt->dump.desc = desc; 996 fwrt->dump.trig = trigger; 997 998 schedule_delayed_work(&fwrt->dump.wk, delay); 999 1000 return 0; 1001 } 1002 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 1003 1004 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 1005 enum iwl_fw_dbg_trigger trig, 1006 const char *str, size_t len, 1007 const struct iwl_fw_dbg_trigger_tlv *trigger) 1008 { 1009 struct iwl_fw_dump_desc *desc; 1010 1011 if (trigger && trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 1012 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", trig); 1013 iwl_force_nmi(fwrt->trans); 1014 return 0; 1015 } 1016 1017 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 1018 if (!desc) 1019 return -ENOMEM; 1020 1021 desc->len = len; 1022 desc->trig_desc.type = cpu_to_le32(trig); 1023 memcpy(desc->trig_desc.data, str, len); 1024 1025 return iwl_fw_dbg_collect_desc(fwrt, desc, trigger); 1026 } 1027 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 1028 1029 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 1030 struct iwl_fw_dbg_trigger_tlv *trigger, 1031 const char *fmt, ...) 1032 { 1033 u16 occurrences = le16_to_cpu(trigger->occurrences); 1034 int ret, len = 0; 1035 char buf[64]; 1036 1037 if (!occurrences) 1038 return 0; 1039 1040 if (fmt) { 1041 va_list ap; 1042 1043 buf[sizeof(buf) - 1] = '\0'; 1044 1045 va_start(ap, fmt); 1046 vsnprintf(buf, sizeof(buf), fmt, ap); 1047 va_end(ap); 1048 1049 /* check for truncation */ 1050 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 1051 buf[sizeof(buf) - 1] = '\0'; 1052 1053 len = strlen(buf) + 1; 1054 } 1055 1056 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 1057 trigger); 1058 1059 if (ret) 1060 return ret; 1061 1062 trigger->occurrences = cpu_to_le16(occurrences - 1); 1063 return 0; 1064 } 1065 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 1066 1067 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 1068 { 1069 u8 *ptr; 1070 int ret; 1071 int i; 1072 1073 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg_conf_tlv), 1074 "Invalid configuration %d\n", conf_id)) 1075 return -EINVAL; 1076 1077 /* EARLY START - firmware's configuration is hard coded */ 1078 if ((!fwrt->fw->dbg_conf_tlv[conf_id] || 1079 !fwrt->fw->dbg_conf_tlv[conf_id]->num_of_hcmds) && 1080 conf_id == FW_DBG_START_FROM_ALIVE) 1081 return 0; 1082 1083 if (!fwrt->fw->dbg_conf_tlv[conf_id]) 1084 return -EINVAL; 1085 1086 if (fwrt->dump.conf != FW_DBG_INVALID) 1087 IWL_WARN(fwrt, "FW already configured (%d) - re-configuring\n", 1088 fwrt->dump.conf); 1089 1090 /* start default config marker cmd for syncing logs */ 1091 iwl_fw_trigger_timestamp(fwrt, 1); 1092 1093 /* Send all HCMDs for configuring the FW debug */ 1094 ptr = (void *)&fwrt->fw->dbg_conf_tlv[conf_id]->hcmd; 1095 for (i = 0; i < fwrt->fw->dbg_conf_tlv[conf_id]->num_of_hcmds; i++) { 1096 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 1097 struct iwl_host_cmd hcmd = { 1098 .id = cmd->id, 1099 .len = { le16_to_cpu(cmd->len), }, 1100 .data = { cmd->data, }, 1101 }; 1102 1103 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 1104 if (ret) 1105 return ret; 1106 1107 ptr += sizeof(*cmd); 1108 ptr += le16_to_cpu(cmd->len); 1109 } 1110 1111 fwrt->dump.conf = conf_id; 1112 1113 return 0; 1114 } 1115 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 1116 1117 void iwl_fw_error_dump_wk(struct work_struct *work) 1118 { 1119 struct iwl_fw_runtime *fwrt = 1120 container_of(work, struct iwl_fw_runtime, dump.wk.work); 1121 1122 if (fwrt->ops && fwrt->ops->dump_start && 1123 fwrt->ops->dump_start(fwrt->ops_ctx)) 1124 return; 1125 1126 if (fwrt->ops && fwrt->ops->fw_running && 1127 !fwrt->ops->fw_running(fwrt->ops_ctx)) { 1128 IWL_ERR(fwrt, "Firmware not running - cannot dump error\n"); 1129 iwl_fw_free_dump_desc(fwrt); 1130 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 1131 goto out; 1132 } 1133 1134 if (fwrt->trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1135 /* stop recording */ 1136 iwl_fw_dbg_stop_recording(fwrt); 1137 1138 iwl_fw_error_dump(fwrt); 1139 1140 /* start recording again if the firmware is not crashed */ 1141 if (!test_bit(STATUS_FW_ERROR, &fwrt->trans->status) && 1142 fwrt->fw->dbg_dest_tlv) { 1143 iwl_clear_bits_prph(fwrt->trans, 1144 MON_BUFF_SAMPLE_CTL, 0x100); 1145 iwl_clear_bits_prph(fwrt->trans, 1146 MON_BUFF_SAMPLE_CTL, 0x1); 1147 iwl_set_bits_prph(fwrt->trans, 1148 MON_BUFF_SAMPLE_CTL, 0x1); 1149 } 1150 } else { 1151 u32 in_sample = iwl_read_prph(fwrt->trans, DBGC_IN_SAMPLE); 1152 u32 out_ctrl = iwl_read_prph(fwrt->trans, DBGC_OUT_CTRL); 1153 1154 iwl_fw_dbg_stop_recording(fwrt); 1155 /* wait before we collect the data till the DBGC stop */ 1156 udelay(500); 1157 1158 iwl_fw_error_dump(fwrt); 1159 1160 /* start recording again if the firmware is not crashed */ 1161 if (!test_bit(STATUS_FW_ERROR, &fwrt->trans->status) && 1162 fwrt->fw->dbg_dest_tlv) { 1163 iwl_write_prph(fwrt->trans, DBGC_IN_SAMPLE, in_sample); 1164 iwl_write_prph(fwrt->trans, DBGC_OUT_CTRL, out_ctrl); 1165 } 1166 } 1167 out: 1168 if (fwrt->ops && fwrt->ops->dump_end) 1169 fwrt->ops->dump_end(fwrt->ops_ctx); 1170 } 1171 1172