1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (C) 2005-2014, 2018-2021 Intel Corporation
4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5  * Copyright (C) 2015-2017 Intel Deutschland GmbH
6  */
7 #include <linux/devcoredump.h>
8 #include "iwl-drv.h"
9 #include "runtime.h"
10 #include "dbg.h"
11 #include "debugfs.h"
12 #include "iwl-io.h"
13 #include "iwl-prph.h"
14 #include "iwl-csr.h"
15 
16 /**
17  * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump
18  *
19  * @fwrt_ptr: pointer to the buffer coming from fwrt
20  * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the
21  *	transport's data.
22  * @trans_len: length of the valid data in trans_ptr
23  * @fwrt_len: length of the valid data in fwrt_ptr
24  */
25 struct iwl_fw_dump_ptrs {
26 	struct iwl_trans_dump_data *trans_ptr;
27 	void *fwrt_ptr;
28 	u32 fwrt_len;
29 };
30 
31 #define RADIO_REG_MAX_READ 0x2ad
32 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt,
33 				struct iwl_fw_error_dump_data **dump_data)
34 {
35 	u8 *pos = (void *)(*dump_data)->data;
36 	int i;
37 
38 	IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n");
39 
40 	if (!iwl_trans_grab_nic_access(fwrt->trans))
41 		return;
42 
43 	(*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG);
44 	(*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ);
45 
46 	for (i = 0; i < RADIO_REG_MAX_READ; i++) {
47 		u32 rd_cmd = RADIO_RSP_RD_CMD;
48 
49 		rd_cmd |= i << RADIO_RSP_ADDR_POS;
50 		iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd);
51 		*pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT);
52 
53 		pos++;
54 	}
55 
56 	*dump_data = iwl_fw_error_next_data(*dump_data);
57 
58 	iwl_trans_release_nic_access(fwrt->trans);
59 }
60 
61 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt,
62 			      struct iwl_fw_error_dump_data **dump_data,
63 			      int size, u32 offset, int fifo_num)
64 {
65 	struct iwl_fw_error_dump_fifo *fifo_hdr;
66 	u32 *fifo_data;
67 	u32 fifo_len;
68 	int i;
69 
70 	fifo_hdr = (void *)(*dump_data)->data;
71 	fifo_data = (void *)fifo_hdr->data;
72 	fifo_len = size;
73 
74 	/* No need to try to read the data if the length is 0 */
75 	if (fifo_len == 0)
76 		return;
77 
78 	/* Add a TLV for the RXF */
79 	(*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF);
80 	(*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
81 
82 	fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
83 	fifo_hdr->available_bytes =
84 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
85 						RXF_RD_D_SPACE + offset));
86 	fifo_hdr->wr_ptr =
87 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
88 						RXF_RD_WR_PTR + offset));
89 	fifo_hdr->rd_ptr =
90 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
91 						RXF_RD_RD_PTR + offset));
92 	fifo_hdr->fence_ptr =
93 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
94 						RXF_RD_FENCE_PTR + offset));
95 	fifo_hdr->fence_mode =
96 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
97 						RXF_SET_FENCE_MODE + offset));
98 
99 	/* Lock fence */
100 	iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1);
101 	/* Set fence pointer to the same place like WR pointer */
102 	iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1);
103 	/* Set fence offset */
104 	iwl_trans_write_prph(fwrt->trans,
105 			     RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);
106 
107 	/* Read FIFO */
108 	fifo_len /= sizeof(u32); /* Size in DWORDS */
109 	for (i = 0; i < fifo_len; i++)
110 		fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
111 						 RXF_FIFO_RD_FENCE_INC +
112 						 offset);
113 	*dump_data = iwl_fw_error_next_data(*dump_data);
114 }
115 
116 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt,
117 			      struct iwl_fw_error_dump_data **dump_data,
118 			      int size, u32 offset, int fifo_num)
119 {
120 	struct iwl_fw_error_dump_fifo *fifo_hdr;
121 	u32 *fifo_data;
122 	u32 fifo_len;
123 	int i;
124 
125 	fifo_hdr = (void *)(*dump_data)->data;
126 	fifo_data = (void *)fifo_hdr->data;
127 	fifo_len = size;
128 
129 	/* No need to try to read the data if the length is 0 */
130 	if (fifo_len == 0)
131 		return;
132 
133 	/* Add a TLV for the FIFO */
134 	(*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF);
135 	(*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
136 
137 	fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
138 	fifo_hdr->available_bytes =
139 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
140 						TXF_FIFO_ITEM_CNT + offset));
141 	fifo_hdr->wr_ptr =
142 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
143 						TXF_WR_PTR + offset));
144 	fifo_hdr->rd_ptr =
145 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
146 						TXF_RD_PTR + offset));
147 	fifo_hdr->fence_ptr =
148 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
149 						TXF_FENCE_PTR + offset));
150 	fifo_hdr->fence_mode =
151 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
152 						TXF_LOCK_FENCE + offset));
153 
154 	/* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
155 	iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset,
156 			     TXF_WR_PTR + offset);
157 
158 	/* Dummy-read to advance the read pointer to the head */
159 	iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset);
160 
161 	/* Read FIFO */
162 	for (i = 0; i < fifo_len / sizeof(u32); i++)
163 		fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
164 						  TXF_READ_MODIFY_DATA +
165 						  offset);
166 
167 	if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf)
168 		fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx,
169 					     fifo_data, fifo_len);
170 
171 	*dump_data = iwl_fw_error_next_data(*dump_data);
172 }
173 
174 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt,
175 			    struct iwl_fw_error_dump_data **dump_data)
176 {
177 	struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
178 
179 	IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n");
180 
181 	if (!iwl_trans_grab_nic_access(fwrt->trans))
182 		return;
183 
184 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) {
185 		/* Pull RXF1 */
186 		iwl_fwrt_dump_rxf(fwrt, dump_data,
187 				  cfg->lmac[0].rxfifo1_size, 0, 0);
188 		/* Pull RXF2 */
189 		iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size,
190 				  RXF_DIFF_FROM_PREV +
191 				  fwrt->trans->trans_cfg->umac_prph_offset, 1);
192 		/* Pull LMAC2 RXF1 */
193 		if (fwrt->smem_cfg.num_lmacs > 1)
194 			iwl_fwrt_dump_rxf(fwrt, dump_data,
195 					  cfg->lmac[1].rxfifo1_size,
196 					  LMAC2_PRPH_OFFSET, 2);
197 	}
198 
199 	iwl_trans_release_nic_access(fwrt->trans);
200 }
201 
202 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
203 			    struct iwl_fw_error_dump_data **dump_data)
204 {
205 	struct iwl_fw_error_dump_fifo *fifo_hdr;
206 	struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
207 	u32 *fifo_data;
208 	u32 fifo_len;
209 	int i, j;
210 
211 	IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n");
212 
213 	if (!iwl_trans_grab_nic_access(fwrt->trans))
214 		return;
215 
216 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) {
217 		/* Pull TXF data from LMAC1 */
218 		for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) {
219 			/* Mark the number of TXF we're pulling now */
220 			iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i);
221 			iwl_fwrt_dump_txf(fwrt, dump_data,
222 					  cfg->lmac[0].txfifo_size[i], 0, i);
223 		}
224 
225 		/* Pull TXF data from LMAC2 */
226 		if (fwrt->smem_cfg.num_lmacs > 1) {
227 			for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries;
228 			     i++) {
229 				/* Mark the number of TXF we're pulling now */
230 				iwl_trans_write_prph(fwrt->trans,
231 						     TXF_LARC_NUM +
232 						     LMAC2_PRPH_OFFSET, i);
233 				iwl_fwrt_dump_txf(fwrt, dump_data,
234 						  cfg->lmac[1].txfifo_size[i],
235 						  LMAC2_PRPH_OFFSET,
236 						  i + cfg->num_txfifo_entries);
237 			}
238 		}
239 	}
240 
241 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
242 	    fw_has_capa(&fwrt->fw->ucode_capa,
243 			IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
244 		/* Pull UMAC internal TXF data from all TXFs */
245 		for (i = 0;
246 		     i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size);
247 		     i++) {
248 			fifo_hdr = (void *)(*dump_data)->data;
249 			fifo_data = (void *)fifo_hdr->data;
250 			fifo_len = fwrt->smem_cfg.internal_txfifo_size[i];
251 
252 			/* No need to try to read the data if the length is 0 */
253 			if (fifo_len == 0)
254 				continue;
255 
256 			/* Add a TLV for the internal FIFOs */
257 			(*dump_data)->type =
258 				cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF);
259 			(*dump_data)->len =
260 				cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
261 
262 			fifo_hdr->fifo_num = cpu_to_le32(i);
263 
264 			/* Mark the number of TXF we're pulling now */
265 			iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i +
266 				fwrt->smem_cfg.num_txfifo_entries);
267 
268 			fifo_hdr->available_bytes =
269 				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
270 								TXF_CPU2_FIFO_ITEM_CNT));
271 			fifo_hdr->wr_ptr =
272 				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
273 								TXF_CPU2_WR_PTR));
274 			fifo_hdr->rd_ptr =
275 				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
276 								TXF_CPU2_RD_PTR));
277 			fifo_hdr->fence_ptr =
278 				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
279 								TXF_CPU2_FENCE_PTR));
280 			fifo_hdr->fence_mode =
281 				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
282 								TXF_CPU2_LOCK_FENCE));
283 
284 			/* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */
285 			iwl_trans_write_prph(fwrt->trans,
286 					     TXF_CPU2_READ_MODIFY_ADDR,
287 					     TXF_CPU2_WR_PTR);
288 
289 			/* Dummy-read to advance the read pointer to head */
290 			iwl_trans_read_prph(fwrt->trans,
291 					    TXF_CPU2_READ_MODIFY_DATA);
292 
293 			/* Read FIFO */
294 			fifo_len /= sizeof(u32); /* Size in DWORDS */
295 			for (j = 0; j < fifo_len; j++)
296 				fifo_data[j] =
297 					iwl_trans_read_prph(fwrt->trans,
298 							    TXF_CPU2_READ_MODIFY_DATA);
299 			*dump_data = iwl_fw_error_next_data(*dump_data);
300 		}
301 	}
302 
303 	iwl_trans_release_nic_access(fwrt->trans);
304 }
305 
306 #define IWL8260_ICCM_OFFSET		0x44000 /* Only for B-step */
307 #define IWL8260_ICCM_LEN		0xC000 /* Only for B-step */
308 
309 struct iwl_prph_range {
310 	u32 start, end;
311 };
312 
313 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = {
314 	{ .start = 0x00a00000, .end = 0x00a00000 },
315 	{ .start = 0x00a0000c, .end = 0x00a00024 },
316 	{ .start = 0x00a0002c, .end = 0x00a0003c },
317 	{ .start = 0x00a00410, .end = 0x00a00418 },
318 	{ .start = 0x00a00420, .end = 0x00a00420 },
319 	{ .start = 0x00a00428, .end = 0x00a00428 },
320 	{ .start = 0x00a00430, .end = 0x00a0043c },
321 	{ .start = 0x00a00444, .end = 0x00a00444 },
322 	{ .start = 0x00a004c0, .end = 0x00a004cc },
323 	{ .start = 0x00a004d8, .end = 0x00a004d8 },
324 	{ .start = 0x00a004e0, .end = 0x00a004f0 },
325 	{ .start = 0x00a00840, .end = 0x00a00840 },
326 	{ .start = 0x00a00850, .end = 0x00a00858 },
327 	{ .start = 0x00a01004, .end = 0x00a01008 },
328 	{ .start = 0x00a01010, .end = 0x00a01010 },
329 	{ .start = 0x00a01018, .end = 0x00a01018 },
330 	{ .start = 0x00a01024, .end = 0x00a01024 },
331 	{ .start = 0x00a0102c, .end = 0x00a01034 },
332 	{ .start = 0x00a0103c, .end = 0x00a01040 },
333 	{ .start = 0x00a01048, .end = 0x00a01094 },
334 	{ .start = 0x00a01c00, .end = 0x00a01c20 },
335 	{ .start = 0x00a01c58, .end = 0x00a01c58 },
336 	{ .start = 0x00a01c7c, .end = 0x00a01c7c },
337 	{ .start = 0x00a01c28, .end = 0x00a01c54 },
338 	{ .start = 0x00a01c5c, .end = 0x00a01c5c },
339 	{ .start = 0x00a01c60, .end = 0x00a01cdc },
340 	{ .start = 0x00a01ce0, .end = 0x00a01d0c },
341 	{ .start = 0x00a01d18, .end = 0x00a01d20 },
342 	{ .start = 0x00a01d2c, .end = 0x00a01d30 },
343 	{ .start = 0x00a01d40, .end = 0x00a01d5c },
344 	{ .start = 0x00a01d80, .end = 0x00a01d80 },
345 	{ .start = 0x00a01d98, .end = 0x00a01d9c },
346 	{ .start = 0x00a01da8, .end = 0x00a01da8 },
347 	{ .start = 0x00a01db8, .end = 0x00a01df4 },
348 	{ .start = 0x00a01dc0, .end = 0x00a01dfc },
349 	{ .start = 0x00a01e00, .end = 0x00a01e2c },
350 	{ .start = 0x00a01e40, .end = 0x00a01e60 },
351 	{ .start = 0x00a01e68, .end = 0x00a01e6c },
352 	{ .start = 0x00a01e74, .end = 0x00a01e74 },
353 	{ .start = 0x00a01e84, .end = 0x00a01e90 },
354 	{ .start = 0x00a01e9c, .end = 0x00a01ec4 },
355 	{ .start = 0x00a01ed0, .end = 0x00a01ee0 },
356 	{ .start = 0x00a01f00, .end = 0x00a01f1c },
357 	{ .start = 0x00a01f44, .end = 0x00a01ffc },
358 	{ .start = 0x00a02000, .end = 0x00a02048 },
359 	{ .start = 0x00a02068, .end = 0x00a020f0 },
360 	{ .start = 0x00a02100, .end = 0x00a02118 },
361 	{ .start = 0x00a02140, .end = 0x00a0214c },
362 	{ .start = 0x00a02168, .end = 0x00a0218c },
363 	{ .start = 0x00a021c0, .end = 0x00a021c0 },
364 	{ .start = 0x00a02400, .end = 0x00a02410 },
365 	{ .start = 0x00a02418, .end = 0x00a02420 },
366 	{ .start = 0x00a02428, .end = 0x00a0242c },
367 	{ .start = 0x00a02434, .end = 0x00a02434 },
368 	{ .start = 0x00a02440, .end = 0x00a02460 },
369 	{ .start = 0x00a02468, .end = 0x00a024b0 },
370 	{ .start = 0x00a024c8, .end = 0x00a024cc },
371 	{ .start = 0x00a02500, .end = 0x00a02504 },
372 	{ .start = 0x00a0250c, .end = 0x00a02510 },
373 	{ .start = 0x00a02540, .end = 0x00a02554 },
374 	{ .start = 0x00a02580, .end = 0x00a025f4 },
375 	{ .start = 0x00a02600, .end = 0x00a0260c },
376 	{ .start = 0x00a02648, .end = 0x00a02650 },
377 	{ .start = 0x00a02680, .end = 0x00a02680 },
378 	{ .start = 0x00a026c0, .end = 0x00a026d0 },
379 	{ .start = 0x00a02700, .end = 0x00a0270c },
380 	{ .start = 0x00a02804, .end = 0x00a02804 },
381 	{ .start = 0x00a02818, .end = 0x00a0281c },
382 	{ .start = 0x00a02c00, .end = 0x00a02db4 },
383 	{ .start = 0x00a02df4, .end = 0x00a02fb0 },
384 	{ .start = 0x00a03000, .end = 0x00a03014 },
385 	{ .start = 0x00a0301c, .end = 0x00a0302c },
386 	{ .start = 0x00a03034, .end = 0x00a03038 },
387 	{ .start = 0x00a03040, .end = 0x00a03048 },
388 	{ .start = 0x00a03060, .end = 0x00a03068 },
389 	{ .start = 0x00a03070, .end = 0x00a03074 },
390 	{ .start = 0x00a0307c, .end = 0x00a0307c },
391 	{ .start = 0x00a03080, .end = 0x00a03084 },
392 	{ .start = 0x00a0308c, .end = 0x00a03090 },
393 	{ .start = 0x00a03098, .end = 0x00a03098 },
394 	{ .start = 0x00a030a0, .end = 0x00a030a0 },
395 	{ .start = 0x00a030a8, .end = 0x00a030b4 },
396 	{ .start = 0x00a030bc, .end = 0x00a030bc },
397 	{ .start = 0x00a030c0, .end = 0x00a0312c },
398 	{ .start = 0x00a03c00, .end = 0x00a03c5c },
399 	{ .start = 0x00a04400, .end = 0x00a04454 },
400 	{ .start = 0x00a04460, .end = 0x00a04474 },
401 	{ .start = 0x00a044c0, .end = 0x00a044ec },
402 	{ .start = 0x00a04500, .end = 0x00a04504 },
403 	{ .start = 0x00a04510, .end = 0x00a04538 },
404 	{ .start = 0x00a04540, .end = 0x00a04548 },
405 	{ .start = 0x00a04560, .end = 0x00a0457c },
406 	{ .start = 0x00a04590, .end = 0x00a04598 },
407 	{ .start = 0x00a045c0, .end = 0x00a045f4 },
408 };
409 
410 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = {
411 	{ .start = 0x00a05c00, .end = 0x00a05c18 },
412 	{ .start = 0x00a05400, .end = 0x00a056e8 },
413 	{ .start = 0x00a08000, .end = 0x00a098bc },
414 	{ .start = 0x00a02400, .end = 0x00a02758 },
415 	{ .start = 0x00a04764, .end = 0x00a0476c },
416 	{ .start = 0x00a04770, .end = 0x00a04774 },
417 	{ .start = 0x00a04620, .end = 0x00a04624 },
418 };
419 
420 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = {
421 	{ .start = 0x00a00000, .end = 0x00a00000 },
422 	{ .start = 0x00a0000c, .end = 0x00a00024 },
423 	{ .start = 0x00a0002c, .end = 0x00a00034 },
424 	{ .start = 0x00a0003c, .end = 0x00a0003c },
425 	{ .start = 0x00a00410, .end = 0x00a00418 },
426 	{ .start = 0x00a00420, .end = 0x00a00420 },
427 	{ .start = 0x00a00428, .end = 0x00a00428 },
428 	{ .start = 0x00a00430, .end = 0x00a0043c },
429 	{ .start = 0x00a00444, .end = 0x00a00444 },
430 	{ .start = 0x00a00840, .end = 0x00a00840 },
431 	{ .start = 0x00a00850, .end = 0x00a00858 },
432 	{ .start = 0x00a01004, .end = 0x00a01008 },
433 	{ .start = 0x00a01010, .end = 0x00a01010 },
434 	{ .start = 0x00a01018, .end = 0x00a01018 },
435 	{ .start = 0x00a01024, .end = 0x00a01024 },
436 	{ .start = 0x00a0102c, .end = 0x00a01034 },
437 	{ .start = 0x00a0103c, .end = 0x00a01040 },
438 	{ .start = 0x00a01048, .end = 0x00a01050 },
439 	{ .start = 0x00a01058, .end = 0x00a01058 },
440 	{ .start = 0x00a01060, .end = 0x00a01070 },
441 	{ .start = 0x00a0108c, .end = 0x00a0108c },
442 	{ .start = 0x00a01c20, .end = 0x00a01c28 },
443 	{ .start = 0x00a01d10, .end = 0x00a01d10 },
444 	{ .start = 0x00a01e28, .end = 0x00a01e2c },
445 	{ .start = 0x00a01e60, .end = 0x00a01e60 },
446 	{ .start = 0x00a01e80, .end = 0x00a01e80 },
447 	{ .start = 0x00a01ea0, .end = 0x00a01ea0 },
448 	{ .start = 0x00a02000, .end = 0x00a0201c },
449 	{ .start = 0x00a02024, .end = 0x00a02024 },
450 	{ .start = 0x00a02040, .end = 0x00a02048 },
451 	{ .start = 0x00a020c0, .end = 0x00a020e0 },
452 	{ .start = 0x00a02400, .end = 0x00a02404 },
453 	{ .start = 0x00a0240c, .end = 0x00a02414 },
454 	{ .start = 0x00a0241c, .end = 0x00a0243c },
455 	{ .start = 0x00a02448, .end = 0x00a024bc },
456 	{ .start = 0x00a024c4, .end = 0x00a024cc },
457 	{ .start = 0x00a02508, .end = 0x00a02508 },
458 	{ .start = 0x00a02510, .end = 0x00a02514 },
459 	{ .start = 0x00a0251c, .end = 0x00a0251c },
460 	{ .start = 0x00a0252c, .end = 0x00a0255c },
461 	{ .start = 0x00a02564, .end = 0x00a025a0 },
462 	{ .start = 0x00a025a8, .end = 0x00a025b4 },
463 	{ .start = 0x00a025c0, .end = 0x00a025c0 },
464 	{ .start = 0x00a025e8, .end = 0x00a025f4 },
465 	{ .start = 0x00a02c08, .end = 0x00a02c18 },
466 	{ .start = 0x00a02c2c, .end = 0x00a02c38 },
467 	{ .start = 0x00a02c68, .end = 0x00a02c78 },
468 	{ .start = 0x00a03000, .end = 0x00a03000 },
469 	{ .start = 0x00a03010, .end = 0x00a03014 },
470 	{ .start = 0x00a0301c, .end = 0x00a0302c },
471 	{ .start = 0x00a03034, .end = 0x00a03038 },
472 	{ .start = 0x00a03040, .end = 0x00a03044 },
473 	{ .start = 0x00a03060, .end = 0x00a03068 },
474 	{ .start = 0x00a03070, .end = 0x00a03070 },
475 	{ .start = 0x00a0307c, .end = 0x00a03084 },
476 	{ .start = 0x00a0308c, .end = 0x00a03090 },
477 	{ .start = 0x00a03098, .end = 0x00a03098 },
478 	{ .start = 0x00a030a0, .end = 0x00a030a0 },
479 	{ .start = 0x00a030a8, .end = 0x00a030b4 },
480 	{ .start = 0x00a030bc, .end = 0x00a030c0 },
481 	{ .start = 0x00a030c8, .end = 0x00a030f4 },
482 	{ .start = 0x00a03100, .end = 0x00a0312c },
483 	{ .start = 0x00a03c00, .end = 0x00a03c5c },
484 	{ .start = 0x00a04400, .end = 0x00a04454 },
485 	{ .start = 0x00a04460, .end = 0x00a04474 },
486 	{ .start = 0x00a044c0, .end = 0x00a044ec },
487 	{ .start = 0x00a04500, .end = 0x00a04504 },
488 	{ .start = 0x00a04510, .end = 0x00a04538 },
489 	{ .start = 0x00a04540, .end = 0x00a04548 },
490 	{ .start = 0x00a04560, .end = 0x00a04560 },
491 	{ .start = 0x00a04570, .end = 0x00a0457c },
492 	{ .start = 0x00a04590, .end = 0x00a04590 },
493 	{ .start = 0x00a04598, .end = 0x00a04598 },
494 	{ .start = 0x00a045c0, .end = 0x00a045f4 },
495 	{ .start = 0x00a05c18, .end = 0x00a05c1c },
496 	{ .start = 0x00a0c000, .end = 0x00a0c018 },
497 	{ .start = 0x00a0c020, .end = 0x00a0c028 },
498 	{ .start = 0x00a0c038, .end = 0x00a0c094 },
499 	{ .start = 0x00a0c0c0, .end = 0x00a0c104 },
500 	{ .start = 0x00a0c10c, .end = 0x00a0c118 },
501 	{ .start = 0x00a0c150, .end = 0x00a0c174 },
502 	{ .start = 0x00a0c17c, .end = 0x00a0c188 },
503 	{ .start = 0x00a0c190, .end = 0x00a0c198 },
504 	{ .start = 0x00a0c1a0, .end = 0x00a0c1a8 },
505 	{ .start = 0x00a0c1b0, .end = 0x00a0c1b8 },
506 };
507 
508 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = {
509 	{ .start = 0x00d03c00, .end = 0x00d03c64 },
510 	{ .start = 0x00d05c18, .end = 0x00d05c1c },
511 	{ .start = 0x00d0c000, .end = 0x00d0c174 },
512 };
513 
514 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start,
515 				u32 len_bytes, __le32 *data)
516 {
517 	u32 i;
518 
519 	for (i = 0; i < len_bytes; i += 4)
520 		*data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i));
521 }
522 
523 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,
524 			  const struct iwl_prph_range *iwl_prph_dump_addr,
525 			  u32 range_len, void *ptr)
526 {
527 	struct iwl_fw_error_dump_prph *prph;
528 	struct iwl_trans *trans = fwrt->trans;
529 	struct iwl_fw_error_dump_data **data =
530 		(struct iwl_fw_error_dump_data **)ptr;
531 	u32 i;
532 
533 	if (!data)
534 		return;
535 
536 	IWL_DEBUG_INFO(trans, "WRT PRPH dump\n");
537 
538 	if (!iwl_trans_grab_nic_access(trans))
539 		return;
540 
541 	for (i = 0; i < range_len; i++) {
542 		/* The range includes both boundaries */
543 		int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
544 			 iwl_prph_dump_addr[i].start + 4;
545 
546 		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
547 		(*data)->len = cpu_to_le32(sizeof(*prph) +
548 					num_bytes_in_chunk);
549 		prph = (void *)(*data)->data;
550 		prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
551 
552 		iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start,
553 				    /* our range is inclusive, hence + 4 */
554 				    iwl_prph_dump_addr[i].end -
555 				    iwl_prph_dump_addr[i].start + 4,
556 				    (void *)prph->data);
557 
558 		*data = iwl_fw_error_next_data(*data);
559 	}
560 
561 	iwl_trans_release_nic_access(trans);
562 }
563 
564 /*
565  * alloc_sgtable - allocates scallerlist table in the given size,
566  * fills it with pages and returns it
567  * @size: the size (in bytes) of the table
568 */
569 static struct scatterlist *alloc_sgtable(int size)
570 {
571 	int alloc_size, nents, i;
572 	struct page *new_page;
573 	struct scatterlist *iter;
574 	struct scatterlist *table;
575 
576 	nents = DIV_ROUND_UP(size, PAGE_SIZE);
577 	table = kcalloc(nents, sizeof(*table), GFP_KERNEL);
578 	if (!table)
579 		return NULL;
580 	sg_init_table(table, nents);
581 	iter = table;
582 	for_each_sg(table, iter, sg_nents(table), i) {
583 		new_page = alloc_page(GFP_KERNEL);
584 		if (!new_page) {
585 			/* release all previous allocated pages in the table */
586 			iter = table;
587 			for_each_sg(table, iter, sg_nents(table), i) {
588 				new_page = sg_page(iter);
589 				if (new_page)
590 					__free_page(new_page);
591 			}
592 			kfree(table);
593 			return NULL;
594 		}
595 		alloc_size = min_t(int, size, PAGE_SIZE);
596 		size -= PAGE_SIZE;
597 		sg_set_page(iter, new_page, alloc_size, 0);
598 	}
599 	return table;
600 }
601 
602 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt,
603 				const struct iwl_prph_range *iwl_prph_dump_addr,
604 				u32 range_len, void *ptr)
605 {
606 	u32 *prph_len = (u32 *)ptr;
607 	int i, num_bytes_in_chunk;
608 
609 	if (!prph_len)
610 		return;
611 
612 	for (i = 0; i < range_len; i++) {
613 		/* The range includes both boundaries */
614 		num_bytes_in_chunk =
615 			iwl_prph_dump_addr[i].end -
616 			iwl_prph_dump_addr[i].start + 4;
617 
618 		*prph_len += sizeof(struct iwl_fw_error_dump_data) +
619 			sizeof(struct iwl_fw_error_dump_prph) +
620 			num_bytes_in_chunk;
621 	}
622 }
623 
624 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr,
625 				void (*handler)(struct iwl_fw_runtime *,
626 						const struct iwl_prph_range *,
627 						u32, void *))
628 {
629 	u32 range_len;
630 
631 	if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
632 		range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210);
633 		handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr);
634 	} else if (fwrt->trans->trans_cfg->device_family >=
635 		   IWL_DEVICE_FAMILY_22000) {
636 		range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000);
637 		handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr);
638 	} else {
639 		range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm);
640 		handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr);
641 
642 		if (fwrt->trans->trans_cfg->mq_rx_supported) {
643 			range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000);
644 			handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr);
645 		}
646 	}
647 }
648 
649 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt,
650 			    struct iwl_fw_error_dump_data **dump_data,
651 			    u32 len, u32 ofs, u32 type)
652 {
653 	struct iwl_fw_error_dump_mem *dump_mem;
654 
655 	if (!len)
656 		return;
657 
658 	(*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
659 	(*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem));
660 	dump_mem = (void *)(*dump_data)->data;
661 	dump_mem->type = cpu_to_le32(type);
662 	dump_mem->offset = cpu_to_le32(ofs);
663 	iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len);
664 	*dump_data = iwl_fw_error_next_data(*dump_data);
665 
666 	if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
667 		fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs,
668 					     dump_mem->data, len);
669 
670 	IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type);
671 }
672 
673 #define ADD_LEN(len, item_len, const_len) \
674 	do {size_t item = item_len; len += (!!item) * const_len + item; } \
675 	while (0)
676 
677 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt,
678 			  struct iwl_fwrt_shared_mem_cfg *mem_cfg)
679 {
680 	size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
681 			 sizeof(struct iwl_fw_error_dump_fifo);
682 	u32 fifo_len = 0;
683 	int i;
684 
685 	if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF))
686 		return 0;
687 
688 	/* Count RXF2 size */
689 	ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len);
690 
691 	/* Count RXF1 sizes */
692 	if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC))
693 		mem_cfg->num_lmacs = MAX_NUM_LMAC;
694 
695 	for (i = 0; i < mem_cfg->num_lmacs; i++)
696 		ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len);
697 
698 	return fifo_len;
699 }
700 
701 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt,
702 			  struct iwl_fwrt_shared_mem_cfg *mem_cfg)
703 {
704 	size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
705 			 sizeof(struct iwl_fw_error_dump_fifo);
706 	u32 fifo_len = 0;
707 	int i;
708 
709 	if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF))
710 		goto dump_internal_txf;
711 
712 	/* Count TXF sizes */
713 	if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC))
714 		mem_cfg->num_lmacs = MAX_NUM_LMAC;
715 
716 	for (i = 0; i < mem_cfg->num_lmacs; i++) {
717 		int j;
718 
719 		for (j = 0; j < mem_cfg->num_txfifo_entries; j++)
720 			ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j],
721 				hdr_len);
722 	}
723 
724 dump_internal_txf:
725 	if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
726 	      fw_has_capa(&fwrt->fw->ucode_capa,
727 			  IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)))
728 		goto out;
729 
730 	for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++)
731 		ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len);
732 
733 out:
734 	return fifo_len;
735 }
736 
737 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt,
738 			    struct iwl_fw_error_dump_data **data)
739 {
740 	int i;
741 
742 	IWL_DEBUG_INFO(fwrt, "WRT paging dump\n");
743 	for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) {
744 		struct iwl_fw_error_dump_paging *paging;
745 		struct page *pages =
746 			fwrt->fw_paging_db[i].fw_paging_block;
747 		dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys;
748 
749 		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
750 		(*data)->len = cpu_to_le32(sizeof(*paging) +
751 					     PAGING_BLOCK_SIZE);
752 		paging =  (void *)(*data)->data;
753 		paging->index = cpu_to_le32(i);
754 		dma_sync_single_for_cpu(fwrt->trans->dev, addr,
755 					PAGING_BLOCK_SIZE,
756 					DMA_BIDIRECTIONAL);
757 		memcpy(paging->data, page_address(pages),
758 		       PAGING_BLOCK_SIZE);
759 		dma_sync_single_for_device(fwrt->trans->dev, addr,
760 					   PAGING_BLOCK_SIZE,
761 					   DMA_BIDIRECTIONAL);
762 		(*data) = iwl_fw_error_next_data(*data);
763 
764 		if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
765 			fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx,
766 						     fwrt->fw_paging_db[i].fw_offs,
767 						     paging->data,
768 						     PAGING_BLOCK_SIZE);
769 	}
770 }
771 
772 static struct iwl_fw_error_dump_file *
773 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt,
774 		       struct iwl_fw_dump_ptrs *fw_error_dump,
775 		       struct iwl_fwrt_dump_data *data)
776 {
777 	struct iwl_fw_error_dump_file *dump_file;
778 	struct iwl_fw_error_dump_data *dump_data;
779 	struct iwl_fw_error_dump_info *dump_info;
780 	struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg;
781 	struct iwl_fw_error_dump_trigger_desc *dump_trig;
782 	u32 sram_len, sram_ofs;
783 	const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv;
784 	struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg;
785 	u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0;
786 	u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len;
787 	u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ?
788 				0 : fwrt->trans->cfg->dccm2_len;
789 	int i;
790 
791 	/* SRAM - include stack CCM if driver knows the values for it */
792 	if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) {
793 		const struct fw_img *img;
794 
795 		if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX)
796 			return NULL;
797 		img = &fwrt->fw->img[fwrt->cur_fw_img];
798 		sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset;
799 		sram_len = img->sec[IWL_UCODE_SECTION_DATA].len;
800 	} else {
801 		sram_ofs = fwrt->trans->cfg->dccm_offset;
802 		sram_len = fwrt->trans->cfg->dccm_len;
803 	}
804 
805 	/* reading RXF/TXF sizes */
806 	if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) {
807 		fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg);
808 		fifo_len += iwl_fw_txf_len(fwrt, mem_cfg);
809 
810 		/* Make room for PRPH registers */
811 		if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH))
812 			iwl_fw_prph_handler(fwrt, &prph_len,
813 					    iwl_fw_get_prph_len);
814 
815 		if (fwrt->trans->trans_cfg->device_family ==
816 		    IWL_DEVICE_FAMILY_7000 &&
817 		    iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG))
818 			radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ;
819 	}
820 
821 	file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len;
822 
823 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO))
824 		file_len += sizeof(*dump_data) + sizeof(*dump_info);
825 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG))
826 		file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg);
827 
828 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) {
829 		size_t hdr_len = sizeof(*dump_data) +
830 				 sizeof(struct iwl_fw_error_dump_mem);
831 
832 		/* Dump SRAM only if no mem_tlvs */
833 		if (!fwrt->fw->dbg.n_mem_tlv)
834 			ADD_LEN(file_len, sram_len, hdr_len);
835 
836 		/* Make room for all mem types that exist */
837 		ADD_LEN(file_len, smem_len, hdr_len);
838 		ADD_LEN(file_len, sram2_len, hdr_len);
839 
840 		for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++)
841 			ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len);
842 	}
843 
844 	/* Make room for fw's virtual image pages, if it exists */
845 	if (iwl_fw_dbg_is_paging_enabled(fwrt))
846 		file_len += fwrt->num_of_paging_blk *
847 			(sizeof(*dump_data) +
848 			 sizeof(struct iwl_fw_error_dump_paging) +
849 			 PAGING_BLOCK_SIZE);
850 
851 	if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
852 		file_len += sizeof(*dump_data) +
853 			fwrt->trans->cfg->d3_debug_data_length * 2;
854 	}
855 
856 	/* If we only want a monitor dump, reset the file length */
857 	if (data->monitor_only) {
858 		file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 +
859 			   sizeof(*dump_info) + sizeof(*dump_smem_cfg);
860 	}
861 
862 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) &&
863 	    data->desc)
864 		file_len += sizeof(*dump_data) + sizeof(*dump_trig) +
865 			data->desc->len;
866 
867 	dump_file = vzalloc(file_len);
868 	if (!dump_file)
869 		return NULL;
870 
871 	fw_error_dump->fwrt_ptr = dump_file;
872 
873 	dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER);
874 	dump_data = (void *)dump_file->data;
875 
876 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) {
877 		dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO);
878 		dump_data->len = cpu_to_le32(sizeof(*dump_info));
879 		dump_info = (void *)dump_data->data;
880 		dump_info->hw_type =
881 			cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev));
882 		dump_info->hw_step =
883 			cpu_to_le32(fwrt->trans->hw_rev_step);
884 		memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable,
885 		       sizeof(dump_info->fw_human_readable));
886 		strncpy(dump_info->dev_human_readable, fwrt->trans->name,
887 			sizeof(dump_info->dev_human_readable) - 1);
888 		strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name,
889 			sizeof(dump_info->bus_human_readable) - 1);
890 		dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs;
891 		dump_info->lmac_err_id[0] =
892 			cpu_to_le32(fwrt->dump.lmac_err_id[0]);
893 		if (fwrt->smem_cfg.num_lmacs > 1)
894 			dump_info->lmac_err_id[1] =
895 				cpu_to_le32(fwrt->dump.lmac_err_id[1]);
896 		dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id);
897 
898 		dump_data = iwl_fw_error_next_data(dump_data);
899 	}
900 
901 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) {
902 		/* Dump shared memory configuration */
903 		dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG);
904 		dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg));
905 		dump_smem_cfg = (void *)dump_data->data;
906 		dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs);
907 		dump_smem_cfg->num_txfifo_entries =
908 			cpu_to_le32(mem_cfg->num_txfifo_entries);
909 		for (i = 0; i < MAX_NUM_LMAC; i++) {
910 			int j;
911 			u32 *txf_size = mem_cfg->lmac[i].txfifo_size;
912 
913 			for (j = 0; j < TX_FIFO_MAX_NUM; j++)
914 				dump_smem_cfg->lmac[i].txfifo_size[j] =
915 					cpu_to_le32(txf_size[j]);
916 			dump_smem_cfg->lmac[i].rxfifo1_size =
917 				cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size);
918 		}
919 		dump_smem_cfg->rxfifo2_size =
920 			cpu_to_le32(mem_cfg->rxfifo2_size);
921 		dump_smem_cfg->internal_txfifo_addr =
922 			cpu_to_le32(mem_cfg->internal_txfifo_addr);
923 		for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) {
924 			dump_smem_cfg->internal_txfifo_size[i] =
925 				cpu_to_le32(mem_cfg->internal_txfifo_size[i]);
926 		}
927 
928 		dump_data = iwl_fw_error_next_data(dump_data);
929 	}
930 
931 	/* We only dump the FIFOs if the FW is in error state */
932 	if (fifo_len) {
933 		iwl_fw_dump_rxf(fwrt, &dump_data);
934 		iwl_fw_dump_txf(fwrt, &dump_data);
935 	}
936 
937 	if (radio_len)
938 		iwl_read_radio_regs(fwrt, &dump_data);
939 
940 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) &&
941 	    data->desc) {
942 		dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO);
943 		dump_data->len = cpu_to_le32(sizeof(*dump_trig) +
944 					     data->desc->len);
945 		dump_trig = (void *)dump_data->data;
946 		memcpy(dump_trig, &data->desc->trig_desc,
947 		       sizeof(*dump_trig) + data->desc->len);
948 
949 		dump_data = iwl_fw_error_next_data(dump_data);
950 	}
951 
952 	/* In case we only want monitor dump, skip to dump trasport data */
953 	if (data->monitor_only)
954 		goto out;
955 
956 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) {
957 		const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem =
958 			fwrt->fw->dbg.mem_tlv;
959 
960 		if (!fwrt->fw->dbg.n_mem_tlv)
961 			iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs,
962 					IWL_FW_ERROR_DUMP_MEM_SRAM);
963 
964 		for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) {
965 			u32 len = le32_to_cpu(fw_dbg_mem[i].len);
966 			u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs);
967 
968 			iwl_fw_dump_mem(fwrt, &dump_data, len, ofs,
969 					le32_to_cpu(fw_dbg_mem[i].data_type));
970 		}
971 
972 		iwl_fw_dump_mem(fwrt, &dump_data, smem_len,
973 				fwrt->trans->cfg->smem_offset,
974 				IWL_FW_ERROR_DUMP_MEM_SMEM);
975 
976 		iwl_fw_dump_mem(fwrt, &dump_data, sram2_len,
977 				fwrt->trans->cfg->dccm2_offset,
978 				IWL_FW_ERROR_DUMP_MEM_SRAM);
979 	}
980 
981 	if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
982 		u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr;
983 		size_t data_size = fwrt->trans->cfg->d3_debug_data_length;
984 
985 		dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA);
986 		dump_data->len = cpu_to_le32(data_size * 2);
987 
988 		memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size);
989 
990 		kfree(fwrt->dump.d3_debug_data);
991 		fwrt->dump.d3_debug_data = NULL;
992 
993 		iwl_trans_read_mem_bytes(fwrt->trans, addr,
994 					 dump_data->data + data_size,
995 					 data_size);
996 
997 		if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
998 			fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr,
999 						     dump_data->data + data_size,
1000 						     data_size);
1001 
1002 		dump_data = iwl_fw_error_next_data(dump_data);
1003 	}
1004 
1005 	/* Dump fw's virtual image */
1006 	if (iwl_fw_dbg_is_paging_enabled(fwrt))
1007 		iwl_dump_paging(fwrt, &dump_data);
1008 
1009 	if (prph_len)
1010 		iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph);
1011 
1012 out:
1013 	dump_file->file_len = cpu_to_le32(file_len);
1014 	return dump_file;
1015 }
1016 
1017 /**
1018  * struct iwl_dump_ini_region_data - region data
1019  * @reg_tlv: region TLV
1020  * @dump_data: dump data
1021  */
1022 struct iwl_dump_ini_region_data {
1023 	struct iwl_ucode_tlv *reg_tlv;
1024 	struct iwl_fwrt_dump_data *dump_data;
1025 };
1026 
1027 static int
1028 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt,
1029 			   struct iwl_dump_ini_region_data *reg_data,
1030 			   void *range_ptr, int idx)
1031 {
1032 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1033 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1034 	__le32 *val = range->data;
1035 	u32 prph_val;
1036 	u32 addr = le32_to_cpu(reg->addrs[idx]) +
1037 		   le32_to_cpu(reg->dev_addr.offset);
1038 	int i;
1039 
1040 	range->internal_base_addr = cpu_to_le32(addr);
1041 	range->range_data_size = reg->dev_addr.size;
1042 	for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1043 		prph_val = iwl_read_prph(fwrt->trans, addr + i);
1044 		if (prph_val == 0x5a5a5a5a)
1045 			return -EBUSY;
1046 		*val++ = cpu_to_le32(prph_val);
1047 	}
1048 
1049 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1050 }
1051 
1052 static int
1053 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt,
1054 			   struct iwl_dump_ini_region_data *reg_data,
1055 			   void *range_ptr, int idx)
1056 {
1057 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1058 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1059 	__le32 *val = range->data;
1060 	u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1;
1061 	u32 indirect_rd_addr = WMAL_MRSPF_1;
1062 	u32 prph_val;
1063 	u32 addr = le32_to_cpu(reg->addrs[idx]);
1064 	u32 dphy_state;
1065 	u32 dphy_addr;
1066 	int i;
1067 
1068 	range->internal_base_addr = cpu_to_le32(addr);
1069 	range->range_data_size = reg->dev_addr.size;
1070 
1071 	if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
1072 		indirect_wr_addr = WMAL_INDRCT_CMD1;
1073 
1074 	indirect_wr_addr += le32_to_cpu(reg->dev_addr.offset);
1075 	indirect_rd_addr += le32_to_cpu(reg->dev_addr.offset);
1076 
1077 	if (!iwl_trans_grab_nic_access(fwrt->trans))
1078 		return -EBUSY;
1079 
1080 	dphy_addr = (reg->dev_addr.offset) ? WFPM_LMAC2_PS_CTL_RW :
1081 					     WFPM_LMAC1_PS_CTL_RW;
1082 	dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr);
1083 
1084 	for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1085 		if (dphy_state == HBUS_TIMEOUT ||
1086 		    (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) !=
1087 		    WFPM_PHYRF_STATE_ON) {
1088 			*val++ = cpu_to_le32(WFPM_DPHY_OFF);
1089 			continue;
1090 		}
1091 
1092 		iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr,
1093 				       WMAL_INDRCT_CMD(addr + i));
1094 		prph_val = iwl_read_prph_no_grab(fwrt->trans,
1095 						 indirect_rd_addr);
1096 		*val++ = cpu_to_le32(prph_val);
1097 	}
1098 
1099 	iwl_trans_release_nic_access(fwrt->trans);
1100 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1101 }
1102 
1103 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt,
1104 				 struct iwl_dump_ini_region_data *reg_data,
1105 				 void *range_ptr, int idx)
1106 {
1107 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1108 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1109 	__le32 *val = range->data;
1110 	u32 addr = le32_to_cpu(reg->addrs[idx]) +
1111 		   le32_to_cpu(reg->dev_addr.offset);
1112 	int i;
1113 
1114 	range->internal_base_addr = cpu_to_le32(addr);
1115 	range->range_data_size = reg->dev_addr.size;
1116 	for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4)
1117 		*val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i));
1118 
1119 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1120 }
1121 
1122 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt,
1123 				    struct iwl_dump_ini_region_data *reg_data,
1124 				    void *range_ptr, int idx)
1125 {
1126 	struct iwl_trans *trans = fwrt->trans;
1127 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1128 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1129 	__le32 *val = range->data;
1130 	u32 addr = le32_to_cpu(reg->addrs[idx]) +
1131 		   le32_to_cpu(reg->dev_addr.offset);
1132 	int i;
1133 
1134 	/* we shouldn't get here if the trans doesn't have read_config32 */
1135 	if (WARN_ON_ONCE(!trans->ops->read_config32))
1136 		return -EOPNOTSUPP;
1137 
1138 	range->internal_base_addr = cpu_to_le32(addr);
1139 	range->range_data_size = reg->dev_addr.size;
1140 	for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1141 		int ret;
1142 		u32 tmp;
1143 
1144 		ret = trans->ops->read_config32(trans, addr + i, &tmp);
1145 		if (ret < 0)
1146 			return ret;
1147 
1148 		*val++ = cpu_to_le32(tmp);
1149 	}
1150 
1151 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1152 }
1153 
1154 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt,
1155 				     struct iwl_dump_ini_region_data *reg_data,
1156 				     void *range_ptr, int idx)
1157 {
1158 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1159 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1160 	u32 addr = le32_to_cpu(reg->addrs[idx]) +
1161 		   le32_to_cpu(reg->dev_addr.offset);
1162 
1163 	range->internal_base_addr = cpu_to_le32(addr);
1164 	range->range_data_size = reg->dev_addr.size;
1165 	iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1166 				 le32_to_cpu(reg->dev_addr.size));
1167 
1168 	if (reg->sub_type == IWL_FW_INI_REGION_DEVICE_MEMORY_SUBTYPE_HW_SMEM &&
1169 	    fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf)
1170 		fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx,
1171 					     range->data,
1172 					     le32_to_cpu(reg->dev_addr.size));
1173 
1174 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1175 }
1176 
1177 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt,
1178 				     void *range_ptr, int idx)
1179 {
1180 	struct page *page = fwrt->fw_paging_db[idx].fw_paging_block;
1181 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1182 	dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys;
1183 	u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size;
1184 
1185 	range->page_num = cpu_to_le32(idx);
1186 	range->range_data_size = cpu_to_le32(page_size);
1187 	dma_sync_single_for_cpu(fwrt->trans->dev, addr,	page_size,
1188 				DMA_BIDIRECTIONAL);
1189 	memcpy(range->data, page_address(page), page_size);
1190 	dma_sync_single_for_device(fwrt->trans->dev, addr, page_size,
1191 				   DMA_BIDIRECTIONAL);
1192 
1193 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1194 }
1195 
1196 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt,
1197 				    struct iwl_dump_ini_region_data *reg_data,
1198 				    void *range_ptr, int idx)
1199 {
1200 	struct iwl_fw_ini_error_dump_range *range;
1201 	u32 page_size;
1202 
1203 	/* all paged index start from 1 to skip CSS section */
1204 	idx++;
1205 
1206 	if (!fwrt->trans->trans_cfg->gen2)
1207 		return _iwl_dump_ini_paging_iter(fwrt, range_ptr, idx);
1208 
1209 	range = range_ptr;
1210 	page_size = fwrt->trans->init_dram.paging[idx].size;
1211 
1212 	range->page_num = cpu_to_le32(idx);
1213 	range->range_data_size = cpu_to_le32(page_size);
1214 	memcpy(range->data, fwrt->trans->init_dram.paging[idx].block,
1215 	       page_size);
1216 
1217 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1218 }
1219 
1220 static int
1221 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt,
1222 			   struct iwl_dump_ini_region_data *reg_data,
1223 			   void *range_ptr, int idx)
1224 {
1225 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1226 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1227 	struct iwl_dram_data *frag;
1228 	u32 alloc_id = le32_to_cpu(reg->dram_alloc_id);
1229 
1230 	frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx];
1231 
1232 	range->dram_base_addr = cpu_to_le64(frag->physical);
1233 	range->range_data_size = cpu_to_le32(frag->size);
1234 
1235 	memcpy(range->data, frag->block, frag->size);
1236 
1237 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1238 }
1239 
1240 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt,
1241 				      struct iwl_dump_ini_region_data *reg_data,
1242 				      void *range_ptr, int idx)
1243 {
1244 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1245 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1246 	u32 addr = le32_to_cpu(reg->internal_buffer.base_addr);
1247 
1248 	range->internal_base_addr = cpu_to_le32(addr);
1249 	range->range_data_size = reg->internal_buffer.size;
1250 	iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1251 				 le32_to_cpu(reg->internal_buffer.size));
1252 
1253 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1254 }
1255 
1256 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt,
1257 			     struct iwl_dump_ini_region_data *reg_data, int idx)
1258 {
1259 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1260 	struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1261 	struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
1262 	int txf_num = cfg->num_txfifo_entries;
1263 	int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size);
1264 	u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]);
1265 
1266 	if (!idx) {
1267 		if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) {
1268 			IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n",
1269 				le32_to_cpu(reg->fifos.offset));
1270 			return false;
1271 		}
1272 
1273 		iter->internal_txf = 0;
1274 		iter->fifo_size = 0;
1275 		iter->fifo = -1;
1276 		if (le32_to_cpu(reg->fifos.offset))
1277 			iter->lmac = 1;
1278 		else
1279 			iter->lmac = 0;
1280 	}
1281 
1282 	if (!iter->internal_txf) {
1283 		for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) {
1284 			iter->fifo_size =
1285 				cfg->lmac[iter->lmac].txfifo_size[iter->fifo];
1286 			if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo)))
1287 				return true;
1288 		}
1289 		iter->fifo--;
1290 	}
1291 
1292 	iter->internal_txf = 1;
1293 
1294 	if (!fw_has_capa(&fwrt->fw->ucode_capa,
1295 			 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))
1296 		return false;
1297 
1298 	for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) {
1299 		iter->fifo_size =
1300 			cfg->internal_txfifo_size[iter->fifo - txf_num];
1301 		if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo)))
1302 			return true;
1303 	}
1304 
1305 	return false;
1306 }
1307 
1308 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
1309 				 struct iwl_dump_ini_region_data *reg_data,
1310 				 void *range_ptr, int idx)
1311 {
1312 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1313 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1314 	struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1315 	struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data;
1316 	u32 offs = le32_to_cpu(reg->fifos.offset), addr;
1317 	u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1318 	u32 registers_size = registers_num * sizeof(*reg_dump);
1319 	__le32 *data;
1320 	int i;
1321 
1322 	if (!iwl_ini_txf_iter(fwrt, reg_data, idx))
1323 		return -EIO;
1324 
1325 	if (!iwl_trans_grab_nic_access(fwrt->trans))
1326 		return -EBUSY;
1327 
1328 	range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo);
1329 	range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num);
1330 	range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size);
1331 
1332 	iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo);
1333 
1334 	/*
1335 	 * read txf registers. for each register, write to the dump the
1336 	 * register address and its value
1337 	 */
1338 	for (i = 0; i < registers_num; i++) {
1339 		addr = le32_to_cpu(reg->addrs[i]) + offs;
1340 
1341 		reg_dump->addr = cpu_to_le32(addr);
1342 		reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans,
1343 								   addr));
1344 
1345 		reg_dump++;
1346 	}
1347 
1348 	if (reg->fifos.hdr_only) {
1349 		range->range_data_size = cpu_to_le32(registers_size);
1350 		goto out;
1351 	}
1352 
1353 	/* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
1354 	iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs,
1355 			       TXF_WR_PTR + offs);
1356 
1357 	/* Dummy-read to advance the read pointer to the head */
1358 	iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs);
1359 
1360 	/* Read FIFO */
1361 	addr = TXF_READ_MODIFY_DATA + offs;
1362 	data = (void *)reg_dump;
1363 	for (i = 0; i < iter->fifo_size; i += sizeof(*data))
1364 		*data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
1365 
1366 	if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf)
1367 		fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx,
1368 					     reg_dump, iter->fifo_size);
1369 
1370 out:
1371 	iwl_trans_release_nic_access(fwrt->trans);
1372 
1373 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1374 }
1375 
1376 struct iwl_ini_rxf_data {
1377 	u32 fifo_num;
1378 	u32 size;
1379 	u32 offset;
1380 };
1381 
1382 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt,
1383 				 struct iwl_dump_ini_region_data *reg_data,
1384 				 struct iwl_ini_rxf_data *data)
1385 {
1386 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1387 	u32 fid1 = le32_to_cpu(reg->fifos.fid[0]);
1388 	u32 fid2 = le32_to_cpu(reg->fifos.fid[1]);
1389 	u8 fifo_idx;
1390 
1391 	if (!data)
1392 		return;
1393 
1394 	/* make sure only one bit is set in only one fid */
1395 	if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1,
1396 		      "fid1=%x, fid2=%x\n", fid1, fid2))
1397 		return;
1398 
1399 	memset(data, 0, sizeof(*data));
1400 
1401 	if (fid1) {
1402 		fifo_idx = ffs(fid1) - 1;
1403 		if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n",
1404 			      fifo_idx))
1405 			return;
1406 
1407 		data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size;
1408 		data->fifo_num = fifo_idx;
1409 	} else {
1410 		u8 max_idx;
1411 
1412 		fifo_idx = ffs(fid2) - 1;
1413 		if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP,
1414 					    SHARED_MEM_CFG_CMD, 0) <= 3)
1415 			max_idx = 0;
1416 		else
1417 			max_idx = 1;
1418 
1419 		if (WARN_ONCE(fifo_idx > max_idx,
1420 			      "invalid umac fifo idx %d", fifo_idx))
1421 			return;
1422 
1423 		/* use bit 31 to distinguish between umac and lmac rxf while
1424 		 * parsing the dump
1425 		 */
1426 		data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT;
1427 
1428 		switch (fifo_idx) {
1429 		case 0:
1430 			data->size = fwrt->smem_cfg.rxfifo2_size;
1431 			data->offset = iwl_umac_prph(fwrt->trans,
1432 						     RXF_DIFF_FROM_PREV);
1433 			break;
1434 		case 1:
1435 			data->size = fwrt->smem_cfg.rxfifo2_control_size;
1436 			data->offset = iwl_umac_prph(fwrt->trans,
1437 						     RXF2C_DIFF_FROM_PREV);
1438 			break;
1439 		}
1440 	}
1441 }
1442 
1443 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,
1444 				 struct iwl_dump_ini_region_data *reg_data,
1445 				 void *range_ptr, int idx)
1446 {
1447 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1448 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1449 	struct iwl_ini_rxf_data rxf_data;
1450 	struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data;
1451 	u32 offs = le32_to_cpu(reg->fifos.offset), addr;
1452 	u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1453 	u32 registers_size = registers_num * sizeof(*reg_dump);
1454 	__le32 *data;
1455 	int i;
1456 
1457 	iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data);
1458 	if (!rxf_data.size)
1459 		return -EIO;
1460 
1461 	if (!iwl_trans_grab_nic_access(fwrt->trans))
1462 		return -EBUSY;
1463 
1464 	range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num);
1465 	range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num);
1466 	range->range_data_size = cpu_to_le32(rxf_data.size + registers_size);
1467 
1468 	/*
1469 	 * read rxf registers. for each register, write to the dump the
1470 	 * register address and its value
1471 	 */
1472 	for (i = 0; i < registers_num; i++) {
1473 		addr = le32_to_cpu(reg->addrs[i]) + offs;
1474 
1475 		reg_dump->addr = cpu_to_le32(addr);
1476 		reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans,
1477 								   addr));
1478 
1479 		reg_dump++;
1480 	}
1481 
1482 	if (reg->fifos.hdr_only) {
1483 		range->range_data_size = cpu_to_le32(registers_size);
1484 		goto out;
1485 	}
1486 
1487 	offs = rxf_data.offset;
1488 
1489 	/* Lock fence */
1490 	iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1);
1491 	/* Set fence pointer to the same place like WR pointer */
1492 	iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1);
1493 	/* Set fence offset */
1494 	iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs,
1495 			       0x0);
1496 
1497 	/* Read FIFO */
1498 	addr =  RXF_FIFO_RD_FENCE_INC + offs;
1499 	data = (void *)reg_dump;
1500 	for (i = 0; i < rxf_data.size; i += sizeof(*data))
1501 		*data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
1502 
1503 out:
1504 	iwl_trans_release_nic_access(fwrt->trans);
1505 
1506 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1507 }
1508 
1509 static int
1510 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt,
1511 			    struct iwl_dump_ini_region_data *reg_data,
1512 			    void *range_ptr, int idx)
1513 {
1514 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1515 	struct iwl_fw_ini_region_err_table *err_table = &reg->err_table;
1516 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1517 	u32 addr = le32_to_cpu(err_table->base_addr) +
1518 		   le32_to_cpu(err_table->offset);
1519 
1520 	range->internal_base_addr = cpu_to_le32(addr);
1521 	range->range_data_size = err_table->size;
1522 	iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1523 				 le32_to_cpu(err_table->size));
1524 
1525 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1526 }
1527 
1528 static int
1529 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt,
1530 			      struct iwl_dump_ini_region_data *reg_data,
1531 			      void *range_ptr, int idx)
1532 {
1533 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1534 	struct iwl_fw_ini_region_special_device_memory *special_mem =
1535 		&reg->special_mem;
1536 
1537 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1538 	u32 addr = le32_to_cpu(special_mem->base_addr) +
1539 		   le32_to_cpu(special_mem->offset);
1540 
1541 	range->internal_base_addr = cpu_to_le32(addr);
1542 	range->range_data_size = special_mem->size;
1543 	iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1544 				 le32_to_cpu(special_mem->size));
1545 
1546 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1547 }
1548 
1549 static int
1550 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt,
1551 			    struct iwl_dump_ini_region_data *reg_data,
1552 			    void *range_ptr, int idx)
1553 {
1554 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1555 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1556 	__le32 *val = range->data;
1557 	u32 prph_data;
1558 	int i;
1559 
1560 	if (!iwl_trans_grab_nic_access(fwrt->trans))
1561 		return -EBUSY;
1562 
1563 	range->range_data_size = reg->dev_addr.size;
1564 	iwl_write_prph_no_grab(fwrt->trans, DBGI_SRAM_TARGET_ACCESS_CFG,
1565 			       DBGI_SRAM_TARGET_ACCESS_CFG_RESET_ADDRESS_MSK);
1566 	for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) {
1567 		prph_data = iwl_read_prph_no_grab(fwrt->trans, (i % 2) ?
1568 					  DBGI_SRAM_TARGET_ACCESS_RDATA_MSB :
1569 					  DBGI_SRAM_TARGET_ACCESS_RDATA_LSB);
1570 		if (prph_data == 0x5a5a5a5a) {
1571 			iwl_trans_release_nic_access(fwrt->trans);
1572 			return -EBUSY;
1573 		}
1574 		*val++ = cpu_to_le32(prph_data);
1575 	}
1576 	iwl_trans_release_nic_access(fwrt->trans);
1577 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1578 }
1579 
1580 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt,
1581 				    struct iwl_dump_ini_region_data *reg_data,
1582 				    void *range_ptr, int idx)
1583 {
1584 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1585 	struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt;
1586 	u32 pkt_len;
1587 
1588 	if (!pkt)
1589 		return -EIO;
1590 
1591 	pkt_len = iwl_rx_packet_payload_len(pkt);
1592 
1593 	memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr));
1594 	range->range_data_size = cpu_to_le32(pkt_len);
1595 
1596 	memcpy(range->data, pkt->data, pkt_len);
1597 
1598 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1599 }
1600 
1601 static void *
1602 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt,
1603 			     struct iwl_dump_ini_region_data *reg_data,
1604 			     void *data)
1605 {
1606 	struct iwl_fw_ini_error_dump *dump = data;
1607 
1608 	dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1609 
1610 	return dump->data;
1611 }
1612 
1613 /**
1614  * mask_apply_and_normalize - applies mask on val and normalize the result
1615  *
1616  * The normalization is based on the first set bit in the mask
1617  *
1618  * @val: value
1619  * @mask: mask to apply and to normalize with
1620  */
1621 static u32 mask_apply_and_normalize(u32 val, u32 mask)
1622 {
1623 	return (val & mask) >> (ffs(mask) - 1);
1624 }
1625 
1626 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id,
1627 			      const struct iwl_fw_mon_reg *reg_info)
1628 {
1629 	u32 val, offs;
1630 
1631 	/* The header addresses of DBGCi is calculate as follows:
1632 	 * DBGC1 address + (0x100 * i)
1633 	 */
1634 	offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100;
1635 
1636 	if (!reg_info || !reg_info->addr || !reg_info->mask)
1637 		return 0;
1638 
1639 	val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs);
1640 
1641 	return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask));
1642 }
1643 
1644 static void *
1645 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt,
1646 			     struct iwl_dump_ini_region_data *reg_data,
1647 			     struct iwl_fw_ini_monitor_dump *data,
1648 			     const struct iwl_fw_mon_regs *addrs)
1649 {
1650 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1651 	u32 alloc_id = le32_to_cpu(reg->dram_alloc_id);
1652 
1653 	if (!iwl_trans_grab_nic_access(fwrt->trans)) {
1654 		IWL_ERR(fwrt, "Failed to get monitor header\n");
1655 		return NULL;
1656 	}
1657 
1658 	data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id,
1659 					  &addrs->write_ptr);
1660 	if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1661 		u32 wrt_ptr = le32_to_cpu(data->write_ptr);
1662 
1663 		data->write_ptr = cpu_to_le32(wrt_ptr >> 2);
1664 	}
1665 	data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id,
1666 					  &addrs->cycle_cnt);
1667 	data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id,
1668 					 &addrs->cur_frag);
1669 
1670 	iwl_trans_release_nic_access(fwrt->trans);
1671 
1672 	data->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1673 
1674 	return data->data;
1675 }
1676 
1677 static void *
1678 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt,
1679 				  struct iwl_dump_ini_region_data *reg_data,
1680 				  void *data)
1681 {
1682 	struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1683 
1684 	return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump,
1685 					    &fwrt->trans->cfg->mon_dram_regs);
1686 }
1687 
1688 static void *
1689 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt,
1690 				  struct iwl_dump_ini_region_data *reg_data,
1691 				  void *data)
1692 {
1693 	struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1694 
1695 	return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump,
1696 					    &fwrt->trans->cfg->mon_smem_regs);
1697 }
1698 
1699 static void *
1700 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt,
1701 				   struct iwl_dump_ini_region_data *reg_data,
1702 				   void *data)
1703 {
1704 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1705 	struct iwl_fw_ini_err_table_dump *dump = data;
1706 
1707 	dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1708 	dump->version = reg->err_table.version;
1709 
1710 	return dump->data;
1711 }
1712 
1713 static void *
1714 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt,
1715 				     struct iwl_dump_ini_region_data *reg_data,
1716 				     void *data)
1717 {
1718 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1719 	struct iwl_fw_ini_special_device_memory *dump = data;
1720 
1721 	dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1722 	dump->type = reg->special_mem.type;
1723 	dump->version = reg->special_mem.version;
1724 
1725 	return dump->data;
1726 }
1727 
1728 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt,
1729 				   struct iwl_dump_ini_region_data *reg_data)
1730 {
1731 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1732 
1733 	return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1734 }
1735 
1736 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt,
1737 				      struct iwl_dump_ini_region_data *reg_data)
1738 {
1739 	if (fwrt->trans->trans_cfg->gen2) {
1740 		if (fwrt->trans->init_dram.paging_cnt)
1741 			return fwrt->trans->init_dram.paging_cnt - 1;
1742 		else
1743 			return 0;
1744 	}
1745 
1746 	return fwrt->num_of_paging_blk;
1747 }
1748 
1749 static u32
1750 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt,
1751 			     struct iwl_dump_ini_region_data *reg_data)
1752 {
1753 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1754 	struct iwl_fw_mon *fw_mon;
1755 	u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);
1756 	int i;
1757 
1758 	fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
1759 
1760 	for (i = 0; i < fw_mon->num_frags; i++) {
1761 		if (!fw_mon->frags[i].size)
1762 			break;
1763 
1764 		ranges++;
1765 	}
1766 
1767 	return ranges;
1768 }
1769 
1770 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt,
1771 				   struct iwl_dump_ini_region_data *reg_data)
1772 {
1773 	u32 num_of_fifos = 0;
1774 
1775 	while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos))
1776 		num_of_fifos++;
1777 
1778 	return num_of_fifos;
1779 }
1780 
1781 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt,
1782 				     struct iwl_dump_ini_region_data *reg_data)
1783 {
1784 	return 1;
1785 }
1786 
1787 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt,
1788 				     struct iwl_dump_ini_region_data *reg_data)
1789 {
1790 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1791 	u32 size = le32_to_cpu(reg->dev_addr.size);
1792 	u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data);
1793 
1794 	if (!size || !ranges)
1795 		return 0;
1796 
1797 	return sizeof(struct iwl_fw_ini_error_dump) + ranges *
1798 		(size + sizeof(struct iwl_fw_ini_error_dump_range));
1799 }
1800 
1801 static u32
1802 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt,
1803 			     struct iwl_dump_ini_region_data *reg_data)
1804 {
1805 	int i;
1806 	u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range);
1807 	u32 size = sizeof(struct iwl_fw_ini_error_dump);
1808 
1809 	/* start from 1 to skip CSS section */
1810 	for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) {
1811 		size += range_header_len;
1812 		if (fwrt->trans->trans_cfg->gen2)
1813 			size += fwrt->trans->init_dram.paging[i].size;
1814 		else
1815 			size += fwrt->fw_paging_db[i].fw_paging_size;
1816 	}
1817 
1818 	return size;
1819 }
1820 
1821 static u32
1822 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt,
1823 			       struct iwl_dump_ini_region_data *reg_data)
1824 {
1825 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1826 	struct iwl_fw_mon *fw_mon;
1827 	u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);
1828 	int i;
1829 
1830 	fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
1831 
1832 	for (i = 0; i < fw_mon->num_frags; i++) {
1833 		struct iwl_dram_data *frag = &fw_mon->frags[i];
1834 
1835 		if (!frag->size)
1836 			break;
1837 
1838 		size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size;
1839 	}
1840 
1841 	if (size)
1842 		size += sizeof(struct iwl_fw_ini_monitor_dump);
1843 
1844 	return size;
1845 }
1846 
1847 static u32
1848 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt,
1849 			       struct iwl_dump_ini_region_data *reg_data)
1850 {
1851 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1852 	u32 size;
1853 
1854 	size = le32_to_cpu(reg->internal_buffer.size);
1855 	if (!size)
1856 		return 0;
1857 
1858 	size += sizeof(struct iwl_fw_ini_monitor_dump) +
1859 		sizeof(struct iwl_fw_ini_error_dump_range);
1860 
1861 	return size;
1862 }
1863 
1864 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt,
1865 				     struct iwl_dump_ini_region_data *reg_data)
1866 {
1867 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1868 	struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1869 	u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1870 	u32 size = 0;
1871 	u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) +
1872 		       registers_num *
1873 		       sizeof(struct iwl_fw_ini_error_dump_register);
1874 
1875 	while (iwl_ini_txf_iter(fwrt, reg_data, size)) {
1876 		size += fifo_hdr;
1877 		if (!reg->fifos.hdr_only)
1878 			size += iter->fifo_size;
1879 	}
1880 
1881 	if (!size)
1882 		return 0;
1883 
1884 	return size + sizeof(struct iwl_fw_ini_error_dump);
1885 }
1886 
1887 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt,
1888 				     struct iwl_dump_ini_region_data *reg_data)
1889 {
1890 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1891 	struct iwl_ini_rxf_data rx_data;
1892 	u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1893 	u32 size = sizeof(struct iwl_fw_ini_error_dump) +
1894 		sizeof(struct iwl_fw_ini_error_dump_range) +
1895 		registers_num * sizeof(struct iwl_fw_ini_error_dump_register);
1896 
1897 	if (reg->fifos.hdr_only)
1898 		return size;
1899 
1900 	iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data);
1901 	size += rx_data.size;
1902 
1903 	return size;
1904 }
1905 
1906 static u32
1907 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt,
1908 				struct iwl_dump_ini_region_data *reg_data)
1909 {
1910 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1911 	u32 size = le32_to_cpu(reg->err_table.size);
1912 
1913 	if (size)
1914 		size += sizeof(struct iwl_fw_ini_err_table_dump) +
1915 			sizeof(struct iwl_fw_ini_error_dump_range);
1916 
1917 	return size;
1918 }
1919 
1920 static u32
1921 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt,
1922 				  struct iwl_dump_ini_region_data *reg_data)
1923 {
1924 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1925 	u32 size = le32_to_cpu(reg->special_mem.size);
1926 
1927 	if (size)
1928 		size += sizeof(struct iwl_fw_ini_special_device_memory) +
1929 			sizeof(struct iwl_fw_ini_error_dump_range);
1930 
1931 	return size;
1932 }
1933 
1934 static u32
1935 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt,
1936 			     struct iwl_dump_ini_region_data *reg_data)
1937 {
1938 	u32 size = 0;
1939 
1940 	if (!reg_data->dump_data->fw_pkt)
1941 		return 0;
1942 
1943 	size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt);
1944 	if (size)
1945 		size += sizeof(struct iwl_fw_ini_error_dump) +
1946 			sizeof(struct iwl_fw_ini_error_dump_range);
1947 
1948 	return size;
1949 }
1950 
1951 /**
1952  * struct iwl_dump_ini_mem_ops - ini memory dump operations
1953  * @get_num_of_ranges: returns the number of memory ranges in the region.
1954  * @get_size: returns the total size of the region.
1955  * @fill_mem_hdr: fills region type specific headers and returns pointer to
1956  *	the first range or NULL if failed to fill headers.
1957  * @fill_range: copies a given memory range into the dump.
1958  *	Returns the size of the range or negative error value otherwise.
1959  */
1960 struct iwl_dump_ini_mem_ops {
1961 	u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt,
1962 				 struct iwl_dump_ini_region_data *reg_data);
1963 	u32 (*get_size)(struct iwl_fw_runtime *fwrt,
1964 			struct iwl_dump_ini_region_data *reg_data);
1965 	void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt,
1966 			      struct iwl_dump_ini_region_data *reg_data,
1967 			      void *data);
1968 	int (*fill_range)(struct iwl_fw_runtime *fwrt,
1969 			  struct iwl_dump_ini_region_data *reg_data,
1970 			  void *range, int idx);
1971 };
1972 
1973 /**
1974  * iwl_dump_ini_mem
1975  *
1976  * Creates a dump tlv and copy a memory region into it.
1977  * Returns the size of the current dump tlv or 0 if failed
1978  *
1979  * @fwrt: fw runtime struct
1980  * @list: list to add the dump tlv to
1981  * @reg_data: memory region
1982  * @ops: memory dump operations
1983  */
1984 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list,
1985 			    struct iwl_dump_ini_region_data *reg_data,
1986 			    const struct iwl_dump_ini_mem_ops *ops)
1987 {
1988 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1989 	struct iwl_fw_ini_dump_entry *entry;
1990 	struct iwl_fw_ini_error_dump_data *tlv;
1991 	struct iwl_fw_ini_error_dump_header *header;
1992 	u32 type = reg->type;
1993 	u32 id = le32_to_cpu(reg->id);
1994 	u32 num_of_ranges, i, size;
1995 	void *range;
1996 
1997 	/*
1998 	 * The higher part of the ID from 2 is irrelevant for
1999 	 * us, so mask it out.
2000 	 */
2001 	if (le32_to_cpu(reg->hdr.version) >= 2)
2002 		id &= IWL_FW_INI_REGION_V2_MASK;
2003 
2004 	if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr ||
2005 	    !ops->fill_range)
2006 		return 0;
2007 
2008 	size = ops->get_size(fwrt, reg_data);
2009 	if (!size)
2010 		return 0;
2011 
2012 	entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size);
2013 	if (!entry)
2014 		return 0;
2015 
2016 	entry->size = sizeof(*tlv) + size;
2017 
2018 	tlv = (void *)entry->data;
2019 	tlv->type = reg->type;
2020 	tlv->sub_type = reg->sub_type;
2021 	tlv->sub_type_ver = reg->sub_type_ver;
2022 	tlv->reserved = reg->reserved;
2023 	tlv->len = cpu_to_le32(size);
2024 
2025 	IWL_DEBUG_FW(fwrt, "WRT: Collecting region: id=%d, type=%d\n", id,
2026 		     type);
2027 
2028 	num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data);
2029 
2030 	header = (void *)tlv->data;
2031 	header->region_id = cpu_to_le32(id);
2032 	header->num_of_ranges = cpu_to_le32(num_of_ranges);
2033 	header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME);
2034 	memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME);
2035 
2036 	range = ops->fill_mem_hdr(fwrt, reg_data, header);
2037 	if (!range) {
2038 		IWL_ERR(fwrt,
2039 			"WRT: Failed to fill region header: id=%d, type=%d\n",
2040 			id, type);
2041 		goto out_err;
2042 	}
2043 
2044 	for (i = 0; i < num_of_ranges; i++) {
2045 		int range_size = ops->fill_range(fwrt, reg_data, range, i);
2046 
2047 		if (range_size < 0) {
2048 			IWL_ERR(fwrt,
2049 				"WRT: Failed to dump region: id=%d, type=%d\n",
2050 				id, type);
2051 			goto out_err;
2052 		}
2053 		range = range + range_size;
2054 	}
2055 
2056 	list_add_tail(&entry->list, list);
2057 
2058 	return entry->size;
2059 
2060 out_err:
2061 	vfree(entry);
2062 
2063 	return 0;
2064 }
2065 
2066 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt,
2067 			     struct iwl_fw_ini_trigger_tlv *trigger,
2068 			     struct list_head *list)
2069 {
2070 	struct iwl_fw_ini_dump_entry *entry;
2071 	struct iwl_fw_error_dump_data *tlv;
2072 	struct iwl_fw_ini_dump_info *dump;
2073 	struct iwl_dbg_tlv_node *node;
2074 	struct iwl_fw_ini_dump_cfg_name *cfg_name;
2075 	u32 size = sizeof(*tlv) + sizeof(*dump);
2076 	u32 num_of_cfg_names = 0;
2077 	u32 hw_type;
2078 
2079 	list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) {
2080 		size += sizeof(*cfg_name);
2081 		num_of_cfg_names++;
2082 	}
2083 
2084 	entry = vzalloc(sizeof(*entry) + size);
2085 	if (!entry)
2086 		return 0;
2087 
2088 	entry->size = size;
2089 
2090 	tlv = (void *)entry->data;
2091 	tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE);
2092 	tlv->len = cpu_to_le32(size - sizeof(*tlv));
2093 
2094 	dump = (void *)tlv->data;
2095 
2096 	dump->version = cpu_to_le32(IWL_INI_DUMP_VER);
2097 	dump->time_point = trigger->time_point;
2098 	dump->trigger_reason = trigger->trigger_reason;
2099 	dump->external_cfg_state =
2100 		cpu_to_le32(fwrt->trans->dbg.external_ini_cfg);
2101 
2102 	dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type);
2103 	dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype);
2104 
2105 	dump->hw_step = cpu_to_le32(fwrt->trans->hw_rev_step);
2106 
2107 	/*
2108 	 * Several HWs all have type == 0x42, so we'll override this value
2109 	 * according to the detected HW
2110 	 */
2111 	hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev);
2112 	if (hw_type == IWL_AX210_HW_TYPE) {
2113 		u32 prph_val = iwl_read_umac_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR);
2114 		u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT);
2115 		u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT);
2116 		u32 masked_bits = is_jacket | (is_cdb << 1);
2117 
2118 		/*
2119 		 * The HW type depends on certain bits in this case, so add
2120 		 * these bits to the HW type. We won't have collisions since we
2121 		 * add these bits after the highest possible bit in the mask.
2122 		 */
2123 		hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT;
2124 	}
2125 	dump->hw_type = cpu_to_le32(hw_type);
2126 
2127 	dump->rf_id_flavor =
2128 		cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id));
2129 	dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id));
2130 	dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id));
2131 	dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id));
2132 
2133 	dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major);
2134 	dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor);
2135 	dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major);
2136 	dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor);
2137 
2138 	dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest);
2139 	dump->regions_mask = trigger->regions_mask &
2140 			     ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk);
2141 
2142 	dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag));
2143 	memcpy(dump->build_tag, fwrt->fw->human_readable,
2144 	       sizeof(dump->build_tag));
2145 
2146 	cfg_name = dump->cfg_names;
2147 	dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names);
2148 	list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) {
2149 		struct iwl_fw_ini_debug_info_tlv *debug_info =
2150 			(void *)node->tlv.data;
2151 
2152 		cfg_name->image_type = debug_info->image_type;
2153 		cfg_name->cfg_name_len =
2154 			cpu_to_le32(IWL_FW_INI_MAX_CFG_NAME);
2155 		memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name,
2156 		       sizeof(cfg_name->cfg_name));
2157 		cfg_name++;
2158 	}
2159 
2160 	/* add dump info TLV to the beginning of the list since it needs to be
2161 	 * the first TLV in the dump
2162 	 */
2163 	list_add(&entry->list, list);
2164 
2165 	return entry->size;
2166 }
2167 
2168 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = {
2169 	[IWL_FW_INI_REGION_INVALID] = {},
2170 	[IWL_FW_INI_REGION_INTERNAL_BUFFER] = {
2171 		.get_num_of_ranges = iwl_dump_ini_single_range,
2172 		.get_size = iwl_dump_ini_mon_smem_get_size,
2173 		.fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header,
2174 		.fill_range = iwl_dump_ini_mon_smem_iter,
2175 	},
2176 	[IWL_FW_INI_REGION_DRAM_BUFFER] = {
2177 		.get_num_of_ranges = iwl_dump_ini_mon_dram_ranges,
2178 		.get_size = iwl_dump_ini_mon_dram_get_size,
2179 		.fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header,
2180 		.fill_range = iwl_dump_ini_mon_dram_iter,
2181 	},
2182 	[IWL_FW_INI_REGION_TXF] = {
2183 		.get_num_of_ranges = iwl_dump_ini_txf_ranges,
2184 		.get_size = iwl_dump_ini_txf_get_size,
2185 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2186 		.fill_range = iwl_dump_ini_txf_iter,
2187 	},
2188 	[IWL_FW_INI_REGION_RXF] = {
2189 		.get_num_of_ranges = iwl_dump_ini_single_range,
2190 		.get_size = iwl_dump_ini_rxf_get_size,
2191 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2192 		.fill_range = iwl_dump_ini_rxf_iter,
2193 	},
2194 	[IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = {
2195 		.get_num_of_ranges = iwl_dump_ini_single_range,
2196 		.get_size = iwl_dump_ini_err_table_get_size,
2197 		.fill_mem_hdr = iwl_dump_ini_err_table_fill_header,
2198 		.fill_range = iwl_dump_ini_err_table_iter,
2199 	},
2200 	[IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = {
2201 		.get_num_of_ranges = iwl_dump_ini_single_range,
2202 		.get_size = iwl_dump_ini_err_table_get_size,
2203 		.fill_mem_hdr = iwl_dump_ini_err_table_fill_header,
2204 		.fill_range = iwl_dump_ini_err_table_iter,
2205 	},
2206 	[IWL_FW_INI_REGION_RSP_OR_NOTIF] = {
2207 		.get_num_of_ranges = iwl_dump_ini_single_range,
2208 		.get_size = iwl_dump_ini_fw_pkt_get_size,
2209 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2210 		.fill_range = iwl_dump_ini_fw_pkt_iter,
2211 	},
2212 	[IWL_FW_INI_REGION_DEVICE_MEMORY] = {
2213 		.get_num_of_ranges = iwl_dump_ini_mem_ranges,
2214 		.get_size = iwl_dump_ini_mem_get_size,
2215 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2216 		.fill_range = iwl_dump_ini_dev_mem_iter,
2217 	},
2218 	[IWL_FW_INI_REGION_PERIPHERY_MAC] = {
2219 		.get_num_of_ranges = iwl_dump_ini_mem_ranges,
2220 		.get_size = iwl_dump_ini_mem_get_size,
2221 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2222 		.fill_range = iwl_dump_ini_prph_mac_iter,
2223 	},
2224 	[IWL_FW_INI_REGION_PERIPHERY_PHY] = {
2225 		.get_num_of_ranges = iwl_dump_ini_mem_ranges,
2226 		.get_size = iwl_dump_ini_mem_get_size,
2227 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2228 		.fill_range = iwl_dump_ini_prph_phy_iter,
2229 	},
2230 	[IWL_FW_INI_REGION_PERIPHERY_AUX] = {},
2231 	[IWL_FW_INI_REGION_PAGING] = {
2232 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2233 		.get_num_of_ranges = iwl_dump_ini_paging_ranges,
2234 		.get_size = iwl_dump_ini_paging_get_size,
2235 		.fill_range = iwl_dump_ini_paging_iter,
2236 	},
2237 	[IWL_FW_INI_REGION_CSR] = {
2238 		.get_num_of_ranges = iwl_dump_ini_mem_ranges,
2239 		.get_size = iwl_dump_ini_mem_get_size,
2240 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2241 		.fill_range = iwl_dump_ini_csr_iter,
2242 	},
2243 	[IWL_FW_INI_REGION_DRAM_IMR] = {},
2244 	[IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = {
2245 		.get_num_of_ranges = iwl_dump_ini_mem_ranges,
2246 		.get_size = iwl_dump_ini_mem_get_size,
2247 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2248 		.fill_range = iwl_dump_ini_config_iter,
2249 	},
2250 	[IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = {
2251 		.get_num_of_ranges = iwl_dump_ini_single_range,
2252 		.get_size = iwl_dump_ini_special_mem_get_size,
2253 		.fill_mem_hdr = iwl_dump_ini_special_mem_fill_header,
2254 		.fill_range = iwl_dump_ini_special_mem_iter,
2255 	},
2256 	[IWL_FW_INI_REGION_DBGI_SRAM] = {
2257 		.get_num_of_ranges = iwl_dump_ini_mem_ranges,
2258 		.get_size = iwl_dump_ini_mem_get_size,
2259 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2260 		.fill_range = iwl_dump_ini_dbgi_sram_iter,
2261 	},
2262 };
2263 
2264 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt,
2265 				struct iwl_fwrt_dump_data *dump_data,
2266 				struct list_head *list)
2267 {
2268 	struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig;
2269 	enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point);
2270 	struct iwl_dump_ini_region_data reg_data = {
2271 		.dump_data = dump_data,
2272 	};
2273 	int i;
2274 	u32 size = 0;
2275 	u64 regions_mask = le64_to_cpu(trigger->regions_mask) &
2276 			   ~(fwrt->trans->dbg.unsupported_region_msk);
2277 
2278 	BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask));
2279 	BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) <
2280 		     ARRAY_SIZE(fwrt->trans->dbg.active_regions));
2281 
2282 	for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) {
2283 		u32 reg_type;
2284 		struct iwl_fw_ini_region_tlv *reg;
2285 
2286 		if (!(BIT_ULL(i) & regions_mask))
2287 			continue;
2288 
2289 		reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i];
2290 		if (!reg_data.reg_tlv) {
2291 			IWL_WARN(fwrt,
2292 				 "WRT: Unassigned region id %d, skipping\n", i);
2293 			continue;
2294 		}
2295 
2296 		reg = (void *)reg_data.reg_tlv->data;
2297 		reg_type = reg->type;
2298 		if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops))
2299 			continue;
2300 
2301 		if (reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY &&
2302 		    tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) {
2303 			IWL_WARN(fwrt,
2304 				 "WRT: trying to collect phy prph at time point: %d, skipping\n",
2305 				 tp_id);
2306 			continue;
2307 		}
2308 
2309 		size += iwl_dump_ini_mem(fwrt, list, &reg_data,
2310 					 &iwl_dump_ini_region_ops[reg_type]);
2311 	}
2312 
2313 	if (size)
2314 		size += iwl_dump_ini_info(fwrt, trigger, list);
2315 
2316 	return size;
2317 }
2318 
2319 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt,
2320 				  struct iwl_fw_ini_trigger_tlv *trig)
2321 {
2322 	enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point);
2323 	u32 usec = le32_to_cpu(trig->ignore_consec);
2324 
2325 	if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
2326 	    tp_id == IWL_FW_INI_TIME_POINT_INVALID ||
2327 	    tp_id >= IWL_FW_INI_TIME_POINT_NUM ||
2328 	    iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec))
2329 		return false;
2330 
2331 	return true;
2332 }
2333 
2334 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt,
2335 				 struct iwl_fwrt_dump_data *dump_data,
2336 				 struct list_head *list)
2337 {
2338 	struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig;
2339 	struct iwl_fw_ini_dump_entry *entry;
2340 	struct iwl_fw_ini_dump_file_hdr *hdr;
2341 	u32 size;
2342 
2343 	if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) ||
2344 	    !le64_to_cpu(trigger->regions_mask))
2345 		return 0;
2346 
2347 	entry = vzalloc(sizeof(*entry) + sizeof(*hdr));
2348 	if (!entry)
2349 		return 0;
2350 
2351 	entry->size = sizeof(*hdr);
2352 
2353 	size = iwl_dump_ini_trigger(fwrt, dump_data, list);
2354 	if (!size) {
2355 		vfree(entry);
2356 		return 0;
2357 	}
2358 
2359 	hdr = (void *)entry->data;
2360 	hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER);
2361 	hdr->file_len = cpu_to_le32(size + entry->size);
2362 
2363 	list_add(&entry->list, list);
2364 
2365 	return le32_to_cpu(hdr->file_len);
2366 }
2367 
2368 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt,
2369 					 const struct iwl_fw_dump_desc *desc)
2370 {
2371 	if (desc && desc != &iwl_dump_desc_assert)
2372 		kfree(desc);
2373 
2374 	fwrt->dump.lmac_err_id[0] = 0;
2375 	if (fwrt->smem_cfg.num_lmacs > 1)
2376 		fwrt->dump.lmac_err_id[1] = 0;
2377 	fwrt->dump.umac_err_id = 0;
2378 }
2379 
2380 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt,
2381 			      struct iwl_fwrt_dump_data *dump_data)
2382 {
2383 	struct iwl_fw_dump_ptrs fw_error_dump = {};
2384 	struct iwl_fw_error_dump_file *dump_file;
2385 	struct scatterlist *sg_dump_data;
2386 	u32 file_len;
2387 	u32 dump_mask = fwrt->fw->dbg.dump_mask;
2388 
2389 	dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data);
2390 	if (!dump_file)
2391 		return;
2392 
2393 	if (dump_data->monitor_only)
2394 		dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR);
2395 
2396 	fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask,
2397 						      fwrt->sanitize_ops,
2398 						      fwrt->sanitize_ctx);
2399 	file_len = le32_to_cpu(dump_file->file_len);
2400 	fw_error_dump.fwrt_len = file_len;
2401 
2402 	if (fw_error_dump.trans_ptr) {
2403 		file_len += fw_error_dump.trans_ptr->len;
2404 		dump_file->file_len = cpu_to_le32(file_len);
2405 	}
2406 
2407 	sg_dump_data = alloc_sgtable(file_len);
2408 	if (sg_dump_data) {
2409 		sg_pcopy_from_buffer(sg_dump_data,
2410 				     sg_nents(sg_dump_data),
2411 				     fw_error_dump.fwrt_ptr,
2412 				     fw_error_dump.fwrt_len, 0);
2413 		if (fw_error_dump.trans_ptr)
2414 			sg_pcopy_from_buffer(sg_dump_data,
2415 					     sg_nents(sg_dump_data),
2416 					     fw_error_dump.trans_ptr->data,
2417 					     fw_error_dump.trans_ptr->len,
2418 					     fw_error_dump.fwrt_len);
2419 		dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
2420 			       GFP_KERNEL);
2421 	}
2422 	vfree(fw_error_dump.fwrt_ptr);
2423 	vfree(fw_error_dump.trans_ptr);
2424 }
2425 
2426 static void iwl_dump_ini_list_free(struct list_head *list)
2427 {
2428 	while (!list_empty(list)) {
2429 		struct iwl_fw_ini_dump_entry *entry =
2430 			list_entry(list->next, typeof(*entry), list);
2431 
2432 		list_del(&entry->list);
2433 		vfree(entry);
2434 	}
2435 }
2436 
2437 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data)
2438 {
2439 	dump_data->trig = NULL;
2440 	kfree(dump_data->fw_pkt);
2441 	dump_data->fw_pkt = NULL;
2442 }
2443 
2444 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt,
2445 				  struct iwl_fwrt_dump_data *dump_data)
2446 {
2447 	struct list_head dump_list = LIST_HEAD_INIT(dump_list);
2448 	struct scatterlist *sg_dump_data;
2449 	u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list);
2450 
2451 	if (!file_len)
2452 		return;
2453 
2454 	sg_dump_data = alloc_sgtable(file_len);
2455 	if (sg_dump_data) {
2456 		struct iwl_fw_ini_dump_entry *entry;
2457 		int sg_entries = sg_nents(sg_dump_data);
2458 		u32 offs = 0;
2459 
2460 		list_for_each_entry(entry, &dump_list, list) {
2461 			sg_pcopy_from_buffer(sg_dump_data, sg_entries,
2462 					     entry->data, entry->size, offs);
2463 			offs += entry->size;
2464 		}
2465 		dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
2466 			       GFP_KERNEL);
2467 	}
2468 	iwl_dump_ini_list_free(&dump_list);
2469 }
2470 
2471 const struct iwl_fw_dump_desc iwl_dump_desc_assert = {
2472 	.trig_desc = {
2473 		.type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT),
2474 	},
2475 };
2476 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert);
2477 
2478 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt,
2479 			    const struct iwl_fw_dump_desc *desc,
2480 			    bool monitor_only,
2481 			    unsigned int delay)
2482 {
2483 	struct iwl_fwrt_wk_data *wk_data;
2484 	unsigned long idx;
2485 
2486 	if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2487 		iwl_fw_free_dump_desc(fwrt, desc);
2488 		return 0;
2489 	}
2490 
2491 	/*
2492 	 * Check there is an available worker.
2493 	 * ffz return value is undefined if no zero exists,
2494 	 * so check against ~0UL first.
2495 	 */
2496 	if (fwrt->dump.active_wks == ~0UL)
2497 		return -EBUSY;
2498 
2499 	idx = ffz(fwrt->dump.active_wks);
2500 
2501 	if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM ||
2502 	    test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks))
2503 		return -EBUSY;
2504 
2505 	wk_data = &fwrt->dump.wks[idx];
2506 
2507 	if (WARN_ON(wk_data->dump_data.desc))
2508 		iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc);
2509 
2510 	wk_data->dump_data.desc = desc;
2511 	wk_data->dump_data.monitor_only = monitor_only;
2512 
2513 	IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n",
2514 		 le32_to_cpu(desc->trig_desc.type));
2515 
2516 	schedule_delayed_work(&wk_data->wk, usecs_to_jiffies(delay));
2517 
2518 	return 0;
2519 }
2520 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc);
2521 
2522 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt,
2523 			     enum iwl_fw_dbg_trigger trig_type)
2524 {
2525 	if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status))
2526 		return -EIO;
2527 
2528 	if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2529 		if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT &&
2530 		    trig_type != FW_DBG_TRIGGER_DRIVER)
2531 			return -EIO;
2532 
2533 		iwl_dbg_tlv_time_point(fwrt,
2534 				       IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT,
2535 				       NULL);
2536 	} else {
2537 		struct iwl_fw_dump_desc *iwl_dump_error_desc;
2538 		int ret;
2539 
2540 		iwl_dump_error_desc =
2541 			kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL);
2542 
2543 		if (!iwl_dump_error_desc)
2544 			return -ENOMEM;
2545 
2546 		iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type);
2547 		iwl_dump_error_desc->len = 0;
2548 
2549 		ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc,
2550 					      false, 0);
2551 		if (ret) {
2552 			kfree(iwl_dump_error_desc);
2553 			return ret;
2554 		}
2555 	}
2556 
2557 	iwl_trans_sync_nmi(fwrt->trans);
2558 
2559 	return 0;
2560 }
2561 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect);
2562 
2563 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt,
2564 		       enum iwl_fw_dbg_trigger trig,
2565 		       const char *str, size_t len,
2566 		       struct iwl_fw_dbg_trigger_tlv *trigger)
2567 {
2568 	struct iwl_fw_dump_desc *desc;
2569 	unsigned int delay = 0;
2570 	bool monitor_only = false;
2571 
2572 	if (trigger) {
2573 		u16 occurrences = le16_to_cpu(trigger->occurrences) - 1;
2574 
2575 		if (!le16_to_cpu(trigger->occurrences))
2576 			return 0;
2577 
2578 		if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) {
2579 			IWL_WARN(fwrt, "Force restart: trigger %d fired.\n",
2580 				 trig);
2581 			iwl_force_nmi(fwrt->trans);
2582 			return 0;
2583 		}
2584 
2585 		trigger->occurrences = cpu_to_le16(occurrences);
2586 		monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY;
2587 
2588 		/* convert msec to usec */
2589 		delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC;
2590 	}
2591 
2592 	desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC);
2593 	if (!desc)
2594 		return -ENOMEM;
2595 
2596 
2597 	desc->len = len;
2598 	desc->trig_desc.type = cpu_to_le32(trig);
2599 	memcpy(desc->trig_desc.data, str, len);
2600 
2601 	return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay);
2602 }
2603 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect);
2604 
2605 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt,
2606 			    struct iwl_fw_dbg_trigger_tlv *trigger,
2607 			    const char *fmt, ...)
2608 {
2609 	int ret, len = 0;
2610 	char buf[64];
2611 
2612 	if (iwl_trans_dbg_ini_valid(fwrt->trans))
2613 		return 0;
2614 
2615 	if (fmt) {
2616 		va_list ap;
2617 
2618 		buf[sizeof(buf) - 1] = '\0';
2619 
2620 		va_start(ap, fmt);
2621 		vsnprintf(buf, sizeof(buf), fmt, ap);
2622 		va_end(ap);
2623 
2624 		/* check for truncation */
2625 		if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
2626 			buf[sizeof(buf) - 1] = '\0';
2627 
2628 		len = strlen(buf) + 1;
2629 	}
2630 
2631 	ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len,
2632 				 trigger);
2633 
2634 	if (ret)
2635 		return ret;
2636 
2637 	return 0;
2638 }
2639 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig);
2640 
2641 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id)
2642 {
2643 	u8 *ptr;
2644 	int ret;
2645 	int i;
2646 
2647 	if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv),
2648 		      "Invalid configuration %d\n", conf_id))
2649 		return -EINVAL;
2650 
2651 	/* EARLY START - firmware's configuration is hard coded */
2652 	if ((!fwrt->fw->dbg.conf_tlv[conf_id] ||
2653 	     !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) &&
2654 	    conf_id == FW_DBG_START_FROM_ALIVE)
2655 		return 0;
2656 
2657 	if (!fwrt->fw->dbg.conf_tlv[conf_id])
2658 		return -EINVAL;
2659 
2660 	if (fwrt->dump.conf != FW_DBG_INVALID)
2661 		IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n",
2662 			 fwrt->dump.conf);
2663 
2664 	/* Send all HCMDs for configuring the FW debug */
2665 	ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd;
2666 	for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) {
2667 		struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
2668 		struct iwl_host_cmd hcmd = {
2669 			.id = cmd->id,
2670 			.len = { le16_to_cpu(cmd->len), },
2671 			.data = { cmd->data, },
2672 		};
2673 
2674 		ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
2675 		if (ret)
2676 			return ret;
2677 
2678 		ptr += sizeof(*cmd);
2679 		ptr += le16_to_cpu(cmd->len);
2680 	}
2681 
2682 	fwrt->dump.conf = conf_id;
2683 
2684 	return 0;
2685 }
2686 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf);
2687 
2688 /* this function assumes dump_start was called beforehand and dump_end will be
2689  * called afterwards
2690  */
2691 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx)
2692 {
2693 	struct iwl_fw_dbg_params params = {0};
2694 	struct iwl_fwrt_dump_data *dump_data =
2695 		&fwrt->dump.wks[wk_idx].dump_data;
2696 
2697 	if (!test_bit(wk_idx, &fwrt->dump.active_wks))
2698 		return;
2699 
2700 	if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) {
2701 		IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n");
2702 		goto out;
2703 	}
2704 
2705 	/* there's no point in fw dump if the bus is dead */
2706 	if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) {
2707 		IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n");
2708 		goto out;
2709 	}
2710 
2711 	iwl_fw_dbg_stop_restart_recording(fwrt, &params, true);
2712 
2713 	IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n");
2714 	if (iwl_trans_dbg_ini_valid(fwrt->trans))
2715 		iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data);
2716 	else
2717 		iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data);
2718 	IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n");
2719 
2720 	iwl_fw_dbg_stop_restart_recording(fwrt, &params, false);
2721 
2722 	if (fwrt->trans->dbg.last_tp_resetfw == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY)
2723 		iwl_force_nmi(fwrt->trans);
2724 
2725 out:
2726 	if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2727 		iwl_fw_error_dump_data_free(dump_data);
2728 	} else {
2729 		iwl_fw_free_dump_desc(fwrt, dump_data->desc);
2730 		dump_data->desc = NULL;
2731 	}
2732 
2733 	clear_bit(wk_idx, &fwrt->dump.active_wks);
2734 }
2735 
2736 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt,
2737 			   struct iwl_fwrt_dump_data *dump_data,
2738 			   bool sync)
2739 {
2740 	struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig;
2741 	enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point);
2742 	u32 occur, delay;
2743 	unsigned long idx;
2744 
2745 	if (!iwl_fw_ini_trigger_on(fwrt, trig)) {
2746 		IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n",
2747 			 tp_id);
2748 		return -EINVAL;
2749 	}
2750 
2751 	delay = le32_to_cpu(trig->dump_delay);
2752 	occur = le32_to_cpu(trig->occurrences);
2753 	if (!occur)
2754 		return 0;
2755 
2756 	trig->occurrences = cpu_to_le32(--occur);
2757 
2758 	/* Check there is an available worker.
2759 	 * ffz return value is undefined if no zero exists,
2760 	 * so check against ~0UL first.
2761 	 */
2762 	if (fwrt->dump.active_wks == ~0UL)
2763 		return -EBUSY;
2764 
2765 	idx = ffz(fwrt->dump.active_wks);
2766 
2767 	if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM ||
2768 	    test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks))
2769 		return -EBUSY;
2770 
2771 	fwrt->dump.wks[idx].dump_data = *dump_data;
2772 
2773 	if (sync)
2774 		delay = 0;
2775 
2776 	IWL_WARN(fwrt,
2777 		 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n",
2778 		 tp_id, (u32)(delay / USEC_PER_MSEC));
2779 
2780 	schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay));
2781 
2782 	if (sync)
2783 		iwl_fw_dbg_collect_sync(fwrt, idx);
2784 
2785 	return 0;
2786 }
2787 
2788 void iwl_fw_error_dump_wk(struct work_struct *work)
2789 {
2790 	struct iwl_fwrt_wk_data *wks =
2791 		container_of(work, typeof(*wks), wk.work);
2792 	struct iwl_fw_runtime *fwrt =
2793 		container_of(wks, typeof(*fwrt), dump.wks[wks->idx]);
2794 
2795 	/* assumes the op mode mutex is locked in dump_start since
2796 	 * iwl_fw_dbg_collect_sync can't run in parallel
2797 	 */
2798 	if (fwrt->ops && fwrt->ops->dump_start &&
2799 	    fwrt->ops->dump_start(fwrt->ops_ctx))
2800 		return;
2801 
2802 	iwl_fw_dbg_collect_sync(fwrt, wks->idx);
2803 
2804 	if (fwrt->ops && fwrt->ops->dump_end)
2805 		fwrt->ops->dump_end(fwrt->ops_ctx);
2806 }
2807 
2808 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt)
2809 {
2810 	const struct iwl_cfg *cfg = fwrt->trans->cfg;
2811 
2812 	if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt))
2813 		return;
2814 
2815 	if (!fwrt->dump.d3_debug_data) {
2816 		fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length,
2817 						   GFP_KERNEL);
2818 		if (!fwrt->dump.d3_debug_data) {
2819 			IWL_ERR(fwrt,
2820 				"failed to allocate memory for D3 debug data\n");
2821 			return;
2822 		}
2823 	}
2824 
2825 	/* if the buffer holds previous debug data it is overwritten */
2826 	iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr,
2827 				 fwrt->dump.d3_debug_data,
2828 				 cfg->d3_debug_data_length);
2829 
2830 	if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
2831 		fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx,
2832 					     cfg->d3_debug_data_base_addr,
2833 					     fwrt->dump.d3_debug_data,
2834 					     cfg->d3_debug_data_length);
2835 }
2836 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data);
2837 
2838 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt)
2839 {
2840 	int i;
2841 
2842 	iwl_dbg_tlv_del_timers(fwrt->trans);
2843 	for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++)
2844 		iwl_fw_dbg_collect_sync(fwrt, i);
2845 
2846 	iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true);
2847 }
2848 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync);
2849 
2850 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend)
2851 {
2852 	struct iwl_dbg_suspend_resume_cmd cmd = {
2853 		.operation = suspend ?
2854 			cpu_to_le32(DBGC_SUSPEND_CMD) :
2855 			cpu_to_le32(DBGC_RESUME_CMD),
2856 	};
2857 	struct iwl_host_cmd hcmd = {
2858 		.id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME),
2859 		.data[0] = &cmd,
2860 		.len[0] = sizeof(cmd),
2861 	};
2862 
2863 	return iwl_trans_send_cmd(trans, &hcmd);
2864 }
2865 
2866 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans,
2867 				      struct iwl_fw_dbg_params *params)
2868 {
2869 	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
2870 		iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
2871 		return;
2872 	}
2873 
2874 	if (params) {
2875 		params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE);
2876 		params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL);
2877 	}
2878 
2879 	iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);
2880 	/* wait for the DBGC to finish writing the internal buffer to DRAM to
2881 	 * avoid halting the HW while writing
2882 	 */
2883 	usleep_range(700, 1000);
2884 	iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0);
2885 }
2886 
2887 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans,
2888 					struct iwl_fw_dbg_params *params)
2889 {
2890 	if (!params)
2891 		return -EIO;
2892 
2893 	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
2894 		iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
2895 		iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
2896 		iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
2897 	} else {
2898 		iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample);
2899 		iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl);
2900 	}
2901 
2902 	return 0;
2903 }
2904 
2905 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt,
2906 				       struct iwl_fw_dbg_params *params,
2907 				       bool stop)
2908 {
2909 	int ret __maybe_unused = 0;
2910 
2911 	if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status))
2912 		return;
2913 
2914 	if (fw_has_capa(&fwrt->fw->ucode_capa,
2915 			IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP))
2916 		ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop);
2917 	else if (stop)
2918 		iwl_fw_dbg_stop_recording(fwrt->trans, params);
2919 	else
2920 		ret = iwl_fw_dbg_restart_recording(fwrt->trans, params);
2921 #ifdef CONFIG_IWLWIFI_DEBUGFS
2922 	if (!ret) {
2923 		if (stop)
2924 			fwrt->trans->dbg.rec_on = false;
2925 		else
2926 			iwl_fw_set_dbg_rec_on(fwrt);
2927 	}
2928 #endif
2929 }
2930 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording);
2931