1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/devcoredump.h> 8 #include "iwl-drv.h" 9 #include "runtime.h" 10 #include "dbg.h" 11 #include "debugfs.h" 12 #include "iwl-io.h" 13 #include "iwl-prph.h" 14 #include "iwl-csr.h" 15 #include "iwl-fh.h" 16 /** 17 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 18 * 19 * @fwrt_ptr: pointer to the buffer coming from fwrt 20 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 21 * transport's data. 22 * @trans_len: length of the valid data in trans_ptr 23 * @fwrt_len: length of the valid data in fwrt_ptr 24 */ 25 struct iwl_fw_dump_ptrs { 26 struct iwl_trans_dump_data *trans_ptr; 27 void *fwrt_ptr; 28 u32 fwrt_len; 29 }; 30 31 #define RADIO_REG_MAX_READ 0x2ad 32 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 33 struct iwl_fw_error_dump_data **dump_data) 34 { 35 u8 *pos = (void *)(*dump_data)->data; 36 int i; 37 38 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 39 40 if (!iwl_trans_grab_nic_access(fwrt->trans)) 41 return; 42 43 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 44 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 45 46 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 47 u32 rd_cmd = RADIO_RSP_RD_CMD; 48 49 rd_cmd |= i << RADIO_RSP_ADDR_POS; 50 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 51 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 52 53 pos++; 54 } 55 56 *dump_data = iwl_fw_error_next_data(*dump_data); 57 58 iwl_trans_release_nic_access(fwrt->trans); 59 } 60 61 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 62 struct iwl_fw_error_dump_data **dump_data, 63 int size, u32 offset, int fifo_num) 64 { 65 struct iwl_fw_error_dump_fifo *fifo_hdr; 66 u32 *fifo_data; 67 u32 fifo_len; 68 int i; 69 70 fifo_hdr = (void *)(*dump_data)->data; 71 fifo_data = (void *)fifo_hdr->data; 72 fifo_len = size; 73 74 /* No need to try to read the data if the length is 0 */ 75 if (fifo_len == 0) 76 return; 77 78 /* Add a TLV for the RXF */ 79 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 80 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 81 82 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 83 fifo_hdr->available_bytes = 84 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 85 RXF_RD_D_SPACE + offset)); 86 fifo_hdr->wr_ptr = 87 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 88 RXF_RD_WR_PTR + offset)); 89 fifo_hdr->rd_ptr = 90 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 91 RXF_RD_RD_PTR + offset)); 92 fifo_hdr->fence_ptr = 93 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 94 RXF_RD_FENCE_PTR + offset)); 95 fifo_hdr->fence_mode = 96 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 97 RXF_SET_FENCE_MODE + offset)); 98 99 /* Lock fence */ 100 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 101 /* Set fence pointer to the same place like WR pointer */ 102 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 103 /* Set fence offset */ 104 iwl_trans_write_prph(fwrt->trans, 105 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 106 107 /* Read FIFO */ 108 fifo_len /= sizeof(u32); /* Size in DWORDS */ 109 for (i = 0; i < fifo_len; i++) 110 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 111 RXF_FIFO_RD_FENCE_INC + 112 offset); 113 *dump_data = iwl_fw_error_next_data(*dump_data); 114 } 115 116 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 117 struct iwl_fw_error_dump_data **dump_data, 118 int size, u32 offset, int fifo_num) 119 { 120 struct iwl_fw_error_dump_fifo *fifo_hdr; 121 u32 *fifo_data; 122 u32 fifo_len; 123 int i; 124 125 fifo_hdr = (void *)(*dump_data)->data; 126 fifo_data = (void *)fifo_hdr->data; 127 fifo_len = size; 128 129 /* No need to try to read the data if the length is 0 */ 130 if (fifo_len == 0) 131 return; 132 133 /* Add a TLV for the FIFO */ 134 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 135 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 136 137 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 138 fifo_hdr->available_bytes = 139 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 140 TXF_FIFO_ITEM_CNT + offset)); 141 fifo_hdr->wr_ptr = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 TXF_WR_PTR + offset)); 144 fifo_hdr->rd_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 TXF_RD_PTR + offset)); 147 fifo_hdr->fence_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 TXF_FENCE_PTR + offset)); 150 fifo_hdr->fence_mode = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 TXF_LOCK_FENCE + offset)); 153 154 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 155 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 156 TXF_WR_PTR + offset); 157 158 /* Dummy-read to advance the read pointer to the head */ 159 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 160 161 /* Read FIFO */ 162 for (i = 0; i < fifo_len / sizeof(u32); i++) 163 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 164 TXF_READ_MODIFY_DATA + 165 offset); 166 167 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 168 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 169 fifo_data, fifo_len); 170 171 *dump_data = iwl_fw_error_next_data(*dump_data); 172 } 173 174 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 175 struct iwl_fw_error_dump_data **dump_data) 176 { 177 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 178 179 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 180 181 if (!iwl_trans_grab_nic_access(fwrt->trans)) 182 return; 183 184 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 185 /* Pull RXF1 */ 186 iwl_fwrt_dump_rxf(fwrt, dump_data, 187 cfg->lmac[0].rxfifo1_size, 0, 0); 188 /* Pull RXF2 */ 189 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 190 RXF_DIFF_FROM_PREV + 191 fwrt->trans->trans_cfg->umac_prph_offset, 1); 192 /* Pull LMAC2 RXF1 */ 193 if (fwrt->smem_cfg.num_lmacs > 1) 194 iwl_fwrt_dump_rxf(fwrt, dump_data, 195 cfg->lmac[1].rxfifo1_size, 196 LMAC2_PRPH_OFFSET, 2); 197 } 198 199 iwl_trans_release_nic_access(fwrt->trans); 200 } 201 202 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 203 struct iwl_fw_error_dump_data **dump_data) 204 { 205 struct iwl_fw_error_dump_fifo *fifo_hdr; 206 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 207 u32 *fifo_data; 208 u32 fifo_len; 209 int i, j; 210 211 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 212 213 if (!iwl_trans_grab_nic_access(fwrt->trans)) 214 return; 215 216 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 217 /* Pull TXF data from LMAC1 */ 218 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 219 /* Mark the number of TXF we're pulling now */ 220 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 221 iwl_fwrt_dump_txf(fwrt, dump_data, 222 cfg->lmac[0].txfifo_size[i], 0, i); 223 } 224 225 /* Pull TXF data from LMAC2 */ 226 if (fwrt->smem_cfg.num_lmacs > 1) { 227 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 228 i++) { 229 /* Mark the number of TXF we're pulling now */ 230 iwl_trans_write_prph(fwrt->trans, 231 TXF_LARC_NUM + 232 LMAC2_PRPH_OFFSET, i); 233 iwl_fwrt_dump_txf(fwrt, dump_data, 234 cfg->lmac[1].txfifo_size[i], 235 LMAC2_PRPH_OFFSET, 236 i + cfg->num_txfifo_entries); 237 } 238 } 239 } 240 241 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 242 fw_has_capa(&fwrt->fw->ucode_capa, 243 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 244 /* Pull UMAC internal TXF data from all TXFs */ 245 for (i = 0; 246 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 247 i++) { 248 fifo_hdr = (void *)(*dump_data)->data; 249 fifo_data = (void *)fifo_hdr->data; 250 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 251 252 /* No need to try to read the data if the length is 0 */ 253 if (fifo_len == 0) 254 continue; 255 256 /* Add a TLV for the internal FIFOs */ 257 (*dump_data)->type = 258 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 259 (*dump_data)->len = 260 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 261 262 fifo_hdr->fifo_num = cpu_to_le32(i); 263 264 /* Mark the number of TXF we're pulling now */ 265 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 266 fwrt->smem_cfg.num_txfifo_entries); 267 268 fifo_hdr->available_bytes = 269 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 270 TXF_CPU2_FIFO_ITEM_CNT)); 271 fifo_hdr->wr_ptr = 272 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 273 TXF_CPU2_WR_PTR)); 274 fifo_hdr->rd_ptr = 275 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 276 TXF_CPU2_RD_PTR)); 277 fifo_hdr->fence_ptr = 278 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 279 TXF_CPU2_FENCE_PTR)); 280 fifo_hdr->fence_mode = 281 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 282 TXF_CPU2_LOCK_FENCE)); 283 284 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 285 iwl_trans_write_prph(fwrt->trans, 286 TXF_CPU2_READ_MODIFY_ADDR, 287 TXF_CPU2_WR_PTR); 288 289 /* Dummy-read to advance the read pointer to head */ 290 iwl_trans_read_prph(fwrt->trans, 291 TXF_CPU2_READ_MODIFY_DATA); 292 293 /* Read FIFO */ 294 fifo_len /= sizeof(u32); /* Size in DWORDS */ 295 for (j = 0; j < fifo_len; j++) 296 fifo_data[j] = 297 iwl_trans_read_prph(fwrt->trans, 298 TXF_CPU2_READ_MODIFY_DATA); 299 *dump_data = iwl_fw_error_next_data(*dump_data); 300 } 301 } 302 303 iwl_trans_release_nic_access(fwrt->trans); 304 } 305 306 struct iwl_prph_range { 307 u32 start, end; 308 }; 309 310 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 311 { .start = 0x00a00000, .end = 0x00a00000 }, 312 { .start = 0x00a0000c, .end = 0x00a00024 }, 313 { .start = 0x00a0002c, .end = 0x00a0003c }, 314 { .start = 0x00a00410, .end = 0x00a00418 }, 315 { .start = 0x00a00420, .end = 0x00a00420 }, 316 { .start = 0x00a00428, .end = 0x00a00428 }, 317 { .start = 0x00a00430, .end = 0x00a0043c }, 318 { .start = 0x00a00444, .end = 0x00a00444 }, 319 { .start = 0x00a004c0, .end = 0x00a004cc }, 320 { .start = 0x00a004d8, .end = 0x00a004d8 }, 321 { .start = 0x00a004e0, .end = 0x00a004f0 }, 322 { .start = 0x00a00840, .end = 0x00a00840 }, 323 { .start = 0x00a00850, .end = 0x00a00858 }, 324 { .start = 0x00a01004, .end = 0x00a01008 }, 325 { .start = 0x00a01010, .end = 0x00a01010 }, 326 { .start = 0x00a01018, .end = 0x00a01018 }, 327 { .start = 0x00a01024, .end = 0x00a01024 }, 328 { .start = 0x00a0102c, .end = 0x00a01034 }, 329 { .start = 0x00a0103c, .end = 0x00a01040 }, 330 { .start = 0x00a01048, .end = 0x00a01094 }, 331 { .start = 0x00a01c00, .end = 0x00a01c20 }, 332 { .start = 0x00a01c58, .end = 0x00a01c58 }, 333 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 334 { .start = 0x00a01c28, .end = 0x00a01c54 }, 335 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 336 { .start = 0x00a01c60, .end = 0x00a01cdc }, 337 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 338 { .start = 0x00a01d18, .end = 0x00a01d20 }, 339 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 340 { .start = 0x00a01d40, .end = 0x00a01d5c }, 341 { .start = 0x00a01d80, .end = 0x00a01d80 }, 342 { .start = 0x00a01d98, .end = 0x00a01d9c }, 343 { .start = 0x00a01da8, .end = 0x00a01da8 }, 344 { .start = 0x00a01db8, .end = 0x00a01df4 }, 345 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 346 { .start = 0x00a01e00, .end = 0x00a01e2c }, 347 { .start = 0x00a01e40, .end = 0x00a01e60 }, 348 { .start = 0x00a01e68, .end = 0x00a01e6c }, 349 { .start = 0x00a01e74, .end = 0x00a01e74 }, 350 { .start = 0x00a01e84, .end = 0x00a01e90 }, 351 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 352 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 353 { .start = 0x00a01f00, .end = 0x00a01f1c }, 354 { .start = 0x00a01f44, .end = 0x00a01ffc }, 355 { .start = 0x00a02000, .end = 0x00a02048 }, 356 { .start = 0x00a02068, .end = 0x00a020f0 }, 357 { .start = 0x00a02100, .end = 0x00a02118 }, 358 { .start = 0x00a02140, .end = 0x00a0214c }, 359 { .start = 0x00a02168, .end = 0x00a0218c }, 360 { .start = 0x00a021c0, .end = 0x00a021c0 }, 361 { .start = 0x00a02400, .end = 0x00a02410 }, 362 { .start = 0x00a02418, .end = 0x00a02420 }, 363 { .start = 0x00a02428, .end = 0x00a0242c }, 364 { .start = 0x00a02434, .end = 0x00a02434 }, 365 { .start = 0x00a02440, .end = 0x00a02460 }, 366 { .start = 0x00a02468, .end = 0x00a024b0 }, 367 { .start = 0x00a024c8, .end = 0x00a024cc }, 368 { .start = 0x00a02500, .end = 0x00a02504 }, 369 { .start = 0x00a0250c, .end = 0x00a02510 }, 370 { .start = 0x00a02540, .end = 0x00a02554 }, 371 { .start = 0x00a02580, .end = 0x00a025f4 }, 372 { .start = 0x00a02600, .end = 0x00a0260c }, 373 { .start = 0x00a02648, .end = 0x00a02650 }, 374 { .start = 0x00a02680, .end = 0x00a02680 }, 375 { .start = 0x00a026c0, .end = 0x00a026d0 }, 376 { .start = 0x00a02700, .end = 0x00a0270c }, 377 { .start = 0x00a02804, .end = 0x00a02804 }, 378 { .start = 0x00a02818, .end = 0x00a0281c }, 379 { .start = 0x00a02c00, .end = 0x00a02db4 }, 380 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 381 { .start = 0x00a03000, .end = 0x00a03014 }, 382 { .start = 0x00a0301c, .end = 0x00a0302c }, 383 { .start = 0x00a03034, .end = 0x00a03038 }, 384 { .start = 0x00a03040, .end = 0x00a03048 }, 385 { .start = 0x00a03060, .end = 0x00a03068 }, 386 { .start = 0x00a03070, .end = 0x00a03074 }, 387 { .start = 0x00a0307c, .end = 0x00a0307c }, 388 { .start = 0x00a03080, .end = 0x00a03084 }, 389 { .start = 0x00a0308c, .end = 0x00a03090 }, 390 { .start = 0x00a03098, .end = 0x00a03098 }, 391 { .start = 0x00a030a0, .end = 0x00a030a0 }, 392 { .start = 0x00a030a8, .end = 0x00a030b4 }, 393 { .start = 0x00a030bc, .end = 0x00a030bc }, 394 { .start = 0x00a030c0, .end = 0x00a0312c }, 395 { .start = 0x00a03c00, .end = 0x00a03c5c }, 396 { .start = 0x00a04400, .end = 0x00a04454 }, 397 { .start = 0x00a04460, .end = 0x00a04474 }, 398 { .start = 0x00a044c0, .end = 0x00a044ec }, 399 { .start = 0x00a04500, .end = 0x00a04504 }, 400 { .start = 0x00a04510, .end = 0x00a04538 }, 401 { .start = 0x00a04540, .end = 0x00a04548 }, 402 { .start = 0x00a04560, .end = 0x00a0457c }, 403 { .start = 0x00a04590, .end = 0x00a04598 }, 404 { .start = 0x00a045c0, .end = 0x00a045f4 }, 405 }; 406 407 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 408 { .start = 0x00a05c00, .end = 0x00a05c18 }, 409 { .start = 0x00a05400, .end = 0x00a056e8 }, 410 { .start = 0x00a08000, .end = 0x00a098bc }, 411 { .start = 0x00a02400, .end = 0x00a02758 }, 412 { .start = 0x00a04764, .end = 0x00a0476c }, 413 { .start = 0x00a04770, .end = 0x00a04774 }, 414 { .start = 0x00a04620, .end = 0x00a04624 }, 415 }; 416 417 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 418 { .start = 0x00a00000, .end = 0x00a00000 }, 419 { .start = 0x00a0000c, .end = 0x00a00024 }, 420 { .start = 0x00a0002c, .end = 0x00a00034 }, 421 { .start = 0x00a0003c, .end = 0x00a0003c }, 422 { .start = 0x00a00410, .end = 0x00a00418 }, 423 { .start = 0x00a00420, .end = 0x00a00420 }, 424 { .start = 0x00a00428, .end = 0x00a00428 }, 425 { .start = 0x00a00430, .end = 0x00a0043c }, 426 { .start = 0x00a00444, .end = 0x00a00444 }, 427 { .start = 0x00a00840, .end = 0x00a00840 }, 428 { .start = 0x00a00850, .end = 0x00a00858 }, 429 { .start = 0x00a01004, .end = 0x00a01008 }, 430 { .start = 0x00a01010, .end = 0x00a01010 }, 431 { .start = 0x00a01018, .end = 0x00a01018 }, 432 { .start = 0x00a01024, .end = 0x00a01024 }, 433 { .start = 0x00a0102c, .end = 0x00a01034 }, 434 { .start = 0x00a0103c, .end = 0x00a01040 }, 435 { .start = 0x00a01048, .end = 0x00a01050 }, 436 { .start = 0x00a01058, .end = 0x00a01058 }, 437 { .start = 0x00a01060, .end = 0x00a01070 }, 438 { .start = 0x00a0108c, .end = 0x00a0108c }, 439 { .start = 0x00a01c20, .end = 0x00a01c28 }, 440 { .start = 0x00a01d10, .end = 0x00a01d10 }, 441 { .start = 0x00a01e28, .end = 0x00a01e2c }, 442 { .start = 0x00a01e60, .end = 0x00a01e60 }, 443 { .start = 0x00a01e80, .end = 0x00a01e80 }, 444 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 445 { .start = 0x00a02000, .end = 0x00a0201c }, 446 { .start = 0x00a02024, .end = 0x00a02024 }, 447 { .start = 0x00a02040, .end = 0x00a02048 }, 448 { .start = 0x00a020c0, .end = 0x00a020e0 }, 449 { .start = 0x00a02400, .end = 0x00a02404 }, 450 { .start = 0x00a0240c, .end = 0x00a02414 }, 451 { .start = 0x00a0241c, .end = 0x00a0243c }, 452 { .start = 0x00a02448, .end = 0x00a024bc }, 453 { .start = 0x00a024c4, .end = 0x00a024cc }, 454 { .start = 0x00a02508, .end = 0x00a02508 }, 455 { .start = 0x00a02510, .end = 0x00a02514 }, 456 { .start = 0x00a0251c, .end = 0x00a0251c }, 457 { .start = 0x00a0252c, .end = 0x00a0255c }, 458 { .start = 0x00a02564, .end = 0x00a025a0 }, 459 { .start = 0x00a025a8, .end = 0x00a025b4 }, 460 { .start = 0x00a025c0, .end = 0x00a025c0 }, 461 { .start = 0x00a025e8, .end = 0x00a025f4 }, 462 { .start = 0x00a02c08, .end = 0x00a02c18 }, 463 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 464 { .start = 0x00a02c68, .end = 0x00a02c78 }, 465 { .start = 0x00a03000, .end = 0x00a03000 }, 466 { .start = 0x00a03010, .end = 0x00a03014 }, 467 { .start = 0x00a0301c, .end = 0x00a0302c }, 468 { .start = 0x00a03034, .end = 0x00a03038 }, 469 { .start = 0x00a03040, .end = 0x00a03044 }, 470 { .start = 0x00a03060, .end = 0x00a03068 }, 471 { .start = 0x00a03070, .end = 0x00a03070 }, 472 { .start = 0x00a0307c, .end = 0x00a03084 }, 473 { .start = 0x00a0308c, .end = 0x00a03090 }, 474 { .start = 0x00a03098, .end = 0x00a03098 }, 475 { .start = 0x00a030a0, .end = 0x00a030a0 }, 476 { .start = 0x00a030a8, .end = 0x00a030b4 }, 477 { .start = 0x00a030bc, .end = 0x00a030c0 }, 478 { .start = 0x00a030c8, .end = 0x00a030f4 }, 479 { .start = 0x00a03100, .end = 0x00a0312c }, 480 { .start = 0x00a03c00, .end = 0x00a03c5c }, 481 { .start = 0x00a04400, .end = 0x00a04454 }, 482 { .start = 0x00a04460, .end = 0x00a04474 }, 483 { .start = 0x00a044c0, .end = 0x00a044ec }, 484 { .start = 0x00a04500, .end = 0x00a04504 }, 485 { .start = 0x00a04510, .end = 0x00a04538 }, 486 { .start = 0x00a04540, .end = 0x00a04548 }, 487 { .start = 0x00a04560, .end = 0x00a04560 }, 488 { .start = 0x00a04570, .end = 0x00a0457c }, 489 { .start = 0x00a04590, .end = 0x00a04590 }, 490 { .start = 0x00a04598, .end = 0x00a04598 }, 491 { .start = 0x00a045c0, .end = 0x00a045f4 }, 492 { .start = 0x00a05c18, .end = 0x00a05c1c }, 493 { .start = 0x00a0c000, .end = 0x00a0c018 }, 494 { .start = 0x00a0c020, .end = 0x00a0c028 }, 495 { .start = 0x00a0c038, .end = 0x00a0c094 }, 496 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 497 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 498 { .start = 0x00a0c150, .end = 0x00a0c174 }, 499 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 500 { .start = 0x00a0c190, .end = 0x00a0c198 }, 501 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 502 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 503 }; 504 505 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 506 { .start = 0x00d03c00, .end = 0x00d03c64 }, 507 { .start = 0x00d05c18, .end = 0x00d05c1c }, 508 { .start = 0x00d0c000, .end = 0x00d0c174 }, 509 }; 510 511 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 512 u32 len_bytes, __le32 *data) 513 { 514 u32 i; 515 516 for (i = 0; i < len_bytes; i += 4) 517 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 518 } 519 520 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 521 const struct iwl_prph_range *iwl_prph_dump_addr, 522 u32 range_len, void *ptr) 523 { 524 struct iwl_fw_error_dump_prph *prph; 525 struct iwl_trans *trans = fwrt->trans; 526 struct iwl_fw_error_dump_data **data = 527 (struct iwl_fw_error_dump_data **)ptr; 528 u32 i; 529 530 if (!data) 531 return; 532 533 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 534 535 if (!iwl_trans_grab_nic_access(trans)) 536 return; 537 538 for (i = 0; i < range_len; i++) { 539 /* The range includes both boundaries */ 540 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 541 iwl_prph_dump_addr[i].start + 4; 542 543 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 544 (*data)->len = cpu_to_le32(sizeof(*prph) + 545 num_bytes_in_chunk); 546 prph = (void *)(*data)->data; 547 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 548 549 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 550 /* our range is inclusive, hence + 4 */ 551 iwl_prph_dump_addr[i].end - 552 iwl_prph_dump_addr[i].start + 4, 553 (void *)prph->data); 554 555 *data = iwl_fw_error_next_data(*data); 556 } 557 558 iwl_trans_release_nic_access(trans); 559 } 560 561 /* 562 * alloc_sgtable - allocates scallerlist table in the given size, 563 * fills it with pages and returns it 564 * @size: the size (in bytes) of the table 565 */ 566 static struct scatterlist *alloc_sgtable(int size) 567 { 568 int alloc_size, nents, i; 569 struct page *new_page; 570 struct scatterlist *iter; 571 struct scatterlist *table; 572 573 nents = DIV_ROUND_UP(size, PAGE_SIZE); 574 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 575 if (!table) 576 return NULL; 577 sg_init_table(table, nents); 578 iter = table; 579 for_each_sg(table, iter, sg_nents(table), i) { 580 new_page = alloc_page(GFP_KERNEL); 581 if (!new_page) { 582 /* release all previous allocated pages in the table */ 583 iter = table; 584 for_each_sg(table, iter, sg_nents(table), i) { 585 new_page = sg_page(iter); 586 if (new_page) 587 __free_page(new_page); 588 } 589 kfree(table); 590 return NULL; 591 } 592 alloc_size = min_t(int, size, PAGE_SIZE); 593 size -= PAGE_SIZE; 594 sg_set_page(iter, new_page, alloc_size, 0); 595 } 596 return table; 597 } 598 599 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 600 const struct iwl_prph_range *iwl_prph_dump_addr, 601 u32 range_len, void *ptr) 602 { 603 u32 *prph_len = (u32 *)ptr; 604 int i, num_bytes_in_chunk; 605 606 if (!prph_len) 607 return; 608 609 for (i = 0; i < range_len; i++) { 610 /* The range includes both boundaries */ 611 num_bytes_in_chunk = 612 iwl_prph_dump_addr[i].end - 613 iwl_prph_dump_addr[i].start + 4; 614 615 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 616 sizeof(struct iwl_fw_error_dump_prph) + 617 num_bytes_in_chunk; 618 } 619 } 620 621 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 622 void (*handler)(struct iwl_fw_runtime *, 623 const struct iwl_prph_range *, 624 u32, void *)) 625 { 626 u32 range_len; 627 628 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 629 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 630 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 631 } else if (fwrt->trans->trans_cfg->device_family >= 632 IWL_DEVICE_FAMILY_22000) { 633 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 634 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 635 } else { 636 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 637 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 638 639 if (fwrt->trans->trans_cfg->mq_rx_supported) { 640 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 641 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 642 } 643 } 644 } 645 646 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 647 struct iwl_fw_error_dump_data **dump_data, 648 u32 len, u32 ofs, u32 type) 649 { 650 struct iwl_fw_error_dump_mem *dump_mem; 651 652 if (!len) 653 return; 654 655 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 656 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 657 dump_mem = (void *)(*dump_data)->data; 658 dump_mem->type = cpu_to_le32(type); 659 dump_mem->offset = cpu_to_le32(ofs); 660 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 661 *dump_data = iwl_fw_error_next_data(*dump_data); 662 663 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 664 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs, 665 dump_mem->data, len); 666 667 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 668 } 669 670 #define ADD_LEN(len, item_len, const_len) \ 671 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 672 while (0) 673 674 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 675 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 676 { 677 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 678 sizeof(struct iwl_fw_error_dump_fifo); 679 u32 fifo_len = 0; 680 int i; 681 682 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 683 return 0; 684 685 /* Count RXF2 size */ 686 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 687 688 /* Count RXF1 sizes */ 689 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 690 mem_cfg->num_lmacs = MAX_NUM_LMAC; 691 692 for (i = 0; i < mem_cfg->num_lmacs; i++) 693 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 694 695 return fifo_len; 696 } 697 698 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 699 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 700 { 701 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 702 sizeof(struct iwl_fw_error_dump_fifo); 703 u32 fifo_len = 0; 704 int i; 705 706 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 707 goto dump_internal_txf; 708 709 /* Count TXF sizes */ 710 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 711 mem_cfg->num_lmacs = MAX_NUM_LMAC; 712 713 for (i = 0; i < mem_cfg->num_lmacs; i++) { 714 int j; 715 716 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 717 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 718 hdr_len); 719 } 720 721 dump_internal_txf: 722 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 723 fw_has_capa(&fwrt->fw->ucode_capa, 724 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 725 goto out; 726 727 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 728 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 729 730 out: 731 return fifo_len; 732 } 733 734 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 735 struct iwl_fw_error_dump_data **data) 736 { 737 int i; 738 739 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 740 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 741 struct iwl_fw_error_dump_paging *paging; 742 struct page *pages = 743 fwrt->fw_paging_db[i].fw_paging_block; 744 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 745 746 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 747 (*data)->len = cpu_to_le32(sizeof(*paging) + 748 PAGING_BLOCK_SIZE); 749 paging = (void *)(*data)->data; 750 paging->index = cpu_to_le32(i); 751 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 752 PAGING_BLOCK_SIZE, 753 DMA_BIDIRECTIONAL); 754 memcpy(paging->data, page_address(pages), 755 PAGING_BLOCK_SIZE); 756 dma_sync_single_for_device(fwrt->trans->dev, addr, 757 PAGING_BLOCK_SIZE, 758 DMA_BIDIRECTIONAL); 759 (*data) = iwl_fw_error_next_data(*data); 760 761 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 762 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 763 fwrt->fw_paging_db[i].fw_offs, 764 paging->data, 765 PAGING_BLOCK_SIZE); 766 } 767 } 768 769 static struct iwl_fw_error_dump_file * 770 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 771 struct iwl_fw_dump_ptrs *fw_error_dump, 772 struct iwl_fwrt_dump_data *data) 773 { 774 struct iwl_fw_error_dump_file *dump_file; 775 struct iwl_fw_error_dump_data *dump_data; 776 struct iwl_fw_error_dump_info *dump_info; 777 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 778 struct iwl_fw_error_dump_trigger_desc *dump_trig; 779 u32 sram_len, sram_ofs; 780 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 781 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 782 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 783 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 784 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 785 0 : fwrt->trans->cfg->dccm2_len; 786 int i; 787 788 /* SRAM - include stack CCM if driver knows the values for it */ 789 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 790 const struct fw_img *img; 791 792 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 793 return NULL; 794 img = &fwrt->fw->img[fwrt->cur_fw_img]; 795 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 796 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 797 } else { 798 sram_ofs = fwrt->trans->cfg->dccm_offset; 799 sram_len = fwrt->trans->cfg->dccm_len; 800 } 801 802 /* reading RXF/TXF sizes */ 803 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 804 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 805 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 806 807 /* Make room for PRPH registers */ 808 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 809 iwl_fw_prph_handler(fwrt, &prph_len, 810 iwl_fw_get_prph_len); 811 812 if (fwrt->trans->trans_cfg->device_family == 813 IWL_DEVICE_FAMILY_7000 && 814 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 815 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 816 } 817 818 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 819 820 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 821 file_len += sizeof(*dump_data) + sizeof(*dump_info); 822 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 823 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 824 825 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 826 size_t hdr_len = sizeof(*dump_data) + 827 sizeof(struct iwl_fw_error_dump_mem); 828 829 /* Dump SRAM only if no mem_tlvs */ 830 if (!fwrt->fw->dbg.n_mem_tlv) 831 ADD_LEN(file_len, sram_len, hdr_len); 832 833 /* Make room for all mem types that exist */ 834 ADD_LEN(file_len, smem_len, hdr_len); 835 ADD_LEN(file_len, sram2_len, hdr_len); 836 837 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 838 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 839 } 840 841 /* Make room for fw's virtual image pages, if it exists */ 842 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 843 file_len += fwrt->num_of_paging_blk * 844 (sizeof(*dump_data) + 845 sizeof(struct iwl_fw_error_dump_paging) + 846 PAGING_BLOCK_SIZE); 847 848 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 849 file_len += sizeof(*dump_data) + 850 fwrt->trans->cfg->d3_debug_data_length * 2; 851 } 852 853 /* If we only want a monitor dump, reset the file length */ 854 if (data->monitor_only) { 855 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 856 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 857 } 858 859 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 860 data->desc) 861 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 862 data->desc->len; 863 864 dump_file = vzalloc(file_len); 865 if (!dump_file) 866 return NULL; 867 868 fw_error_dump->fwrt_ptr = dump_file; 869 870 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 871 dump_data = (void *)dump_file->data; 872 873 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 874 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 875 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 876 dump_info = (void *)dump_data->data; 877 dump_info->hw_type = 878 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 879 dump_info->hw_step = 880 cpu_to_le32(fwrt->trans->hw_rev_step); 881 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 882 sizeof(dump_info->fw_human_readable)); 883 strncpy(dump_info->dev_human_readable, fwrt->trans->name, 884 sizeof(dump_info->dev_human_readable) - 1); 885 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 886 sizeof(dump_info->bus_human_readable) - 1); 887 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 888 dump_info->lmac_err_id[0] = 889 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 890 if (fwrt->smem_cfg.num_lmacs > 1) 891 dump_info->lmac_err_id[1] = 892 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 893 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 894 895 dump_data = iwl_fw_error_next_data(dump_data); 896 } 897 898 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 899 /* Dump shared memory configuration */ 900 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 901 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 902 dump_smem_cfg = (void *)dump_data->data; 903 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 904 dump_smem_cfg->num_txfifo_entries = 905 cpu_to_le32(mem_cfg->num_txfifo_entries); 906 for (i = 0; i < MAX_NUM_LMAC; i++) { 907 int j; 908 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 909 910 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 911 dump_smem_cfg->lmac[i].txfifo_size[j] = 912 cpu_to_le32(txf_size[j]); 913 dump_smem_cfg->lmac[i].rxfifo1_size = 914 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 915 } 916 dump_smem_cfg->rxfifo2_size = 917 cpu_to_le32(mem_cfg->rxfifo2_size); 918 dump_smem_cfg->internal_txfifo_addr = 919 cpu_to_le32(mem_cfg->internal_txfifo_addr); 920 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 921 dump_smem_cfg->internal_txfifo_size[i] = 922 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 923 } 924 925 dump_data = iwl_fw_error_next_data(dump_data); 926 } 927 928 /* We only dump the FIFOs if the FW is in error state */ 929 if (fifo_len) { 930 iwl_fw_dump_rxf(fwrt, &dump_data); 931 iwl_fw_dump_txf(fwrt, &dump_data); 932 } 933 934 if (radio_len) 935 iwl_read_radio_regs(fwrt, &dump_data); 936 937 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 938 data->desc) { 939 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 940 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 941 data->desc->len); 942 dump_trig = (void *)dump_data->data; 943 memcpy(dump_trig, &data->desc->trig_desc, 944 sizeof(*dump_trig) + data->desc->len); 945 946 dump_data = iwl_fw_error_next_data(dump_data); 947 } 948 949 /* In case we only want monitor dump, skip to dump trasport data */ 950 if (data->monitor_only) 951 goto out; 952 953 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 954 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 955 fwrt->fw->dbg.mem_tlv; 956 957 if (!fwrt->fw->dbg.n_mem_tlv) 958 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 959 IWL_FW_ERROR_DUMP_MEM_SRAM); 960 961 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 962 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 963 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 964 965 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 966 le32_to_cpu(fw_dbg_mem[i].data_type)); 967 } 968 969 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 970 fwrt->trans->cfg->smem_offset, 971 IWL_FW_ERROR_DUMP_MEM_SMEM); 972 973 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 974 fwrt->trans->cfg->dccm2_offset, 975 IWL_FW_ERROR_DUMP_MEM_SRAM); 976 } 977 978 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 979 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 980 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 981 982 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 983 dump_data->len = cpu_to_le32(data_size * 2); 984 985 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 986 987 kfree(fwrt->dump.d3_debug_data); 988 fwrt->dump.d3_debug_data = NULL; 989 990 iwl_trans_read_mem_bytes(fwrt->trans, addr, 991 dump_data->data + data_size, 992 data_size); 993 994 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 995 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr, 996 dump_data->data + data_size, 997 data_size); 998 999 dump_data = iwl_fw_error_next_data(dump_data); 1000 } 1001 1002 /* Dump fw's virtual image */ 1003 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1004 iwl_dump_paging(fwrt, &dump_data); 1005 1006 if (prph_len) 1007 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1008 1009 out: 1010 dump_file->file_len = cpu_to_le32(file_len); 1011 return dump_file; 1012 } 1013 1014 /** 1015 * struct iwl_dump_ini_region_data - region data 1016 * @reg_tlv: region TLV 1017 * @dump_data: dump data 1018 */ 1019 struct iwl_dump_ini_region_data { 1020 struct iwl_ucode_tlv *reg_tlv; 1021 struct iwl_fwrt_dump_data *dump_data; 1022 }; 1023 1024 static int 1025 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt, 1026 struct iwl_dump_ini_region_data *reg_data, 1027 void *range_ptr, u32 range_len, int idx) 1028 { 1029 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1030 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1031 __le32 *val = range->data; 1032 u32 prph_val; 1033 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1034 le32_to_cpu(reg->dev_addr.offset); 1035 int i; 1036 1037 range->internal_base_addr = cpu_to_le32(addr); 1038 range->range_data_size = reg->dev_addr.size; 1039 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1040 prph_val = iwl_read_prph(fwrt->trans, addr + i); 1041 if (iwl_trans_is_hw_error_value(prph_val)) 1042 return -EBUSY; 1043 *val++ = cpu_to_le32(prph_val); 1044 } 1045 1046 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1047 } 1048 1049 static int 1050 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt, 1051 struct iwl_dump_ini_region_data *reg_data, 1052 void *range_ptr, u32 range_len, int idx) 1053 { 1054 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1055 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1056 __le32 *val = range->data; 1057 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1; 1058 u32 indirect_rd_addr = WMAL_MRSPF_1; 1059 u32 prph_val; 1060 u32 addr = le32_to_cpu(reg->addrs[idx]); 1061 u32 dphy_state; 1062 u32 dphy_addr; 1063 int i; 1064 1065 range->internal_base_addr = cpu_to_le32(addr); 1066 range->range_data_size = reg->dev_addr.size; 1067 1068 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 1069 indirect_wr_addr = WMAL_INDRCT_CMD1; 1070 1071 indirect_wr_addr += le32_to_cpu(reg->dev_addr.offset); 1072 indirect_rd_addr += le32_to_cpu(reg->dev_addr.offset); 1073 1074 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1075 return -EBUSY; 1076 1077 dphy_addr = (reg->dev_addr.offset) ? WFPM_LMAC2_PS_CTL_RW : 1078 WFPM_LMAC1_PS_CTL_RW; 1079 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1080 1081 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1082 if (dphy_state == HBUS_TIMEOUT || 1083 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1084 WFPM_PHYRF_STATE_ON) { 1085 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1086 continue; 1087 } 1088 1089 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr, 1090 WMAL_INDRCT_CMD(addr + i)); 1091 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1092 indirect_rd_addr); 1093 *val++ = cpu_to_le32(prph_val); 1094 } 1095 1096 iwl_trans_release_nic_access(fwrt->trans); 1097 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1098 } 1099 1100 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1101 struct iwl_dump_ini_region_data *reg_data, 1102 void *range_ptr, u32 range_len, int idx) 1103 { 1104 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1105 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1106 __le32 *val = range->data; 1107 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1108 le32_to_cpu(reg->dev_addr.offset); 1109 int i; 1110 1111 range->internal_base_addr = cpu_to_le32(addr); 1112 range->range_data_size = reg->dev_addr.size; 1113 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) 1114 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1115 1116 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1117 } 1118 1119 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt, 1120 struct iwl_dump_ini_region_data *reg_data, 1121 void *range_ptr, u32 range_len, int idx) 1122 { 1123 struct iwl_trans *trans = fwrt->trans; 1124 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1125 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1126 __le32 *val = range->data; 1127 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1128 le32_to_cpu(reg->dev_addr.offset); 1129 int i; 1130 1131 /* we shouldn't get here if the trans doesn't have read_config32 */ 1132 if (WARN_ON_ONCE(!trans->ops->read_config32)) 1133 return -EOPNOTSUPP; 1134 1135 range->internal_base_addr = cpu_to_le32(addr); 1136 range->range_data_size = reg->dev_addr.size; 1137 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1138 int ret; 1139 u32 tmp; 1140 1141 ret = trans->ops->read_config32(trans, addr + i, &tmp); 1142 if (ret < 0) 1143 return ret; 1144 1145 *val++ = cpu_to_le32(tmp); 1146 } 1147 1148 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1149 } 1150 1151 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1152 struct iwl_dump_ini_region_data *reg_data, 1153 void *range_ptr, u32 range_len, int idx) 1154 { 1155 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1156 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1157 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1158 le32_to_cpu(reg->dev_addr.offset); 1159 1160 range->internal_base_addr = cpu_to_le32(addr); 1161 range->range_data_size = reg->dev_addr.size; 1162 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1163 le32_to_cpu(reg->dev_addr.size)); 1164 1165 if (reg->sub_type == IWL_FW_INI_REGION_DEVICE_MEMORY_SUBTYPE_HW_SMEM && 1166 fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1167 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1168 range->data, 1169 le32_to_cpu(reg->dev_addr.size)); 1170 1171 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1172 } 1173 1174 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1175 void *range_ptr, u32 range_len, int idx) 1176 { 1177 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block; 1178 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1179 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1180 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1181 1182 range->page_num = cpu_to_le32(idx); 1183 range->range_data_size = cpu_to_le32(page_size); 1184 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1185 DMA_BIDIRECTIONAL); 1186 memcpy(range->data, page_address(page), page_size); 1187 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1188 DMA_BIDIRECTIONAL); 1189 1190 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1191 } 1192 1193 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1194 struct iwl_dump_ini_region_data *reg_data, 1195 void *range_ptr, u32 range_len, int idx) 1196 { 1197 struct iwl_fw_ini_error_dump_range *range; 1198 u32 page_size; 1199 1200 /* all paged index start from 1 to skip CSS section */ 1201 idx++; 1202 1203 if (!fwrt->trans->trans_cfg->gen2) 1204 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, range_len, idx); 1205 1206 range = range_ptr; 1207 page_size = fwrt->trans->init_dram.paging[idx].size; 1208 1209 range->page_num = cpu_to_le32(idx); 1210 range->range_data_size = cpu_to_le32(page_size); 1211 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1212 page_size); 1213 1214 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1215 } 1216 1217 static int 1218 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1219 struct iwl_dump_ini_region_data *reg_data, 1220 void *range_ptr, u32 range_len, int idx) 1221 { 1222 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1223 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1224 struct iwl_dram_data *frag; 1225 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1226 1227 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx]; 1228 1229 range->dram_base_addr = cpu_to_le64(frag->physical); 1230 range->range_data_size = cpu_to_le32(frag->size); 1231 1232 memcpy(range->data, frag->block, frag->size); 1233 1234 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1235 } 1236 1237 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt, 1238 struct iwl_dump_ini_region_data *reg_data, 1239 void *range_ptr, u32 range_len, int idx) 1240 { 1241 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1242 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1243 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr); 1244 1245 range->internal_base_addr = cpu_to_le32(addr); 1246 range->range_data_size = reg->internal_buffer.size; 1247 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1248 le32_to_cpu(reg->internal_buffer.size)); 1249 1250 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1251 } 1252 1253 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1254 struct iwl_dump_ini_region_data *reg_data, int idx) 1255 { 1256 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1257 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1258 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1259 int txf_num = cfg->num_txfifo_entries; 1260 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1261 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]); 1262 1263 if (!idx) { 1264 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) { 1265 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n", 1266 le32_to_cpu(reg->fifos.offset)); 1267 return false; 1268 } 1269 1270 iter->internal_txf = 0; 1271 iter->fifo_size = 0; 1272 iter->fifo = -1; 1273 if (le32_to_cpu(reg->fifos.offset)) 1274 iter->lmac = 1; 1275 else 1276 iter->lmac = 0; 1277 } 1278 1279 if (!iter->internal_txf) { 1280 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1281 iter->fifo_size = 1282 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1283 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1284 return true; 1285 } 1286 iter->fifo--; 1287 } 1288 1289 iter->internal_txf = 1; 1290 1291 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1292 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1293 return false; 1294 1295 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1296 iter->fifo_size = 1297 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1298 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1299 return true; 1300 } 1301 1302 return false; 1303 } 1304 1305 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1306 struct iwl_dump_ini_region_data *reg_data, 1307 void *range_ptr, u32 range_len, int idx) 1308 { 1309 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1310 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1311 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1312 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1313 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1314 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1315 u32 registers_size = registers_num * sizeof(*reg_dump); 1316 __le32 *data; 1317 int i; 1318 1319 if (!iwl_ini_txf_iter(fwrt, reg_data, idx)) 1320 return -EIO; 1321 1322 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1323 return -EBUSY; 1324 1325 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1326 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1327 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1328 1329 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1330 1331 /* 1332 * read txf registers. for each register, write to the dump the 1333 * register address and its value 1334 */ 1335 for (i = 0; i < registers_num; i++) { 1336 addr = le32_to_cpu(reg->addrs[i]) + offs; 1337 1338 reg_dump->addr = cpu_to_le32(addr); 1339 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1340 addr)); 1341 1342 reg_dump++; 1343 } 1344 1345 if (reg->fifos.hdr_only) { 1346 range->range_data_size = cpu_to_le32(registers_size); 1347 goto out; 1348 } 1349 1350 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1351 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1352 TXF_WR_PTR + offs); 1353 1354 /* Dummy-read to advance the read pointer to the head */ 1355 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1356 1357 /* Read FIFO */ 1358 addr = TXF_READ_MODIFY_DATA + offs; 1359 data = (void *)reg_dump; 1360 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1361 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1362 1363 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1364 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1365 reg_dump, iter->fifo_size); 1366 1367 out: 1368 iwl_trans_release_nic_access(fwrt->trans); 1369 1370 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1371 } 1372 1373 struct iwl_ini_rxf_data { 1374 u32 fifo_num; 1375 u32 size; 1376 u32 offset; 1377 }; 1378 1379 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1380 struct iwl_dump_ini_region_data *reg_data, 1381 struct iwl_ini_rxf_data *data) 1382 { 1383 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1384 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]); 1385 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]); 1386 u8 fifo_idx; 1387 1388 if (!data) 1389 return; 1390 1391 memset(data, 0, sizeof(*data)); 1392 1393 /* make sure only one bit is set in only one fid */ 1394 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1, 1395 "fid1=%x, fid2=%x\n", fid1, fid2)) 1396 return; 1397 1398 if (fid1) { 1399 fifo_idx = ffs(fid1) - 1; 1400 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n", 1401 fifo_idx)) 1402 return; 1403 1404 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1405 data->fifo_num = fifo_idx; 1406 } else { 1407 u8 max_idx; 1408 1409 fifo_idx = ffs(fid2) - 1; 1410 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP, 1411 SHARED_MEM_CFG_CMD, 0) <= 3) 1412 max_idx = 0; 1413 else 1414 max_idx = 1; 1415 1416 if (WARN_ONCE(fifo_idx > max_idx, 1417 "invalid umac fifo idx %d", fifo_idx)) 1418 return; 1419 1420 /* use bit 31 to distinguish between umac and lmac rxf while 1421 * parsing the dump 1422 */ 1423 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1424 1425 switch (fifo_idx) { 1426 case 0: 1427 data->size = fwrt->smem_cfg.rxfifo2_size; 1428 data->offset = iwl_umac_prph(fwrt->trans, 1429 RXF_DIFF_FROM_PREV); 1430 break; 1431 case 1: 1432 data->size = fwrt->smem_cfg.rxfifo2_control_size; 1433 data->offset = iwl_umac_prph(fwrt->trans, 1434 RXF2C_DIFF_FROM_PREV); 1435 break; 1436 } 1437 } 1438 } 1439 1440 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1441 struct iwl_dump_ini_region_data *reg_data, 1442 void *range_ptr, u32 range_len, int idx) 1443 { 1444 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1445 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1446 struct iwl_ini_rxf_data rxf_data; 1447 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1448 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1449 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1450 u32 registers_size = registers_num * sizeof(*reg_dump); 1451 __le32 *data; 1452 int i; 1453 1454 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data); 1455 if (!rxf_data.size) 1456 return -EIO; 1457 1458 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1459 return -EBUSY; 1460 1461 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1462 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1463 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1464 1465 /* 1466 * read rxf registers. for each register, write to the dump the 1467 * register address and its value 1468 */ 1469 for (i = 0; i < registers_num; i++) { 1470 addr = le32_to_cpu(reg->addrs[i]) + offs; 1471 1472 reg_dump->addr = cpu_to_le32(addr); 1473 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1474 addr)); 1475 1476 reg_dump++; 1477 } 1478 1479 if (reg->fifos.hdr_only) { 1480 range->range_data_size = cpu_to_le32(registers_size); 1481 goto out; 1482 } 1483 1484 offs = rxf_data.offset; 1485 1486 /* Lock fence */ 1487 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1488 /* Set fence pointer to the same place like WR pointer */ 1489 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1490 /* Set fence offset */ 1491 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1492 0x0); 1493 1494 /* Read FIFO */ 1495 addr = RXF_FIFO_RD_FENCE_INC + offs; 1496 data = (void *)reg_dump; 1497 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1498 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1499 1500 out: 1501 iwl_trans_release_nic_access(fwrt->trans); 1502 1503 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1504 } 1505 1506 static int 1507 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt, 1508 struct iwl_dump_ini_region_data *reg_data, 1509 void *range_ptr, u32 range_len, int idx) 1510 { 1511 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1512 struct iwl_fw_ini_region_err_table *err_table = ®->err_table; 1513 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1514 u32 addr = le32_to_cpu(err_table->base_addr) + 1515 le32_to_cpu(err_table->offset); 1516 1517 range->internal_base_addr = cpu_to_le32(addr); 1518 range->range_data_size = err_table->size; 1519 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1520 le32_to_cpu(err_table->size)); 1521 1522 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1523 } 1524 1525 static int 1526 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt, 1527 struct iwl_dump_ini_region_data *reg_data, 1528 void *range_ptr, u32 range_len, int idx) 1529 { 1530 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1531 struct iwl_fw_ini_region_special_device_memory *special_mem = 1532 ®->special_mem; 1533 1534 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1535 u32 addr = le32_to_cpu(special_mem->base_addr) + 1536 le32_to_cpu(special_mem->offset); 1537 1538 range->internal_base_addr = cpu_to_le32(addr); 1539 range->range_data_size = special_mem->size; 1540 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1541 le32_to_cpu(special_mem->size)); 1542 1543 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1544 } 1545 1546 static int 1547 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt, 1548 struct iwl_dump_ini_region_data *reg_data, 1549 void *range_ptr, u32 range_len, int idx) 1550 { 1551 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1552 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1553 __le32 *val = range->data; 1554 u32 prph_data; 1555 int i; 1556 1557 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1558 return -EBUSY; 1559 1560 range->range_data_size = reg->dev_addr.size; 1561 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) { 1562 prph_data = iwl_read_prph_no_grab(fwrt->trans, (i % 2) ? 1563 DBGI_SRAM_TARGET_ACCESS_RDATA_MSB : 1564 DBGI_SRAM_TARGET_ACCESS_RDATA_LSB); 1565 if (iwl_trans_is_hw_error_value(prph_data)) { 1566 iwl_trans_release_nic_access(fwrt->trans); 1567 return -EBUSY; 1568 } 1569 *val++ = cpu_to_le32(prph_data); 1570 } 1571 iwl_trans_release_nic_access(fwrt->trans); 1572 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1573 } 1574 1575 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt, 1576 struct iwl_dump_ini_region_data *reg_data, 1577 void *range_ptr, u32 range_len, int idx) 1578 { 1579 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1580 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt; 1581 u32 pkt_len; 1582 1583 if (!pkt) 1584 return -EIO; 1585 1586 pkt_len = iwl_rx_packet_payload_len(pkt); 1587 1588 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr)); 1589 range->range_data_size = cpu_to_le32(pkt_len); 1590 1591 memcpy(range->data, pkt->data, pkt_len); 1592 1593 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1594 } 1595 1596 static int iwl_dump_ini_imr_iter(struct iwl_fw_runtime *fwrt, 1597 struct iwl_dump_ini_region_data *reg_data, 1598 void *range_ptr, u32 range_len, int idx) 1599 { 1600 /* read the IMR memory and DMA it to SRAM */ 1601 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1602 u64 imr_curr_addr = fwrt->trans->dbg.imr_data.imr_curr_addr; 1603 u32 imr_rem_bytes = fwrt->trans->dbg.imr_data.imr2sram_remainbyte; 1604 u32 sram_addr = fwrt->trans->dbg.imr_data.sram_addr; 1605 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1606 u32 size_to_dump = (imr_rem_bytes > sram_size) ? sram_size : imr_rem_bytes; 1607 1608 range->range_data_size = cpu_to_le32(size_to_dump); 1609 if (iwl_trans_write_imr_mem(fwrt->trans, sram_addr, 1610 imr_curr_addr, size_to_dump)) { 1611 IWL_ERR(fwrt, "WRT_DEBUG: IMR Memory transfer failed\n"); 1612 return -1; 1613 } 1614 1615 fwrt->trans->dbg.imr_data.imr_curr_addr = imr_curr_addr + size_to_dump; 1616 fwrt->trans->dbg.imr_data.imr2sram_remainbyte -= size_to_dump; 1617 1618 iwl_trans_read_mem_bytes(fwrt->trans, sram_addr, range->data, 1619 size_to_dump); 1620 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1621 } 1622 1623 static void * 1624 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1625 struct iwl_dump_ini_region_data *reg_data, 1626 void *data, u32 data_len) 1627 { 1628 struct iwl_fw_ini_error_dump *dump = data; 1629 1630 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1631 1632 return dump->data; 1633 } 1634 1635 /** 1636 * mask_apply_and_normalize - applies mask on val and normalize the result 1637 * 1638 * The normalization is based on the first set bit in the mask 1639 * 1640 * @val: value 1641 * @mask: mask to apply and to normalize with 1642 */ 1643 static u32 mask_apply_and_normalize(u32 val, u32 mask) 1644 { 1645 return (val & mask) >> (ffs(mask) - 1); 1646 } 1647 1648 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1649 const struct iwl_fw_mon_reg *reg_info) 1650 { 1651 u32 val, offs; 1652 1653 /* The header addresses of DBGCi is calculate as follows: 1654 * DBGC1 address + (0x100 * i) 1655 */ 1656 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100; 1657 1658 if (!reg_info || !reg_info->addr || !reg_info->mask) 1659 return 0; 1660 1661 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs); 1662 1663 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask)); 1664 } 1665 1666 static void * 1667 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1668 struct iwl_fw_ini_monitor_dump *data, 1669 const struct iwl_fw_mon_regs *addrs) 1670 { 1671 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 1672 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1673 return NULL; 1674 } 1675 1676 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id, 1677 &addrs->write_ptr); 1678 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1679 u32 wrt_ptr = le32_to_cpu(data->write_ptr); 1680 1681 data->write_ptr = cpu_to_le32(wrt_ptr >> 2); 1682 } 1683 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id, 1684 &addrs->cycle_cnt); 1685 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id, 1686 &addrs->cur_frag); 1687 1688 iwl_trans_release_nic_access(fwrt->trans); 1689 1690 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1691 1692 return data->data; 1693 } 1694 1695 static void * 1696 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1697 struct iwl_dump_ini_region_data *reg_data, 1698 void *data, u32 data_len) 1699 { 1700 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1701 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1702 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1703 1704 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1705 &fwrt->trans->cfg->mon_dram_regs); 1706 } 1707 1708 static void * 1709 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1710 struct iwl_dump_ini_region_data *reg_data, 1711 void *data, u32 data_len) 1712 { 1713 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1714 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1715 u32 alloc_id = le32_to_cpu(reg->internal_buffer.alloc_id); 1716 1717 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1718 &fwrt->trans->cfg->mon_smem_regs); 1719 } 1720 1721 static void * 1722 iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime *fwrt, 1723 struct iwl_dump_ini_region_data *reg_data, 1724 void *data, u32 data_len) 1725 { 1726 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1727 1728 return iwl_dump_ini_mon_fill_header(fwrt, 1729 /* no offset calculation later */ 1730 IWL_FW_INI_ALLOCATION_ID_DBGC1, 1731 mon_dump, 1732 &fwrt->trans->cfg->mon_dbgi_regs); 1733 } 1734 1735 static void * 1736 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt, 1737 struct iwl_dump_ini_region_data *reg_data, 1738 void *data, u32 data_len) 1739 { 1740 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1741 struct iwl_fw_ini_err_table_dump *dump = data; 1742 1743 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1744 dump->version = reg->err_table.version; 1745 1746 return dump->data; 1747 } 1748 1749 static void * 1750 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt, 1751 struct iwl_dump_ini_region_data *reg_data, 1752 void *data, u32 data_len) 1753 { 1754 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1755 struct iwl_fw_ini_special_device_memory *dump = data; 1756 1757 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1758 dump->type = reg->special_mem.type; 1759 dump->version = reg->special_mem.version; 1760 1761 return dump->data; 1762 } 1763 1764 static void * 1765 iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime *fwrt, 1766 struct iwl_dump_ini_region_data *reg_data, 1767 void *data, u32 data_len) 1768 { 1769 struct iwl_fw_ini_error_dump *dump = data; 1770 1771 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1772 1773 return dump->data; 1774 } 1775 1776 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1777 struct iwl_dump_ini_region_data *reg_data) 1778 { 1779 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1780 1781 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1782 } 1783 1784 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1785 struct iwl_dump_ini_region_data *reg_data) 1786 { 1787 if (fwrt->trans->trans_cfg->gen2) { 1788 if (fwrt->trans->init_dram.paging_cnt) 1789 return fwrt->trans->init_dram.paging_cnt - 1; 1790 else 1791 return 0; 1792 } 1793 1794 return fwrt->num_of_paging_blk; 1795 } 1796 1797 static u32 1798 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1799 struct iwl_dump_ini_region_data *reg_data) 1800 { 1801 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1802 struct iwl_fw_mon *fw_mon; 1803 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1804 int i; 1805 1806 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1807 1808 for (i = 0; i < fw_mon->num_frags; i++) { 1809 if (!fw_mon->frags[i].size) 1810 break; 1811 1812 ranges++; 1813 } 1814 1815 return ranges; 1816 } 1817 1818 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1819 struct iwl_dump_ini_region_data *reg_data) 1820 { 1821 u32 num_of_fifos = 0; 1822 1823 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos)) 1824 num_of_fifos++; 1825 1826 return num_of_fifos; 1827 } 1828 1829 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt, 1830 struct iwl_dump_ini_region_data *reg_data) 1831 { 1832 return 1; 1833 } 1834 1835 static u32 iwl_dump_ini_imr_ranges(struct iwl_fw_runtime *fwrt, 1836 struct iwl_dump_ini_region_data *reg_data) 1837 { 1838 /* range is total number of pages need to copied from 1839 *IMR memory to SRAM and later from SRAM to DRAM 1840 */ 1841 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 1842 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 1843 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1844 1845 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 1846 IWL_DEBUG_INFO(fwrt, 1847 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 1848 imr_enable, imr_size, sram_size); 1849 return 0; 1850 } 1851 1852 return((imr_size % sram_size) ? (imr_size / sram_size + 1) : (imr_size / sram_size)); 1853 } 1854 1855 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1856 struct iwl_dump_ini_region_data *reg_data) 1857 { 1858 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1859 u32 size = le32_to_cpu(reg->dev_addr.size); 1860 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1861 1862 if (!size || !ranges) 1863 return 0; 1864 1865 return sizeof(struct iwl_fw_ini_error_dump) + ranges * 1866 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1867 } 1868 1869 static u32 1870 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1871 struct iwl_dump_ini_region_data *reg_data) 1872 { 1873 int i; 1874 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1875 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1876 1877 /* start from 1 to skip CSS section */ 1878 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) { 1879 size += range_header_len; 1880 if (fwrt->trans->trans_cfg->gen2) 1881 size += fwrt->trans->init_dram.paging[i].size; 1882 else 1883 size += fwrt->fw_paging_db[i].fw_paging_size; 1884 } 1885 1886 return size; 1887 } 1888 1889 static u32 1890 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 1891 struct iwl_dump_ini_region_data *reg_data) 1892 { 1893 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1894 struct iwl_fw_mon *fw_mon; 1895 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1896 int i; 1897 1898 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1899 1900 for (i = 0; i < fw_mon->num_frags; i++) { 1901 struct iwl_dram_data *frag = &fw_mon->frags[i]; 1902 1903 if (!frag->size) 1904 break; 1905 1906 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size; 1907 } 1908 1909 if (size) 1910 size += sizeof(struct iwl_fw_ini_monitor_dump); 1911 1912 return size; 1913 } 1914 1915 static u32 1916 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 1917 struct iwl_dump_ini_region_data *reg_data) 1918 { 1919 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1920 u32 size; 1921 1922 size = le32_to_cpu(reg->internal_buffer.size); 1923 if (!size) 1924 return 0; 1925 1926 size += sizeof(struct iwl_fw_ini_monitor_dump) + 1927 sizeof(struct iwl_fw_ini_error_dump_range); 1928 1929 return size; 1930 } 1931 1932 static u32 iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime *fwrt, 1933 struct iwl_dump_ini_region_data *reg_data) 1934 { 1935 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1936 u32 size = le32_to_cpu(reg->dev_addr.size); 1937 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1938 1939 if (!size || !ranges) 1940 return 0; 1941 1942 return sizeof(struct iwl_fw_ini_monitor_dump) + ranges * 1943 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1944 } 1945 1946 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 1947 struct iwl_dump_ini_region_data *reg_data) 1948 { 1949 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1950 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1951 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1952 u32 size = 0; 1953 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 1954 registers_num * 1955 sizeof(struct iwl_fw_ini_error_dump_register); 1956 1957 while (iwl_ini_txf_iter(fwrt, reg_data, size)) { 1958 size += fifo_hdr; 1959 if (!reg->fifos.hdr_only) 1960 size += iter->fifo_size; 1961 } 1962 1963 if (!size) 1964 return 0; 1965 1966 return size + sizeof(struct iwl_fw_ini_error_dump); 1967 } 1968 1969 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 1970 struct iwl_dump_ini_region_data *reg_data) 1971 { 1972 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1973 struct iwl_ini_rxf_data rx_data; 1974 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1975 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 1976 sizeof(struct iwl_fw_ini_error_dump_range) + 1977 registers_num * sizeof(struct iwl_fw_ini_error_dump_register); 1978 1979 if (reg->fifos.hdr_only) 1980 return size; 1981 1982 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data); 1983 size += rx_data.size; 1984 1985 return size; 1986 } 1987 1988 static u32 1989 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt, 1990 struct iwl_dump_ini_region_data *reg_data) 1991 { 1992 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1993 u32 size = le32_to_cpu(reg->err_table.size); 1994 1995 if (size) 1996 size += sizeof(struct iwl_fw_ini_err_table_dump) + 1997 sizeof(struct iwl_fw_ini_error_dump_range); 1998 1999 return size; 2000 } 2001 2002 static u32 2003 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt, 2004 struct iwl_dump_ini_region_data *reg_data) 2005 { 2006 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2007 u32 size = le32_to_cpu(reg->special_mem.size); 2008 2009 if (size) 2010 size += sizeof(struct iwl_fw_ini_special_device_memory) + 2011 sizeof(struct iwl_fw_ini_error_dump_range); 2012 2013 return size; 2014 } 2015 2016 static u32 2017 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt, 2018 struct iwl_dump_ini_region_data *reg_data) 2019 { 2020 u32 size = 0; 2021 2022 if (!reg_data->dump_data->fw_pkt) 2023 return 0; 2024 2025 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt); 2026 if (size) 2027 size += sizeof(struct iwl_fw_ini_error_dump) + 2028 sizeof(struct iwl_fw_ini_error_dump_range); 2029 2030 return size; 2031 } 2032 2033 static u32 2034 iwl_dump_ini_imr_get_size(struct iwl_fw_runtime *fwrt, 2035 struct iwl_dump_ini_region_data *reg_data) 2036 { 2037 u32 ranges = 0; 2038 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 2039 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 2040 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 2041 2042 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 2043 IWL_DEBUG_INFO(fwrt, 2044 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 2045 imr_enable, imr_size, sram_size); 2046 return 0; 2047 } 2048 ranges = iwl_dump_ini_imr_ranges(fwrt, reg_data); 2049 if (!ranges) { 2050 IWL_ERR(fwrt, "WRT: ranges :=%d\n", ranges); 2051 return 0; 2052 } 2053 imr_size += sizeof(struct iwl_fw_ini_error_dump) + 2054 ranges * sizeof(struct iwl_fw_ini_error_dump_range); 2055 return imr_size; 2056 } 2057 2058 /** 2059 * struct iwl_dump_ini_mem_ops - ini memory dump operations 2060 * @get_num_of_ranges: returns the number of memory ranges in the region. 2061 * @get_size: returns the total size of the region. 2062 * @fill_mem_hdr: fills region type specific headers and returns pointer to 2063 * the first range or NULL if failed to fill headers. 2064 * @fill_range: copies a given memory range into the dump. 2065 * Returns the size of the range or negative error value otherwise. 2066 */ 2067 struct iwl_dump_ini_mem_ops { 2068 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 2069 struct iwl_dump_ini_region_data *reg_data); 2070 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 2071 struct iwl_dump_ini_region_data *reg_data); 2072 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 2073 struct iwl_dump_ini_region_data *reg_data, 2074 void *data, u32 data_len); 2075 int (*fill_range)(struct iwl_fw_runtime *fwrt, 2076 struct iwl_dump_ini_region_data *reg_data, 2077 void *range, u32 range_len, int idx); 2078 }; 2079 2080 /** 2081 * iwl_dump_ini_mem 2082 * 2083 * Creates a dump tlv and copy a memory region into it. 2084 * Returns the size of the current dump tlv or 0 if failed 2085 * 2086 * @fwrt: fw runtime struct 2087 * @list: list to add the dump tlv to 2088 * @reg_data: memory region 2089 * @ops: memory dump operations 2090 */ 2091 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 2092 struct iwl_dump_ini_region_data *reg_data, 2093 const struct iwl_dump_ini_mem_ops *ops) 2094 { 2095 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2096 struct iwl_fw_ini_dump_entry *entry; 2097 struct iwl_fw_ini_error_dump_data *tlv; 2098 struct iwl_fw_ini_error_dump_header *header; 2099 u32 type = reg->type; 2100 u32 id = le32_get_bits(reg->id, IWL_FW_INI_REGION_ID_MASK); 2101 u32 num_of_ranges, i, size; 2102 u8 *range; 2103 u32 free_size; 2104 u64 header_size; 2105 u32 dump_policy = IWL_FW_INI_DUMP_VERBOSE; 2106 2107 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: dump type=%d, id=%d, type=%d\n", 2108 dump_policy, id, type); 2109 2110 if (le32_to_cpu(reg->hdr.version) >= 2) { 2111 u32 dp = le32_get_bits(reg->id, 2112 IWL_FW_INI_REGION_DUMP_POLICY_MASK); 2113 2114 if (dump_policy == IWL_FW_INI_DUMP_VERBOSE && 2115 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_NO_LIMIT)) { 2116 IWL_DEBUG_FW(fwrt, 2117 "WRT: no dump - type %d and policy mismatch=%d\n", 2118 dump_policy, dp); 2119 return 0; 2120 } else if (dump_policy == IWL_FW_INI_DUMP_MEDIUM && 2121 !(dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_MAX_LIMIT_5MB)) { 2122 IWL_DEBUG_FW(fwrt, 2123 "WRT: no dump - type %d and policy mismatch=%d\n", 2124 dump_policy, dp); 2125 return 0; 2126 } else if (dump_policy == IWL_FW_INI_DUMP_BRIEF && 2127 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_MAX_LIMIT_600KB)) { 2128 IWL_DEBUG_FW(fwrt, 2129 "WRT: no dump - type %d and policy mismatch=%d\n", 2130 dump_policy, dp); 2131 return 0; 2132 } 2133 } 2134 2135 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 2136 !ops->fill_range) { 2137 IWL_DEBUG_FW(fwrt, "WRT: no ops for collecting data\n"); 2138 return 0; 2139 } 2140 2141 size = ops->get_size(fwrt, reg_data); 2142 2143 if (size < sizeof(*header)) { 2144 IWL_DEBUG_FW(fwrt, "WRT: size didn't include space for header\n"); 2145 return 0; 2146 } 2147 2148 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size); 2149 if (!entry) 2150 return 0; 2151 2152 entry->size = sizeof(*tlv) + size; 2153 2154 tlv = (void *)entry->data; 2155 tlv->type = reg->type; 2156 tlv->sub_type = reg->sub_type; 2157 tlv->sub_type_ver = reg->sub_type_ver; 2158 tlv->reserved = reg->reserved; 2159 tlv->len = cpu_to_le32(size); 2160 2161 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data); 2162 2163 header = (void *)tlv->data; 2164 header->region_id = cpu_to_le32(id); 2165 header->num_of_ranges = cpu_to_le32(num_of_ranges); 2166 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME); 2167 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME); 2168 2169 free_size = size; 2170 range = ops->fill_mem_hdr(fwrt, reg_data, header, free_size); 2171 if (!range) { 2172 IWL_ERR(fwrt, 2173 "WRT: Failed to fill region header: id=%d, type=%d\n", 2174 id, type); 2175 goto out_err; 2176 } 2177 2178 header_size = range - (u8 *)header; 2179 2180 if (WARN(header_size > free_size, 2181 "header size %llu > free_size %d", 2182 header_size, free_size)) { 2183 IWL_ERR(fwrt, 2184 "WRT: fill_mem_hdr used more than given free_size\n"); 2185 goto out_err; 2186 } 2187 2188 free_size -= header_size; 2189 2190 for (i = 0; i < num_of_ranges; i++) { 2191 int range_size = ops->fill_range(fwrt, reg_data, range, 2192 free_size, i); 2193 2194 if (range_size < 0) { 2195 IWL_ERR(fwrt, 2196 "WRT: Failed to dump region: id=%d, type=%d\n", 2197 id, type); 2198 goto out_err; 2199 } 2200 2201 if (WARN(range_size > free_size, "range_size %d > free_size %d", 2202 range_size, free_size)) { 2203 IWL_ERR(fwrt, 2204 "WRT: fill_raged used more than given free_size\n"); 2205 goto out_err; 2206 } 2207 2208 free_size -= range_size; 2209 range = range + range_size; 2210 } 2211 2212 list_add_tail(&entry->list, list); 2213 2214 return entry->size; 2215 2216 out_err: 2217 vfree(entry); 2218 2219 return 0; 2220 } 2221 2222 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 2223 struct iwl_fw_ini_trigger_tlv *trigger, 2224 struct list_head *list) 2225 { 2226 struct iwl_fw_ini_dump_entry *entry; 2227 struct iwl_fw_error_dump_data *tlv; 2228 struct iwl_fw_ini_dump_info *dump; 2229 struct iwl_dbg_tlv_node *node; 2230 struct iwl_fw_ini_dump_cfg_name *cfg_name; 2231 u32 size = sizeof(*tlv) + sizeof(*dump); 2232 u32 num_of_cfg_names = 0; 2233 u32 hw_type; 2234 2235 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2236 size += sizeof(*cfg_name); 2237 num_of_cfg_names++; 2238 } 2239 2240 entry = vzalloc(sizeof(*entry) + size); 2241 if (!entry) 2242 return 0; 2243 2244 entry->size = size; 2245 2246 tlv = (void *)entry->data; 2247 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 2248 tlv->len = cpu_to_le32(size - sizeof(*tlv)); 2249 2250 dump = (void *)tlv->data; 2251 2252 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 2253 dump->time_point = trigger->time_point; 2254 dump->trigger_reason = trigger->trigger_reason; 2255 dump->external_cfg_state = 2256 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 2257 2258 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 2259 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 2260 2261 dump->hw_step = cpu_to_le32(fwrt->trans->hw_rev_step); 2262 2263 /* 2264 * Several HWs all have type == 0x42, so we'll override this value 2265 * according to the detected HW 2266 */ 2267 hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev); 2268 if (hw_type == IWL_AX210_HW_TYPE) { 2269 u32 prph_val = iwl_read_umac_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR); 2270 u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT); 2271 u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT); 2272 u32 masked_bits = is_jacket | (is_cdb << 1); 2273 2274 /* 2275 * The HW type depends on certain bits in this case, so add 2276 * these bits to the HW type. We won't have collisions since we 2277 * add these bits after the highest possible bit in the mask. 2278 */ 2279 hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT; 2280 } 2281 dump->hw_type = cpu_to_le32(hw_type); 2282 2283 dump->rf_id_flavor = 2284 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id)); 2285 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id)); 2286 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id)); 2287 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id)); 2288 2289 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 2290 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 2291 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 2292 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 2293 2294 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest); 2295 dump->regions_mask = trigger->regions_mask & 2296 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk); 2297 2298 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 2299 memcpy(dump->build_tag, fwrt->fw->human_readable, 2300 sizeof(dump->build_tag)); 2301 2302 cfg_name = dump->cfg_names; 2303 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names); 2304 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2305 struct iwl_fw_ini_debug_info_tlv *debug_info = 2306 (void *)node->tlv.data; 2307 2308 cfg_name->image_type = debug_info->image_type; 2309 cfg_name->cfg_name_len = 2310 cpu_to_le32(IWL_FW_INI_MAX_CFG_NAME); 2311 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name, 2312 sizeof(cfg_name->cfg_name)); 2313 cfg_name++; 2314 } 2315 2316 /* add dump info TLV to the beginning of the list since it needs to be 2317 * the first TLV in the dump 2318 */ 2319 list_add(&entry->list, list); 2320 2321 return entry->size; 2322 } 2323 2324 static u32 iwl_dump_ini_file_name_info(struct iwl_fw_runtime *fwrt, 2325 struct list_head *list) 2326 { 2327 struct iwl_fw_ini_dump_entry *entry; 2328 struct iwl_dump_file_name_info *tlv; 2329 u32 len = strnlen(fwrt->trans->dbg.dump_file_name_ext, 2330 IWL_FW_INI_MAX_NAME); 2331 2332 if (!fwrt->trans->dbg.dump_file_name_ext_valid) 2333 return 0; 2334 2335 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + len); 2336 if (!entry) 2337 return 0; 2338 2339 entry->size = sizeof(*tlv) + len; 2340 2341 tlv = (void *)entry->data; 2342 tlv->type = cpu_to_le32(IWL_INI_DUMP_NAME_TYPE); 2343 tlv->len = cpu_to_le32(len); 2344 memcpy(tlv->data, fwrt->trans->dbg.dump_file_name_ext, len); 2345 2346 /* add the dump file name extension tlv to the list */ 2347 list_add_tail(&entry->list, list); 2348 2349 fwrt->trans->dbg.dump_file_name_ext_valid = false; 2350 2351 return entry->size; 2352 } 2353 2354 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 2355 [IWL_FW_INI_REGION_INVALID] = {}, 2356 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 2357 .get_num_of_ranges = iwl_dump_ini_single_range, 2358 .get_size = iwl_dump_ini_mon_smem_get_size, 2359 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 2360 .fill_range = iwl_dump_ini_mon_smem_iter, 2361 }, 2362 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 2363 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 2364 .get_size = iwl_dump_ini_mon_dram_get_size, 2365 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 2366 .fill_range = iwl_dump_ini_mon_dram_iter, 2367 }, 2368 [IWL_FW_INI_REGION_TXF] = { 2369 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 2370 .get_size = iwl_dump_ini_txf_get_size, 2371 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2372 .fill_range = iwl_dump_ini_txf_iter, 2373 }, 2374 [IWL_FW_INI_REGION_RXF] = { 2375 .get_num_of_ranges = iwl_dump_ini_single_range, 2376 .get_size = iwl_dump_ini_rxf_get_size, 2377 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2378 .fill_range = iwl_dump_ini_rxf_iter, 2379 }, 2380 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 2381 .get_num_of_ranges = iwl_dump_ini_single_range, 2382 .get_size = iwl_dump_ini_err_table_get_size, 2383 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2384 .fill_range = iwl_dump_ini_err_table_iter, 2385 }, 2386 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 2387 .get_num_of_ranges = iwl_dump_ini_single_range, 2388 .get_size = iwl_dump_ini_err_table_get_size, 2389 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2390 .fill_range = iwl_dump_ini_err_table_iter, 2391 }, 2392 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = { 2393 .get_num_of_ranges = iwl_dump_ini_single_range, 2394 .get_size = iwl_dump_ini_fw_pkt_get_size, 2395 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2396 .fill_range = iwl_dump_ini_fw_pkt_iter, 2397 }, 2398 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 2399 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2400 .get_size = iwl_dump_ini_mem_get_size, 2401 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2402 .fill_range = iwl_dump_ini_dev_mem_iter, 2403 }, 2404 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 2405 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2406 .get_size = iwl_dump_ini_mem_get_size, 2407 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2408 .fill_range = iwl_dump_ini_prph_mac_iter, 2409 }, 2410 [IWL_FW_INI_REGION_PERIPHERY_PHY] = { 2411 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2412 .get_size = iwl_dump_ini_mem_get_size, 2413 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2414 .fill_range = iwl_dump_ini_prph_phy_iter, 2415 }, 2416 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 2417 [IWL_FW_INI_REGION_PAGING] = { 2418 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2419 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 2420 .get_size = iwl_dump_ini_paging_get_size, 2421 .fill_range = iwl_dump_ini_paging_iter, 2422 }, 2423 [IWL_FW_INI_REGION_CSR] = { 2424 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2425 .get_size = iwl_dump_ini_mem_get_size, 2426 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2427 .fill_range = iwl_dump_ini_csr_iter, 2428 }, 2429 [IWL_FW_INI_REGION_DRAM_IMR] = { 2430 .get_num_of_ranges = iwl_dump_ini_imr_ranges, 2431 .get_size = iwl_dump_ini_imr_get_size, 2432 .fill_mem_hdr = iwl_dump_ini_imr_fill_header, 2433 .fill_range = iwl_dump_ini_imr_iter, 2434 }, 2435 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = { 2436 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2437 .get_size = iwl_dump_ini_mem_get_size, 2438 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2439 .fill_range = iwl_dump_ini_config_iter, 2440 }, 2441 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = { 2442 .get_num_of_ranges = iwl_dump_ini_single_range, 2443 .get_size = iwl_dump_ini_special_mem_get_size, 2444 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header, 2445 .fill_range = iwl_dump_ini_special_mem_iter, 2446 }, 2447 [IWL_FW_INI_REGION_DBGI_SRAM] = { 2448 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2449 .get_size = iwl_dump_ini_mon_dbgi_get_size, 2450 .fill_mem_hdr = iwl_dump_ini_mon_dbgi_fill_header, 2451 .fill_range = iwl_dump_ini_dbgi_sram_iter, 2452 }, 2453 }; 2454 2455 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 2456 struct iwl_fwrt_dump_data *dump_data, 2457 struct list_head *list) 2458 { 2459 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2460 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point); 2461 struct iwl_dump_ini_region_data reg_data = { 2462 .dump_data = dump_data, 2463 }; 2464 struct iwl_dump_ini_region_data imr_reg_data = { 2465 .dump_data = dump_data, 2466 }; 2467 int i; 2468 u32 size = 0; 2469 u64 regions_mask = le64_to_cpu(trigger->regions_mask) & 2470 ~(fwrt->trans->dbg.unsupported_region_msk); 2471 2472 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask)); 2473 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) < 2474 ARRAY_SIZE(fwrt->trans->dbg.active_regions)); 2475 2476 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) { 2477 u32 reg_type; 2478 struct iwl_fw_ini_region_tlv *reg; 2479 2480 if (!(BIT_ULL(i) & regions_mask)) 2481 continue; 2482 2483 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2484 if (!reg_data.reg_tlv) { 2485 IWL_WARN(fwrt, 2486 "WRT: Unassigned region id %d, skipping\n", i); 2487 continue; 2488 } 2489 2490 reg = (void *)reg_data.reg_tlv->data; 2491 reg_type = reg->type; 2492 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 2493 continue; 2494 2495 if (reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY && 2496 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) { 2497 IWL_WARN(fwrt, 2498 "WRT: trying to collect phy prph at time point: %d, skipping\n", 2499 tp_id); 2500 continue; 2501 } 2502 /* 2503 * DRAM_IMR can be collected only for FW/HW error timepoint 2504 * when fw is not alive. In addition, it must be collected 2505 * lastly as it overwrites SRAM that can possibly contain 2506 * debug data which also need to be collected. 2507 */ 2508 if (reg_type == IWL_FW_INI_REGION_DRAM_IMR) { 2509 if (tp_id == IWL_FW_INI_TIME_POINT_FW_ASSERT || 2510 tp_id == IWL_FW_INI_TIME_POINT_FW_HW_ERROR) 2511 imr_reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2512 else 2513 IWL_INFO(fwrt, 2514 "WRT: trying to collect DRAM_IMR at time point: %d, skipping\n", 2515 tp_id); 2516 /* continue to next region */ 2517 continue; 2518 } 2519 2520 2521 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2522 &iwl_dump_ini_region_ops[reg_type]); 2523 } 2524 /* collect DRAM_IMR region in the last */ 2525 if (imr_reg_data.reg_tlv) 2526 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2527 &iwl_dump_ini_region_ops[IWL_FW_INI_REGION_DRAM_IMR]); 2528 2529 if (size) { 2530 size += iwl_dump_ini_file_name_info(fwrt, list); 2531 size += iwl_dump_ini_info(fwrt, trigger, list); 2532 } 2533 2534 return size; 2535 } 2536 2537 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt, 2538 struct iwl_fw_ini_trigger_tlv *trig) 2539 { 2540 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2541 u32 usec = le32_to_cpu(trig->ignore_consec); 2542 2543 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 2544 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 2545 tp_id >= IWL_FW_INI_TIME_POINT_NUM || 2546 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec)) 2547 return false; 2548 2549 return true; 2550 } 2551 2552 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 2553 struct iwl_fwrt_dump_data *dump_data, 2554 struct list_head *list) 2555 { 2556 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2557 struct iwl_fw_ini_dump_entry *entry; 2558 struct iwl_fw_ini_dump_file_hdr *hdr; 2559 u32 size; 2560 2561 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) || 2562 !le64_to_cpu(trigger->regions_mask)) 2563 return 0; 2564 2565 entry = vzalloc(sizeof(*entry) + sizeof(*hdr)); 2566 if (!entry) 2567 return 0; 2568 2569 entry->size = sizeof(*hdr); 2570 2571 size = iwl_dump_ini_trigger(fwrt, dump_data, list); 2572 if (!size) { 2573 vfree(entry); 2574 return 0; 2575 } 2576 2577 hdr = (void *)entry->data; 2578 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 2579 hdr->file_len = cpu_to_le32(size + entry->size); 2580 2581 list_add(&entry->list, list); 2582 2583 return le32_to_cpu(hdr->file_len); 2584 } 2585 2586 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt, 2587 const struct iwl_fw_dump_desc *desc) 2588 { 2589 if (desc && desc != &iwl_dump_desc_assert) 2590 kfree(desc); 2591 2592 fwrt->dump.lmac_err_id[0] = 0; 2593 if (fwrt->smem_cfg.num_lmacs > 1) 2594 fwrt->dump.lmac_err_id[1] = 0; 2595 fwrt->dump.umac_err_id = 0; 2596 } 2597 2598 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt, 2599 struct iwl_fwrt_dump_data *dump_data) 2600 { 2601 struct iwl_fw_dump_ptrs fw_error_dump = {}; 2602 struct iwl_fw_error_dump_file *dump_file; 2603 struct scatterlist *sg_dump_data; 2604 u32 file_len; 2605 u32 dump_mask = fwrt->fw->dbg.dump_mask; 2606 2607 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data); 2608 if (!dump_file) 2609 return; 2610 2611 if (dump_data->monitor_only) 2612 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR); 2613 2614 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask, 2615 fwrt->sanitize_ops, 2616 fwrt->sanitize_ctx); 2617 file_len = le32_to_cpu(dump_file->file_len); 2618 fw_error_dump.fwrt_len = file_len; 2619 2620 if (fw_error_dump.trans_ptr) { 2621 file_len += fw_error_dump.trans_ptr->len; 2622 dump_file->file_len = cpu_to_le32(file_len); 2623 } 2624 2625 sg_dump_data = alloc_sgtable(file_len); 2626 if (sg_dump_data) { 2627 sg_pcopy_from_buffer(sg_dump_data, 2628 sg_nents(sg_dump_data), 2629 fw_error_dump.fwrt_ptr, 2630 fw_error_dump.fwrt_len, 0); 2631 if (fw_error_dump.trans_ptr) 2632 sg_pcopy_from_buffer(sg_dump_data, 2633 sg_nents(sg_dump_data), 2634 fw_error_dump.trans_ptr->data, 2635 fw_error_dump.trans_ptr->len, 2636 fw_error_dump.fwrt_len); 2637 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2638 GFP_KERNEL); 2639 } 2640 vfree(fw_error_dump.fwrt_ptr); 2641 vfree(fw_error_dump.trans_ptr); 2642 } 2643 2644 static void iwl_dump_ini_list_free(struct list_head *list) 2645 { 2646 while (!list_empty(list)) { 2647 struct iwl_fw_ini_dump_entry *entry = 2648 list_entry(list->next, typeof(*entry), list); 2649 2650 list_del(&entry->list); 2651 vfree(entry); 2652 } 2653 } 2654 2655 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data) 2656 { 2657 dump_data->trig = NULL; 2658 kfree(dump_data->fw_pkt); 2659 dump_data->fw_pkt = NULL; 2660 } 2661 2662 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, 2663 struct iwl_fwrt_dump_data *dump_data) 2664 { 2665 LIST_HEAD(dump_list); 2666 struct scatterlist *sg_dump_data; 2667 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list); 2668 2669 if (!file_len) 2670 return; 2671 2672 sg_dump_data = alloc_sgtable(file_len); 2673 if (sg_dump_data) { 2674 struct iwl_fw_ini_dump_entry *entry; 2675 int sg_entries = sg_nents(sg_dump_data); 2676 u32 offs = 0; 2677 2678 list_for_each_entry(entry, &dump_list, list) { 2679 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2680 entry->data, entry->size, offs); 2681 offs += entry->size; 2682 } 2683 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2684 GFP_KERNEL); 2685 } 2686 iwl_dump_ini_list_free(&dump_list); 2687 } 2688 2689 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2690 .trig_desc = { 2691 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2692 }, 2693 }; 2694 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2695 2696 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2697 const struct iwl_fw_dump_desc *desc, 2698 bool monitor_only, 2699 unsigned int delay) 2700 { 2701 struct iwl_fwrt_wk_data *wk_data; 2702 unsigned long idx; 2703 2704 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2705 iwl_fw_free_dump_desc(fwrt, desc); 2706 return 0; 2707 } 2708 2709 /* 2710 * Check there is an available worker. 2711 * ffz return value is undefined if no zero exists, 2712 * so check against ~0UL first. 2713 */ 2714 if (fwrt->dump.active_wks == ~0UL) 2715 return -EBUSY; 2716 2717 idx = ffz(fwrt->dump.active_wks); 2718 2719 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2720 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2721 return -EBUSY; 2722 2723 wk_data = &fwrt->dump.wks[idx]; 2724 2725 if (WARN_ON(wk_data->dump_data.desc)) 2726 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc); 2727 2728 wk_data->dump_data.desc = desc; 2729 wk_data->dump_data.monitor_only = monitor_only; 2730 2731 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2732 le32_to_cpu(desc->trig_desc.type)); 2733 2734 schedule_delayed_work(&wk_data->wk, usecs_to_jiffies(delay)); 2735 2736 return 0; 2737 } 2738 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2739 2740 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2741 enum iwl_fw_dbg_trigger trig_type) 2742 { 2743 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2744 return -EIO; 2745 2746 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2747 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT && 2748 trig_type != FW_DBG_TRIGGER_DRIVER) 2749 return -EIO; 2750 2751 iwl_dbg_tlv_time_point(fwrt, 2752 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT, 2753 NULL); 2754 } else { 2755 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2756 int ret; 2757 2758 iwl_dump_error_desc = 2759 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2760 2761 if (!iwl_dump_error_desc) 2762 return -ENOMEM; 2763 2764 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2765 iwl_dump_error_desc->len = 0; 2766 2767 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, 2768 false, 0); 2769 if (ret) { 2770 kfree(iwl_dump_error_desc); 2771 return ret; 2772 } 2773 } 2774 2775 iwl_trans_sync_nmi(fwrt->trans); 2776 2777 return 0; 2778 } 2779 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2780 2781 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2782 enum iwl_fw_dbg_trigger trig, 2783 const char *str, size_t len, 2784 struct iwl_fw_dbg_trigger_tlv *trigger) 2785 { 2786 struct iwl_fw_dump_desc *desc; 2787 unsigned int delay = 0; 2788 bool monitor_only = false; 2789 2790 if (trigger) { 2791 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2792 2793 if (!le16_to_cpu(trigger->occurrences)) 2794 return 0; 2795 2796 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2797 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2798 trig); 2799 iwl_force_nmi(fwrt->trans); 2800 return 0; 2801 } 2802 2803 trigger->occurrences = cpu_to_le16(occurrences); 2804 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2805 2806 /* convert msec to usec */ 2807 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2808 } 2809 2810 desc = kzalloc(struct_size(desc, trig_desc.data, len), GFP_ATOMIC); 2811 if (!desc) 2812 return -ENOMEM; 2813 2814 2815 desc->len = len; 2816 desc->trig_desc.type = cpu_to_le32(trig); 2817 memcpy(desc->trig_desc.data, str, len); 2818 2819 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2820 } 2821 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2822 2823 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2824 struct iwl_fw_dbg_trigger_tlv *trigger, 2825 const char *fmt, ...) 2826 { 2827 int ret, len = 0; 2828 char buf[64]; 2829 2830 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2831 return 0; 2832 2833 if (fmt) { 2834 va_list ap; 2835 2836 buf[sizeof(buf) - 1] = '\0'; 2837 2838 va_start(ap, fmt); 2839 vsnprintf(buf, sizeof(buf), fmt, ap); 2840 va_end(ap); 2841 2842 /* check for truncation */ 2843 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2844 buf[sizeof(buf) - 1] = '\0'; 2845 2846 len = strlen(buf) + 1; 2847 } 2848 2849 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2850 trigger); 2851 2852 if (ret) 2853 return ret; 2854 2855 return 0; 2856 } 2857 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2858 2859 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2860 { 2861 u8 *ptr; 2862 int ret; 2863 int i; 2864 2865 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 2866 "Invalid configuration %d\n", conf_id)) 2867 return -EINVAL; 2868 2869 /* EARLY START - firmware's configuration is hard coded */ 2870 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 2871 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 2872 conf_id == FW_DBG_START_FROM_ALIVE) 2873 return 0; 2874 2875 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 2876 return -EINVAL; 2877 2878 if (fwrt->dump.conf != FW_DBG_INVALID) 2879 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n", 2880 fwrt->dump.conf); 2881 2882 /* Send all HCMDs for configuring the FW debug */ 2883 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 2884 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 2885 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 2886 struct iwl_host_cmd hcmd = { 2887 .id = cmd->id, 2888 .len = { le16_to_cpu(cmd->len), }, 2889 .data = { cmd->data, }, 2890 }; 2891 2892 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 2893 if (ret) 2894 return ret; 2895 2896 ptr += sizeof(*cmd); 2897 ptr += le16_to_cpu(cmd->len); 2898 } 2899 2900 fwrt->dump.conf = conf_id; 2901 2902 return 0; 2903 } 2904 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 2905 2906 void iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime *fwrt, 2907 u32 timepoint, 2908 u32 timepoint_data) 2909 { 2910 struct iwl_dbg_dump_complete_cmd hcmd_data; 2911 struct iwl_host_cmd hcmd = { 2912 .id = WIDE_ID(DEBUG_GROUP, FW_DUMP_COMPLETE_CMD), 2913 .data[0] = &hcmd_data, 2914 .len[0] = sizeof(hcmd_data), 2915 }; 2916 2917 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 2918 return; 2919 2920 if (fw_has_capa(&fwrt->fw->ucode_capa, 2921 IWL_UCODE_TLV_CAPA_DUMP_COMPLETE_SUPPORT)) { 2922 hcmd_data.tp = cpu_to_le32(timepoint); 2923 hcmd_data.tp_data = cpu_to_le32(timepoint_data); 2924 iwl_trans_send_cmd(fwrt->trans, &hcmd); 2925 } 2926 } 2927 2928 /* this function assumes dump_start was called beforehand and dump_end will be 2929 * called afterwards 2930 */ 2931 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 2932 { 2933 struct iwl_fw_dbg_params params = {0}; 2934 struct iwl_fwrt_dump_data *dump_data = 2935 &fwrt->dump.wks[wk_idx].dump_data; 2936 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 2937 return; 2938 2939 if (!dump_data->trig) { 2940 IWL_ERR(fwrt, "dump trigger data is not set\n"); 2941 goto out; 2942 } 2943 2944 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) { 2945 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n"); 2946 goto out; 2947 } 2948 2949 /* there's no point in fw dump if the bus is dead */ 2950 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 2951 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 2952 goto out; 2953 } 2954 2955 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true); 2956 2957 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 2958 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2959 iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 2960 else 2961 iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 2962 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 2963 2964 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 2965 2966 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2967 u32 policy = le32_to_cpu(dump_data->trig->apply_policy); 2968 u32 time_point = le32_to_cpu(dump_data->trig->time_point); 2969 2970 if (policy & IWL_FW_INI_APPLY_POLICY_DUMP_COMPLETE_CMD) { 2971 IWL_DEBUG_FW_INFO(fwrt, "WRT: sending dump complete\n"); 2972 iwl_send_dbg_dump_complete_cmd(fwrt, time_point, 0); 2973 } 2974 } 2975 2976 if (fwrt->trans->dbg.last_tp_resetfw == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) 2977 iwl_force_nmi(fwrt->trans); 2978 2979 out: 2980 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2981 iwl_fw_error_dump_data_free(dump_data); 2982 } else { 2983 iwl_fw_free_dump_desc(fwrt, dump_data->desc); 2984 dump_data->desc = NULL; 2985 } 2986 2987 clear_bit(wk_idx, &fwrt->dump.active_wks); 2988 } 2989 2990 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 2991 struct iwl_fwrt_dump_data *dump_data, 2992 bool sync) 2993 { 2994 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig; 2995 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2996 u32 occur, delay; 2997 unsigned long idx; 2998 2999 if (!iwl_fw_ini_trigger_on(fwrt, trig)) { 3000 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 3001 tp_id); 3002 return -EINVAL; 3003 } 3004 3005 delay = le32_to_cpu(trig->dump_delay); 3006 occur = le32_to_cpu(trig->occurrences); 3007 if (!occur) 3008 return 0; 3009 3010 trig->occurrences = cpu_to_le32(--occur); 3011 3012 /* Check there is an available worker. 3013 * ffz return value is undefined if no zero exists, 3014 * so check against ~0UL first. 3015 */ 3016 if (fwrt->dump.active_wks == ~0UL) 3017 return -EBUSY; 3018 3019 idx = ffz(fwrt->dump.active_wks); 3020 3021 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 3022 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 3023 return -EBUSY; 3024 3025 fwrt->dump.wks[idx].dump_data = *dump_data; 3026 3027 if (sync) 3028 delay = 0; 3029 3030 IWL_WARN(fwrt, 3031 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n", 3032 tp_id, (u32)(delay / USEC_PER_MSEC)); 3033 3034 if (sync) 3035 iwl_fw_dbg_collect_sync(fwrt, idx); 3036 else 3037 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay)); 3038 3039 return 0; 3040 } 3041 3042 void iwl_fw_error_dump_wk(struct work_struct *work) 3043 { 3044 struct iwl_fwrt_wk_data *wks = 3045 container_of(work, typeof(*wks), wk.work); 3046 struct iwl_fw_runtime *fwrt = 3047 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]); 3048 3049 /* assumes the op mode mutex is locked in dump_start since 3050 * iwl_fw_dbg_collect_sync can't run in parallel 3051 */ 3052 if (fwrt->ops && fwrt->ops->dump_start) 3053 fwrt->ops->dump_start(fwrt->ops_ctx); 3054 3055 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 3056 3057 if (fwrt->ops && fwrt->ops->dump_end) 3058 fwrt->ops->dump_end(fwrt->ops_ctx); 3059 } 3060 3061 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 3062 { 3063 const struct iwl_cfg *cfg = fwrt->trans->cfg; 3064 3065 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 3066 return; 3067 3068 if (!fwrt->dump.d3_debug_data) { 3069 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 3070 GFP_KERNEL); 3071 if (!fwrt->dump.d3_debug_data) { 3072 IWL_ERR(fwrt, 3073 "failed to allocate memory for D3 debug data\n"); 3074 return; 3075 } 3076 } 3077 3078 /* if the buffer holds previous debug data it is overwritten */ 3079 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 3080 fwrt->dump.d3_debug_data, 3081 cfg->d3_debug_data_length); 3082 3083 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 3084 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 3085 cfg->d3_debug_data_base_addr, 3086 fwrt->dump.d3_debug_data, 3087 cfg->d3_debug_data_length); 3088 } 3089 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 3090 3091 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 3092 { 3093 int i; 3094 3095 iwl_dbg_tlv_del_timers(fwrt->trans); 3096 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 3097 iwl_fw_dbg_collect_sync(fwrt, i); 3098 3099 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 3100 } 3101 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 3102 3103 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 3104 { 3105 struct iwl_dbg_suspend_resume_cmd cmd = { 3106 .operation = suspend ? 3107 cpu_to_le32(DBGC_SUSPEND_CMD) : 3108 cpu_to_le32(DBGC_RESUME_CMD), 3109 }; 3110 struct iwl_host_cmd hcmd = { 3111 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 3112 .data[0] = &cmd, 3113 .len[0] = sizeof(cmd), 3114 }; 3115 3116 return iwl_trans_send_cmd(trans, &hcmd); 3117 } 3118 3119 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 3120 struct iwl_fw_dbg_params *params) 3121 { 3122 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3123 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3124 return; 3125 } 3126 3127 if (params) { 3128 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 3129 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 3130 } 3131 3132 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 3133 /* wait for the DBGC to finish writing the internal buffer to DRAM to 3134 * avoid halting the HW while writing 3135 */ 3136 usleep_range(700, 1000); 3137 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 3138 } 3139 3140 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 3141 struct iwl_fw_dbg_params *params) 3142 { 3143 if (!params) 3144 return -EIO; 3145 3146 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3147 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3148 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3149 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3150 } else { 3151 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 3152 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 3153 } 3154 3155 return 0; 3156 } 3157 3158 int iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime *fwrt) 3159 { 3160 struct iwl_mvm_marker marker = { 3161 .dw_len = sizeof(struct iwl_mvm_marker) / 4, 3162 .marker_id = MARKER_ID_SYNC_CLOCK, 3163 }; 3164 struct iwl_host_cmd hcmd = { 3165 .flags = CMD_ASYNC, 3166 .id = WIDE_ID(LONG_GROUP, MARKER_CMD), 3167 .dataflags = {}, 3168 }; 3169 struct iwl_mvm_marker_rsp *resp; 3170 int cmd_ver = iwl_fw_lookup_cmd_ver(fwrt->fw, 3171 WIDE_ID(LONG_GROUP, MARKER_CMD), 3172 IWL_FW_CMD_VER_UNKNOWN); 3173 int ret; 3174 3175 if (cmd_ver == 1) { 3176 /* the real timestamp is taken from the ftrace clock 3177 * this is for finding the match between fw and kernel logs 3178 */ 3179 marker.timestamp = cpu_to_le64(fwrt->timestamp.seq++); 3180 } else if (cmd_ver == 2) { 3181 marker.timestamp = cpu_to_le64(ktime_get_boottime_ns()); 3182 } else { 3183 IWL_DEBUG_INFO(fwrt, 3184 "Invalid version of Marker CMD. Ver = %d\n", 3185 cmd_ver); 3186 return -EINVAL; 3187 } 3188 3189 hcmd.data[0] = ▮ 3190 hcmd.len[0] = sizeof(marker); 3191 3192 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 3193 3194 if (cmd_ver > 1 && hcmd.resp_pkt) { 3195 resp = (void *)hcmd.resp_pkt->data; 3196 IWL_DEBUG_INFO(fwrt, "FW GP2 time: %u\n", 3197 le32_to_cpu(resp->gp2)); 3198 } 3199 3200 return ret; 3201 } 3202 3203 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 3204 struct iwl_fw_dbg_params *params, 3205 bool stop) 3206 { 3207 int ret __maybe_unused = 0; 3208 3209 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 3210 return; 3211 3212 if (fw_has_capa(&fwrt->fw->ucode_capa, 3213 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) { 3214 if (stop) 3215 iwl_fw_send_timestamp_marker_cmd(fwrt); 3216 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 3217 } else if (stop) { 3218 iwl_fw_dbg_stop_recording(fwrt->trans, params); 3219 } else { 3220 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 3221 } 3222 #ifdef CONFIG_IWLWIFI_DEBUGFS 3223 if (!ret) { 3224 if (stop) 3225 fwrt->trans->dbg.rec_on = false; 3226 else 3227 iwl_fw_set_dbg_rec_on(fwrt); 3228 } 3229 #endif 3230 } 3231 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 3232