1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/devcoredump.h> 8 #include "iwl-drv.h" 9 #include "runtime.h" 10 #include "dbg.h" 11 #include "debugfs.h" 12 #include "iwl-io.h" 13 #include "iwl-prph.h" 14 #include "iwl-csr.h" 15 16 /** 17 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 18 * 19 * @fwrt_ptr: pointer to the buffer coming from fwrt 20 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 21 * transport's data. 22 * @trans_len: length of the valid data in trans_ptr 23 * @fwrt_len: length of the valid data in fwrt_ptr 24 */ 25 struct iwl_fw_dump_ptrs { 26 struct iwl_trans_dump_data *trans_ptr; 27 void *fwrt_ptr; 28 u32 fwrt_len; 29 }; 30 31 #define RADIO_REG_MAX_READ 0x2ad 32 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 33 struct iwl_fw_error_dump_data **dump_data) 34 { 35 u8 *pos = (void *)(*dump_data)->data; 36 int i; 37 38 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 39 40 if (!iwl_trans_grab_nic_access(fwrt->trans)) 41 return; 42 43 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 44 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 45 46 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 47 u32 rd_cmd = RADIO_RSP_RD_CMD; 48 49 rd_cmd |= i << RADIO_RSP_ADDR_POS; 50 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 51 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 52 53 pos++; 54 } 55 56 *dump_data = iwl_fw_error_next_data(*dump_data); 57 58 iwl_trans_release_nic_access(fwrt->trans); 59 } 60 61 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 62 struct iwl_fw_error_dump_data **dump_data, 63 int size, u32 offset, int fifo_num) 64 { 65 struct iwl_fw_error_dump_fifo *fifo_hdr; 66 u32 *fifo_data; 67 u32 fifo_len; 68 int i; 69 70 fifo_hdr = (void *)(*dump_data)->data; 71 fifo_data = (void *)fifo_hdr->data; 72 fifo_len = size; 73 74 /* No need to try to read the data if the length is 0 */ 75 if (fifo_len == 0) 76 return; 77 78 /* Add a TLV for the RXF */ 79 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 80 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 81 82 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 83 fifo_hdr->available_bytes = 84 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 85 RXF_RD_D_SPACE + offset)); 86 fifo_hdr->wr_ptr = 87 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 88 RXF_RD_WR_PTR + offset)); 89 fifo_hdr->rd_ptr = 90 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 91 RXF_RD_RD_PTR + offset)); 92 fifo_hdr->fence_ptr = 93 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 94 RXF_RD_FENCE_PTR + offset)); 95 fifo_hdr->fence_mode = 96 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 97 RXF_SET_FENCE_MODE + offset)); 98 99 /* Lock fence */ 100 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 101 /* Set fence pointer to the same place like WR pointer */ 102 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 103 /* Set fence offset */ 104 iwl_trans_write_prph(fwrt->trans, 105 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 106 107 /* Read FIFO */ 108 fifo_len /= sizeof(u32); /* Size in DWORDS */ 109 for (i = 0; i < fifo_len; i++) 110 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 111 RXF_FIFO_RD_FENCE_INC + 112 offset); 113 *dump_data = iwl_fw_error_next_data(*dump_data); 114 } 115 116 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 117 struct iwl_fw_error_dump_data **dump_data, 118 int size, u32 offset, int fifo_num) 119 { 120 struct iwl_fw_error_dump_fifo *fifo_hdr; 121 u32 *fifo_data; 122 u32 fifo_len; 123 int i; 124 125 fifo_hdr = (void *)(*dump_data)->data; 126 fifo_data = (void *)fifo_hdr->data; 127 fifo_len = size; 128 129 /* No need to try to read the data if the length is 0 */ 130 if (fifo_len == 0) 131 return; 132 133 /* Add a TLV for the FIFO */ 134 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 135 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 136 137 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 138 fifo_hdr->available_bytes = 139 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 140 TXF_FIFO_ITEM_CNT + offset)); 141 fifo_hdr->wr_ptr = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 TXF_WR_PTR + offset)); 144 fifo_hdr->rd_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 TXF_RD_PTR + offset)); 147 fifo_hdr->fence_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 TXF_FENCE_PTR + offset)); 150 fifo_hdr->fence_mode = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 TXF_LOCK_FENCE + offset)); 153 154 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 155 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 156 TXF_WR_PTR + offset); 157 158 /* Dummy-read to advance the read pointer to the head */ 159 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 160 161 /* Read FIFO */ 162 fifo_len /= sizeof(u32); /* Size in DWORDS */ 163 for (i = 0; i < fifo_len; i++) 164 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 165 TXF_READ_MODIFY_DATA + 166 offset); 167 *dump_data = iwl_fw_error_next_data(*dump_data); 168 } 169 170 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 171 struct iwl_fw_error_dump_data **dump_data) 172 { 173 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 174 175 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 176 177 if (!iwl_trans_grab_nic_access(fwrt->trans)) 178 return; 179 180 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 181 /* Pull RXF1 */ 182 iwl_fwrt_dump_rxf(fwrt, dump_data, 183 cfg->lmac[0].rxfifo1_size, 0, 0); 184 /* Pull RXF2 */ 185 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 186 RXF_DIFF_FROM_PREV + 187 fwrt->trans->trans_cfg->umac_prph_offset, 1); 188 /* Pull LMAC2 RXF1 */ 189 if (fwrt->smem_cfg.num_lmacs > 1) 190 iwl_fwrt_dump_rxf(fwrt, dump_data, 191 cfg->lmac[1].rxfifo1_size, 192 LMAC2_PRPH_OFFSET, 2); 193 } 194 195 iwl_trans_release_nic_access(fwrt->trans); 196 } 197 198 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 199 struct iwl_fw_error_dump_data **dump_data) 200 { 201 struct iwl_fw_error_dump_fifo *fifo_hdr; 202 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 203 u32 *fifo_data; 204 u32 fifo_len; 205 int i, j; 206 207 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 208 209 if (!iwl_trans_grab_nic_access(fwrt->trans)) 210 return; 211 212 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 213 /* Pull TXF data from LMAC1 */ 214 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 215 /* Mark the number of TXF we're pulling now */ 216 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 217 iwl_fwrt_dump_txf(fwrt, dump_data, 218 cfg->lmac[0].txfifo_size[i], 0, i); 219 } 220 221 /* Pull TXF data from LMAC2 */ 222 if (fwrt->smem_cfg.num_lmacs > 1) { 223 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 224 i++) { 225 /* Mark the number of TXF we're pulling now */ 226 iwl_trans_write_prph(fwrt->trans, 227 TXF_LARC_NUM + 228 LMAC2_PRPH_OFFSET, i); 229 iwl_fwrt_dump_txf(fwrt, dump_data, 230 cfg->lmac[1].txfifo_size[i], 231 LMAC2_PRPH_OFFSET, 232 i + cfg->num_txfifo_entries); 233 } 234 } 235 } 236 237 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 238 fw_has_capa(&fwrt->fw->ucode_capa, 239 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 240 /* Pull UMAC internal TXF data from all TXFs */ 241 for (i = 0; 242 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 243 i++) { 244 fifo_hdr = (void *)(*dump_data)->data; 245 fifo_data = (void *)fifo_hdr->data; 246 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 247 248 /* No need to try to read the data if the length is 0 */ 249 if (fifo_len == 0) 250 continue; 251 252 /* Add a TLV for the internal FIFOs */ 253 (*dump_data)->type = 254 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 255 (*dump_data)->len = 256 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 257 258 fifo_hdr->fifo_num = cpu_to_le32(i); 259 260 /* Mark the number of TXF we're pulling now */ 261 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 262 fwrt->smem_cfg.num_txfifo_entries); 263 264 fifo_hdr->available_bytes = 265 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 266 TXF_CPU2_FIFO_ITEM_CNT)); 267 fifo_hdr->wr_ptr = 268 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 269 TXF_CPU2_WR_PTR)); 270 fifo_hdr->rd_ptr = 271 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 272 TXF_CPU2_RD_PTR)); 273 fifo_hdr->fence_ptr = 274 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 275 TXF_CPU2_FENCE_PTR)); 276 fifo_hdr->fence_mode = 277 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 278 TXF_CPU2_LOCK_FENCE)); 279 280 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 281 iwl_trans_write_prph(fwrt->trans, 282 TXF_CPU2_READ_MODIFY_ADDR, 283 TXF_CPU2_WR_PTR); 284 285 /* Dummy-read to advance the read pointer to head */ 286 iwl_trans_read_prph(fwrt->trans, 287 TXF_CPU2_READ_MODIFY_DATA); 288 289 /* Read FIFO */ 290 fifo_len /= sizeof(u32); /* Size in DWORDS */ 291 for (j = 0; j < fifo_len; j++) 292 fifo_data[j] = 293 iwl_trans_read_prph(fwrt->trans, 294 TXF_CPU2_READ_MODIFY_DATA); 295 *dump_data = iwl_fw_error_next_data(*dump_data); 296 } 297 } 298 299 iwl_trans_release_nic_access(fwrt->trans); 300 } 301 302 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ 303 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ 304 305 struct iwl_prph_range { 306 u32 start, end; 307 }; 308 309 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 310 { .start = 0x00a00000, .end = 0x00a00000 }, 311 { .start = 0x00a0000c, .end = 0x00a00024 }, 312 { .start = 0x00a0002c, .end = 0x00a0003c }, 313 { .start = 0x00a00410, .end = 0x00a00418 }, 314 { .start = 0x00a00420, .end = 0x00a00420 }, 315 { .start = 0x00a00428, .end = 0x00a00428 }, 316 { .start = 0x00a00430, .end = 0x00a0043c }, 317 { .start = 0x00a00444, .end = 0x00a00444 }, 318 { .start = 0x00a004c0, .end = 0x00a004cc }, 319 { .start = 0x00a004d8, .end = 0x00a004d8 }, 320 { .start = 0x00a004e0, .end = 0x00a004f0 }, 321 { .start = 0x00a00840, .end = 0x00a00840 }, 322 { .start = 0x00a00850, .end = 0x00a00858 }, 323 { .start = 0x00a01004, .end = 0x00a01008 }, 324 { .start = 0x00a01010, .end = 0x00a01010 }, 325 { .start = 0x00a01018, .end = 0x00a01018 }, 326 { .start = 0x00a01024, .end = 0x00a01024 }, 327 { .start = 0x00a0102c, .end = 0x00a01034 }, 328 { .start = 0x00a0103c, .end = 0x00a01040 }, 329 { .start = 0x00a01048, .end = 0x00a01094 }, 330 { .start = 0x00a01c00, .end = 0x00a01c20 }, 331 { .start = 0x00a01c58, .end = 0x00a01c58 }, 332 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 333 { .start = 0x00a01c28, .end = 0x00a01c54 }, 334 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 335 { .start = 0x00a01c60, .end = 0x00a01cdc }, 336 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 337 { .start = 0x00a01d18, .end = 0x00a01d20 }, 338 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 339 { .start = 0x00a01d40, .end = 0x00a01d5c }, 340 { .start = 0x00a01d80, .end = 0x00a01d80 }, 341 { .start = 0x00a01d98, .end = 0x00a01d9c }, 342 { .start = 0x00a01da8, .end = 0x00a01da8 }, 343 { .start = 0x00a01db8, .end = 0x00a01df4 }, 344 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 345 { .start = 0x00a01e00, .end = 0x00a01e2c }, 346 { .start = 0x00a01e40, .end = 0x00a01e60 }, 347 { .start = 0x00a01e68, .end = 0x00a01e6c }, 348 { .start = 0x00a01e74, .end = 0x00a01e74 }, 349 { .start = 0x00a01e84, .end = 0x00a01e90 }, 350 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 351 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 352 { .start = 0x00a01f00, .end = 0x00a01f1c }, 353 { .start = 0x00a01f44, .end = 0x00a01ffc }, 354 { .start = 0x00a02000, .end = 0x00a02048 }, 355 { .start = 0x00a02068, .end = 0x00a020f0 }, 356 { .start = 0x00a02100, .end = 0x00a02118 }, 357 { .start = 0x00a02140, .end = 0x00a0214c }, 358 { .start = 0x00a02168, .end = 0x00a0218c }, 359 { .start = 0x00a021c0, .end = 0x00a021c0 }, 360 { .start = 0x00a02400, .end = 0x00a02410 }, 361 { .start = 0x00a02418, .end = 0x00a02420 }, 362 { .start = 0x00a02428, .end = 0x00a0242c }, 363 { .start = 0x00a02434, .end = 0x00a02434 }, 364 { .start = 0x00a02440, .end = 0x00a02460 }, 365 { .start = 0x00a02468, .end = 0x00a024b0 }, 366 { .start = 0x00a024c8, .end = 0x00a024cc }, 367 { .start = 0x00a02500, .end = 0x00a02504 }, 368 { .start = 0x00a0250c, .end = 0x00a02510 }, 369 { .start = 0x00a02540, .end = 0x00a02554 }, 370 { .start = 0x00a02580, .end = 0x00a025f4 }, 371 { .start = 0x00a02600, .end = 0x00a0260c }, 372 { .start = 0x00a02648, .end = 0x00a02650 }, 373 { .start = 0x00a02680, .end = 0x00a02680 }, 374 { .start = 0x00a026c0, .end = 0x00a026d0 }, 375 { .start = 0x00a02700, .end = 0x00a0270c }, 376 { .start = 0x00a02804, .end = 0x00a02804 }, 377 { .start = 0x00a02818, .end = 0x00a0281c }, 378 { .start = 0x00a02c00, .end = 0x00a02db4 }, 379 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 380 { .start = 0x00a03000, .end = 0x00a03014 }, 381 { .start = 0x00a0301c, .end = 0x00a0302c }, 382 { .start = 0x00a03034, .end = 0x00a03038 }, 383 { .start = 0x00a03040, .end = 0x00a03048 }, 384 { .start = 0x00a03060, .end = 0x00a03068 }, 385 { .start = 0x00a03070, .end = 0x00a03074 }, 386 { .start = 0x00a0307c, .end = 0x00a0307c }, 387 { .start = 0x00a03080, .end = 0x00a03084 }, 388 { .start = 0x00a0308c, .end = 0x00a03090 }, 389 { .start = 0x00a03098, .end = 0x00a03098 }, 390 { .start = 0x00a030a0, .end = 0x00a030a0 }, 391 { .start = 0x00a030a8, .end = 0x00a030b4 }, 392 { .start = 0x00a030bc, .end = 0x00a030bc }, 393 { .start = 0x00a030c0, .end = 0x00a0312c }, 394 { .start = 0x00a03c00, .end = 0x00a03c5c }, 395 { .start = 0x00a04400, .end = 0x00a04454 }, 396 { .start = 0x00a04460, .end = 0x00a04474 }, 397 { .start = 0x00a044c0, .end = 0x00a044ec }, 398 { .start = 0x00a04500, .end = 0x00a04504 }, 399 { .start = 0x00a04510, .end = 0x00a04538 }, 400 { .start = 0x00a04540, .end = 0x00a04548 }, 401 { .start = 0x00a04560, .end = 0x00a0457c }, 402 { .start = 0x00a04590, .end = 0x00a04598 }, 403 { .start = 0x00a045c0, .end = 0x00a045f4 }, 404 }; 405 406 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 407 { .start = 0x00a05c00, .end = 0x00a05c18 }, 408 { .start = 0x00a05400, .end = 0x00a056e8 }, 409 { .start = 0x00a08000, .end = 0x00a098bc }, 410 { .start = 0x00a02400, .end = 0x00a02758 }, 411 { .start = 0x00a04764, .end = 0x00a0476c }, 412 { .start = 0x00a04770, .end = 0x00a04774 }, 413 { .start = 0x00a04620, .end = 0x00a04624 }, 414 }; 415 416 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 417 { .start = 0x00a00000, .end = 0x00a00000 }, 418 { .start = 0x00a0000c, .end = 0x00a00024 }, 419 { .start = 0x00a0002c, .end = 0x00a00034 }, 420 { .start = 0x00a0003c, .end = 0x00a0003c }, 421 { .start = 0x00a00410, .end = 0x00a00418 }, 422 { .start = 0x00a00420, .end = 0x00a00420 }, 423 { .start = 0x00a00428, .end = 0x00a00428 }, 424 { .start = 0x00a00430, .end = 0x00a0043c }, 425 { .start = 0x00a00444, .end = 0x00a00444 }, 426 { .start = 0x00a00840, .end = 0x00a00840 }, 427 { .start = 0x00a00850, .end = 0x00a00858 }, 428 { .start = 0x00a01004, .end = 0x00a01008 }, 429 { .start = 0x00a01010, .end = 0x00a01010 }, 430 { .start = 0x00a01018, .end = 0x00a01018 }, 431 { .start = 0x00a01024, .end = 0x00a01024 }, 432 { .start = 0x00a0102c, .end = 0x00a01034 }, 433 { .start = 0x00a0103c, .end = 0x00a01040 }, 434 { .start = 0x00a01048, .end = 0x00a01050 }, 435 { .start = 0x00a01058, .end = 0x00a01058 }, 436 { .start = 0x00a01060, .end = 0x00a01070 }, 437 { .start = 0x00a0108c, .end = 0x00a0108c }, 438 { .start = 0x00a01c20, .end = 0x00a01c28 }, 439 { .start = 0x00a01d10, .end = 0x00a01d10 }, 440 { .start = 0x00a01e28, .end = 0x00a01e2c }, 441 { .start = 0x00a01e60, .end = 0x00a01e60 }, 442 { .start = 0x00a01e80, .end = 0x00a01e80 }, 443 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 444 { .start = 0x00a02000, .end = 0x00a0201c }, 445 { .start = 0x00a02024, .end = 0x00a02024 }, 446 { .start = 0x00a02040, .end = 0x00a02048 }, 447 { .start = 0x00a020c0, .end = 0x00a020e0 }, 448 { .start = 0x00a02400, .end = 0x00a02404 }, 449 { .start = 0x00a0240c, .end = 0x00a02414 }, 450 { .start = 0x00a0241c, .end = 0x00a0243c }, 451 { .start = 0x00a02448, .end = 0x00a024bc }, 452 { .start = 0x00a024c4, .end = 0x00a024cc }, 453 { .start = 0x00a02508, .end = 0x00a02508 }, 454 { .start = 0x00a02510, .end = 0x00a02514 }, 455 { .start = 0x00a0251c, .end = 0x00a0251c }, 456 { .start = 0x00a0252c, .end = 0x00a0255c }, 457 { .start = 0x00a02564, .end = 0x00a025a0 }, 458 { .start = 0x00a025a8, .end = 0x00a025b4 }, 459 { .start = 0x00a025c0, .end = 0x00a025c0 }, 460 { .start = 0x00a025e8, .end = 0x00a025f4 }, 461 { .start = 0x00a02c08, .end = 0x00a02c18 }, 462 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 463 { .start = 0x00a02c68, .end = 0x00a02c78 }, 464 { .start = 0x00a03000, .end = 0x00a03000 }, 465 { .start = 0x00a03010, .end = 0x00a03014 }, 466 { .start = 0x00a0301c, .end = 0x00a0302c }, 467 { .start = 0x00a03034, .end = 0x00a03038 }, 468 { .start = 0x00a03040, .end = 0x00a03044 }, 469 { .start = 0x00a03060, .end = 0x00a03068 }, 470 { .start = 0x00a03070, .end = 0x00a03070 }, 471 { .start = 0x00a0307c, .end = 0x00a03084 }, 472 { .start = 0x00a0308c, .end = 0x00a03090 }, 473 { .start = 0x00a03098, .end = 0x00a03098 }, 474 { .start = 0x00a030a0, .end = 0x00a030a0 }, 475 { .start = 0x00a030a8, .end = 0x00a030b4 }, 476 { .start = 0x00a030bc, .end = 0x00a030c0 }, 477 { .start = 0x00a030c8, .end = 0x00a030f4 }, 478 { .start = 0x00a03100, .end = 0x00a0312c }, 479 { .start = 0x00a03c00, .end = 0x00a03c5c }, 480 { .start = 0x00a04400, .end = 0x00a04454 }, 481 { .start = 0x00a04460, .end = 0x00a04474 }, 482 { .start = 0x00a044c0, .end = 0x00a044ec }, 483 { .start = 0x00a04500, .end = 0x00a04504 }, 484 { .start = 0x00a04510, .end = 0x00a04538 }, 485 { .start = 0x00a04540, .end = 0x00a04548 }, 486 { .start = 0x00a04560, .end = 0x00a04560 }, 487 { .start = 0x00a04570, .end = 0x00a0457c }, 488 { .start = 0x00a04590, .end = 0x00a04590 }, 489 { .start = 0x00a04598, .end = 0x00a04598 }, 490 { .start = 0x00a045c0, .end = 0x00a045f4 }, 491 { .start = 0x00a05c18, .end = 0x00a05c1c }, 492 { .start = 0x00a0c000, .end = 0x00a0c018 }, 493 { .start = 0x00a0c020, .end = 0x00a0c028 }, 494 { .start = 0x00a0c038, .end = 0x00a0c094 }, 495 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 496 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 497 { .start = 0x00a0c150, .end = 0x00a0c174 }, 498 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 499 { .start = 0x00a0c190, .end = 0x00a0c198 }, 500 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 501 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 502 }; 503 504 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 505 { .start = 0x00d03c00, .end = 0x00d03c64 }, 506 { .start = 0x00d05c18, .end = 0x00d05c1c }, 507 { .start = 0x00d0c000, .end = 0x00d0c174 }, 508 }; 509 510 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 511 u32 len_bytes, __le32 *data) 512 { 513 u32 i; 514 515 for (i = 0; i < len_bytes; i += 4) 516 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 517 } 518 519 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 520 const struct iwl_prph_range *iwl_prph_dump_addr, 521 u32 range_len, void *ptr) 522 { 523 struct iwl_fw_error_dump_prph *prph; 524 struct iwl_trans *trans = fwrt->trans; 525 struct iwl_fw_error_dump_data **data = 526 (struct iwl_fw_error_dump_data **)ptr; 527 u32 i; 528 529 if (!data) 530 return; 531 532 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 533 534 if (!iwl_trans_grab_nic_access(trans)) 535 return; 536 537 for (i = 0; i < range_len; i++) { 538 /* The range includes both boundaries */ 539 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 540 iwl_prph_dump_addr[i].start + 4; 541 542 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 543 (*data)->len = cpu_to_le32(sizeof(*prph) + 544 num_bytes_in_chunk); 545 prph = (void *)(*data)->data; 546 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 547 548 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 549 /* our range is inclusive, hence + 4 */ 550 iwl_prph_dump_addr[i].end - 551 iwl_prph_dump_addr[i].start + 4, 552 (void *)prph->data); 553 554 *data = iwl_fw_error_next_data(*data); 555 } 556 557 iwl_trans_release_nic_access(trans); 558 } 559 560 /* 561 * alloc_sgtable - allocates scallerlist table in the given size, 562 * fills it with pages and returns it 563 * @size: the size (in bytes) of the table 564 */ 565 static struct scatterlist *alloc_sgtable(int size) 566 { 567 int alloc_size, nents, i; 568 struct page *new_page; 569 struct scatterlist *iter; 570 struct scatterlist *table; 571 572 nents = DIV_ROUND_UP(size, PAGE_SIZE); 573 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 574 if (!table) 575 return NULL; 576 sg_init_table(table, nents); 577 iter = table; 578 for_each_sg(table, iter, sg_nents(table), i) { 579 new_page = alloc_page(GFP_KERNEL); 580 if (!new_page) { 581 /* release all previous allocated pages in the table */ 582 iter = table; 583 for_each_sg(table, iter, sg_nents(table), i) { 584 new_page = sg_page(iter); 585 if (new_page) 586 __free_page(new_page); 587 } 588 kfree(table); 589 return NULL; 590 } 591 alloc_size = min_t(int, size, PAGE_SIZE); 592 size -= PAGE_SIZE; 593 sg_set_page(iter, new_page, alloc_size, 0); 594 } 595 return table; 596 } 597 598 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 599 const struct iwl_prph_range *iwl_prph_dump_addr, 600 u32 range_len, void *ptr) 601 { 602 u32 *prph_len = (u32 *)ptr; 603 int i, num_bytes_in_chunk; 604 605 if (!prph_len) 606 return; 607 608 for (i = 0; i < range_len; i++) { 609 /* The range includes both boundaries */ 610 num_bytes_in_chunk = 611 iwl_prph_dump_addr[i].end - 612 iwl_prph_dump_addr[i].start + 4; 613 614 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 615 sizeof(struct iwl_fw_error_dump_prph) + 616 num_bytes_in_chunk; 617 } 618 } 619 620 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 621 void (*handler)(struct iwl_fw_runtime *, 622 const struct iwl_prph_range *, 623 u32, void *)) 624 { 625 u32 range_len; 626 627 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 628 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 629 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 630 } else if (fwrt->trans->trans_cfg->device_family >= 631 IWL_DEVICE_FAMILY_22000) { 632 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 633 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 634 } else { 635 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 636 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 637 638 if (fwrt->trans->trans_cfg->mq_rx_supported) { 639 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 640 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 641 } 642 } 643 } 644 645 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 646 struct iwl_fw_error_dump_data **dump_data, 647 u32 len, u32 ofs, u32 type) 648 { 649 struct iwl_fw_error_dump_mem *dump_mem; 650 651 if (!len) 652 return; 653 654 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 655 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 656 dump_mem = (void *)(*dump_data)->data; 657 dump_mem->type = cpu_to_le32(type); 658 dump_mem->offset = cpu_to_le32(ofs); 659 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 660 *dump_data = iwl_fw_error_next_data(*dump_data); 661 662 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 663 } 664 665 #define ADD_LEN(len, item_len, const_len) \ 666 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 667 while (0) 668 669 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 670 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 671 { 672 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 673 sizeof(struct iwl_fw_error_dump_fifo); 674 u32 fifo_len = 0; 675 int i; 676 677 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 678 return 0; 679 680 /* Count RXF2 size */ 681 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 682 683 /* Count RXF1 sizes */ 684 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 685 mem_cfg->num_lmacs = MAX_NUM_LMAC; 686 687 for (i = 0; i < mem_cfg->num_lmacs; i++) 688 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 689 690 return fifo_len; 691 } 692 693 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 694 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 695 { 696 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 697 sizeof(struct iwl_fw_error_dump_fifo); 698 u32 fifo_len = 0; 699 int i; 700 701 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 702 goto dump_internal_txf; 703 704 /* Count TXF sizes */ 705 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 706 mem_cfg->num_lmacs = MAX_NUM_LMAC; 707 708 for (i = 0; i < mem_cfg->num_lmacs; i++) { 709 int j; 710 711 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 712 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 713 hdr_len); 714 } 715 716 dump_internal_txf: 717 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 718 fw_has_capa(&fwrt->fw->ucode_capa, 719 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 720 goto out; 721 722 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 723 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 724 725 out: 726 return fifo_len; 727 } 728 729 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 730 struct iwl_fw_error_dump_data **data) 731 { 732 int i; 733 734 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 735 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 736 struct iwl_fw_error_dump_paging *paging; 737 struct page *pages = 738 fwrt->fw_paging_db[i].fw_paging_block; 739 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 740 741 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 742 (*data)->len = cpu_to_le32(sizeof(*paging) + 743 PAGING_BLOCK_SIZE); 744 paging = (void *)(*data)->data; 745 paging->index = cpu_to_le32(i); 746 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 747 PAGING_BLOCK_SIZE, 748 DMA_BIDIRECTIONAL); 749 memcpy(paging->data, page_address(pages), 750 PAGING_BLOCK_SIZE); 751 dma_sync_single_for_device(fwrt->trans->dev, addr, 752 PAGING_BLOCK_SIZE, 753 DMA_BIDIRECTIONAL); 754 (*data) = iwl_fw_error_next_data(*data); 755 } 756 } 757 758 static struct iwl_fw_error_dump_file * 759 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 760 struct iwl_fw_dump_ptrs *fw_error_dump, 761 struct iwl_fwrt_dump_data *data) 762 { 763 struct iwl_fw_error_dump_file *dump_file; 764 struct iwl_fw_error_dump_data *dump_data; 765 struct iwl_fw_error_dump_info *dump_info; 766 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 767 struct iwl_fw_error_dump_trigger_desc *dump_trig; 768 u32 sram_len, sram_ofs; 769 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 770 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 771 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 772 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 773 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 774 0 : fwrt->trans->cfg->dccm2_len; 775 int i; 776 777 /* SRAM - include stack CCM if driver knows the values for it */ 778 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 779 const struct fw_img *img; 780 781 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 782 return NULL; 783 img = &fwrt->fw->img[fwrt->cur_fw_img]; 784 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 785 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 786 } else { 787 sram_ofs = fwrt->trans->cfg->dccm_offset; 788 sram_len = fwrt->trans->cfg->dccm_len; 789 } 790 791 /* reading RXF/TXF sizes */ 792 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 793 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 794 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 795 796 /* Make room for PRPH registers */ 797 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 798 iwl_fw_prph_handler(fwrt, &prph_len, 799 iwl_fw_get_prph_len); 800 801 if (fwrt->trans->trans_cfg->device_family == 802 IWL_DEVICE_FAMILY_7000 && 803 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 804 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 805 } 806 807 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 808 809 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 810 file_len += sizeof(*dump_data) + sizeof(*dump_info); 811 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 812 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 813 814 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 815 size_t hdr_len = sizeof(*dump_data) + 816 sizeof(struct iwl_fw_error_dump_mem); 817 818 /* Dump SRAM only if no mem_tlvs */ 819 if (!fwrt->fw->dbg.n_mem_tlv) 820 ADD_LEN(file_len, sram_len, hdr_len); 821 822 /* Make room for all mem types that exist */ 823 ADD_LEN(file_len, smem_len, hdr_len); 824 ADD_LEN(file_len, sram2_len, hdr_len); 825 826 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 827 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 828 } 829 830 /* Make room for fw's virtual image pages, if it exists */ 831 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 832 file_len += fwrt->num_of_paging_blk * 833 (sizeof(*dump_data) + 834 sizeof(struct iwl_fw_error_dump_paging) + 835 PAGING_BLOCK_SIZE); 836 837 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 838 file_len += sizeof(*dump_data) + 839 fwrt->trans->cfg->d3_debug_data_length * 2; 840 } 841 842 /* If we only want a monitor dump, reset the file length */ 843 if (data->monitor_only) { 844 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 845 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 846 } 847 848 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 849 data->desc) 850 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 851 data->desc->len; 852 853 dump_file = vzalloc(file_len); 854 if (!dump_file) 855 return NULL; 856 857 fw_error_dump->fwrt_ptr = dump_file; 858 859 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 860 dump_data = (void *)dump_file->data; 861 862 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 863 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 864 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 865 dump_info = (void *)dump_data->data; 866 dump_info->hw_type = 867 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 868 dump_info->hw_step = 869 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 870 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 871 sizeof(dump_info->fw_human_readable)); 872 strncpy(dump_info->dev_human_readable, fwrt->trans->name, 873 sizeof(dump_info->dev_human_readable) - 1); 874 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 875 sizeof(dump_info->bus_human_readable) - 1); 876 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 877 dump_info->lmac_err_id[0] = 878 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 879 if (fwrt->smem_cfg.num_lmacs > 1) 880 dump_info->lmac_err_id[1] = 881 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 882 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 883 884 dump_data = iwl_fw_error_next_data(dump_data); 885 } 886 887 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 888 /* Dump shared memory configuration */ 889 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 890 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 891 dump_smem_cfg = (void *)dump_data->data; 892 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 893 dump_smem_cfg->num_txfifo_entries = 894 cpu_to_le32(mem_cfg->num_txfifo_entries); 895 for (i = 0; i < MAX_NUM_LMAC; i++) { 896 int j; 897 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 898 899 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 900 dump_smem_cfg->lmac[i].txfifo_size[j] = 901 cpu_to_le32(txf_size[j]); 902 dump_smem_cfg->lmac[i].rxfifo1_size = 903 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 904 } 905 dump_smem_cfg->rxfifo2_size = 906 cpu_to_le32(mem_cfg->rxfifo2_size); 907 dump_smem_cfg->internal_txfifo_addr = 908 cpu_to_le32(mem_cfg->internal_txfifo_addr); 909 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 910 dump_smem_cfg->internal_txfifo_size[i] = 911 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 912 } 913 914 dump_data = iwl_fw_error_next_data(dump_data); 915 } 916 917 /* We only dump the FIFOs if the FW is in error state */ 918 if (fifo_len) { 919 iwl_fw_dump_rxf(fwrt, &dump_data); 920 iwl_fw_dump_txf(fwrt, &dump_data); 921 } 922 923 if (radio_len) 924 iwl_read_radio_regs(fwrt, &dump_data); 925 926 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 927 data->desc) { 928 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 929 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 930 data->desc->len); 931 dump_trig = (void *)dump_data->data; 932 memcpy(dump_trig, &data->desc->trig_desc, 933 sizeof(*dump_trig) + data->desc->len); 934 935 dump_data = iwl_fw_error_next_data(dump_data); 936 } 937 938 /* In case we only want monitor dump, skip to dump trasport data */ 939 if (data->monitor_only) 940 goto out; 941 942 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 943 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 944 fwrt->fw->dbg.mem_tlv; 945 946 if (!fwrt->fw->dbg.n_mem_tlv) 947 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 948 IWL_FW_ERROR_DUMP_MEM_SRAM); 949 950 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 951 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 952 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 953 954 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 955 le32_to_cpu(fw_dbg_mem[i].data_type)); 956 } 957 958 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 959 fwrt->trans->cfg->smem_offset, 960 IWL_FW_ERROR_DUMP_MEM_SMEM); 961 962 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 963 fwrt->trans->cfg->dccm2_offset, 964 IWL_FW_ERROR_DUMP_MEM_SRAM); 965 } 966 967 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 968 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 969 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 970 971 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 972 dump_data->len = cpu_to_le32(data_size * 2); 973 974 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 975 976 kfree(fwrt->dump.d3_debug_data); 977 fwrt->dump.d3_debug_data = NULL; 978 979 iwl_trans_read_mem_bytes(fwrt->trans, addr, 980 dump_data->data + data_size, 981 data_size); 982 983 dump_data = iwl_fw_error_next_data(dump_data); 984 } 985 986 /* Dump fw's virtual image */ 987 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 988 iwl_dump_paging(fwrt, &dump_data); 989 990 if (prph_len) 991 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 992 993 out: 994 dump_file->file_len = cpu_to_le32(file_len); 995 return dump_file; 996 } 997 998 /** 999 * struct iwl_dump_ini_region_data - region data 1000 * @reg_tlv: region TLV 1001 * @dump_data: dump data 1002 */ 1003 struct iwl_dump_ini_region_data { 1004 struct iwl_ucode_tlv *reg_tlv; 1005 struct iwl_fwrt_dump_data *dump_data; 1006 }; 1007 1008 static int 1009 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt, 1010 struct iwl_dump_ini_region_data *reg_data, 1011 void *range_ptr, int idx) 1012 { 1013 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1014 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1015 __le32 *val = range->data; 1016 u32 prph_val; 1017 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1018 le32_to_cpu(reg->dev_addr.offset); 1019 int i; 1020 1021 range->internal_base_addr = cpu_to_le32(addr); 1022 range->range_data_size = reg->dev_addr.size; 1023 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1024 prph_val = iwl_read_prph(fwrt->trans, addr + i); 1025 if (prph_val == 0x5a5a5a5a) 1026 return -EBUSY; 1027 *val++ = cpu_to_le32(prph_val); 1028 } 1029 1030 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1031 } 1032 1033 static int 1034 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt, 1035 struct iwl_dump_ini_region_data *reg_data, 1036 void *range_ptr, int idx) 1037 { 1038 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1039 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1040 __le32 *val = range->data; 1041 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1; 1042 u32 indirect_rd_addr = WMAL_MRSPF_1; 1043 u32 prph_val; 1044 u32 addr = le32_to_cpu(reg->addrs[idx]); 1045 u32 dphy_state; 1046 u32 dphy_addr; 1047 int i; 1048 1049 range->internal_base_addr = cpu_to_le32(addr); 1050 range->range_data_size = reg->dev_addr.size; 1051 1052 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 1053 indirect_wr_addr = WMAL_INDRCT_CMD1; 1054 1055 indirect_wr_addr += le32_to_cpu(reg->dev_addr.offset); 1056 indirect_rd_addr += le32_to_cpu(reg->dev_addr.offset); 1057 1058 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1059 return -EBUSY; 1060 1061 dphy_addr = (reg->dev_addr.offset) ? WFPM_LMAC2_PS_CTL_RW : 1062 WFPM_LMAC1_PS_CTL_RW; 1063 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1064 1065 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1066 if (dphy_state == HBUS_TIMEOUT || 1067 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1068 WFPM_PHYRF_STATE_ON) { 1069 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1070 continue; 1071 } 1072 1073 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr, 1074 WMAL_INDRCT_CMD(addr + i)); 1075 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1076 indirect_rd_addr); 1077 *val++ = cpu_to_le32(prph_val); 1078 } 1079 1080 iwl_trans_release_nic_access(fwrt->trans); 1081 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1082 } 1083 1084 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1085 struct iwl_dump_ini_region_data *reg_data, 1086 void *range_ptr, int idx) 1087 { 1088 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1089 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1090 __le32 *val = range->data; 1091 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1092 le32_to_cpu(reg->dev_addr.offset); 1093 int i; 1094 1095 range->internal_base_addr = cpu_to_le32(addr); 1096 range->range_data_size = reg->dev_addr.size; 1097 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) 1098 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1099 1100 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1101 } 1102 1103 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt, 1104 struct iwl_dump_ini_region_data *reg_data, 1105 void *range_ptr, int idx) 1106 { 1107 struct iwl_trans *trans = fwrt->trans; 1108 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1109 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1110 __le32 *val = range->data; 1111 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1112 le32_to_cpu(reg->dev_addr.offset); 1113 int i; 1114 1115 /* we shouldn't get here if the trans doesn't have read_config32 */ 1116 if (WARN_ON_ONCE(!trans->ops->read_config32)) 1117 return -EOPNOTSUPP; 1118 1119 range->internal_base_addr = cpu_to_le32(addr); 1120 range->range_data_size = reg->dev_addr.size; 1121 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1122 int ret; 1123 u32 tmp; 1124 1125 ret = trans->ops->read_config32(trans, addr + i, &tmp); 1126 if (ret < 0) 1127 return ret; 1128 1129 *val++ = cpu_to_le32(tmp); 1130 } 1131 1132 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1133 } 1134 1135 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1136 struct iwl_dump_ini_region_data *reg_data, 1137 void *range_ptr, int idx) 1138 { 1139 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1140 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1141 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1142 le32_to_cpu(reg->dev_addr.offset); 1143 1144 range->internal_base_addr = cpu_to_le32(addr); 1145 range->range_data_size = reg->dev_addr.size; 1146 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1147 le32_to_cpu(reg->dev_addr.size)); 1148 1149 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1150 } 1151 1152 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1153 void *range_ptr, int idx) 1154 { 1155 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block; 1156 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1157 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1158 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1159 1160 range->page_num = cpu_to_le32(idx); 1161 range->range_data_size = cpu_to_le32(page_size); 1162 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1163 DMA_BIDIRECTIONAL); 1164 memcpy(range->data, page_address(page), page_size); 1165 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1166 DMA_BIDIRECTIONAL); 1167 1168 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1169 } 1170 1171 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1172 struct iwl_dump_ini_region_data *reg_data, 1173 void *range_ptr, int idx) 1174 { 1175 struct iwl_fw_ini_error_dump_range *range; 1176 u32 page_size; 1177 1178 /* all paged index start from 1 to skip CSS section */ 1179 idx++; 1180 1181 if (!fwrt->trans->trans_cfg->gen2) 1182 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, idx); 1183 1184 range = range_ptr; 1185 page_size = fwrt->trans->init_dram.paging[idx].size; 1186 1187 range->page_num = cpu_to_le32(idx); 1188 range->range_data_size = cpu_to_le32(page_size); 1189 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1190 page_size); 1191 1192 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1193 } 1194 1195 static int 1196 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1197 struct iwl_dump_ini_region_data *reg_data, 1198 void *range_ptr, int idx) 1199 { 1200 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1201 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1202 struct iwl_dram_data *frag; 1203 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1204 1205 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx]; 1206 1207 range->dram_base_addr = cpu_to_le64(frag->physical); 1208 range->range_data_size = cpu_to_le32(frag->size); 1209 1210 memcpy(range->data, frag->block, frag->size); 1211 1212 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1213 } 1214 1215 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt, 1216 struct iwl_dump_ini_region_data *reg_data, 1217 void *range_ptr, int idx) 1218 { 1219 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1220 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1221 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr); 1222 1223 range->internal_base_addr = cpu_to_le32(addr); 1224 range->range_data_size = reg->internal_buffer.size; 1225 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1226 le32_to_cpu(reg->internal_buffer.size)); 1227 1228 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1229 } 1230 1231 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1232 struct iwl_dump_ini_region_data *reg_data, int idx) 1233 { 1234 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1235 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1236 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1237 int txf_num = cfg->num_txfifo_entries; 1238 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1239 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]); 1240 1241 if (!idx) { 1242 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) { 1243 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n", 1244 le32_to_cpu(reg->fifos.offset)); 1245 return false; 1246 } 1247 1248 iter->internal_txf = 0; 1249 iter->fifo_size = 0; 1250 iter->fifo = -1; 1251 if (le32_to_cpu(reg->fifos.offset)) 1252 iter->lmac = 1; 1253 else 1254 iter->lmac = 0; 1255 } 1256 1257 if (!iter->internal_txf) { 1258 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1259 iter->fifo_size = 1260 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1261 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1262 return true; 1263 } 1264 iter->fifo--; 1265 } 1266 1267 iter->internal_txf = 1; 1268 1269 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1270 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1271 return false; 1272 1273 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1274 iter->fifo_size = 1275 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1276 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1277 return true; 1278 } 1279 1280 return false; 1281 } 1282 1283 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1284 struct iwl_dump_ini_region_data *reg_data, 1285 void *range_ptr, int idx) 1286 { 1287 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1288 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1289 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1290 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1291 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1292 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1293 u32 registers_size = registers_num * sizeof(*reg_dump); 1294 __le32 *data; 1295 int i; 1296 1297 if (!iwl_ini_txf_iter(fwrt, reg_data, idx)) 1298 return -EIO; 1299 1300 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1301 return -EBUSY; 1302 1303 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1304 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1305 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1306 1307 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1308 1309 /* 1310 * read txf registers. for each register, write to the dump the 1311 * register address and its value 1312 */ 1313 for (i = 0; i < registers_num; i++) { 1314 addr = le32_to_cpu(reg->addrs[i]) + offs; 1315 1316 reg_dump->addr = cpu_to_le32(addr); 1317 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1318 addr)); 1319 1320 reg_dump++; 1321 } 1322 1323 if (reg->fifos.hdr_only) { 1324 range->range_data_size = cpu_to_le32(registers_size); 1325 goto out; 1326 } 1327 1328 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1329 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1330 TXF_WR_PTR + offs); 1331 1332 /* Dummy-read to advance the read pointer to the head */ 1333 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1334 1335 /* Read FIFO */ 1336 addr = TXF_READ_MODIFY_DATA + offs; 1337 data = (void *)reg_dump; 1338 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1339 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1340 1341 out: 1342 iwl_trans_release_nic_access(fwrt->trans); 1343 1344 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1345 } 1346 1347 struct iwl_ini_rxf_data { 1348 u32 fifo_num; 1349 u32 size; 1350 u32 offset; 1351 }; 1352 1353 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1354 struct iwl_dump_ini_region_data *reg_data, 1355 struct iwl_ini_rxf_data *data) 1356 { 1357 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1358 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]); 1359 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]); 1360 u8 fifo_idx; 1361 1362 if (!data) 1363 return; 1364 1365 /* make sure only one bit is set in only one fid */ 1366 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1, 1367 "fid1=%x, fid2=%x\n", fid1, fid2)) 1368 return; 1369 1370 memset(data, 0, sizeof(*data)); 1371 1372 if (fid1) { 1373 fifo_idx = ffs(fid1) - 1; 1374 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n", 1375 fifo_idx)) 1376 return; 1377 1378 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1379 data->fifo_num = fifo_idx; 1380 } else { 1381 u8 max_idx; 1382 1383 fifo_idx = ffs(fid2) - 1; 1384 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP, 1385 SHARED_MEM_CFG_CMD, 0) <= 3) 1386 max_idx = 0; 1387 else 1388 max_idx = 1; 1389 1390 if (WARN_ONCE(fifo_idx > max_idx, 1391 "invalid umac fifo idx %d", fifo_idx)) 1392 return; 1393 1394 /* use bit 31 to distinguish between umac and lmac rxf while 1395 * parsing the dump 1396 */ 1397 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1398 1399 switch (fifo_idx) { 1400 case 0: 1401 data->size = fwrt->smem_cfg.rxfifo2_size; 1402 data->offset = iwl_umac_prph(fwrt->trans, 1403 RXF_DIFF_FROM_PREV); 1404 break; 1405 case 1: 1406 data->size = fwrt->smem_cfg.rxfifo2_control_size; 1407 data->offset = iwl_umac_prph(fwrt->trans, 1408 RXF2C_DIFF_FROM_PREV); 1409 break; 1410 } 1411 } 1412 } 1413 1414 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1415 struct iwl_dump_ini_region_data *reg_data, 1416 void *range_ptr, int idx) 1417 { 1418 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1419 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1420 struct iwl_ini_rxf_data rxf_data; 1421 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1422 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1423 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1424 u32 registers_size = registers_num * sizeof(*reg_dump); 1425 __le32 *data; 1426 int i; 1427 1428 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data); 1429 if (!rxf_data.size) 1430 return -EIO; 1431 1432 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1433 return -EBUSY; 1434 1435 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1436 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1437 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1438 1439 /* 1440 * read rxf registers. for each register, write to the dump the 1441 * register address and its value 1442 */ 1443 for (i = 0; i < registers_num; i++) { 1444 addr = le32_to_cpu(reg->addrs[i]) + offs; 1445 1446 reg_dump->addr = cpu_to_le32(addr); 1447 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1448 addr)); 1449 1450 reg_dump++; 1451 } 1452 1453 if (reg->fifos.hdr_only) { 1454 range->range_data_size = cpu_to_le32(registers_size); 1455 goto out; 1456 } 1457 1458 offs = rxf_data.offset; 1459 1460 /* Lock fence */ 1461 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1462 /* Set fence pointer to the same place like WR pointer */ 1463 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1464 /* Set fence offset */ 1465 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1466 0x0); 1467 1468 /* Read FIFO */ 1469 addr = RXF_FIFO_RD_FENCE_INC + offs; 1470 data = (void *)reg_dump; 1471 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1472 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1473 1474 out: 1475 iwl_trans_release_nic_access(fwrt->trans); 1476 1477 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1478 } 1479 1480 static int 1481 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt, 1482 struct iwl_dump_ini_region_data *reg_data, 1483 void *range_ptr, int idx) 1484 { 1485 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1486 struct iwl_fw_ini_region_err_table *err_table = ®->err_table; 1487 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1488 u32 addr = le32_to_cpu(err_table->base_addr) + 1489 le32_to_cpu(err_table->offset); 1490 1491 range->internal_base_addr = cpu_to_le32(addr); 1492 range->range_data_size = err_table->size; 1493 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1494 le32_to_cpu(err_table->size)); 1495 1496 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1497 } 1498 1499 static int 1500 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt, 1501 struct iwl_dump_ini_region_data *reg_data, 1502 void *range_ptr, int idx) 1503 { 1504 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1505 struct iwl_fw_ini_region_special_device_memory *special_mem = 1506 ®->special_mem; 1507 1508 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1509 u32 addr = le32_to_cpu(special_mem->base_addr) + 1510 le32_to_cpu(special_mem->offset); 1511 1512 range->internal_base_addr = cpu_to_le32(addr); 1513 range->range_data_size = special_mem->size; 1514 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1515 le32_to_cpu(special_mem->size)); 1516 1517 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1518 } 1519 1520 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt, 1521 struct iwl_dump_ini_region_data *reg_data, 1522 void *range_ptr, int idx) 1523 { 1524 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1525 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt; 1526 u32 pkt_len; 1527 1528 if (!pkt) 1529 return -EIO; 1530 1531 pkt_len = iwl_rx_packet_payload_len(pkt); 1532 1533 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr)); 1534 range->range_data_size = cpu_to_le32(pkt_len); 1535 1536 memcpy(range->data, pkt->data, pkt_len); 1537 1538 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1539 } 1540 1541 static void * 1542 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1543 struct iwl_dump_ini_region_data *reg_data, 1544 void *data) 1545 { 1546 struct iwl_fw_ini_error_dump *dump = data; 1547 1548 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1549 1550 return dump->ranges; 1551 } 1552 1553 /** 1554 * mask_apply_and_normalize - applies mask on val and normalize the result 1555 * 1556 * The normalization is based on the first set bit in the mask 1557 * 1558 * @val: value 1559 * @mask: mask to apply and to normalize with 1560 */ 1561 static u32 mask_apply_and_normalize(u32 val, u32 mask) 1562 { 1563 return (val & mask) >> (ffs(mask) - 1); 1564 } 1565 1566 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1567 const struct iwl_fw_mon_reg *reg_info) 1568 { 1569 u32 val, offs; 1570 1571 /* The header addresses of DBGCi is calculate as follows: 1572 * DBGC1 address + (0x100 * i) 1573 */ 1574 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100; 1575 1576 if (!reg_info || !reg_info->addr || !reg_info->mask) 1577 return 0; 1578 1579 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs); 1580 1581 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask)); 1582 } 1583 1584 static void * 1585 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, 1586 struct iwl_dump_ini_region_data *reg_data, 1587 struct iwl_fw_ini_monitor_dump *data, 1588 const struct iwl_fw_mon_regs *addrs) 1589 { 1590 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1591 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1592 1593 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 1594 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1595 return NULL; 1596 } 1597 1598 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id, 1599 &addrs->write_ptr); 1600 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1601 u32 wrt_ptr = le32_to_cpu(data->write_ptr); 1602 1603 data->write_ptr = cpu_to_le32(wrt_ptr >> 2); 1604 } 1605 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id, 1606 &addrs->cycle_cnt); 1607 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id, 1608 &addrs->cur_frag); 1609 1610 iwl_trans_release_nic_access(fwrt->trans); 1611 1612 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1613 1614 return data->ranges; 1615 } 1616 1617 static void * 1618 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1619 struct iwl_dump_ini_region_data *reg_data, 1620 void *data) 1621 { 1622 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1623 1624 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump, 1625 &fwrt->trans->cfg->mon_dram_regs); 1626 } 1627 1628 static void * 1629 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1630 struct iwl_dump_ini_region_data *reg_data, 1631 void *data) 1632 { 1633 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1634 1635 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump, 1636 &fwrt->trans->cfg->mon_smem_regs); 1637 } 1638 1639 static void * 1640 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt, 1641 struct iwl_dump_ini_region_data *reg_data, 1642 void *data) 1643 { 1644 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1645 struct iwl_fw_ini_err_table_dump *dump = data; 1646 1647 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1648 dump->version = reg->err_table.version; 1649 1650 return dump->ranges; 1651 } 1652 1653 static void * 1654 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt, 1655 struct iwl_dump_ini_region_data *reg_data, 1656 void *data) 1657 { 1658 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1659 struct iwl_fw_ini_special_device_memory *dump = data; 1660 1661 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1662 dump->type = reg->special_mem.type; 1663 dump->version = reg->special_mem.version; 1664 1665 return dump->ranges; 1666 } 1667 1668 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1669 struct iwl_dump_ini_region_data *reg_data) 1670 { 1671 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1672 1673 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1674 } 1675 1676 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1677 struct iwl_dump_ini_region_data *reg_data) 1678 { 1679 if (fwrt->trans->trans_cfg->gen2) { 1680 if (fwrt->trans->init_dram.paging_cnt) 1681 return fwrt->trans->init_dram.paging_cnt - 1; 1682 else 1683 return 0; 1684 } 1685 1686 return fwrt->num_of_paging_blk; 1687 } 1688 1689 static u32 1690 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1691 struct iwl_dump_ini_region_data *reg_data) 1692 { 1693 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1694 struct iwl_fw_mon *fw_mon; 1695 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1696 int i; 1697 1698 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1699 1700 for (i = 0; i < fw_mon->num_frags; i++) { 1701 if (!fw_mon->frags[i].size) 1702 break; 1703 1704 ranges++; 1705 } 1706 1707 return ranges; 1708 } 1709 1710 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1711 struct iwl_dump_ini_region_data *reg_data) 1712 { 1713 u32 num_of_fifos = 0; 1714 1715 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos)) 1716 num_of_fifos++; 1717 1718 return num_of_fifos; 1719 } 1720 1721 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt, 1722 struct iwl_dump_ini_region_data *reg_data) 1723 { 1724 return 1; 1725 } 1726 1727 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1728 struct iwl_dump_ini_region_data *reg_data) 1729 { 1730 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1731 u32 size = le32_to_cpu(reg->dev_addr.size); 1732 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1733 1734 if (!size || !ranges) 1735 return 0; 1736 1737 return sizeof(struct iwl_fw_ini_error_dump) + ranges * 1738 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1739 } 1740 1741 static u32 1742 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1743 struct iwl_dump_ini_region_data *reg_data) 1744 { 1745 int i; 1746 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1747 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1748 1749 /* start from 1 to skip CSS section */ 1750 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) { 1751 size += range_header_len; 1752 if (fwrt->trans->trans_cfg->gen2) 1753 size += fwrt->trans->init_dram.paging[i].size; 1754 else 1755 size += fwrt->fw_paging_db[i].fw_paging_size; 1756 } 1757 1758 return size; 1759 } 1760 1761 static u32 1762 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 1763 struct iwl_dump_ini_region_data *reg_data) 1764 { 1765 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1766 struct iwl_fw_mon *fw_mon; 1767 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1768 int i; 1769 1770 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1771 1772 for (i = 0; i < fw_mon->num_frags; i++) { 1773 struct iwl_dram_data *frag = &fw_mon->frags[i]; 1774 1775 if (!frag->size) 1776 break; 1777 1778 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size; 1779 } 1780 1781 if (size) 1782 size += sizeof(struct iwl_fw_ini_monitor_dump); 1783 1784 return size; 1785 } 1786 1787 static u32 1788 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 1789 struct iwl_dump_ini_region_data *reg_data) 1790 { 1791 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1792 u32 size; 1793 1794 size = le32_to_cpu(reg->internal_buffer.size); 1795 if (!size) 1796 return 0; 1797 1798 size += sizeof(struct iwl_fw_ini_monitor_dump) + 1799 sizeof(struct iwl_fw_ini_error_dump_range); 1800 1801 return size; 1802 } 1803 1804 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 1805 struct iwl_dump_ini_region_data *reg_data) 1806 { 1807 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1808 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1809 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1810 u32 size = 0; 1811 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 1812 registers_num * 1813 sizeof(struct iwl_fw_ini_error_dump_register); 1814 1815 while (iwl_ini_txf_iter(fwrt, reg_data, size)) { 1816 size += fifo_hdr; 1817 if (!reg->fifos.hdr_only) 1818 size += iter->fifo_size; 1819 } 1820 1821 if (!size) 1822 return 0; 1823 1824 return size + sizeof(struct iwl_fw_ini_error_dump); 1825 } 1826 1827 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 1828 struct iwl_dump_ini_region_data *reg_data) 1829 { 1830 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1831 struct iwl_ini_rxf_data rx_data; 1832 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1833 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 1834 sizeof(struct iwl_fw_ini_error_dump_range) + 1835 registers_num * sizeof(struct iwl_fw_ini_error_dump_register); 1836 1837 if (reg->fifos.hdr_only) 1838 return size; 1839 1840 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data); 1841 size += rx_data.size; 1842 1843 return size; 1844 } 1845 1846 static u32 1847 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt, 1848 struct iwl_dump_ini_region_data *reg_data) 1849 { 1850 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1851 u32 size = le32_to_cpu(reg->err_table.size); 1852 1853 if (size) 1854 size += sizeof(struct iwl_fw_ini_err_table_dump) + 1855 sizeof(struct iwl_fw_ini_error_dump_range); 1856 1857 return size; 1858 } 1859 1860 static u32 1861 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt, 1862 struct iwl_dump_ini_region_data *reg_data) 1863 { 1864 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1865 u32 size = le32_to_cpu(reg->special_mem.size); 1866 1867 if (size) 1868 size += sizeof(struct iwl_fw_ini_special_device_memory) + 1869 sizeof(struct iwl_fw_ini_error_dump_range); 1870 1871 return size; 1872 } 1873 1874 static u32 1875 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt, 1876 struct iwl_dump_ini_region_data *reg_data) 1877 { 1878 u32 size = 0; 1879 1880 if (!reg_data->dump_data->fw_pkt) 1881 return 0; 1882 1883 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt); 1884 if (size) 1885 size += sizeof(struct iwl_fw_ini_error_dump) + 1886 sizeof(struct iwl_fw_ini_error_dump_range); 1887 1888 return size; 1889 } 1890 1891 /** 1892 * struct iwl_dump_ini_mem_ops - ini memory dump operations 1893 * @get_num_of_ranges: returns the number of memory ranges in the region. 1894 * @get_size: returns the total size of the region. 1895 * @fill_mem_hdr: fills region type specific headers and returns pointer to 1896 * the first range or NULL if failed to fill headers. 1897 * @fill_range: copies a given memory range into the dump. 1898 * Returns the size of the range or negative error value otherwise. 1899 */ 1900 struct iwl_dump_ini_mem_ops { 1901 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 1902 struct iwl_dump_ini_region_data *reg_data); 1903 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 1904 struct iwl_dump_ini_region_data *reg_data); 1905 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 1906 struct iwl_dump_ini_region_data *reg_data, 1907 void *data); 1908 int (*fill_range)(struct iwl_fw_runtime *fwrt, 1909 struct iwl_dump_ini_region_data *reg_data, 1910 void *range, int idx); 1911 }; 1912 1913 /** 1914 * iwl_dump_ini_mem 1915 * 1916 * Creates a dump tlv and copy a memory region into it. 1917 * Returns the size of the current dump tlv or 0 if failed 1918 * 1919 * @fwrt: fw runtime struct 1920 * @list: list to add the dump tlv to 1921 * @reg_data: memory region 1922 * @ops: memory dump operations 1923 */ 1924 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 1925 struct iwl_dump_ini_region_data *reg_data, 1926 const struct iwl_dump_ini_mem_ops *ops) 1927 { 1928 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1929 struct iwl_fw_ini_dump_entry *entry; 1930 struct iwl_fw_error_dump_data *tlv; 1931 struct iwl_fw_ini_error_dump_header *header; 1932 u32 type = le32_to_cpu(reg->type), id = le32_to_cpu(reg->id); 1933 u32 num_of_ranges, i, size; 1934 void *range; 1935 1936 /* 1937 * The higher part of the ID in version 2 is irrelevant for 1938 * us, so mask it out. 1939 */ 1940 if (le32_to_cpu(reg->hdr.version) == 2) 1941 id &= IWL_FW_INI_REGION_V2_MASK; 1942 1943 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 1944 !ops->fill_range) 1945 return 0; 1946 1947 size = ops->get_size(fwrt, reg_data); 1948 if (!size) 1949 return 0; 1950 1951 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size); 1952 if (!entry) 1953 return 0; 1954 1955 entry->size = sizeof(*tlv) + size; 1956 1957 tlv = (void *)entry->data; 1958 tlv->type = reg->type; 1959 tlv->len = cpu_to_le32(size); 1960 1961 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: id=%d, type=%d\n", id, 1962 type); 1963 1964 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data); 1965 1966 header = (void *)tlv->data; 1967 header->region_id = cpu_to_le32(id); 1968 header->num_of_ranges = cpu_to_le32(num_of_ranges); 1969 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME); 1970 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME); 1971 1972 range = ops->fill_mem_hdr(fwrt, reg_data, header); 1973 if (!range) { 1974 IWL_ERR(fwrt, 1975 "WRT: Failed to fill region header: id=%d, type=%d\n", 1976 id, type); 1977 goto out_err; 1978 } 1979 1980 for (i = 0; i < num_of_ranges; i++) { 1981 int range_size = ops->fill_range(fwrt, reg_data, range, i); 1982 1983 if (range_size < 0) { 1984 IWL_ERR(fwrt, 1985 "WRT: Failed to dump region: id=%d, type=%d\n", 1986 id, type); 1987 goto out_err; 1988 } 1989 range = range + range_size; 1990 } 1991 1992 list_add_tail(&entry->list, list); 1993 1994 return entry->size; 1995 1996 out_err: 1997 vfree(entry); 1998 1999 return 0; 2000 } 2001 2002 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 2003 struct iwl_fw_ini_trigger_tlv *trigger, 2004 struct list_head *list) 2005 { 2006 struct iwl_fw_ini_dump_entry *entry; 2007 struct iwl_fw_error_dump_data *tlv; 2008 struct iwl_fw_ini_dump_info *dump; 2009 struct iwl_dbg_tlv_node *node; 2010 struct iwl_fw_ini_dump_cfg_name *cfg_name; 2011 u32 size = sizeof(*tlv) + sizeof(*dump); 2012 u32 num_of_cfg_names = 0; 2013 u32 hw_type; 2014 2015 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2016 size += sizeof(*cfg_name); 2017 num_of_cfg_names++; 2018 } 2019 2020 entry = vzalloc(sizeof(*entry) + size); 2021 if (!entry) 2022 return 0; 2023 2024 entry->size = size; 2025 2026 tlv = (void *)entry->data; 2027 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 2028 tlv->len = cpu_to_le32(size - sizeof(*tlv)); 2029 2030 dump = (void *)tlv->data; 2031 2032 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 2033 dump->time_point = trigger->time_point; 2034 dump->trigger_reason = trigger->trigger_reason; 2035 dump->external_cfg_state = 2036 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 2037 2038 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 2039 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 2040 2041 dump->hw_step = cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 2042 2043 /* 2044 * Several HWs all have type == 0x42, so we'll override this value 2045 * according to the detected HW 2046 */ 2047 hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev); 2048 if (hw_type == IWL_AX210_HW_TYPE) { 2049 u32 prph_val = iwl_read_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR); 2050 u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT); 2051 u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT); 2052 u32 masked_bits = is_jacket | (is_cdb << 1); 2053 2054 /* 2055 * The HW type depends on certain bits in this case, so add 2056 * these bits to the HW type. We won't have collisions since we 2057 * add these bits after the highest possible bit in the mask. 2058 */ 2059 hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT; 2060 } 2061 dump->hw_type = cpu_to_le32(hw_type); 2062 2063 dump->rf_id_flavor = 2064 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id)); 2065 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id)); 2066 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id)); 2067 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id)); 2068 2069 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 2070 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 2071 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 2072 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 2073 2074 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest); 2075 dump->regions_mask = trigger->regions_mask & 2076 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk); 2077 2078 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 2079 memcpy(dump->build_tag, fwrt->fw->human_readable, 2080 sizeof(dump->build_tag)); 2081 2082 cfg_name = dump->cfg_names; 2083 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names); 2084 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2085 struct iwl_fw_ini_debug_info_tlv *debug_info = 2086 (void *)node->tlv.data; 2087 2088 cfg_name->image_type = debug_info->image_type; 2089 cfg_name->cfg_name_len = 2090 cpu_to_le32(IWL_FW_INI_MAX_CFG_NAME); 2091 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name, 2092 sizeof(cfg_name->cfg_name)); 2093 cfg_name++; 2094 } 2095 2096 /* add dump info TLV to the beginning of the list since it needs to be 2097 * the first TLV in the dump 2098 */ 2099 list_add(&entry->list, list); 2100 2101 return entry->size; 2102 } 2103 2104 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 2105 [IWL_FW_INI_REGION_INVALID] = {}, 2106 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 2107 .get_num_of_ranges = iwl_dump_ini_single_range, 2108 .get_size = iwl_dump_ini_mon_smem_get_size, 2109 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 2110 .fill_range = iwl_dump_ini_mon_smem_iter, 2111 }, 2112 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 2113 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 2114 .get_size = iwl_dump_ini_mon_dram_get_size, 2115 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 2116 .fill_range = iwl_dump_ini_mon_dram_iter, 2117 }, 2118 [IWL_FW_INI_REGION_TXF] = { 2119 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 2120 .get_size = iwl_dump_ini_txf_get_size, 2121 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2122 .fill_range = iwl_dump_ini_txf_iter, 2123 }, 2124 [IWL_FW_INI_REGION_RXF] = { 2125 .get_num_of_ranges = iwl_dump_ini_single_range, 2126 .get_size = iwl_dump_ini_rxf_get_size, 2127 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2128 .fill_range = iwl_dump_ini_rxf_iter, 2129 }, 2130 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 2131 .get_num_of_ranges = iwl_dump_ini_single_range, 2132 .get_size = iwl_dump_ini_err_table_get_size, 2133 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2134 .fill_range = iwl_dump_ini_err_table_iter, 2135 }, 2136 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 2137 .get_num_of_ranges = iwl_dump_ini_single_range, 2138 .get_size = iwl_dump_ini_err_table_get_size, 2139 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2140 .fill_range = iwl_dump_ini_err_table_iter, 2141 }, 2142 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = { 2143 .get_num_of_ranges = iwl_dump_ini_single_range, 2144 .get_size = iwl_dump_ini_fw_pkt_get_size, 2145 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2146 .fill_range = iwl_dump_ini_fw_pkt_iter, 2147 }, 2148 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 2149 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2150 .get_size = iwl_dump_ini_mem_get_size, 2151 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2152 .fill_range = iwl_dump_ini_dev_mem_iter, 2153 }, 2154 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 2155 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2156 .get_size = iwl_dump_ini_mem_get_size, 2157 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2158 .fill_range = iwl_dump_ini_prph_mac_iter, 2159 }, 2160 [IWL_FW_INI_REGION_PERIPHERY_PHY] = { 2161 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2162 .get_size = iwl_dump_ini_mem_get_size, 2163 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2164 .fill_range = iwl_dump_ini_prph_phy_iter, 2165 }, 2166 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 2167 [IWL_FW_INI_REGION_PAGING] = { 2168 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2169 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 2170 .get_size = iwl_dump_ini_paging_get_size, 2171 .fill_range = iwl_dump_ini_paging_iter, 2172 }, 2173 [IWL_FW_INI_REGION_CSR] = { 2174 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2175 .get_size = iwl_dump_ini_mem_get_size, 2176 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2177 .fill_range = iwl_dump_ini_csr_iter, 2178 }, 2179 [IWL_FW_INI_REGION_DRAM_IMR] = {}, 2180 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = { 2181 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2182 .get_size = iwl_dump_ini_mem_get_size, 2183 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2184 .fill_range = iwl_dump_ini_config_iter, 2185 }, 2186 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = { 2187 .get_num_of_ranges = iwl_dump_ini_single_range, 2188 .get_size = iwl_dump_ini_special_mem_get_size, 2189 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header, 2190 .fill_range = iwl_dump_ini_special_mem_iter, 2191 }, 2192 }; 2193 2194 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 2195 struct iwl_fwrt_dump_data *dump_data, 2196 struct list_head *list) 2197 { 2198 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2199 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point); 2200 struct iwl_dump_ini_region_data reg_data = { 2201 .dump_data = dump_data, 2202 }; 2203 int i; 2204 u32 size = 0; 2205 u64 regions_mask = le64_to_cpu(trigger->regions_mask) & 2206 ~(fwrt->trans->dbg.unsupported_region_msk); 2207 2208 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask)); 2209 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) < 2210 ARRAY_SIZE(fwrt->trans->dbg.active_regions)); 2211 2212 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) { 2213 u32 reg_type; 2214 struct iwl_fw_ini_region_tlv *reg; 2215 2216 if (!(BIT_ULL(i) & regions_mask)) 2217 continue; 2218 2219 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2220 if (!reg_data.reg_tlv) { 2221 IWL_WARN(fwrt, 2222 "WRT: Unassigned region id %d, skipping\n", i); 2223 continue; 2224 } 2225 2226 reg = (void *)reg_data.reg_tlv->data; 2227 reg_type = le32_to_cpu(reg->type); 2228 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 2229 continue; 2230 2231 if (reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY && 2232 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) { 2233 IWL_WARN(fwrt, 2234 "WRT: trying to collect phy prph at time point: %d, skipping\n", 2235 tp_id); 2236 continue; 2237 } 2238 2239 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2240 &iwl_dump_ini_region_ops[reg_type]); 2241 } 2242 2243 if (size) 2244 size += iwl_dump_ini_info(fwrt, trigger, list); 2245 2246 return size; 2247 } 2248 2249 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt, 2250 struct iwl_fw_ini_trigger_tlv *trig) 2251 { 2252 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2253 u32 usec = le32_to_cpu(trig->ignore_consec); 2254 2255 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 2256 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 2257 tp_id >= IWL_FW_INI_TIME_POINT_NUM || 2258 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec)) 2259 return false; 2260 2261 return true; 2262 } 2263 2264 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 2265 struct iwl_fwrt_dump_data *dump_data, 2266 struct list_head *list) 2267 { 2268 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2269 struct iwl_fw_ini_dump_entry *entry; 2270 struct iwl_fw_ini_dump_file_hdr *hdr; 2271 u32 size; 2272 2273 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) || 2274 !le64_to_cpu(trigger->regions_mask)) 2275 return 0; 2276 2277 entry = vzalloc(sizeof(*entry) + sizeof(*hdr)); 2278 if (!entry) 2279 return 0; 2280 2281 entry->size = sizeof(*hdr); 2282 2283 size = iwl_dump_ini_trigger(fwrt, dump_data, list); 2284 if (!size) { 2285 vfree(entry); 2286 return 0; 2287 } 2288 2289 hdr = (void *)entry->data; 2290 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 2291 hdr->file_len = cpu_to_le32(size + entry->size); 2292 2293 list_add(&entry->list, list); 2294 2295 return le32_to_cpu(hdr->file_len); 2296 } 2297 2298 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt, 2299 const struct iwl_fw_dump_desc *desc) 2300 { 2301 if (desc && desc != &iwl_dump_desc_assert) 2302 kfree(desc); 2303 2304 fwrt->dump.lmac_err_id[0] = 0; 2305 if (fwrt->smem_cfg.num_lmacs > 1) 2306 fwrt->dump.lmac_err_id[1] = 0; 2307 fwrt->dump.umac_err_id = 0; 2308 } 2309 2310 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt, 2311 struct iwl_fwrt_dump_data *dump_data) 2312 { 2313 struct iwl_fw_dump_ptrs fw_error_dump = {}; 2314 struct iwl_fw_error_dump_file *dump_file; 2315 struct scatterlist *sg_dump_data; 2316 u32 file_len; 2317 u32 dump_mask = fwrt->fw->dbg.dump_mask; 2318 2319 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data); 2320 if (!dump_file) 2321 return; 2322 2323 if (dump_data->monitor_only) 2324 dump_mask &= IWL_FW_ERROR_DUMP_FW_MONITOR; 2325 2326 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask); 2327 file_len = le32_to_cpu(dump_file->file_len); 2328 fw_error_dump.fwrt_len = file_len; 2329 2330 if (fw_error_dump.trans_ptr) { 2331 file_len += fw_error_dump.trans_ptr->len; 2332 dump_file->file_len = cpu_to_le32(file_len); 2333 } 2334 2335 sg_dump_data = alloc_sgtable(file_len); 2336 if (sg_dump_data) { 2337 sg_pcopy_from_buffer(sg_dump_data, 2338 sg_nents(sg_dump_data), 2339 fw_error_dump.fwrt_ptr, 2340 fw_error_dump.fwrt_len, 0); 2341 if (fw_error_dump.trans_ptr) 2342 sg_pcopy_from_buffer(sg_dump_data, 2343 sg_nents(sg_dump_data), 2344 fw_error_dump.trans_ptr->data, 2345 fw_error_dump.trans_ptr->len, 2346 fw_error_dump.fwrt_len); 2347 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2348 GFP_KERNEL); 2349 } 2350 vfree(fw_error_dump.fwrt_ptr); 2351 vfree(fw_error_dump.trans_ptr); 2352 } 2353 2354 static void iwl_dump_ini_list_free(struct list_head *list) 2355 { 2356 while (!list_empty(list)) { 2357 struct iwl_fw_ini_dump_entry *entry = 2358 list_entry(list->next, typeof(*entry), list); 2359 2360 list_del(&entry->list); 2361 vfree(entry); 2362 } 2363 } 2364 2365 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data) 2366 { 2367 dump_data->trig = NULL; 2368 kfree(dump_data->fw_pkt); 2369 dump_data->fw_pkt = NULL; 2370 } 2371 2372 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, 2373 struct iwl_fwrt_dump_data *dump_data) 2374 { 2375 struct list_head dump_list = LIST_HEAD_INIT(dump_list); 2376 struct scatterlist *sg_dump_data; 2377 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list); 2378 2379 if (!file_len) 2380 return; 2381 2382 sg_dump_data = alloc_sgtable(file_len); 2383 if (sg_dump_data) { 2384 struct iwl_fw_ini_dump_entry *entry; 2385 int sg_entries = sg_nents(sg_dump_data); 2386 u32 offs = 0; 2387 2388 list_for_each_entry(entry, &dump_list, list) { 2389 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2390 entry->data, entry->size, offs); 2391 offs += entry->size; 2392 } 2393 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2394 GFP_KERNEL); 2395 } 2396 iwl_dump_ini_list_free(&dump_list); 2397 } 2398 2399 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2400 .trig_desc = { 2401 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2402 }, 2403 }; 2404 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2405 2406 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2407 const struct iwl_fw_dump_desc *desc, 2408 bool monitor_only, 2409 unsigned int delay) 2410 { 2411 struct iwl_fwrt_wk_data *wk_data; 2412 unsigned long idx; 2413 2414 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2415 iwl_fw_free_dump_desc(fwrt, desc); 2416 return 0; 2417 } 2418 2419 /* 2420 * Check there is an available worker. 2421 * ffz return value is undefined if no zero exists, 2422 * so check against ~0UL first. 2423 */ 2424 if (fwrt->dump.active_wks == ~0UL) 2425 return -EBUSY; 2426 2427 idx = ffz(fwrt->dump.active_wks); 2428 2429 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2430 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2431 return -EBUSY; 2432 2433 wk_data = &fwrt->dump.wks[idx]; 2434 2435 if (WARN_ON(wk_data->dump_data.desc)) 2436 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc); 2437 2438 wk_data->dump_data.desc = desc; 2439 wk_data->dump_data.monitor_only = monitor_only; 2440 2441 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2442 le32_to_cpu(desc->trig_desc.type)); 2443 2444 schedule_delayed_work(&wk_data->wk, usecs_to_jiffies(delay)); 2445 2446 return 0; 2447 } 2448 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2449 2450 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2451 enum iwl_fw_dbg_trigger trig_type) 2452 { 2453 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2454 return -EIO; 2455 2456 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2457 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT && 2458 trig_type != FW_DBG_TRIGGER_DRIVER) 2459 return -EIO; 2460 2461 iwl_dbg_tlv_time_point(fwrt, 2462 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT, 2463 NULL); 2464 } else { 2465 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2466 int ret; 2467 2468 iwl_dump_error_desc = 2469 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2470 2471 if (!iwl_dump_error_desc) 2472 return -ENOMEM; 2473 2474 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2475 iwl_dump_error_desc->len = 0; 2476 2477 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, 2478 false, 0); 2479 if (ret) { 2480 kfree(iwl_dump_error_desc); 2481 return ret; 2482 } 2483 } 2484 2485 iwl_trans_sync_nmi(fwrt->trans); 2486 2487 return 0; 2488 } 2489 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2490 2491 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2492 enum iwl_fw_dbg_trigger trig, 2493 const char *str, size_t len, 2494 struct iwl_fw_dbg_trigger_tlv *trigger) 2495 { 2496 struct iwl_fw_dump_desc *desc; 2497 unsigned int delay = 0; 2498 bool monitor_only = false; 2499 2500 if (trigger) { 2501 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2502 2503 if (!le16_to_cpu(trigger->occurrences)) 2504 return 0; 2505 2506 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2507 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2508 trig); 2509 iwl_force_nmi(fwrt->trans); 2510 return 0; 2511 } 2512 2513 trigger->occurrences = cpu_to_le16(occurrences); 2514 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2515 2516 /* convert msec to usec */ 2517 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2518 } 2519 2520 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 2521 if (!desc) 2522 return -ENOMEM; 2523 2524 2525 desc->len = len; 2526 desc->trig_desc.type = cpu_to_le32(trig); 2527 memcpy(desc->trig_desc.data, str, len); 2528 2529 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2530 } 2531 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2532 2533 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 2534 struct iwl_fwrt_dump_data *dump_data) 2535 { 2536 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig; 2537 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2538 u32 occur, delay; 2539 unsigned long idx; 2540 2541 if (!iwl_fw_ini_trigger_on(fwrt, trig)) { 2542 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 2543 tp_id); 2544 return -EINVAL; 2545 } 2546 2547 delay = le32_to_cpu(trig->dump_delay); 2548 occur = le32_to_cpu(trig->occurrences); 2549 if (!occur) 2550 return 0; 2551 2552 trig->occurrences = cpu_to_le32(--occur); 2553 2554 /* Check there is an available worker. 2555 * ffz return value is undefined if no zero exists, 2556 * so check against ~0UL first. 2557 */ 2558 if (fwrt->dump.active_wks == ~0UL) 2559 return -EBUSY; 2560 2561 idx = ffz(fwrt->dump.active_wks); 2562 2563 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2564 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2565 return -EBUSY; 2566 2567 fwrt->dump.wks[idx].dump_data = *dump_data; 2568 2569 IWL_WARN(fwrt, 2570 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n", 2571 tp_id, (u32)(delay / USEC_PER_MSEC)); 2572 2573 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay)); 2574 2575 return 0; 2576 } 2577 2578 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2579 struct iwl_fw_dbg_trigger_tlv *trigger, 2580 const char *fmt, ...) 2581 { 2582 int ret, len = 0; 2583 char buf[64]; 2584 2585 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2586 return 0; 2587 2588 if (fmt) { 2589 va_list ap; 2590 2591 buf[sizeof(buf) - 1] = '\0'; 2592 2593 va_start(ap, fmt); 2594 vsnprintf(buf, sizeof(buf), fmt, ap); 2595 va_end(ap); 2596 2597 /* check for truncation */ 2598 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2599 buf[sizeof(buf) - 1] = '\0'; 2600 2601 len = strlen(buf) + 1; 2602 } 2603 2604 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2605 trigger); 2606 2607 if (ret) 2608 return ret; 2609 2610 return 0; 2611 } 2612 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2613 2614 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2615 { 2616 u8 *ptr; 2617 int ret; 2618 int i; 2619 2620 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 2621 "Invalid configuration %d\n", conf_id)) 2622 return -EINVAL; 2623 2624 /* EARLY START - firmware's configuration is hard coded */ 2625 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 2626 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 2627 conf_id == FW_DBG_START_FROM_ALIVE) 2628 return 0; 2629 2630 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 2631 return -EINVAL; 2632 2633 if (fwrt->dump.conf != FW_DBG_INVALID) 2634 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n", 2635 fwrt->dump.conf); 2636 2637 /* Send all HCMDs for configuring the FW debug */ 2638 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 2639 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 2640 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 2641 struct iwl_host_cmd hcmd = { 2642 .id = cmd->id, 2643 .len = { le16_to_cpu(cmd->len), }, 2644 .data = { cmd->data, }, 2645 }; 2646 2647 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 2648 if (ret) 2649 return ret; 2650 2651 ptr += sizeof(*cmd); 2652 ptr += le16_to_cpu(cmd->len); 2653 } 2654 2655 fwrt->dump.conf = conf_id; 2656 2657 return 0; 2658 } 2659 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 2660 2661 /* this function assumes dump_start was called beforehand and dump_end will be 2662 * called afterwards 2663 */ 2664 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 2665 { 2666 struct iwl_fw_dbg_params params = {0}; 2667 struct iwl_fwrt_dump_data *dump_data = 2668 &fwrt->dump.wks[wk_idx].dump_data; 2669 2670 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 2671 return; 2672 2673 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) { 2674 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n"); 2675 goto out; 2676 } 2677 2678 /* there's no point in fw dump if the bus is dead */ 2679 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 2680 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 2681 goto out; 2682 } 2683 2684 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true); 2685 2686 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 2687 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2688 iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 2689 else 2690 iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 2691 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 2692 2693 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 2694 2695 out: 2696 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2697 iwl_fw_error_dump_data_free(dump_data); 2698 } else { 2699 iwl_fw_free_dump_desc(fwrt, dump_data->desc); 2700 dump_data->desc = NULL; 2701 } 2702 2703 clear_bit(wk_idx, &fwrt->dump.active_wks); 2704 } 2705 2706 void iwl_fw_error_dump_wk(struct work_struct *work) 2707 { 2708 struct iwl_fwrt_wk_data *wks = 2709 container_of(work, typeof(*wks), wk.work); 2710 struct iwl_fw_runtime *fwrt = 2711 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]); 2712 2713 /* assumes the op mode mutex is locked in dump_start since 2714 * iwl_fw_dbg_collect_sync can't run in parallel 2715 */ 2716 if (fwrt->ops && fwrt->ops->dump_start && 2717 fwrt->ops->dump_start(fwrt->ops_ctx)) 2718 return; 2719 2720 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 2721 2722 if (fwrt->ops && fwrt->ops->dump_end) 2723 fwrt->ops->dump_end(fwrt->ops_ctx); 2724 } 2725 2726 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 2727 { 2728 const struct iwl_cfg *cfg = fwrt->trans->cfg; 2729 2730 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 2731 return; 2732 2733 if (!fwrt->dump.d3_debug_data) { 2734 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 2735 GFP_KERNEL); 2736 if (!fwrt->dump.d3_debug_data) { 2737 IWL_ERR(fwrt, 2738 "failed to allocate memory for D3 debug data\n"); 2739 return; 2740 } 2741 } 2742 2743 /* if the buffer holds previous debug data it is overwritten */ 2744 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 2745 fwrt->dump.d3_debug_data, 2746 cfg->d3_debug_data_length); 2747 } 2748 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 2749 2750 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 2751 { 2752 int i; 2753 2754 iwl_dbg_tlv_del_timers(fwrt->trans); 2755 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 2756 iwl_fw_dbg_collect_sync(fwrt, i); 2757 2758 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 2759 } 2760 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 2761 2762 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 2763 { 2764 struct iwl_dbg_suspend_resume_cmd cmd = { 2765 .operation = suspend ? 2766 cpu_to_le32(DBGC_SUSPEND_CMD) : 2767 cpu_to_le32(DBGC_RESUME_CMD), 2768 }; 2769 struct iwl_host_cmd hcmd = { 2770 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 2771 .data[0] = &cmd, 2772 .len[0] = sizeof(cmd), 2773 }; 2774 2775 return iwl_trans_send_cmd(trans, &hcmd); 2776 } 2777 2778 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 2779 struct iwl_fw_dbg_params *params) 2780 { 2781 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 2782 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 2783 return; 2784 } 2785 2786 if (params) { 2787 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 2788 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 2789 } 2790 2791 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 2792 /* wait for the DBGC to finish writing the internal buffer to DRAM to 2793 * avoid halting the HW while writing 2794 */ 2795 usleep_range(700, 1000); 2796 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 2797 } 2798 2799 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 2800 struct iwl_fw_dbg_params *params) 2801 { 2802 if (!params) 2803 return -EIO; 2804 2805 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 2806 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 2807 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 2808 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 2809 } else { 2810 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 2811 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 2812 } 2813 2814 return 0; 2815 } 2816 2817 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 2818 struct iwl_fw_dbg_params *params, 2819 bool stop) 2820 { 2821 int ret __maybe_unused = 0; 2822 2823 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 2824 return; 2825 2826 if (fw_has_capa(&fwrt->fw->ucode_capa, 2827 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) 2828 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 2829 else if (stop) 2830 iwl_fw_dbg_stop_recording(fwrt->trans, params); 2831 else 2832 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 2833 #ifdef CONFIG_IWLWIFI_DEBUGFS 2834 if (!ret) { 2835 if (stop) 2836 fwrt->trans->dbg.rec_on = false; 2837 else 2838 iwl_fw_set_dbg_rec_on(fwrt); 2839 } 2840 #endif 2841 } 2842 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 2843