1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #include <linux/devcoredump.h> 65 #include "iwl-drv.h" 66 #include "runtime.h" 67 #include "dbg.h" 68 #include "debugfs.h" 69 #include "iwl-io.h" 70 #include "iwl-prph.h" 71 #include "iwl-csr.h" 72 73 /** 74 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 75 * 76 * @fwrt_ptr: pointer to the buffer coming from fwrt 77 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 78 * transport's data. 79 * @trans_len: length of the valid data in trans_ptr 80 * @fwrt_len: length of the valid data in fwrt_ptr 81 */ 82 struct iwl_fw_dump_ptrs { 83 struct iwl_trans_dump_data *trans_ptr; 84 void *fwrt_ptr; 85 u32 fwrt_len; 86 }; 87 88 #define RADIO_REG_MAX_READ 0x2ad 89 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 90 struct iwl_fw_error_dump_data **dump_data) 91 { 92 u8 *pos = (void *)(*dump_data)->data; 93 unsigned long flags; 94 int i; 95 96 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 97 98 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 99 return; 100 101 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 102 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 103 104 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 105 u32 rd_cmd = RADIO_RSP_RD_CMD; 106 107 rd_cmd |= i << RADIO_RSP_ADDR_POS; 108 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 109 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 110 111 pos++; 112 } 113 114 *dump_data = iwl_fw_error_next_data(*dump_data); 115 116 iwl_trans_release_nic_access(fwrt->trans, &flags); 117 } 118 119 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 120 struct iwl_fw_error_dump_data **dump_data, 121 int size, u32 offset, int fifo_num) 122 { 123 struct iwl_fw_error_dump_fifo *fifo_hdr; 124 u32 *fifo_data; 125 u32 fifo_len; 126 int i; 127 128 fifo_hdr = (void *)(*dump_data)->data; 129 fifo_data = (void *)fifo_hdr->data; 130 fifo_len = size; 131 132 /* No need to try to read the data if the length is 0 */ 133 if (fifo_len == 0) 134 return; 135 136 /* Add a TLV for the RXF */ 137 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 138 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 139 140 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 141 fifo_hdr->available_bytes = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 RXF_RD_D_SPACE + offset)); 144 fifo_hdr->wr_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 RXF_RD_WR_PTR + offset)); 147 fifo_hdr->rd_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 RXF_RD_RD_PTR + offset)); 150 fifo_hdr->fence_ptr = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 RXF_RD_FENCE_PTR + offset)); 153 fifo_hdr->fence_mode = 154 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 155 RXF_SET_FENCE_MODE + offset)); 156 157 /* Lock fence */ 158 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 159 /* Set fence pointer to the same place like WR pointer */ 160 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 161 /* Set fence offset */ 162 iwl_trans_write_prph(fwrt->trans, 163 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 164 165 /* Read FIFO */ 166 fifo_len /= sizeof(u32); /* Size in DWORDS */ 167 for (i = 0; i < fifo_len; i++) 168 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 169 RXF_FIFO_RD_FENCE_INC + 170 offset); 171 *dump_data = iwl_fw_error_next_data(*dump_data); 172 } 173 174 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 175 struct iwl_fw_error_dump_data **dump_data, 176 int size, u32 offset, int fifo_num) 177 { 178 struct iwl_fw_error_dump_fifo *fifo_hdr; 179 u32 *fifo_data; 180 u32 fifo_len; 181 int i; 182 183 fifo_hdr = (void *)(*dump_data)->data; 184 fifo_data = (void *)fifo_hdr->data; 185 fifo_len = size; 186 187 /* No need to try to read the data if the length is 0 */ 188 if (fifo_len == 0) 189 return; 190 191 /* Add a TLV for the FIFO */ 192 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 193 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 194 195 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 196 fifo_hdr->available_bytes = 197 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 198 TXF_FIFO_ITEM_CNT + offset)); 199 fifo_hdr->wr_ptr = 200 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 201 TXF_WR_PTR + offset)); 202 fifo_hdr->rd_ptr = 203 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 204 TXF_RD_PTR + offset)); 205 fifo_hdr->fence_ptr = 206 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 207 TXF_FENCE_PTR + offset)); 208 fifo_hdr->fence_mode = 209 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 210 TXF_LOCK_FENCE + offset)); 211 212 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 213 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 214 TXF_WR_PTR + offset); 215 216 /* Dummy-read to advance the read pointer to the head */ 217 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 218 219 /* Read FIFO */ 220 fifo_len /= sizeof(u32); /* Size in DWORDS */ 221 for (i = 0; i < fifo_len; i++) 222 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 223 TXF_READ_MODIFY_DATA + 224 offset); 225 *dump_data = iwl_fw_error_next_data(*dump_data); 226 } 227 228 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 229 struct iwl_fw_error_dump_data **dump_data) 230 { 231 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 232 unsigned long flags; 233 234 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 235 236 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 237 return; 238 239 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 240 /* Pull RXF1 */ 241 iwl_fwrt_dump_rxf(fwrt, dump_data, 242 cfg->lmac[0].rxfifo1_size, 0, 0); 243 /* Pull RXF2 */ 244 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 245 RXF_DIFF_FROM_PREV + 246 fwrt->trans->trans_cfg->umac_prph_offset, 1); 247 /* Pull LMAC2 RXF1 */ 248 if (fwrt->smem_cfg.num_lmacs > 1) 249 iwl_fwrt_dump_rxf(fwrt, dump_data, 250 cfg->lmac[1].rxfifo1_size, 251 LMAC2_PRPH_OFFSET, 2); 252 } 253 254 iwl_trans_release_nic_access(fwrt->trans, &flags); 255 } 256 257 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 258 struct iwl_fw_error_dump_data **dump_data) 259 { 260 struct iwl_fw_error_dump_fifo *fifo_hdr; 261 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 262 u32 *fifo_data; 263 u32 fifo_len; 264 unsigned long flags; 265 int i, j; 266 267 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 268 269 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 270 return; 271 272 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 273 /* Pull TXF data from LMAC1 */ 274 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 275 /* Mark the number of TXF we're pulling now */ 276 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 277 iwl_fwrt_dump_txf(fwrt, dump_data, 278 cfg->lmac[0].txfifo_size[i], 0, i); 279 } 280 281 /* Pull TXF data from LMAC2 */ 282 if (fwrt->smem_cfg.num_lmacs > 1) { 283 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 284 i++) { 285 /* Mark the number of TXF we're pulling now */ 286 iwl_trans_write_prph(fwrt->trans, 287 TXF_LARC_NUM + 288 LMAC2_PRPH_OFFSET, i); 289 iwl_fwrt_dump_txf(fwrt, dump_data, 290 cfg->lmac[1].txfifo_size[i], 291 LMAC2_PRPH_OFFSET, 292 i + cfg->num_txfifo_entries); 293 } 294 } 295 } 296 297 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 298 fw_has_capa(&fwrt->fw->ucode_capa, 299 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 300 /* Pull UMAC internal TXF data from all TXFs */ 301 for (i = 0; 302 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 303 i++) { 304 fifo_hdr = (void *)(*dump_data)->data; 305 fifo_data = (void *)fifo_hdr->data; 306 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 307 308 /* No need to try to read the data if the length is 0 */ 309 if (fifo_len == 0) 310 continue; 311 312 /* Add a TLV for the internal FIFOs */ 313 (*dump_data)->type = 314 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 315 (*dump_data)->len = 316 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 317 318 fifo_hdr->fifo_num = cpu_to_le32(i); 319 320 /* Mark the number of TXF we're pulling now */ 321 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 322 fwrt->smem_cfg.num_txfifo_entries); 323 324 fifo_hdr->available_bytes = 325 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 326 TXF_CPU2_FIFO_ITEM_CNT)); 327 fifo_hdr->wr_ptr = 328 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 329 TXF_CPU2_WR_PTR)); 330 fifo_hdr->rd_ptr = 331 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 332 TXF_CPU2_RD_PTR)); 333 fifo_hdr->fence_ptr = 334 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 335 TXF_CPU2_FENCE_PTR)); 336 fifo_hdr->fence_mode = 337 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 338 TXF_CPU2_LOCK_FENCE)); 339 340 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 341 iwl_trans_write_prph(fwrt->trans, 342 TXF_CPU2_READ_MODIFY_ADDR, 343 TXF_CPU2_WR_PTR); 344 345 /* Dummy-read to advance the read pointer to head */ 346 iwl_trans_read_prph(fwrt->trans, 347 TXF_CPU2_READ_MODIFY_DATA); 348 349 /* Read FIFO */ 350 fifo_len /= sizeof(u32); /* Size in DWORDS */ 351 for (j = 0; j < fifo_len; j++) 352 fifo_data[j] = 353 iwl_trans_read_prph(fwrt->trans, 354 TXF_CPU2_READ_MODIFY_DATA); 355 *dump_data = iwl_fw_error_next_data(*dump_data); 356 } 357 } 358 359 iwl_trans_release_nic_access(fwrt->trans, &flags); 360 } 361 362 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ 363 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ 364 365 struct iwl_prph_range { 366 u32 start, end; 367 }; 368 369 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 370 { .start = 0x00a00000, .end = 0x00a00000 }, 371 { .start = 0x00a0000c, .end = 0x00a00024 }, 372 { .start = 0x00a0002c, .end = 0x00a0003c }, 373 { .start = 0x00a00410, .end = 0x00a00418 }, 374 { .start = 0x00a00420, .end = 0x00a00420 }, 375 { .start = 0x00a00428, .end = 0x00a00428 }, 376 { .start = 0x00a00430, .end = 0x00a0043c }, 377 { .start = 0x00a00444, .end = 0x00a00444 }, 378 { .start = 0x00a004c0, .end = 0x00a004cc }, 379 { .start = 0x00a004d8, .end = 0x00a004d8 }, 380 { .start = 0x00a004e0, .end = 0x00a004f0 }, 381 { .start = 0x00a00840, .end = 0x00a00840 }, 382 { .start = 0x00a00850, .end = 0x00a00858 }, 383 { .start = 0x00a01004, .end = 0x00a01008 }, 384 { .start = 0x00a01010, .end = 0x00a01010 }, 385 { .start = 0x00a01018, .end = 0x00a01018 }, 386 { .start = 0x00a01024, .end = 0x00a01024 }, 387 { .start = 0x00a0102c, .end = 0x00a01034 }, 388 { .start = 0x00a0103c, .end = 0x00a01040 }, 389 { .start = 0x00a01048, .end = 0x00a01094 }, 390 { .start = 0x00a01c00, .end = 0x00a01c20 }, 391 { .start = 0x00a01c58, .end = 0x00a01c58 }, 392 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 393 { .start = 0x00a01c28, .end = 0x00a01c54 }, 394 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 395 { .start = 0x00a01c60, .end = 0x00a01cdc }, 396 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 397 { .start = 0x00a01d18, .end = 0x00a01d20 }, 398 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 399 { .start = 0x00a01d40, .end = 0x00a01d5c }, 400 { .start = 0x00a01d80, .end = 0x00a01d80 }, 401 { .start = 0x00a01d98, .end = 0x00a01d9c }, 402 { .start = 0x00a01da8, .end = 0x00a01da8 }, 403 { .start = 0x00a01db8, .end = 0x00a01df4 }, 404 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 405 { .start = 0x00a01e00, .end = 0x00a01e2c }, 406 { .start = 0x00a01e40, .end = 0x00a01e60 }, 407 { .start = 0x00a01e68, .end = 0x00a01e6c }, 408 { .start = 0x00a01e74, .end = 0x00a01e74 }, 409 { .start = 0x00a01e84, .end = 0x00a01e90 }, 410 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 411 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 412 { .start = 0x00a01f00, .end = 0x00a01f1c }, 413 { .start = 0x00a01f44, .end = 0x00a01ffc }, 414 { .start = 0x00a02000, .end = 0x00a02048 }, 415 { .start = 0x00a02068, .end = 0x00a020f0 }, 416 { .start = 0x00a02100, .end = 0x00a02118 }, 417 { .start = 0x00a02140, .end = 0x00a0214c }, 418 { .start = 0x00a02168, .end = 0x00a0218c }, 419 { .start = 0x00a021c0, .end = 0x00a021c0 }, 420 { .start = 0x00a02400, .end = 0x00a02410 }, 421 { .start = 0x00a02418, .end = 0x00a02420 }, 422 { .start = 0x00a02428, .end = 0x00a0242c }, 423 { .start = 0x00a02434, .end = 0x00a02434 }, 424 { .start = 0x00a02440, .end = 0x00a02460 }, 425 { .start = 0x00a02468, .end = 0x00a024b0 }, 426 { .start = 0x00a024c8, .end = 0x00a024cc }, 427 { .start = 0x00a02500, .end = 0x00a02504 }, 428 { .start = 0x00a0250c, .end = 0x00a02510 }, 429 { .start = 0x00a02540, .end = 0x00a02554 }, 430 { .start = 0x00a02580, .end = 0x00a025f4 }, 431 { .start = 0x00a02600, .end = 0x00a0260c }, 432 { .start = 0x00a02648, .end = 0x00a02650 }, 433 { .start = 0x00a02680, .end = 0x00a02680 }, 434 { .start = 0x00a026c0, .end = 0x00a026d0 }, 435 { .start = 0x00a02700, .end = 0x00a0270c }, 436 { .start = 0x00a02804, .end = 0x00a02804 }, 437 { .start = 0x00a02818, .end = 0x00a0281c }, 438 { .start = 0x00a02c00, .end = 0x00a02db4 }, 439 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 440 { .start = 0x00a03000, .end = 0x00a03014 }, 441 { .start = 0x00a0301c, .end = 0x00a0302c }, 442 { .start = 0x00a03034, .end = 0x00a03038 }, 443 { .start = 0x00a03040, .end = 0x00a03048 }, 444 { .start = 0x00a03060, .end = 0x00a03068 }, 445 { .start = 0x00a03070, .end = 0x00a03074 }, 446 { .start = 0x00a0307c, .end = 0x00a0307c }, 447 { .start = 0x00a03080, .end = 0x00a03084 }, 448 { .start = 0x00a0308c, .end = 0x00a03090 }, 449 { .start = 0x00a03098, .end = 0x00a03098 }, 450 { .start = 0x00a030a0, .end = 0x00a030a0 }, 451 { .start = 0x00a030a8, .end = 0x00a030b4 }, 452 { .start = 0x00a030bc, .end = 0x00a030bc }, 453 { .start = 0x00a030c0, .end = 0x00a0312c }, 454 { .start = 0x00a03c00, .end = 0x00a03c5c }, 455 { .start = 0x00a04400, .end = 0x00a04454 }, 456 { .start = 0x00a04460, .end = 0x00a04474 }, 457 { .start = 0x00a044c0, .end = 0x00a044ec }, 458 { .start = 0x00a04500, .end = 0x00a04504 }, 459 { .start = 0x00a04510, .end = 0x00a04538 }, 460 { .start = 0x00a04540, .end = 0x00a04548 }, 461 { .start = 0x00a04560, .end = 0x00a0457c }, 462 { .start = 0x00a04590, .end = 0x00a04598 }, 463 { .start = 0x00a045c0, .end = 0x00a045f4 }, 464 }; 465 466 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 467 { .start = 0x00a05c00, .end = 0x00a05c18 }, 468 { .start = 0x00a05400, .end = 0x00a056e8 }, 469 { .start = 0x00a08000, .end = 0x00a098bc }, 470 { .start = 0x00a02400, .end = 0x00a02758 }, 471 { .start = 0x00a04764, .end = 0x00a0476c }, 472 { .start = 0x00a04770, .end = 0x00a04774 }, 473 { .start = 0x00a04620, .end = 0x00a04624 }, 474 }; 475 476 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 477 { .start = 0x00a00000, .end = 0x00a00000 }, 478 { .start = 0x00a0000c, .end = 0x00a00024 }, 479 { .start = 0x00a0002c, .end = 0x00a00034 }, 480 { .start = 0x00a0003c, .end = 0x00a0003c }, 481 { .start = 0x00a00410, .end = 0x00a00418 }, 482 { .start = 0x00a00420, .end = 0x00a00420 }, 483 { .start = 0x00a00428, .end = 0x00a00428 }, 484 { .start = 0x00a00430, .end = 0x00a0043c }, 485 { .start = 0x00a00444, .end = 0x00a00444 }, 486 { .start = 0x00a00840, .end = 0x00a00840 }, 487 { .start = 0x00a00850, .end = 0x00a00858 }, 488 { .start = 0x00a01004, .end = 0x00a01008 }, 489 { .start = 0x00a01010, .end = 0x00a01010 }, 490 { .start = 0x00a01018, .end = 0x00a01018 }, 491 { .start = 0x00a01024, .end = 0x00a01024 }, 492 { .start = 0x00a0102c, .end = 0x00a01034 }, 493 { .start = 0x00a0103c, .end = 0x00a01040 }, 494 { .start = 0x00a01048, .end = 0x00a01050 }, 495 { .start = 0x00a01058, .end = 0x00a01058 }, 496 { .start = 0x00a01060, .end = 0x00a01070 }, 497 { .start = 0x00a0108c, .end = 0x00a0108c }, 498 { .start = 0x00a01c20, .end = 0x00a01c28 }, 499 { .start = 0x00a01d10, .end = 0x00a01d10 }, 500 { .start = 0x00a01e28, .end = 0x00a01e2c }, 501 { .start = 0x00a01e60, .end = 0x00a01e60 }, 502 { .start = 0x00a01e80, .end = 0x00a01e80 }, 503 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 504 { .start = 0x00a02000, .end = 0x00a0201c }, 505 { .start = 0x00a02024, .end = 0x00a02024 }, 506 { .start = 0x00a02040, .end = 0x00a02048 }, 507 { .start = 0x00a020c0, .end = 0x00a020e0 }, 508 { .start = 0x00a02400, .end = 0x00a02404 }, 509 { .start = 0x00a0240c, .end = 0x00a02414 }, 510 { .start = 0x00a0241c, .end = 0x00a0243c }, 511 { .start = 0x00a02448, .end = 0x00a024bc }, 512 { .start = 0x00a024c4, .end = 0x00a024cc }, 513 { .start = 0x00a02508, .end = 0x00a02508 }, 514 { .start = 0x00a02510, .end = 0x00a02514 }, 515 { .start = 0x00a0251c, .end = 0x00a0251c }, 516 { .start = 0x00a0252c, .end = 0x00a0255c }, 517 { .start = 0x00a02564, .end = 0x00a025a0 }, 518 { .start = 0x00a025a8, .end = 0x00a025b4 }, 519 { .start = 0x00a025c0, .end = 0x00a025c0 }, 520 { .start = 0x00a025e8, .end = 0x00a025f4 }, 521 { .start = 0x00a02c08, .end = 0x00a02c18 }, 522 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 523 { .start = 0x00a02c68, .end = 0x00a02c78 }, 524 { .start = 0x00a03000, .end = 0x00a03000 }, 525 { .start = 0x00a03010, .end = 0x00a03014 }, 526 { .start = 0x00a0301c, .end = 0x00a0302c }, 527 { .start = 0x00a03034, .end = 0x00a03038 }, 528 { .start = 0x00a03040, .end = 0x00a03044 }, 529 { .start = 0x00a03060, .end = 0x00a03068 }, 530 { .start = 0x00a03070, .end = 0x00a03070 }, 531 { .start = 0x00a0307c, .end = 0x00a03084 }, 532 { .start = 0x00a0308c, .end = 0x00a03090 }, 533 { .start = 0x00a03098, .end = 0x00a03098 }, 534 { .start = 0x00a030a0, .end = 0x00a030a0 }, 535 { .start = 0x00a030a8, .end = 0x00a030b4 }, 536 { .start = 0x00a030bc, .end = 0x00a030c0 }, 537 { .start = 0x00a030c8, .end = 0x00a030f4 }, 538 { .start = 0x00a03100, .end = 0x00a0312c }, 539 { .start = 0x00a03c00, .end = 0x00a03c5c }, 540 { .start = 0x00a04400, .end = 0x00a04454 }, 541 { .start = 0x00a04460, .end = 0x00a04474 }, 542 { .start = 0x00a044c0, .end = 0x00a044ec }, 543 { .start = 0x00a04500, .end = 0x00a04504 }, 544 { .start = 0x00a04510, .end = 0x00a04538 }, 545 { .start = 0x00a04540, .end = 0x00a04548 }, 546 { .start = 0x00a04560, .end = 0x00a04560 }, 547 { .start = 0x00a04570, .end = 0x00a0457c }, 548 { .start = 0x00a04590, .end = 0x00a04590 }, 549 { .start = 0x00a04598, .end = 0x00a04598 }, 550 { .start = 0x00a045c0, .end = 0x00a045f4 }, 551 { .start = 0x00a05c18, .end = 0x00a05c1c }, 552 { .start = 0x00a0c000, .end = 0x00a0c018 }, 553 { .start = 0x00a0c020, .end = 0x00a0c028 }, 554 { .start = 0x00a0c038, .end = 0x00a0c094 }, 555 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 556 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 557 { .start = 0x00a0c150, .end = 0x00a0c174 }, 558 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 559 { .start = 0x00a0c190, .end = 0x00a0c198 }, 560 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 561 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 562 }; 563 564 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 565 { .start = 0x00d03c00, .end = 0x00d03c64 }, 566 { .start = 0x00d05c18, .end = 0x00d05c1c }, 567 { .start = 0x00d0c000, .end = 0x00d0c174 }, 568 }; 569 570 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 571 u32 len_bytes, __le32 *data) 572 { 573 u32 i; 574 575 for (i = 0; i < len_bytes; i += 4) 576 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 577 } 578 579 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 580 const struct iwl_prph_range *iwl_prph_dump_addr, 581 u32 range_len, void *ptr) 582 { 583 struct iwl_fw_error_dump_prph *prph; 584 struct iwl_trans *trans = fwrt->trans; 585 struct iwl_fw_error_dump_data **data = 586 (struct iwl_fw_error_dump_data **)ptr; 587 unsigned long flags; 588 u32 i; 589 590 if (!data) 591 return; 592 593 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 594 595 if (!iwl_trans_grab_nic_access(trans, &flags)) 596 return; 597 598 for (i = 0; i < range_len; i++) { 599 /* The range includes both boundaries */ 600 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 601 iwl_prph_dump_addr[i].start + 4; 602 603 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 604 (*data)->len = cpu_to_le32(sizeof(*prph) + 605 num_bytes_in_chunk); 606 prph = (void *)(*data)->data; 607 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 608 609 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 610 /* our range is inclusive, hence + 4 */ 611 iwl_prph_dump_addr[i].end - 612 iwl_prph_dump_addr[i].start + 4, 613 (void *)prph->data); 614 615 *data = iwl_fw_error_next_data(*data); 616 } 617 618 iwl_trans_release_nic_access(trans, &flags); 619 } 620 621 /* 622 * alloc_sgtable - allocates scallerlist table in the given size, 623 * fills it with pages and returns it 624 * @size: the size (in bytes) of the table 625 */ 626 static struct scatterlist *alloc_sgtable(int size) 627 { 628 int alloc_size, nents, i; 629 struct page *new_page; 630 struct scatterlist *iter; 631 struct scatterlist *table; 632 633 nents = DIV_ROUND_UP(size, PAGE_SIZE); 634 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 635 if (!table) 636 return NULL; 637 sg_init_table(table, nents); 638 iter = table; 639 for_each_sg(table, iter, sg_nents(table), i) { 640 new_page = alloc_page(GFP_KERNEL); 641 if (!new_page) { 642 /* release all previous allocated pages in the table */ 643 iter = table; 644 for_each_sg(table, iter, sg_nents(table), i) { 645 new_page = sg_page(iter); 646 if (new_page) 647 __free_page(new_page); 648 } 649 return NULL; 650 } 651 alloc_size = min_t(int, size, PAGE_SIZE); 652 size -= PAGE_SIZE; 653 sg_set_page(iter, new_page, alloc_size, 0); 654 } 655 return table; 656 } 657 658 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 659 const struct iwl_prph_range *iwl_prph_dump_addr, 660 u32 range_len, void *ptr) 661 { 662 u32 *prph_len = (u32 *)ptr; 663 int i, num_bytes_in_chunk; 664 665 if (!prph_len) 666 return; 667 668 for (i = 0; i < range_len; i++) { 669 /* The range includes both boundaries */ 670 num_bytes_in_chunk = 671 iwl_prph_dump_addr[i].end - 672 iwl_prph_dump_addr[i].start + 4; 673 674 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 675 sizeof(struct iwl_fw_error_dump_prph) + 676 num_bytes_in_chunk; 677 } 678 } 679 680 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 681 void (*handler)(struct iwl_fw_runtime *, 682 const struct iwl_prph_range *, 683 u32, void *)) 684 { 685 u32 range_len; 686 687 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 688 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 689 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 690 } else if (fwrt->trans->trans_cfg->device_family >= 691 IWL_DEVICE_FAMILY_22000) { 692 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 693 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 694 } else { 695 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 696 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 697 698 if (fwrt->trans->trans_cfg->mq_rx_supported) { 699 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 700 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 701 } 702 } 703 } 704 705 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 706 struct iwl_fw_error_dump_data **dump_data, 707 u32 len, u32 ofs, u32 type) 708 { 709 struct iwl_fw_error_dump_mem *dump_mem; 710 711 if (!len) 712 return; 713 714 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 715 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 716 dump_mem = (void *)(*dump_data)->data; 717 dump_mem->type = cpu_to_le32(type); 718 dump_mem->offset = cpu_to_le32(ofs); 719 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 720 *dump_data = iwl_fw_error_next_data(*dump_data); 721 722 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 723 } 724 725 #define ADD_LEN(len, item_len, const_len) \ 726 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 727 while (0) 728 729 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 730 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 731 { 732 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 733 sizeof(struct iwl_fw_error_dump_fifo); 734 u32 fifo_len = 0; 735 int i; 736 737 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 738 return 0; 739 740 /* Count RXF2 size */ 741 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 742 743 /* Count RXF1 sizes */ 744 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 745 mem_cfg->num_lmacs = MAX_NUM_LMAC; 746 747 for (i = 0; i < mem_cfg->num_lmacs; i++) 748 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 749 750 return fifo_len; 751 } 752 753 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 754 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 755 { 756 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 757 sizeof(struct iwl_fw_error_dump_fifo); 758 u32 fifo_len = 0; 759 int i; 760 761 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 762 goto dump_internal_txf; 763 764 /* Count TXF sizes */ 765 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 766 mem_cfg->num_lmacs = MAX_NUM_LMAC; 767 768 for (i = 0; i < mem_cfg->num_lmacs; i++) { 769 int j; 770 771 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 772 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 773 hdr_len); 774 } 775 776 dump_internal_txf: 777 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 778 fw_has_capa(&fwrt->fw->ucode_capa, 779 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 780 goto out; 781 782 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 783 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 784 785 out: 786 return fifo_len; 787 } 788 789 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 790 struct iwl_fw_error_dump_data **data) 791 { 792 int i; 793 794 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 795 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 796 struct iwl_fw_error_dump_paging *paging; 797 struct page *pages = 798 fwrt->fw_paging_db[i].fw_paging_block; 799 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 800 801 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 802 (*data)->len = cpu_to_le32(sizeof(*paging) + 803 PAGING_BLOCK_SIZE); 804 paging = (void *)(*data)->data; 805 paging->index = cpu_to_le32(i); 806 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 807 PAGING_BLOCK_SIZE, 808 DMA_BIDIRECTIONAL); 809 memcpy(paging->data, page_address(pages), 810 PAGING_BLOCK_SIZE); 811 dma_sync_single_for_device(fwrt->trans->dev, addr, 812 PAGING_BLOCK_SIZE, 813 DMA_BIDIRECTIONAL); 814 (*data) = iwl_fw_error_next_data(*data); 815 } 816 } 817 818 static struct iwl_fw_error_dump_file * 819 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 820 struct iwl_fw_dump_ptrs *fw_error_dump) 821 { 822 struct iwl_fw_error_dump_file *dump_file; 823 struct iwl_fw_error_dump_data *dump_data; 824 struct iwl_fw_error_dump_info *dump_info; 825 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 826 struct iwl_fw_error_dump_trigger_desc *dump_trig; 827 u32 sram_len, sram_ofs; 828 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 829 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 830 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 831 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 832 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 833 0 : fwrt->trans->cfg->dccm2_len; 834 int i; 835 836 /* SRAM - include stack CCM if driver knows the values for it */ 837 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 838 const struct fw_img *img; 839 840 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 841 return NULL; 842 img = &fwrt->fw->img[fwrt->cur_fw_img]; 843 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 844 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 845 } else { 846 sram_ofs = fwrt->trans->cfg->dccm_offset; 847 sram_len = fwrt->trans->cfg->dccm_len; 848 } 849 850 /* reading RXF/TXF sizes */ 851 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 852 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 853 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 854 855 /* Make room for PRPH registers */ 856 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 857 iwl_fw_prph_handler(fwrt, &prph_len, 858 iwl_fw_get_prph_len); 859 860 if (fwrt->trans->trans_cfg->device_family == 861 IWL_DEVICE_FAMILY_7000 && 862 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 863 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 864 } 865 866 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 867 868 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 869 file_len += sizeof(*dump_data) + sizeof(*dump_info); 870 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 871 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 872 873 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 874 size_t hdr_len = sizeof(*dump_data) + 875 sizeof(struct iwl_fw_error_dump_mem); 876 877 /* Dump SRAM only if no mem_tlvs */ 878 if (!fwrt->fw->dbg.n_mem_tlv) 879 ADD_LEN(file_len, sram_len, hdr_len); 880 881 /* Make room for all mem types that exist */ 882 ADD_LEN(file_len, smem_len, hdr_len); 883 ADD_LEN(file_len, sram2_len, hdr_len); 884 885 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 886 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 887 } 888 889 /* Make room for fw's virtual image pages, if it exists */ 890 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 891 file_len += fwrt->num_of_paging_blk * 892 (sizeof(*dump_data) + 893 sizeof(struct iwl_fw_error_dump_paging) + 894 PAGING_BLOCK_SIZE); 895 896 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 897 file_len += sizeof(*dump_data) + 898 fwrt->trans->cfg->d3_debug_data_length * 2; 899 } 900 901 /* If we only want a monitor dump, reset the file length */ 902 if (fwrt->dump.monitor_only) { 903 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 904 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 905 } 906 907 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 908 fwrt->dump.desc) 909 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 910 fwrt->dump.desc->len; 911 912 dump_file = vzalloc(file_len); 913 if (!dump_file) 914 return NULL; 915 916 fw_error_dump->fwrt_ptr = dump_file; 917 918 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 919 dump_data = (void *)dump_file->data; 920 921 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 922 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 923 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 924 dump_info = (void *)dump_data->data; 925 dump_info->hw_type = 926 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 927 dump_info->hw_step = 928 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 929 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 930 sizeof(dump_info->fw_human_readable)); 931 strncpy(dump_info->dev_human_readable, fwrt->trans->cfg->name, 932 sizeof(dump_info->dev_human_readable) - 1); 933 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 934 sizeof(dump_info->bus_human_readable) - 1); 935 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 936 dump_info->lmac_err_id[0] = 937 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 938 if (fwrt->smem_cfg.num_lmacs > 1) 939 dump_info->lmac_err_id[1] = 940 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 941 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 942 943 dump_data = iwl_fw_error_next_data(dump_data); 944 } 945 946 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 947 /* Dump shared memory configuration */ 948 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 949 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 950 dump_smem_cfg = (void *)dump_data->data; 951 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 952 dump_smem_cfg->num_txfifo_entries = 953 cpu_to_le32(mem_cfg->num_txfifo_entries); 954 for (i = 0; i < MAX_NUM_LMAC; i++) { 955 int j; 956 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 957 958 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 959 dump_smem_cfg->lmac[i].txfifo_size[j] = 960 cpu_to_le32(txf_size[j]); 961 dump_smem_cfg->lmac[i].rxfifo1_size = 962 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 963 } 964 dump_smem_cfg->rxfifo2_size = 965 cpu_to_le32(mem_cfg->rxfifo2_size); 966 dump_smem_cfg->internal_txfifo_addr = 967 cpu_to_le32(mem_cfg->internal_txfifo_addr); 968 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 969 dump_smem_cfg->internal_txfifo_size[i] = 970 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 971 } 972 973 dump_data = iwl_fw_error_next_data(dump_data); 974 } 975 976 /* We only dump the FIFOs if the FW is in error state */ 977 if (fifo_len) { 978 iwl_fw_dump_rxf(fwrt, &dump_data); 979 iwl_fw_dump_txf(fwrt, &dump_data); 980 } 981 982 if (radio_len) 983 iwl_read_radio_regs(fwrt, &dump_data); 984 985 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 986 fwrt->dump.desc) { 987 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 988 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 989 fwrt->dump.desc->len); 990 dump_trig = (void *)dump_data->data; 991 memcpy(dump_trig, &fwrt->dump.desc->trig_desc, 992 sizeof(*dump_trig) + fwrt->dump.desc->len); 993 994 dump_data = iwl_fw_error_next_data(dump_data); 995 } 996 997 /* In case we only want monitor dump, skip to dump trasport data */ 998 if (fwrt->dump.monitor_only) 999 goto out; 1000 1001 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 1002 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 1003 fwrt->fw->dbg.mem_tlv; 1004 1005 if (!fwrt->fw->dbg.n_mem_tlv) 1006 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 1007 IWL_FW_ERROR_DUMP_MEM_SRAM); 1008 1009 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 1010 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 1011 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 1012 1013 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 1014 le32_to_cpu(fw_dbg_mem[i].data_type)); 1015 } 1016 1017 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 1018 fwrt->trans->cfg->smem_offset, 1019 IWL_FW_ERROR_DUMP_MEM_SMEM); 1020 1021 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 1022 fwrt->trans->cfg->dccm2_offset, 1023 IWL_FW_ERROR_DUMP_MEM_SRAM); 1024 } 1025 1026 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 1027 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 1028 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 1029 1030 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 1031 dump_data->len = cpu_to_le32(data_size * 2); 1032 1033 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 1034 1035 kfree(fwrt->dump.d3_debug_data); 1036 fwrt->dump.d3_debug_data = NULL; 1037 1038 iwl_trans_read_mem_bytes(fwrt->trans, addr, 1039 dump_data->data + data_size, 1040 data_size); 1041 1042 dump_data = iwl_fw_error_next_data(dump_data); 1043 } 1044 1045 /* Dump fw's virtual image */ 1046 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1047 iwl_dump_paging(fwrt, &dump_data); 1048 1049 if (prph_len) 1050 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1051 1052 out: 1053 dump_file->file_len = cpu_to_le32(file_len); 1054 return dump_file; 1055 } 1056 1057 static int iwl_dump_ini_prph_iter(struct iwl_fw_runtime *fwrt, 1058 struct iwl_fw_ini_region_cfg *reg, 1059 void *range_ptr, int idx) 1060 { 1061 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1062 __le32 *val = range->data; 1063 u32 prph_val; 1064 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1065 int i; 1066 1067 range->internal_base_addr = cpu_to_le32(addr); 1068 range->range_data_size = reg->internal.range_data_size; 1069 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) { 1070 prph_val = iwl_read_prph(fwrt->trans, addr + i); 1071 if (prph_val == 0x5a5a5a5a) 1072 return -EBUSY; 1073 *val++ = cpu_to_le32(prph_val); 1074 } 1075 1076 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1077 } 1078 1079 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1080 struct iwl_fw_ini_region_cfg *reg, 1081 void *range_ptr, int idx) 1082 { 1083 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1084 __le32 *val = range->data; 1085 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1086 int i; 1087 1088 range->internal_base_addr = cpu_to_le32(addr); 1089 range->range_data_size = reg->internal.range_data_size; 1090 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) 1091 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1092 1093 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1094 } 1095 1096 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1097 struct iwl_fw_ini_region_cfg *reg, 1098 void *range_ptr, int idx) 1099 { 1100 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1101 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1102 1103 range->internal_base_addr = cpu_to_le32(addr); 1104 range->range_data_size = reg->internal.range_data_size; 1105 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1106 le32_to_cpu(reg->internal.range_data_size)); 1107 1108 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1109 } 1110 1111 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1112 struct iwl_fw_ini_region_cfg *reg, 1113 void *range_ptr, int idx) 1114 { 1115 /* increase idx by 1 since the pages are from 1 to 1116 * fwrt->num_of_paging_blk + 1 1117 */ 1118 struct page *page = fwrt->fw_paging_db[++idx].fw_paging_block; 1119 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1120 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1121 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1122 1123 range->page_num = cpu_to_le32(idx); 1124 range->range_data_size = cpu_to_le32(page_size); 1125 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1126 DMA_BIDIRECTIONAL); 1127 memcpy(range->data, page_address(page), page_size); 1128 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1129 DMA_BIDIRECTIONAL); 1130 1131 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1132 } 1133 1134 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1135 struct iwl_fw_ini_region_cfg *reg, 1136 void *range_ptr, int idx) 1137 { 1138 struct iwl_fw_ini_error_dump_range *range; 1139 u32 page_size; 1140 1141 if (!fwrt->trans->trans_cfg->gen2) 1142 return _iwl_dump_ini_paging_iter(fwrt, reg, range_ptr, idx); 1143 1144 range = range_ptr; 1145 page_size = fwrt->trans->init_dram.paging[idx].size; 1146 1147 range->page_num = cpu_to_le32(idx); 1148 range->range_data_size = cpu_to_le32(page_size); 1149 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1150 page_size); 1151 1152 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1153 } 1154 1155 static int 1156 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1157 struct iwl_fw_ini_region_cfg *reg, void *range_ptr, 1158 int idx) 1159 { 1160 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1161 u32 start_addr = iwl_read_umac_prph(fwrt->trans, 1162 MON_BUFF_BASE_ADDR_VER2); 1163 1164 if (start_addr == 0x5a5a5a5a) 1165 return -EBUSY; 1166 1167 range->dram_base_addr = cpu_to_le64(start_addr); 1168 range->range_data_size = cpu_to_le32(fwrt->trans->dbg.fw_mon[idx].size); 1169 1170 memcpy(range->data, fwrt->trans->dbg.fw_mon[idx].block, 1171 fwrt->trans->dbg.fw_mon[idx].size); 1172 1173 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1174 } 1175 1176 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1177 struct iwl_fw_ini_region_cfg *reg, int idx) 1178 { 1179 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1180 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1181 int txf_num = cfg->num_txfifo_entries; 1182 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1183 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid1); 1184 1185 if (!idx) { 1186 if (le32_to_cpu(reg->offset) && 1187 WARN_ONCE(cfg->num_lmacs == 1, 1188 "Invalid lmac offset: 0x%x\n", 1189 le32_to_cpu(reg->offset))) 1190 return false; 1191 1192 iter->internal_txf = 0; 1193 iter->fifo_size = 0; 1194 iter->fifo = -1; 1195 if (le32_to_cpu(reg->offset)) 1196 iter->lmac = 1; 1197 else 1198 iter->lmac = 0; 1199 } 1200 1201 if (!iter->internal_txf) 1202 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1203 iter->fifo_size = 1204 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1205 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1206 return true; 1207 } 1208 1209 iter->internal_txf = 1; 1210 1211 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1212 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1213 return false; 1214 1215 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1216 iter->fifo_size = 1217 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1218 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1219 return true; 1220 } 1221 1222 return false; 1223 } 1224 1225 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1226 struct iwl_fw_ini_region_cfg *reg, 1227 void *range_ptr, int idx) 1228 { 1229 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1230 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1231 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1232 u32 offs = le32_to_cpu(reg->offset), addr; 1233 u32 registers_size = 1234 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump); 1235 __le32 *data; 1236 unsigned long flags; 1237 int i; 1238 1239 if (!iwl_ini_txf_iter(fwrt, reg, idx)) 1240 return -EIO; 1241 1242 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1243 return -EBUSY; 1244 1245 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1246 range->fifo_hdr.num_of_registers = reg->fifos.num_of_registers; 1247 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1248 1249 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1250 1251 /* 1252 * read txf registers. for each register, write to the dump the 1253 * register address and its value 1254 */ 1255 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { 1256 addr = le32_to_cpu(reg->start_addr[i]) + offs; 1257 1258 reg_dump->addr = cpu_to_le32(addr); 1259 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1260 addr)); 1261 1262 reg_dump++; 1263 } 1264 1265 if (reg->fifos.header_only) { 1266 range->range_data_size = cpu_to_le32(registers_size); 1267 goto out; 1268 } 1269 1270 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1271 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1272 TXF_WR_PTR + offs); 1273 1274 /* Dummy-read to advance the read pointer to the head */ 1275 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1276 1277 /* Read FIFO */ 1278 addr = TXF_READ_MODIFY_DATA + offs; 1279 data = (void *)reg_dump; 1280 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1281 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1282 1283 out: 1284 iwl_trans_release_nic_access(fwrt->trans, &flags); 1285 1286 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1287 } 1288 1289 struct iwl_ini_rxf_data { 1290 u32 fifo_num; 1291 u32 size; 1292 u32 offset; 1293 }; 1294 1295 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1296 struct iwl_fw_ini_region_cfg *reg, 1297 struct iwl_ini_rxf_data *data) 1298 { 1299 u32 fid1 = le32_to_cpu(reg->fifos.fid1); 1300 u32 fid2 = le32_to_cpu(reg->fifos.fid2); 1301 u32 fifo_idx; 1302 1303 if (!data) 1304 return; 1305 1306 memset(data, 0, sizeof(*data)); 1307 1308 if (WARN_ON_ONCE((fid1 && fid2) || (!fid1 && !fid2))) 1309 return; 1310 1311 fifo_idx = ffs(fid1) - 1; 1312 if (fid1 && !WARN_ON_ONCE((~BIT(fifo_idx) & fid1) || 1313 fifo_idx >= MAX_NUM_LMAC)) { 1314 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1315 data->fifo_num = fifo_idx; 1316 return; 1317 } 1318 1319 fifo_idx = ffs(fid2) - 1; 1320 if (fid2 && !WARN_ON_ONCE(fifo_idx != 0)) { 1321 data->size = fwrt->smem_cfg.rxfifo2_size; 1322 data->offset = RXF_DIFF_FROM_PREV; 1323 /* use bit 31 to distinguish between umac and lmac rxf while 1324 * parsing the dump 1325 */ 1326 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1327 return; 1328 } 1329 } 1330 1331 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1332 struct iwl_fw_ini_region_cfg *reg, 1333 void *range_ptr, int idx) 1334 { 1335 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1336 struct iwl_ini_rxf_data rxf_data; 1337 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1338 u32 offs = le32_to_cpu(reg->offset), addr; 1339 u32 registers_size = 1340 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump); 1341 __le32 *data; 1342 unsigned long flags; 1343 int i; 1344 1345 iwl_ini_get_rxf_data(fwrt, reg, &rxf_data); 1346 if (!rxf_data.size) 1347 return -EIO; 1348 1349 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1350 return -EBUSY; 1351 1352 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1353 range->fifo_hdr.num_of_registers = reg->fifos.num_of_registers; 1354 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1355 1356 /* 1357 * read rxf registers. for each register, write to the dump the 1358 * register address and its value 1359 */ 1360 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { 1361 addr = le32_to_cpu(reg->start_addr[i]) + offs; 1362 1363 reg_dump->addr = cpu_to_le32(addr); 1364 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1365 addr)); 1366 1367 reg_dump++; 1368 } 1369 1370 if (reg->fifos.header_only) { 1371 range->range_data_size = cpu_to_le32(registers_size); 1372 goto out; 1373 } 1374 1375 /* 1376 * region register have absolute value so apply rxf offset after 1377 * reading the registers 1378 */ 1379 offs += rxf_data.offset; 1380 1381 /* Lock fence */ 1382 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1383 /* Set fence pointer to the same place like WR pointer */ 1384 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1385 /* Set fence offset */ 1386 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1387 0x0); 1388 1389 /* Read FIFO */ 1390 addr = RXF_FIFO_RD_FENCE_INC + offs; 1391 data = (void *)reg_dump; 1392 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1393 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1394 1395 out: 1396 iwl_trans_release_nic_access(fwrt->trans, &flags); 1397 1398 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1399 } 1400 1401 static void *iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1402 struct iwl_fw_ini_region_cfg *reg, 1403 void *data) 1404 { 1405 struct iwl_fw_ini_error_dump *dump = data; 1406 1407 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1408 1409 return dump->ranges; 1410 } 1411 1412 static void 1413 *iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, 1414 struct iwl_fw_ini_region_cfg *reg, 1415 struct iwl_fw_ini_monitor_dump *data, 1416 u32 write_ptr_addr, u32 write_ptr_msk, 1417 u32 cycle_cnt_addr, u32 cycle_cnt_msk) 1418 { 1419 u32 write_ptr, cycle_cnt; 1420 unsigned long flags; 1421 1422 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) { 1423 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1424 return NULL; 1425 } 1426 1427 write_ptr = iwl_read_prph_no_grab(fwrt->trans, write_ptr_addr); 1428 cycle_cnt = iwl_read_prph_no_grab(fwrt->trans, cycle_cnt_addr); 1429 1430 iwl_trans_release_nic_access(fwrt->trans, &flags); 1431 1432 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1433 data->write_ptr = cpu_to_le32(write_ptr & write_ptr_msk); 1434 data->cycle_cnt = cpu_to_le32(cycle_cnt & cycle_cnt_msk); 1435 1436 return data->ranges; 1437 } 1438 1439 static void 1440 *iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1441 struct iwl_fw_ini_region_cfg *reg, 1442 void *data) 1443 { 1444 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1445 u32 write_ptr_addr, write_ptr_msk, cycle_cnt_addr, cycle_cnt_msk; 1446 1447 switch (fwrt->trans->trans_cfg->device_family) { 1448 case IWL_DEVICE_FAMILY_9000: 1449 case IWL_DEVICE_FAMILY_22000: 1450 write_ptr_addr = MON_BUFF_WRPTR_VER2; 1451 write_ptr_msk = -1; 1452 cycle_cnt_addr = MON_BUFF_CYCLE_CNT_VER2; 1453 cycle_cnt_msk = -1; 1454 break; 1455 default: 1456 IWL_ERR(fwrt, "Unsupported device family %d\n", 1457 fwrt->trans->trans_cfg->device_family); 1458 return NULL; 1459 } 1460 1461 return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, write_ptr_addr, 1462 write_ptr_msk, cycle_cnt_addr, 1463 cycle_cnt_msk); 1464 } 1465 1466 static void 1467 *iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1468 struct iwl_fw_ini_region_cfg *reg, 1469 void *data) 1470 { 1471 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1472 const struct iwl_cfg *cfg = fwrt->trans->cfg; 1473 1474 if (fwrt->trans->trans_cfg->device_family != IWL_DEVICE_FAMILY_9000 && 1475 fwrt->trans->trans_cfg->device_family != IWL_DEVICE_FAMILY_22000) { 1476 IWL_ERR(fwrt, "Unsupported device family %d\n", 1477 fwrt->trans->trans_cfg->device_family); 1478 return NULL; 1479 } 1480 1481 return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, 1482 cfg->fw_mon_smem_write_ptr_addr, 1483 cfg->fw_mon_smem_write_ptr_msk, 1484 cfg->fw_mon_smem_cycle_cnt_ptr_addr, 1485 cfg->fw_mon_smem_cycle_cnt_ptr_msk); 1486 1487 } 1488 1489 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1490 struct iwl_fw_ini_region_cfg *reg) 1491 { 1492 return le32_to_cpu(reg->internal.num_of_ranges); 1493 } 1494 1495 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1496 struct iwl_fw_ini_region_cfg *reg) 1497 { 1498 if (fwrt->trans->trans_cfg->gen2) 1499 return fwrt->trans->init_dram.paging_cnt; 1500 1501 return fwrt->num_of_paging_blk; 1502 } 1503 1504 static u32 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1505 struct iwl_fw_ini_region_cfg *reg) 1506 { 1507 return 1; 1508 } 1509 1510 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1511 struct iwl_fw_ini_region_cfg *reg) 1512 { 1513 u32 num_of_fifos = 0; 1514 1515 while (iwl_ini_txf_iter(fwrt, reg, num_of_fifos)) 1516 num_of_fifos++; 1517 1518 return num_of_fifos; 1519 } 1520 1521 static u32 iwl_dump_ini_rxf_ranges(struct iwl_fw_runtime *fwrt, 1522 struct iwl_fw_ini_region_cfg *reg) 1523 { 1524 /* Each Rx fifo needs a different offset and therefore, it's 1525 * region can contain only one fifo, i.e. 1 memory range. 1526 */ 1527 return 1; 1528 } 1529 1530 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1531 struct iwl_fw_ini_region_cfg *reg) 1532 { 1533 return sizeof(struct iwl_fw_ini_error_dump) + 1534 iwl_dump_ini_mem_ranges(fwrt, reg) * 1535 (sizeof(struct iwl_fw_ini_error_dump_range) + 1536 le32_to_cpu(reg->internal.range_data_size)); 1537 } 1538 1539 static u32 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1540 struct iwl_fw_ini_region_cfg *reg) 1541 { 1542 int i; 1543 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1544 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1545 1546 if (fwrt->trans->trans_cfg->gen2) { 1547 for (i = 0; i < iwl_dump_ini_paging_ranges(fwrt, reg); i++) 1548 size += range_header_len + 1549 fwrt->trans->init_dram.paging[i].size; 1550 } else { 1551 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg); i++) 1552 size += range_header_len + 1553 fwrt->fw_paging_db[i].fw_paging_size; 1554 } 1555 1556 return size; 1557 } 1558 1559 static u32 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 1560 struct iwl_fw_ini_region_cfg *reg) 1561 { 1562 u32 size = sizeof(struct iwl_fw_ini_monitor_dump) + 1563 sizeof(struct iwl_fw_ini_error_dump_range); 1564 1565 if (fwrt->trans->dbg.num_blocks) 1566 size += fwrt->trans->dbg.fw_mon[0].size; 1567 1568 return size; 1569 } 1570 1571 static u32 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 1572 struct iwl_fw_ini_region_cfg *reg) 1573 { 1574 return sizeof(struct iwl_fw_ini_monitor_dump) + 1575 iwl_dump_ini_mem_ranges(fwrt, reg) * 1576 (sizeof(struct iwl_fw_ini_error_dump_range) + 1577 le32_to_cpu(reg->internal.range_data_size)); 1578 } 1579 1580 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 1581 struct iwl_fw_ini_region_cfg *reg) 1582 { 1583 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1584 u32 size = 0; 1585 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 1586 le32_to_cpu(reg->fifos.num_of_registers) * 1587 sizeof(struct iwl_fw_ini_error_dump_register); 1588 1589 while (iwl_ini_txf_iter(fwrt, reg, size)) { 1590 size += fifo_hdr; 1591 if (!reg->fifos.header_only) 1592 size += iter->fifo_size; 1593 } 1594 1595 if (size) 1596 size += sizeof(struct iwl_fw_ini_error_dump); 1597 1598 return size; 1599 } 1600 1601 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 1602 struct iwl_fw_ini_region_cfg *reg) 1603 { 1604 struct iwl_ini_rxf_data rx_data; 1605 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 1606 sizeof(struct iwl_fw_ini_error_dump_range) + 1607 le32_to_cpu(reg->fifos.num_of_registers) * 1608 sizeof(struct iwl_fw_ini_error_dump_register); 1609 1610 if (reg->fifos.header_only) 1611 return size; 1612 1613 iwl_ini_get_rxf_data(fwrt, reg, &rx_data); 1614 size += rx_data.size; 1615 1616 return size; 1617 } 1618 1619 /** 1620 * struct iwl_dump_ini_mem_ops - ini memory dump operations 1621 * @get_num_of_ranges: returns the number of memory ranges in the region. 1622 * @get_size: returns the total size of the region. 1623 * @fill_mem_hdr: fills region type specific headers and returns pointer to 1624 * the first range or NULL if failed to fill headers. 1625 * @fill_range: copies a given memory range into the dump. 1626 * Returns the size of the range or negative error value otherwise. 1627 */ 1628 struct iwl_dump_ini_mem_ops { 1629 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 1630 struct iwl_fw_ini_region_cfg *reg); 1631 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 1632 struct iwl_fw_ini_region_cfg *reg); 1633 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 1634 struct iwl_fw_ini_region_cfg *reg, void *data); 1635 int (*fill_range)(struct iwl_fw_runtime *fwrt, 1636 struct iwl_fw_ini_region_cfg *reg, void *range, 1637 int idx); 1638 }; 1639 1640 /** 1641 * iwl_dump_ini_mem 1642 * 1643 * Creates a dump tlv and copy a memory region into it. 1644 * Returns the size of the current dump tlv or 0 if failed 1645 * 1646 * @fwrt: fw runtime struct 1647 * @list: list to add the dump tlv to 1648 * @reg: memory region 1649 * @ops: memory dump operations 1650 */ 1651 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 1652 struct iwl_fw_ini_region_cfg *reg, 1653 const struct iwl_dump_ini_mem_ops *ops) 1654 { 1655 struct iwl_fw_ini_dump_entry *entry; 1656 struct iwl_fw_error_dump_data *tlv; 1657 struct iwl_fw_ini_error_dump_header *header; 1658 u32 num_of_ranges, i, type = le32_to_cpu(reg->region_type), size; 1659 void *range; 1660 1661 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 1662 !ops->fill_range) 1663 return 0; 1664 1665 size = ops->get_size(fwrt, reg); 1666 if (!size) 1667 return 0; 1668 1669 entry = kmalloc(sizeof(*entry) + sizeof(*tlv) + size, GFP_KERNEL); 1670 if (!entry) 1671 return 0; 1672 1673 entry->size = sizeof(*tlv) + size; 1674 1675 tlv = (void *)entry->data; 1676 tlv->type = cpu_to_le32(type); 1677 tlv->len = cpu_to_le32(size); 1678 1679 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: id=%d, type=%d\n", 1680 le32_to_cpu(reg->region_id), type); 1681 1682 num_of_ranges = ops->get_num_of_ranges(fwrt, reg); 1683 1684 header = (void *)tlv->data; 1685 header->region_id = reg->region_id; 1686 header->num_of_ranges = cpu_to_le32(num_of_ranges); 1687 header->name_len = cpu_to_le32(min_t(int, IWL_FW_INI_MAX_NAME, 1688 le32_to_cpu(reg->name_len))); 1689 memcpy(header->name, reg->name, le32_to_cpu(header->name_len)); 1690 1691 range = ops->fill_mem_hdr(fwrt, reg, header); 1692 if (!range) { 1693 IWL_ERR(fwrt, 1694 "WRT: Failed to fill region header: id=%d, type=%d\n", 1695 le32_to_cpu(reg->region_id), type); 1696 goto out_err; 1697 } 1698 1699 for (i = 0; i < num_of_ranges; i++) { 1700 int range_size = ops->fill_range(fwrt, reg, range, i); 1701 1702 if (range_size < 0) { 1703 IWL_ERR(fwrt, 1704 "WRT: Failed to dump region: id=%d, type=%d\n", 1705 le32_to_cpu(reg->region_id), type); 1706 goto out_err; 1707 } 1708 range = range + range_size; 1709 } 1710 1711 list_add_tail(&entry->list, list); 1712 1713 return entry->size; 1714 1715 out_err: 1716 kfree(entry); 1717 1718 return 0; 1719 } 1720 1721 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 1722 struct iwl_fw_ini_trigger *trigger, 1723 struct list_head *list) 1724 { 1725 struct iwl_fw_ini_dump_entry *entry; 1726 struct iwl_fw_error_dump_data *tlv; 1727 struct iwl_fw_ini_dump_info *dump; 1728 u32 reg_ids_size = le32_to_cpu(trigger->num_regions) * sizeof(__le32); 1729 u32 size = sizeof(*tlv) + sizeof(*dump) + reg_ids_size; 1730 1731 entry = kmalloc(sizeof(*entry) + size, GFP_KERNEL); 1732 if (!entry) 1733 return 0; 1734 1735 entry->size = size; 1736 1737 tlv = (void *)entry->data; 1738 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 1739 tlv->len = cpu_to_le32(sizeof(*dump) + reg_ids_size); 1740 1741 dump = (void *)tlv->data; 1742 1743 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 1744 dump->trigger_id = trigger->trigger_id; 1745 dump->is_external_cfg = 1746 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 1747 1748 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 1749 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 1750 1751 dump->hw_step = cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 1752 dump->hw_type = cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 1753 1754 dump->rf_id_flavor = 1755 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id)); 1756 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id)); 1757 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id)); 1758 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id)); 1759 1760 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 1761 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 1762 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 1763 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 1764 1765 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 1766 memcpy(dump->build_tag, fwrt->fw->human_readable, 1767 sizeof(dump->build_tag)); 1768 1769 dump->img_name_len = cpu_to_le32(sizeof(dump->img_name)); 1770 memcpy(dump->img_name, fwrt->dump.img_name, sizeof(dump->img_name)); 1771 1772 dump->internal_dbg_cfg_name_len = 1773 cpu_to_le32(sizeof(dump->internal_dbg_cfg_name)); 1774 memcpy(dump->internal_dbg_cfg_name, fwrt->dump.internal_dbg_cfg_name, 1775 sizeof(dump->internal_dbg_cfg_name)); 1776 1777 dump->external_dbg_cfg_name_len = 1778 cpu_to_le32(sizeof(dump->external_dbg_cfg_name)); 1779 1780 memcpy(dump->external_dbg_cfg_name, fwrt->dump.external_dbg_cfg_name, 1781 sizeof(dump->external_dbg_cfg_name)); 1782 1783 dump->regions_num = trigger->num_regions; 1784 memcpy(dump->region_ids, trigger->data, reg_ids_size); 1785 1786 /* add dump info TLV to the beginning of the list since it needs to be 1787 * the first TLV in the dump 1788 */ 1789 list_add(&entry->list, list); 1790 1791 return entry->size; 1792 } 1793 1794 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 1795 [IWL_FW_INI_REGION_INVALID] = {}, 1796 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 1797 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 1798 .get_size = iwl_dump_ini_mem_get_size, 1799 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1800 .fill_range = iwl_dump_ini_dev_mem_iter, 1801 }, 1802 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 1803 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 1804 .get_size = iwl_dump_ini_mem_get_size, 1805 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1806 .fill_range = iwl_dump_ini_prph_iter, 1807 }, 1808 [IWL_FW_INI_REGION_PERIPHERY_PHY] = {}, 1809 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 1810 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 1811 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 1812 .get_size = iwl_dump_ini_mon_dram_get_size, 1813 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 1814 .fill_range = iwl_dump_ini_mon_dram_iter, 1815 }, 1816 [IWL_FW_INI_REGION_DRAM_IMR] = {}, 1817 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 1818 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 1819 .get_size = iwl_dump_ini_mon_smem_get_size, 1820 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 1821 .fill_range = iwl_dump_ini_dev_mem_iter, 1822 }, 1823 [IWL_FW_INI_REGION_TXF] = { 1824 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 1825 .get_size = iwl_dump_ini_txf_get_size, 1826 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1827 .fill_range = iwl_dump_ini_txf_iter, 1828 }, 1829 [IWL_FW_INI_REGION_RXF] = { 1830 .get_num_of_ranges = iwl_dump_ini_rxf_ranges, 1831 .get_size = iwl_dump_ini_rxf_get_size, 1832 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1833 .fill_range = iwl_dump_ini_rxf_iter, 1834 }, 1835 [IWL_FW_INI_REGION_PAGING] = { 1836 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1837 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 1838 .get_size = iwl_dump_ini_paging_get_size, 1839 .fill_range = iwl_dump_ini_paging_iter, 1840 }, 1841 [IWL_FW_INI_REGION_CSR] = { 1842 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 1843 .get_size = iwl_dump_ini_mem_get_size, 1844 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1845 .fill_range = iwl_dump_ini_csr_iter, 1846 }, 1847 [IWL_FW_INI_REGION_NOTIFICATION] = {}, 1848 [IWL_FW_INI_REGION_DHC] = {}, 1849 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 1850 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 1851 .get_size = iwl_dump_ini_mem_get_size, 1852 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1853 .fill_range = iwl_dump_ini_dev_mem_iter, 1854 }, 1855 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 1856 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 1857 .get_size = iwl_dump_ini_mem_get_size, 1858 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 1859 .fill_range = iwl_dump_ini_dev_mem_iter, 1860 }, 1861 }; 1862 1863 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 1864 struct iwl_fw_ini_trigger *trigger, 1865 struct list_head *list) 1866 { 1867 int i; 1868 u32 size = 0; 1869 1870 for (i = 0; i < le32_to_cpu(trigger->num_regions); i++) { 1871 u32 reg_id = le32_to_cpu(trigger->data[i]), reg_type; 1872 struct iwl_fw_ini_region_cfg *reg; 1873 1874 if (WARN_ON(reg_id >= ARRAY_SIZE(fwrt->dump.active_regs))) 1875 continue; 1876 1877 reg = fwrt->dump.active_regs[reg_id]; 1878 if (!reg) { 1879 IWL_WARN(fwrt, 1880 "WRT: Unassigned region id %d, skipping\n", 1881 reg_id); 1882 continue; 1883 } 1884 1885 /* currently the driver supports always on domain only */ 1886 if (le32_to_cpu(reg->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON) 1887 continue; 1888 1889 reg_type = le32_to_cpu(reg->region_type); 1890 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 1891 continue; 1892 1893 size += iwl_dump_ini_mem(fwrt, list, reg, 1894 &iwl_dump_ini_region_ops[reg_type]); 1895 } 1896 1897 if (size) 1898 size += iwl_dump_ini_info(fwrt, trigger, list); 1899 1900 return size; 1901 } 1902 1903 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 1904 enum iwl_fw_ini_trigger_id trig_id, 1905 struct list_head *list) 1906 { 1907 struct iwl_fw_ini_dump_entry *entry; 1908 struct iwl_fw_ini_dump_file_hdr *hdr; 1909 struct iwl_fw_ini_trigger *trigger; 1910 u32 size; 1911 1912 if (!iwl_fw_ini_trigger_on(fwrt, trig_id)) 1913 return 0; 1914 1915 trigger = fwrt->dump.active_trigs[trig_id].trig; 1916 if (!trigger || !le32_to_cpu(trigger->num_regions)) 1917 return 0; 1918 1919 entry = kmalloc(sizeof(*entry) + sizeof(*hdr), GFP_KERNEL); 1920 if (!entry) 1921 return 0; 1922 1923 entry->size = sizeof(*hdr); 1924 1925 size = iwl_dump_ini_trigger(fwrt, trigger, list); 1926 if (!size) { 1927 kfree(entry); 1928 return 0; 1929 } 1930 1931 hdr = (void *)entry->data; 1932 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 1933 hdr->file_len = cpu_to_le32(size + entry->size); 1934 1935 list_add(&entry->list, list); 1936 1937 return le32_to_cpu(hdr->file_len); 1938 } 1939 1940 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt) 1941 { 1942 struct iwl_fw_dump_ptrs fw_error_dump = {}; 1943 struct iwl_fw_error_dump_file *dump_file; 1944 struct scatterlist *sg_dump_data; 1945 u32 file_len; 1946 u32 dump_mask = fwrt->fw->dbg.dump_mask; 1947 1948 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump); 1949 if (!dump_file) 1950 goto out; 1951 1952 if (fwrt->dump.monitor_only) 1953 dump_mask &= IWL_FW_ERROR_DUMP_FW_MONITOR; 1954 1955 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask); 1956 file_len = le32_to_cpu(dump_file->file_len); 1957 fw_error_dump.fwrt_len = file_len; 1958 1959 if (fw_error_dump.trans_ptr) { 1960 file_len += fw_error_dump.trans_ptr->len; 1961 dump_file->file_len = cpu_to_le32(file_len); 1962 } 1963 1964 sg_dump_data = alloc_sgtable(file_len); 1965 if (sg_dump_data) { 1966 sg_pcopy_from_buffer(sg_dump_data, 1967 sg_nents(sg_dump_data), 1968 fw_error_dump.fwrt_ptr, 1969 fw_error_dump.fwrt_len, 0); 1970 if (fw_error_dump.trans_ptr) 1971 sg_pcopy_from_buffer(sg_dump_data, 1972 sg_nents(sg_dump_data), 1973 fw_error_dump.trans_ptr->data, 1974 fw_error_dump.trans_ptr->len, 1975 fw_error_dump.fwrt_len); 1976 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 1977 GFP_KERNEL); 1978 } 1979 vfree(fw_error_dump.fwrt_ptr); 1980 vfree(fw_error_dump.trans_ptr); 1981 1982 out: 1983 iwl_fw_free_dump_desc(fwrt); 1984 } 1985 1986 static void iwl_dump_ini_list_free(struct list_head *list) 1987 { 1988 while (!list_empty(list)) { 1989 struct iwl_fw_ini_dump_entry *entry = 1990 list_entry(list->next, typeof(*entry), list); 1991 1992 list_del(&entry->list); 1993 kfree(entry); 1994 } 1995 } 1996 1997 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, u8 wk_idx) 1998 { 1999 enum iwl_fw_ini_trigger_id trig_id = fwrt->dump.wks[wk_idx].ini_trig_id; 2000 struct list_head dump_list = LIST_HEAD_INIT(dump_list); 2001 struct scatterlist *sg_dump_data; 2002 u32 file_len; 2003 2004 file_len = iwl_dump_ini_file_gen(fwrt, trig_id, &dump_list); 2005 if (!file_len) 2006 goto out; 2007 2008 sg_dump_data = alloc_sgtable(file_len); 2009 if (sg_dump_data) { 2010 struct iwl_fw_ini_dump_entry *entry; 2011 int sg_entries = sg_nents(sg_dump_data); 2012 u32 offs = 0; 2013 2014 list_for_each_entry(entry, &dump_list, list) { 2015 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2016 entry->data, entry->size, offs); 2017 offs += entry->size; 2018 } 2019 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2020 GFP_KERNEL); 2021 } 2022 iwl_dump_ini_list_free(&dump_list); 2023 2024 out: 2025 fwrt->dump.wks[wk_idx].ini_trig_id = IWL_FW_TRIGGER_ID_INVALID; 2026 } 2027 2028 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2029 .trig_desc = { 2030 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2031 }, 2032 }; 2033 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2034 2035 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2036 const struct iwl_fw_dump_desc *desc, 2037 bool monitor_only, 2038 unsigned int delay) 2039 { 2040 u32 trig_type = le32_to_cpu(desc->trig_desc.type); 2041 int ret; 2042 2043 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2044 ret = iwl_fw_dbg_ini_collect(fwrt, trig_type); 2045 if (!ret) 2046 iwl_fw_free_dump_desc(fwrt); 2047 2048 return ret; 2049 } 2050 2051 /* use wks[0] since dump flow prior to ini does not need to support 2052 * consecutive triggers collection 2053 */ 2054 if (test_and_set_bit(fwrt->dump.wks[0].idx, &fwrt->dump.active_wks)) 2055 return -EBUSY; 2056 2057 if (WARN_ON(fwrt->dump.desc)) 2058 iwl_fw_free_dump_desc(fwrt); 2059 2060 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2061 le32_to_cpu(desc->trig_desc.type)); 2062 2063 fwrt->dump.desc = desc; 2064 fwrt->dump.monitor_only = monitor_only; 2065 2066 schedule_delayed_work(&fwrt->dump.wks[0].wk, usecs_to_jiffies(delay)); 2067 2068 return 0; 2069 } 2070 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2071 2072 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2073 enum iwl_fw_dbg_trigger trig_type) 2074 { 2075 int ret; 2076 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2077 2078 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2079 return -EIO; 2080 2081 iwl_dump_error_desc = kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2082 if (!iwl_dump_error_desc) 2083 return -ENOMEM; 2084 2085 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2086 iwl_dump_error_desc->len = 0; 2087 2088 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, false, 0); 2089 if (ret) 2090 kfree(iwl_dump_error_desc); 2091 else 2092 iwl_trans_sync_nmi(fwrt->trans); 2093 2094 return ret; 2095 } 2096 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2097 2098 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2099 enum iwl_fw_dbg_trigger trig, 2100 const char *str, size_t len, 2101 struct iwl_fw_dbg_trigger_tlv *trigger) 2102 { 2103 struct iwl_fw_dump_desc *desc; 2104 unsigned int delay = 0; 2105 bool monitor_only = false; 2106 2107 if (trigger) { 2108 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2109 2110 if (!le16_to_cpu(trigger->occurrences)) 2111 return 0; 2112 2113 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2114 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2115 trig); 2116 iwl_force_nmi(fwrt->trans); 2117 return 0; 2118 } 2119 2120 trigger->occurrences = cpu_to_le16(occurrences); 2121 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2122 2123 /* convert msec to usec */ 2124 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2125 } 2126 2127 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 2128 if (!desc) 2129 return -ENOMEM; 2130 2131 2132 desc->len = len; 2133 desc->trig_desc.type = cpu_to_le32(trig); 2134 memcpy(desc->trig_desc.data, str, len); 2135 2136 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2137 } 2138 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2139 2140 int _iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 2141 enum iwl_fw_ini_trigger_id id) 2142 { 2143 struct iwl_fw_ini_active_triggers *active; 2144 u32 occur, delay; 2145 unsigned long idx; 2146 2147 if (WARN_ON(!iwl_fw_ini_trigger_on(fwrt, id))) 2148 return -EINVAL; 2149 2150 if (!iwl_fw_ini_trigger_on(fwrt, id)) { 2151 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 2152 id); 2153 return -EINVAL; 2154 } 2155 2156 active = &fwrt->dump.active_trigs[id]; 2157 delay = le32_to_cpu(active->trig->dump_delay); 2158 occur = le32_to_cpu(active->trig->occurrences); 2159 if (!occur) 2160 return 0; 2161 2162 active->trig->occurrences = cpu_to_le32(--occur); 2163 2164 if (le32_to_cpu(active->trig->force_restart)) { 2165 IWL_WARN(fwrt, "WRT: Force restart: trigger %d fired.\n", id); 2166 iwl_force_nmi(fwrt->trans); 2167 return 0; 2168 } 2169 2170 /* Check there is an available worker. 2171 * ffz return value is undefined if no zero exists, 2172 * so check against ~0UL first. 2173 */ 2174 if (fwrt->dump.active_wks == ~0UL) 2175 return -EBUSY; 2176 2177 idx = ffz(fwrt->dump.active_wks); 2178 2179 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2180 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2181 return -EBUSY; 2182 2183 fwrt->dump.wks[idx].ini_trig_id = id; 2184 2185 IWL_WARN(fwrt, "WRT: Collecting data: ini trigger %d fired.\n", id); 2186 2187 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay)); 2188 2189 return 0; 2190 } 2191 IWL_EXPORT_SYMBOL(_iwl_fw_dbg_ini_collect); 2192 2193 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, u32 legacy_trigger_id) 2194 { 2195 int id; 2196 2197 switch (legacy_trigger_id) { 2198 case FW_DBG_TRIGGER_FW_ASSERT: 2199 case FW_DBG_TRIGGER_ALIVE_TIMEOUT: 2200 case FW_DBG_TRIGGER_DRIVER: 2201 id = IWL_FW_TRIGGER_ID_FW_ASSERT; 2202 break; 2203 case FW_DBG_TRIGGER_USER: 2204 id = IWL_FW_TRIGGER_ID_USER_TRIGGER; 2205 break; 2206 default: 2207 return -EIO; 2208 } 2209 2210 return _iwl_fw_dbg_ini_collect(fwrt, id); 2211 } 2212 IWL_EXPORT_SYMBOL(iwl_fw_dbg_ini_collect); 2213 2214 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2215 struct iwl_fw_dbg_trigger_tlv *trigger, 2216 const char *fmt, ...) 2217 { 2218 int ret, len = 0; 2219 char buf[64]; 2220 2221 if (fmt) { 2222 va_list ap; 2223 2224 buf[sizeof(buf) - 1] = '\0'; 2225 2226 va_start(ap, fmt); 2227 vsnprintf(buf, sizeof(buf), fmt, ap); 2228 va_end(ap); 2229 2230 /* check for truncation */ 2231 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2232 buf[sizeof(buf) - 1] = '\0'; 2233 2234 len = strlen(buf) + 1; 2235 } 2236 2237 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2238 trigger); 2239 2240 if (ret) 2241 return ret; 2242 2243 return 0; 2244 } 2245 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2246 2247 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2248 { 2249 u8 *ptr; 2250 int ret; 2251 int i; 2252 2253 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 2254 "Invalid configuration %d\n", conf_id)) 2255 return -EINVAL; 2256 2257 /* EARLY START - firmware's configuration is hard coded */ 2258 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 2259 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 2260 conf_id == FW_DBG_START_FROM_ALIVE) 2261 return 0; 2262 2263 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 2264 return -EINVAL; 2265 2266 if (fwrt->dump.conf != FW_DBG_INVALID) 2267 IWL_WARN(fwrt, "FW already configured (%d) - re-configuring\n", 2268 fwrt->dump.conf); 2269 2270 /* Send all HCMDs for configuring the FW debug */ 2271 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 2272 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 2273 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 2274 struct iwl_host_cmd hcmd = { 2275 .id = cmd->id, 2276 .len = { le16_to_cpu(cmd->len), }, 2277 .data = { cmd->data, }, 2278 }; 2279 2280 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 2281 if (ret) 2282 return ret; 2283 2284 ptr += sizeof(*cmd); 2285 ptr += le16_to_cpu(cmd->len); 2286 } 2287 2288 fwrt->dump.conf = conf_id; 2289 2290 return 0; 2291 } 2292 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 2293 2294 /* this function assumes dump_start was called beforehand and dump_end will be 2295 * called afterwards 2296 */ 2297 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 2298 { 2299 struct iwl_fw_dbg_params params = {0}; 2300 2301 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 2302 return; 2303 2304 if (fwrt->ops && fwrt->ops->fw_running && 2305 !fwrt->ops->fw_running(fwrt->ops_ctx)) { 2306 IWL_ERR(fwrt, "Firmware not running - cannot dump error\n"); 2307 iwl_fw_free_dump_desc(fwrt); 2308 goto out; 2309 } 2310 2311 /* there's no point in fw dump if the bus is dead */ 2312 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 2313 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 2314 goto out; 2315 } 2316 2317 if (iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true)) { 2318 IWL_ERR(fwrt, "Failed to stop DBGC recording, aborting dump\n"); 2319 goto out; 2320 } 2321 2322 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 2323 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2324 iwl_fw_error_ini_dump(fwrt, wk_idx); 2325 else 2326 iwl_fw_error_dump(fwrt); 2327 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 2328 2329 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 2330 2331 out: 2332 clear_bit(wk_idx, &fwrt->dump.active_wks); 2333 } 2334 2335 void iwl_fw_error_dump_wk(struct work_struct *work) 2336 { 2337 struct iwl_fw_runtime *fwrt; 2338 typeof(fwrt->dump.wks[0]) *wks; 2339 2340 wks = container_of(work, typeof(fwrt->dump.wks[0]), wk.work); 2341 fwrt = container_of(wks, struct iwl_fw_runtime, dump.wks[wks->idx]); 2342 2343 /* assumes the op mode mutex is locked in dump_start since 2344 * iwl_fw_dbg_collect_sync can't run in parallel 2345 */ 2346 if (fwrt->ops && fwrt->ops->dump_start && 2347 fwrt->ops->dump_start(fwrt->ops_ctx)) 2348 return; 2349 2350 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 2351 2352 if (fwrt->ops && fwrt->ops->dump_end) 2353 fwrt->ops->dump_end(fwrt->ops_ctx); 2354 } 2355 2356 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 2357 { 2358 const struct iwl_cfg *cfg = fwrt->trans->cfg; 2359 2360 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 2361 return; 2362 2363 if (!fwrt->dump.d3_debug_data) { 2364 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 2365 GFP_KERNEL); 2366 if (!fwrt->dump.d3_debug_data) { 2367 IWL_ERR(fwrt, 2368 "failed to allocate memory for D3 debug data\n"); 2369 return; 2370 } 2371 } 2372 2373 /* if the buffer holds previous debug data it is overwritten */ 2374 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 2375 fwrt->dump.d3_debug_data, 2376 cfg->d3_debug_data_length); 2377 } 2378 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 2379 2380 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 2381 { 2382 int i; 2383 2384 iwl_dbg_tlv_del_timers(fwrt->trans); 2385 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 2386 iwl_fw_dbg_collect_sync(fwrt, i); 2387 2388 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 2389 } 2390 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 2391 2392 #define FSEQ_REG(x) { .addr = (x), .str = #x, } 2393 2394 void iwl_fw_error_print_fseq_regs(struct iwl_fw_runtime *fwrt) 2395 { 2396 struct iwl_trans *trans = fwrt->trans; 2397 unsigned long flags; 2398 int i; 2399 struct { 2400 u32 addr; 2401 const char *str; 2402 } fseq_regs[] = { 2403 FSEQ_REG(FSEQ_ERROR_CODE), 2404 FSEQ_REG(FSEQ_TOP_INIT_VERSION), 2405 FSEQ_REG(FSEQ_CNVIO_INIT_VERSION), 2406 FSEQ_REG(FSEQ_OTP_VERSION), 2407 FSEQ_REG(FSEQ_TOP_CONTENT_VERSION), 2408 FSEQ_REG(FSEQ_ALIVE_TOKEN), 2409 FSEQ_REG(FSEQ_CNVI_ID), 2410 FSEQ_REG(FSEQ_CNVR_ID), 2411 FSEQ_REG(CNVI_AUX_MISC_CHIP), 2412 FSEQ_REG(CNVR_AUX_MISC_CHIP), 2413 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM), 2414 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR), 2415 }; 2416 2417 if (!iwl_trans_grab_nic_access(trans, &flags)) 2418 return; 2419 2420 IWL_ERR(fwrt, "Fseq Registers:\n"); 2421 2422 for (i = 0; i < ARRAY_SIZE(fseq_regs); i++) 2423 IWL_ERR(fwrt, "0x%08X | %s\n", 2424 iwl_read_prph_no_grab(trans, fseq_regs[i].addr), 2425 fseq_regs[i].str); 2426 2427 iwl_trans_release_nic_access(trans, &flags); 2428 } 2429 IWL_EXPORT_SYMBOL(iwl_fw_error_print_fseq_regs); 2430 2431 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 2432 { 2433 struct iwl_dbg_suspend_resume_cmd cmd = { 2434 .operation = suspend ? 2435 cpu_to_le32(DBGC_SUSPEND_CMD) : 2436 cpu_to_le32(DBGC_RESUME_CMD), 2437 }; 2438 struct iwl_host_cmd hcmd = { 2439 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 2440 .data[0] = &cmd, 2441 .len[0] = sizeof(cmd), 2442 }; 2443 2444 return iwl_trans_send_cmd(trans, &hcmd); 2445 } 2446 2447 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 2448 struct iwl_fw_dbg_params *params) 2449 { 2450 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 2451 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 2452 return; 2453 } 2454 2455 if (params) { 2456 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 2457 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 2458 } 2459 2460 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 2461 /* wait for the DBGC to finish writing the internal buffer to DRAM to 2462 * avoid halting the HW while writing 2463 */ 2464 usleep_range(700, 1000); 2465 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 2466 } 2467 2468 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 2469 struct iwl_fw_dbg_params *params) 2470 { 2471 if (!params) 2472 return -EIO; 2473 2474 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 2475 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 2476 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 2477 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 2478 } else { 2479 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 2480 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 2481 } 2482 2483 return 0; 2484 } 2485 2486 int iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 2487 struct iwl_fw_dbg_params *params, 2488 bool stop) 2489 { 2490 int ret = 0; 2491 2492 /* if the FW crashed or not debug monitor cfg was given, there is 2493 * no point in changing the recording state 2494 */ 2495 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status) || 2496 (!fwrt->trans->dbg.dest_tlv && 2497 fwrt->trans->dbg.ini_dest == IWL_FW_INI_LOCATION_INVALID)) 2498 return 0; 2499 2500 if (fw_has_capa(&fwrt->fw->ucode_capa, 2501 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) 2502 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 2503 else if (stop) 2504 iwl_fw_dbg_stop_recording(fwrt->trans, params); 2505 else 2506 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 2507 #ifdef CONFIG_IWLWIFI_DEBUGFS 2508 if (!ret) { 2509 if (stop) 2510 fwrt->trans->dbg.rec_on = false; 2511 else 2512 iwl_fw_set_dbg_rec_on(fwrt); 2513 } 2514 #endif 2515 2516 return ret; 2517 } 2518 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 2519