1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #include <linux/devcoredump.h> 65 #include "iwl-drv.h" 66 #include "runtime.h" 67 #include "dbg.h" 68 #include "debugfs.h" 69 #include "iwl-io.h" 70 #include "iwl-prph.h" 71 #include "iwl-csr.h" 72 73 /** 74 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 75 * 76 * @fwrt_ptr: pointer to the buffer coming from fwrt 77 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 78 * transport's data. 79 * @trans_len: length of the valid data in trans_ptr 80 * @fwrt_len: length of the valid data in fwrt_ptr 81 */ 82 struct iwl_fw_dump_ptrs { 83 struct iwl_trans_dump_data *trans_ptr; 84 void *fwrt_ptr; 85 u32 fwrt_len; 86 }; 87 88 #define RADIO_REG_MAX_READ 0x2ad 89 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 90 struct iwl_fw_error_dump_data **dump_data) 91 { 92 u8 *pos = (void *)(*dump_data)->data; 93 unsigned long flags; 94 int i; 95 96 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 97 98 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 99 return; 100 101 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 102 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 103 104 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 105 u32 rd_cmd = RADIO_RSP_RD_CMD; 106 107 rd_cmd |= i << RADIO_RSP_ADDR_POS; 108 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 109 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 110 111 pos++; 112 } 113 114 *dump_data = iwl_fw_error_next_data(*dump_data); 115 116 iwl_trans_release_nic_access(fwrt->trans, &flags); 117 } 118 119 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 120 struct iwl_fw_error_dump_data **dump_data, 121 int size, u32 offset, int fifo_num) 122 { 123 struct iwl_fw_error_dump_fifo *fifo_hdr; 124 u32 *fifo_data; 125 u32 fifo_len; 126 int i; 127 128 fifo_hdr = (void *)(*dump_data)->data; 129 fifo_data = (void *)fifo_hdr->data; 130 fifo_len = size; 131 132 /* No need to try to read the data if the length is 0 */ 133 if (fifo_len == 0) 134 return; 135 136 /* Add a TLV for the RXF */ 137 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 138 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 139 140 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 141 fifo_hdr->available_bytes = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 RXF_RD_D_SPACE + offset)); 144 fifo_hdr->wr_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 RXF_RD_WR_PTR + offset)); 147 fifo_hdr->rd_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 RXF_RD_RD_PTR + offset)); 150 fifo_hdr->fence_ptr = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 RXF_RD_FENCE_PTR + offset)); 153 fifo_hdr->fence_mode = 154 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 155 RXF_SET_FENCE_MODE + offset)); 156 157 /* Lock fence */ 158 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 159 /* Set fence pointer to the same place like WR pointer */ 160 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 161 /* Set fence offset */ 162 iwl_trans_write_prph(fwrt->trans, 163 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 164 165 /* Read FIFO */ 166 fifo_len /= sizeof(u32); /* Size in DWORDS */ 167 for (i = 0; i < fifo_len; i++) 168 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 169 RXF_FIFO_RD_FENCE_INC + 170 offset); 171 *dump_data = iwl_fw_error_next_data(*dump_data); 172 } 173 174 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 175 struct iwl_fw_error_dump_data **dump_data, 176 int size, u32 offset, int fifo_num) 177 { 178 struct iwl_fw_error_dump_fifo *fifo_hdr; 179 u32 *fifo_data; 180 u32 fifo_len; 181 int i; 182 183 fifo_hdr = (void *)(*dump_data)->data; 184 fifo_data = (void *)fifo_hdr->data; 185 fifo_len = size; 186 187 /* No need to try to read the data if the length is 0 */ 188 if (fifo_len == 0) 189 return; 190 191 /* Add a TLV for the FIFO */ 192 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 193 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 194 195 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 196 fifo_hdr->available_bytes = 197 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 198 TXF_FIFO_ITEM_CNT + offset)); 199 fifo_hdr->wr_ptr = 200 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 201 TXF_WR_PTR + offset)); 202 fifo_hdr->rd_ptr = 203 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 204 TXF_RD_PTR + offset)); 205 fifo_hdr->fence_ptr = 206 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 207 TXF_FENCE_PTR + offset)); 208 fifo_hdr->fence_mode = 209 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 210 TXF_LOCK_FENCE + offset)); 211 212 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 213 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 214 TXF_WR_PTR + offset); 215 216 /* Dummy-read to advance the read pointer to the head */ 217 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 218 219 /* Read FIFO */ 220 fifo_len /= sizeof(u32); /* Size in DWORDS */ 221 for (i = 0; i < fifo_len; i++) 222 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 223 TXF_READ_MODIFY_DATA + 224 offset); 225 *dump_data = iwl_fw_error_next_data(*dump_data); 226 } 227 228 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 229 struct iwl_fw_error_dump_data **dump_data) 230 { 231 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 232 unsigned long flags; 233 234 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 235 236 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 237 return; 238 239 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 240 /* Pull RXF1 */ 241 iwl_fwrt_dump_rxf(fwrt, dump_data, 242 cfg->lmac[0].rxfifo1_size, 0, 0); 243 /* Pull RXF2 */ 244 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 245 RXF_DIFF_FROM_PREV + 246 fwrt->trans->cfg->umac_prph_offset, 1); 247 /* Pull LMAC2 RXF1 */ 248 if (fwrt->smem_cfg.num_lmacs > 1) 249 iwl_fwrt_dump_rxf(fwrt, dump_data, 250 cfg->lmac[1].rxfifo1_size, 251 LMAC2_PRPH_OFFSET, 2); 252 } 253 254 iwl_trans_release_nic_access(fwrt->trans, &flags); 255 } 256 257 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 258 struct iwl_fw_error_dump_data **dump_data) 259 { 260 struct iwl_fw_error_dump_fifo *fifo_hdr; 261 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 262 u32 *fifo_data; 263 u32 fifo_len; 264 unsigned long flags; 265 int i, j; 266 267 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 268 269 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 270 return; 271 272 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 273 /* Pull TXF data from LMAC1 */ 274 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 275 /* Mark the number of TXF we're pulling now */ 276 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 277 iwl_fwrt_dump_txf(fwrt, dump_data, 278 cfg->lmac[0].txfifo_size[i], 0, i); 279 } 280 281 /* Pull TXF data from LMAC2 */ 282 if (fwrt->smem_cfg.num_lmacs > 1) { 283 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 284 i++) { 285 /* Mark the number of TXF we're pulling now */ 286 iwl_trans_write_prph(fwrt->trans, 287 TXF_LARC_NUM + 288 LMAC2_PRPH_OFFSET, i); 289 iwl_fwrt_dump_txf(fwrt, dump_data, 290 cfg->lmac[1].txfifo_size[i], 291 LMAC2_PRPH_OFFSET, 292 i + cfg->num_txfifo_entries); 293 } 294 } 295 } 296 297 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 298 fw_has_capa(&fwrt->fw->ucode_capa, 299 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 300 /* Pull UMAC internal TXF data from all TXFs */ 301 for (i = 0; 302 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 303 i++) { 304 fifo_hdr = (void *)(*dump_data)->data; 305 fifo_data = (void *)fifo_hdr->data; 306 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 307 308 /* No need to try to read the data if the length is 0 */ 309 if (fifo_len == 0) 310 continue; 311 312 /* Add a TLV for the internal FIFOs */ 313 (*dump_data)->type = 314 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 315 (*dump_data)->len = 316 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 317 318 fifo_hdr->fifo_num = cpu_to_le32(i); 319 320 /* Mark the number of TXF we're pulling now */ 321 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 322 fwrt->smem_cfg.num_txfifo_entries); 323 324 fifo_hdr->available_bytes = 325 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 326 TXF_CPU2_FIFO_ITEM_CNT)); 327 fifo_hdr->wr_ptr = 328 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 329 TXF_CPU2_WR_PTR)); 330 fifo_hdr->rd_ptr = 331 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 332 TXF_CPU2_RD_PTR)); 333 fifo_hdr->fence_ptr = 334 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 335 TXF_CPU2_FENCE_PTR)); 336 fifo_hdr->fence_mode = 337 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 338 TXF_CPU2_LOCK_FENCE)); 339 340 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 341 iwl_trans_write_prph(fwrt->trans, 342 TXF_CPU2_READ_MODIFY_ADDR, 343 TXF_CPU2_WR_PTR); 344 345 /* Dummy-read to advance the read pointer to head */ 346 iwl_trans_read_prph(fwrt->trans, 347 TXF_CPU2_READ_MODIFY_DATA); 348 349 /* Read FIFO */ 350 fifo_len /= sizeof(u32); /* Size in DWORDS */ 351 for (j = 0; j < fifo_len; j++) 352 fifo_data[j] = 353 iwl_trans_read_prph(fwrt->trans, 354 TXF_CPU2_READ_MODIFY_DATA); 355 *dump_data = iwl_fw_error_next_data(*dump_data); 356 } 357 } 358 359 iwl_trans_release_nic_access(fwrt->trans, &flags); 360 } 361 362 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ 363 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ 364 365 struct iwl_prph_range { 366 u32 start, end; 367 }; 368 369 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 370 { .start = 0x00a00000, .end = 0x00a00000 }, 371 { .start = 0x00a0000c, .end = 0x00a00024 }, 372 { .start = 0x00a0002c, .end = 0x00a0003c }, 373 { .start = 0x00a00410, .end = 0x00a00418 }, 374 { .start = 0x00a00420, .end = 0x00a00420 }, 375 { .start = 0x00a00428, .end = 0x00a00428 }, 376 { .start = 0x00a00430, .end = 0x00a0043c }, 377 { .start = 0x00a00444, .end = 0x00a00444 }, 378 { .start = 0x00a004c0, .end = 0x00a004cc }, 379 { .start = 0x00a004d8, .end = 0x00a004d8 }, 380 { .start = 0x00a004e0, .end = 0x00a004f0 }, 381 { .start = 0x00a00840, .end = 0x00a00840 }, 382 { .start = 0x00a00850, .end = 0x00a00858 }, 383 { .start = 0x00a01004, .end = 0x00a01008 }, 384 { .start = 0x00a01010, .end = 0x00a01010 }, 385 { .start = 0x00a01018, .end = 0x00a01018 }, 386 { .start = 0x00a01024, .end = 0x00a01024 }, 387 { .start = 0x00a0102c, .end = 0x00a01034 }, 388 { .start = 0x00a0103c, .end = 0x00a01040 }, 389 { .start = 0x00a01048, .end = 0x00a01094 }, 390 { .start = 0x00a01c00, .end = 0x00a01c20 }, 391 { .start = 0x00a01c58, .end = 0x00a01c58 }, 392 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 393 { .start = 0x00a01c28, .end = 0x00a01c54 }, 394 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 395 { .start = 0x00a01c60, .end = 0x00a01cdc }, 396 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 397 { .start = 0x00a01d18, .end = 0x00a01d20 }, 398 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 399 { .start = 0x00a01d40, .end = 0x00a01d5c }, 400 { .start = 0x00a01d80, .end = 0x00a01d80 }, 401 { .start = 0x00a01d98, .end = 0x00a01d9c }, 402 { .start = 0x00a01da8, .end = 0x00a01da8 }, 403 { .start = 0x00a01db8, .end = 0x00a01df4 }, 404 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 405 { .start = 0x00a01e00, .end = 0x00a01e2c }, 406 { .start = 0x00a01e40, .end = 0x00a01e60 }, 407 { .start = 0x00a01e68, .end = 0x00a01e6c }, 408 { .start = 0x00a01e74, .end = 0x00a01e74 }, 409 { .start = 0x00a01e84, .end = 0x00a01e90 }, 410 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 411 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 412 { .start = 0x00a01f00, .end = 0x00a01f1c }, 413 { .start = 0x00a01f44, .end = 0x00a01ffc }, 414 { .start = 0x00a02000, .end = 0x00a02048 }, 415 { .start = 0x00a02068, .end = 0x00a020f0 }, 416 { .start = 0x00a02100, .end = 0x00a02118 }, 417 { .start = 0x00a02140, .end = 0x00a0214c }, 418 { .start = 0x00a02168, .end = 0x00a0218c }, 419 { .start = 0x00a021c0, .end = 0x00a021c0 }, 420 { .start = 0x00a02400, .end = 0x00a02410 }, 421 { .start = 0x00a02418, .end = 0x00a02420 }, 422 { .start = 0x00a02428, .end = 0x00a0242c }, 423 { .start = 0x00a02434, .end = 0x00a02434 }, 424 { .start = 0x00a02440, .end = 0x00a02460 }, 425 { .start = 0x00a02468, .end = 0x00a024b0 }, 426 { .start = 0x00a024c8, .end = 0x00a024cc }, 427 { .start = 0x00a02500, .end = 0x00a02504 }, 428 { .start = 0x00a0250c, .end = 0x00a02510 }, 429 { .start = 0x00a02540, .end = 0x00a02554 }, 430 { .start = 0x00a02580, .end = 0x00a025f4 }, 431 { .start = 0x00a02600, .end = 0x00a0260c }, 432 { .start = 0x00a02648, .end = 0x00a02650 }, 433 { .start = 0x00a02680, .end = 0x00a02680 }, 434 { .start = 0x00a026c0, .end = 0x00a026d0 }, 435 { .start = 0x00a02700, .end = 0x00a0270c }, 436 { .start = 0x00a02804, .end = 0x00a02804 }, 437 { .start = 0x00a02818, .end = 0x00a0281c }, 438 { .start = 0x00a02c00, .end = 0x00a02db4 }, 439 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 440 { .start = 0x00a03000, .end = 0x00a03014 }, 441 { .start = 0x00a0301c, .end = 0x00a0302c }, 442 { .start = 0x00a03034, .end = 0x00a03038 }, 443 { .start = 0x00a03040, .end = 0x00a03048 }, 444 { .start = 0x00a03060, .end = 0x00a03068 }, 445 { .start = 0x00a03070, .end = 0x00a03074 }, 446 { .start = 0x00a0307c, .end = 0x00a0307c }, 447 { .start = 0x00a03080, .end = 0x00a03084 }, 448 { .start = 0x00a0308c, .end = 0x00a03090 }, 449 { .start = 0x00a03098, .end = 0x00a03098 }, 450 { .start = 0x00a030a0, .end = 0x00a030a0 }, 451 { .start = 0x00a030a8, .end = 0x00a030b4 }, 452 { .start = 0x00a030bc, .end = 0x00a030bc }, 453 { .start = 0x00a030c0, .end = 0x00a0312c }, 454 { .start = 0x00a03c00, .end = 0x00a03c5c }, 455 { .start = 0x00a04400, .end = 0x00a04454 }, 456 { .start = 0x00a04460, .end = 0x00a04474 }, 457 { .start = 0x00a044c0, .end = 0x00a044ec }, 458 { .start = 0x00a04500, .end = 0x00a04504 }, 459 { .start = 0x00a04510, .end = 0x00a04538 }, 460 { .start = 0x00a04540, .end = 0x00a04548 }, 461 { .start = 0x00a04560, .end = 0x00a0457c }, 462 { .start = 0x00a04590, .end = 0x00a04598 }, 463 { .start = 0x00a045c0, .end = 0x00a045f4 }, 464 }; 465 466 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 467 { .start = 0x00a05c00, .end = 0x00a05c18 }, 468 { .start = 0x00a05400, .end = 0x00a056e8 }, 469 { .start = 0x00a08000, .end = 0x00a098bc }, 470 { .start = 0x00a02400, .end = 0x00a02758 }, 471 }; 472 473 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 474 { .start = 0x00a00000, .end = 0x00a00000 }, 475 { .start = 0x00a0000c, .end = 0x00a00024 }, 476 { .start = 0x00a0002c, .end = 0x00a00034 }, 477 { .start = 0x00a0003c, .end = 0x00a0003c }, 478 { .start = 0x00a00410, .end = 0x00a00418 }, 479 { .start = 0x00a00420, .end = 0x00a00420 }, 480 { .start = 0x00a00428, .end = 0x00a00428 }, 481 { .start = 0x00a00430, .end = 0x00a0043c }, 482 { .start = 0x00a00444, .end = 0x00a00444 }, 483 { .start = 0x00a00840, .end = 0x00a00840 }, 484 { .start = 0x00a00850, .end = 0x00a00858 }, 485 { .start = 0x00a01004, .end = 0x00a01008 }, 486 { .start = 0x00a01010, .end = 0x00a01010 }, 487 { .start = 0x00a01018, .end = 0x00a01018 }, 488 { .start = 0x00a01024, .end = 0x00a01024 }, 489 { .start = 0x00a0102c, .end = 0x00a01034 }, 490 { .start = 0x00a0103c, .end = 0x00a01040 }, 491 { .start = 0x00a01048, .end = 0x00a01050 }, 492 { .start = 0x00a01058, .end = 0x00a01058 }, 493 { .start = 0x00a01060, .end = 0x00a01070 }, 494 { .start = 0x00a0108c, .end = 0x00a0108c }, 495 { .start = 0x00a01c20, .end = 0x00a01c28 }, 496 { .start = 0x00a01d10, .end = 0x00a01d10 }, 497 { .start = 0x00a01e28, .end = 0x00a01e2c }, 498 { .start = 0x00a01e60, .end = 0x00a01e60 }, 499 { .start = 0x00a01e80, .end = 0x00a01e80 }, 500 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 501 { .start = 0x00a02000, .end = 0x00a0201c }, 502 { .start = 0x00a02024, .end = 0x00a02024 }, 503 { .start = 0x00a02040, .end = 0x00a02048 }, 504 { .start = 0x00a020c0, .end = 0x00a020e0 }, 505 { .start = 0x00a02400, .end = 0x00a02404 }, 506 { .start = 0x00a0240c, .end = 0x00a02414 }, 507 { .start = 0x00a0241c, .end = 0x00a0243c }, 508 { .start = 0x00a02448, .end = 0x00a024bc }, 509 { .start = 0x00a024c4, .end = 0x00a024cc }, 510 { .start = 0x00a02508, .end = 0x00a02508 }, 511 { .start = 0x00a02510, .end = 0x00a02514 }, 512 { .start = 0x00a0251c, .end = 0x00a0251c }, 513 { .start = 0x00a0252c, .end = 0x00a0255c }, 514 { .start = 0x00a02564, .end = 0x00a025a0 }, 515 { .start = 0x00a025a8, .end = 0x00a025b4 }, 516 { .start = 0x00a025c0, .end = 0x00a025c0 }, 517 { .start = 0x00a025e8, .end = 0x00a025f4 }, 518 { .start = 0x00a02c08, .end = 0x00a02c18 }, 519 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 520 { .start = 0x00a02c68, .end = 0x00a02c78 }, 521 { .start = 0x00a03000, .end = 0x00a03000 }, 522 { .start = 0x00a03010, .end = 0x00a03014 }, 523 { .start = 0x00a0301c, .end = 0x00a0302c }, 524 { .start = 0x00a03034, .end = 0x00a03038 }, 525 { .start = 0x00a03040, .end = 0x00a03044 }, 526 { .start = 0x00a03060, .end = 0x00a03068 }, 527 { .start = 0x00a03070, .end = 0x00a03070 }, 528 { .start = 0x00a0307c, .end = 0x00a03084 }, 529 { .start = 0x00a0308c, .end = 0x00a03090 }, 530 { .start = 0x00a03098, .end = 0x00a03098 }, 531 { .start = 0x00a030a0, .end = 0x00a030a0 }, 532 { .start = 0x00a030a8, .end = 0x00a030b4 }, 533 { .start = 0x00a030bc, .end = 0x00a030c0 }, 534 { .start = 0x00a030c8, .end = 0x00a030f4 }, 535 { .start = 0x00a03100, .end = 0x00a0312c }, 536 { .start = 0x00a03c00, .end = 0x00a03c5c }, 537 { .start = 0x00a04400, .end = 0x00a04454 }, 538 { .start = 0x00a04460, .end = 0x00a04474 }, 539 { .start = 0x00a044c0, .end = 0x00a044ec }, 540 { .start = 0x00a04500, .end = 0x00a04504 }, 541 { .start = 0x00a04510, .end = 0x00a04538 }, 542 { .start = 0x00a04540, .end = 0x00a04548 }, 543 { .start = 0x00a04560, .end = 0x00a04560 }, 544 { .start = 0x00a04570, .end = 0x00a0457c }, 545 { .start = 0x00a04590, .end = 0x00a04590 }, 546 { .start = 0x00a04598, .end = 0x00a04598 }, 547 { .start = 0x00a045c0, .end = 0x00a045f4 }, 548 { .start = 0x00a0c000, .end = 0x00a0c018 }, 549 { .start = 0x00a0c020, .end = 0x00a0c028 }, 550 { .start = 0x00a0c038, .end = 0x00a0c094 }, 551 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 552 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 553 { .start = 0x00a0c150, .end = 0x00a0c174 }, 554 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 555 { .start = 0x00a0c190, .end = 0x00a0c198 }, 556 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 557 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 558 }; 559 560 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 561 u32 len_bytes, __le32 *data) 562 { 563 u32 i; 564 565 for (i = 0; i < len_bytes; i += 4) 566 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 567 } 568 569 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 570 const struct iwl_prph_range *iwl_prph_dump_addr, 571 u32 range_len, void *ptr) 572 { 573 struct iwl_fw_error_dump_prph *prph; 574 struct iwl_trans *trans = fwrt->trans; 575 struct iwl_fw_error_dump_data **data = 576 (struct iwl_fw_error_dump_data **)ptr; 577 unsigned long flags; 578 u32 i; 579 580 if (!data) 581 return; 582 583 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 584 585 if (!iwl_trans_grab_nic_access(trans, &flags)) 586 return; 587 588 for (i = 0; i < range_len; i++) { 589 /* The range includes both boundaries */ 590 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 591 iwl_prph_dump_addr[i].start + 4; 592 593 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 594 (*data)->len = cpu_to_le32(sizeof(*prph) + 595 num_bytes_in_chunk); 596 prph = (void *)(*data)->data; 597 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 598 599 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 600 /* our range is inclusive, hence + 4 */ 601 iwl_prph_dump_addr[i].end - 602 iwl_prph_dump_addr[i].start + 4, 603 (void *)prph->data); 604 605 *data = iwl_fw_error_next_data(*data); 606 } 607 608 iwl_trans_release_nic_access(trans, &flags); 609 } 610 611 /* 612 * alloc_sgtable - allocates scallerlist table in the given size, 613 * fills it with pages and returns it 614 * @size: the size (in bytes) of the table 615 */ 616 static struct scatterlist *alloc_sgtable(int size) 617 { 618 int alloc_size, nents, i; 619 struct page *new_page; 620 struct scatterlist *iter; 621 struct scatterlist *table; 622 623 nents = DIV_ROUND_UP(size, PAGE_SIZE); 624 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 625 if (!table) 626 return NULL; 627 sg_init_table(table, nents); 628 iter = table; 629 for_each_sg(table, iter, sg_nents(table), i) { 630 new_page = alloc_page(GFP_KERNEL); 631 if (!new_page) { 632 /* release all previous allocated pages in the table */ 633 iter = table; 634 for_each_sg(table, iter, sg_nents(table), i) { 635 new_page = sg_page(iter); 636 if (new_page) 637 __free_page(new_page); 638 } 639 return NULL; 640 } 641 alloc_size = min_t(int, size, PAGE_SIZE); 642 size -= PAGE_SIZE; 643 sg_set_page(iter, new_page, alloc_size, 0); 644 } 645 return table; 646 } 647 648 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 649 const struct iwl_prph_range *iwl_prph_dump_addr, 650 u32 range_len, void *ptr) 651 { 652 u32 *prph_len = (u32 *)ptr; 653 int i, num_bytes_in_chunk; 654 655 if (!prph_len) 656 return; 657 658 for (i = 0; i < range_len; i++) { 659 /* The range includes both boundaries */ 660 num_bytes_in_chunk = 661 iwl_prph_dump_addr[i].end - 662 iwl_prph_dump_addr[i].start + 4; 663 664 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 665 sizeof(struct iwl_fw_error_dump_prph) + 666 num_bytes_in_chunk; 667 } 668 } 669 670 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 671 void (*handler)(struct iwl_fw_runtime *, 672 const struct iwl_prph_range *, 673 u32, void *)) 674 { 675 u32 range_len; 676 677 if (fwrt->trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 678 /* TODO */ 679 } else if (fwrt->trans->cfg->device_family >= IWL_DEVICE_FAMILY_22000) { 680 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 681 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 682 } else { 683 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 684 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 685 686 if (fwrt->trans->cfg->mq_rx_supported) { 687 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 688 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 689 } 690 } 691 } 692 693 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 694 struct iwl_fw_error_dump_data **dump_data, 695 u32 len, u32 ofs, u32 type) 696 { 697 struct iwl_fw_error_dump_mem *dump_mem; 698 699 if (!len) 700 return; 701 702 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 703 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 704 dump_mem = (void *)(*dump_data)->data; 705 dump_mem->type = cpu_to_le32(type); 706 dump_mem->offset = cpu_to_le32(ofs); 707 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 708 *dump_data = iwl_fw_error_next_data(*dump_data); 709 710 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 711 } 712 713 #define ADD_LEN(len, item_len, const_len) \ 714 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 715 while (0) 716 717 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 718 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 719 { 720 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 721 sizeof(struct iwl_fw_error_dump_fifo); 722 u32 fifo_len = 0; 723 int i; 724 725 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 726 return 0; 727 728 /* Count RXF2 size */ 729 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 730 731 /* Count RXF1 sizes */ 732 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 733 mem_cfg->num_lmacs = MAX_NUM_LMAC; 734 735 for (i = 0; i < mem_cfg->num_lmacs; i++) 736 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 737 738 return fifo_len; 739 } 740 741 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 742 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 743 { 744 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 745 sizeof(struct iwl_fw_error_dump_fifo); 746 u32 fifo_len = 0; 747 int i; 748 749 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 750 goto dump_internal_txf; 751 752 /* Count TXF sizes */ 753 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 754 mem_cfg->num_lmacs = MAX_NUM_LMAC; 755 756 for (i = 0; i < mem_cfg->num_lmacs; i++) { 757 int j; 758 759 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 760 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 761 hdr_len); 762 } 763 764 dump_internal_txf: 765 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 766 fw_has_capa(&fwrt->fw->ucode_capa, 767 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 768 goto out; 769 770 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 771 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 772 773 out: 774 return fifo_len; 775 } 776 777 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 778 struct iwl_fw_error_dump_data **data) 779 { 780 int i; 781 782 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 783 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 784 struct iwl_fw_error_dump_paging *paging; 785 struct page *pages = 786 fwrt->fw_paging_db[i].fw_paging_block; 787 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 788 789 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 790 (*data)->len = cpu_to_le32(sizeof(*paging) + 791 PAGING_BLOCK_SIZE); 792 paging = (void *)(*data)->data; 793 paging->index = cpu_to_le32(i); 794 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 795 PAGING_BLOCK_SIZE, 796 DMA_BIDIRECTIONAL); 797 memcpy(paging->data, page_address(pages), 798 PAGING_BLOCK_SIZE); 799 dma_sync_single_for_device(fwrt->trans->dev, addr, 800 PAGING_BLOCK_SIZE, 801 DMA_BIDIRECTIONAL); 802 (*data) = iwl_fw_error_next_data(*data); 803 } 804 } 805 806 static struct iwl_fw_error_dump_file * 807 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 808 struct iwl_fw_dump_ptrs *fw_error_dump) 809 { 810 struct iwl_fw_error_dump_file *dump_file; 811 struct iwl_fw_error_dump_data *dump_data; 812 struct iwl_fw_error_dump_info *dump_info; 813 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 814 struct iwl_fw_error_dump_trigger_desc *dump_trig; 815 u32 sram_len, sram_ofs; 816 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 817 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 818 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 819 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 820 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 821 0 : fwrt->trans->cfg->dccm2_len; 822 int i; 823 824 /* SRAM - include stack CCM if driver knows the values for it */ 825 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 826 const struct fw_img *img; 827 828 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 829 return NULL; 830 img = &fwrt->fw->img[fwrt->cur_fw_img]; 831 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 832 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 833 } else { 834 sram_ofs = fwrt->trans->cfg->dccm_offset; 835 sram_len = fwrt->trans->cfg->dccm_len; 836 } 837 838 /* reading RXF/TXF sizes */ 839 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 840 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 841 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 842 843 /* Make room for PRPH registers */ 844 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 845 iwl_fw_prph_handler(fwrt, &prph_len, 846 iwl_fw_get_prph_len); 847 848 if (fwrt->trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 && 849 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 850 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 851 } 852 853 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 854 855 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 856 file_len += sizeof(*dump_data) + sizeof(*dump_info); 857 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 858 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 859 860 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 861 size_t hdr_len = sizeof(*dump_data) + 862 sizeof(struct iwl_fw_error_dump_mem); 863 864 /* Dump SRAM only if no mem_tlvs */ 865 if (!fwrt->fw->dbg.n_mem_tlv) 866 ADD_LEN(file_len, sram_len, hdr_len); 867 868 /* Make room for all mem types that exist */ 869 ADD_LEN(file_len, smem_len, hdr_len); 870 ADD_LEN(file_len, sram2_len, hdr_len); 871 872 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 873 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 874 } 875 876 /* Make room for fw's virtual image pages, if it exists */ 877 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 878 file_len += fwrt->num_of_paging_blk * 879 (sizeof(*dump_data) + 880 sizeof(struct iwl_fw_error_dump_paging) + 881 PAGING_BLOCK_SIZE); 882 883 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 884 file_len += sizeof(*dump_data) + 885 fwrt->trans->cfg->d3_debug_data_length * 2; 886 } 887 888 /* If we only want a monitor dump, reset the file length */ 889 if (fwrt->dump.monitor_only) { 890 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 891 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 892 } 893 894 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 895 fwrt->dump.desc) 896 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 897 fwrt->dump.desc->len; 898 899 dump_file = vzalloc(file_len); 900 if (!dump_file) 901 return NULL; 902 903 fw_error_dump->fwrt_ptr = dump_file; 904 905 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 906 dump_data = (void *)dump_file->data; 907 908 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 909 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 910 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 911 dump_info = (void *)dump_data->data; 912 dump_info->device_family = 913 fwrt->trans->cfg->device_family == 914 IWL_DEVICE_FAMILY_7000 ? 915 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_7) : 916 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_8); 917 dump_info->hw_step = 918 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 919 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 920 sizeof(dump_info->fw_human_readable)); 921 strncpy(dump_info->dev_human_readable, fwrt->trans->cfg->name, 922 sizeof(dump_info->dev_human_readable) - 1); 923 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 924 sizeof(dump_info->bus_human_readable) - 1); 925 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 926 dump_info->lmac_err_id[0] = 927 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 928 if (fwrt->smem_cfg.num_lmacs > 1) 929 dump_info->lmac_err_id[1] = 930 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 931 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 932 933 dump_data = iwl_fw_error_next_data(dump_data); 934 } 935 936 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 937 /* Dump shared memory configuration */ 938 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 939 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 940 dump_smem_cfg = (void *)dump_data->data; 941 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 942 dump_smem_cfg->num_txfifo_entries = 943 cpu_to_le32(mem_cfg->num_txfifo_entries); 944 for (i = 0; i < MAX_NUM_LMAC; i++) { 945 int j; 946 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 947 948 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 949 dump_smem_cfg->lmac[i].txfifo_size[j] = 950 cpu_to_le32(txf_size[j]); 951 dump_smem_cfg->lmac[i].rxfifo1_size = 952 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 953 } 954 dump_smem_cfg->rxfifo2_size = 955 cpu_to_le32(mem_cfg->rxfifo2_size); 956 dump_smem_cfg->internal_txfifo_addr = 957 cpu_to_le32(mem_cfg->internal_txfifo_addr); 958 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 959 dump_smem_cfg->internal_txfifo_size[i] = 960 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 961 } 962 963 dump_data = iwl_fw_error_next_data(dump_data); 964 } 965 966 /* We only dump the FIFOs if the FW is in error state */ 967 if (fifo_len) { 968 iwl_fw_dump_rxf(fwrt, &dump_data); 969 iwl_fw_dump_txf(fwrt, &dump_data); 970 } 971 972 if (radio_len) 973 iwl_read_radio_regs(fwrt, &dump_data); 974 975 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 976 fwrt->dump.desc) { 977 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 978 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 979 fwrt->dump.desc->len); 980 dump_trig = (void *)dump_data->data; 981 memcpy(dump_trig, &fwrt->dump.desc->trig_desc, 982 sizeof(*dump_trig) + fwrt->dump.desc->len); 983 984 dump_data = iwl_fw_error_next_data(dump_data); 985 } 986 987 /* In case we only want monitor dump, skip to dump trasport data */ 988 if (fwrt->dump.monitor_only) 989 goto out; 990 991 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 992 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 993 fwrt->fw->dbg.mem_tlv; 994 995 if (!fwrt->fw->dbg.n_mem_tlv) 996 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 997 IWL_FW_ERROR_DUMP_MEM_SRAM); 998 999 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 1000 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 1001 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 1002 1003 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 1004 le32_to_cpu(fw_dbg_mem[i].data_type)); 1005 } 1006 1007 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 1008 fwrt->trans->cfg->smem_offset, 1009 IWL_FW_ERROR_DUMP_MEM_SMEM); 1010 1011 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 1012 fwrt->trans->cfg->dccm2_offset, 1013 IWL_FW_ERROR_DUMP_MEM_SRAM); 1014 } 1015 1016 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 1017 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 1018 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 1019 1020 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 1021 dump_data->len = cpu_to_le32(data_size * 2); 1022 1023 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 1024 1025 kfree(fwrt->dump.d3_debug_data); 1026 fwrt->dump.d3_debug_data = NULL; 1027 1028 iwl_trans_read_mem_bytes(fwrt->trans, addr, 1029 dump_data->data + data_size, 1030 data_size); 1031 1032 dump_data = iwl_fw_error_next_data(dump_data); 1033 } 1034 1035 /* Dump fw's virtual image */ 1036 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1037 iwl_dump_paging(fwrt, &dump_data); 1038 1039 if (prph_len) 1040 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1041 1042 out: 1043 dump_file->file_len = cpu_to_le32(file_len); 1044 return dump_file; 1045 } 1046 1047 static int iwl_dump_ini_prph_iter(struct iwl_fw_runtime *fwrt, 1048 struct iwl_fw_ini_region_cfg *reg, 1049 void *range_ptr, int idx) 1050 { 1051 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1052 __le32 *val = range->data; 1053 u32 prph_val; 1054 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1055 int i; 1056 1057 range->start_addr = cpu_to_le64(addr); 1058 range->range_data_size = reg->internal.range_data_size; 1059 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) { 1060 prph_val = iwl_read_prph(fwrt->trans, addr + i); 1061 if (prph_val == 0x5a5a5a5a) 1062 return -EBUSY; 1063 *val++ = cpu_to_le32(prph_val); 1064 } 1065 1066 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1067 } 1068 1069 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1070 struct iwl_fw_ini_region_cfg *reg, 1071 void *range_ptr, int idx) 1072 { 1073 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1074 __le32 *val = range->data; 1075 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1076 int i; 1077 1078 range->start_addr = cpu_to_le64(addr); 1079 range->range_data_size = reg->internal.range_data_size; 1080 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) 1081 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1082 1083 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1084 } 1085 1086 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1087 struct iwl_fw_ini_region_cfg *reg, 1088 void *range_ptr, int idx) 1089 { 1090 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1091 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1092 1093 range->start_addr = cpu_to_le64(addr); 1094 range->range_data_size = reg->internal.range_data_size; 1095 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1096 le32_to_cpu(reg->internal.range_data_size)); 1097 1098 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1099 } 1100 1101 static int 1102 iwl_dump_ini_paging_gen2_iter(struct iwl_fw_runtime *fwrt, 1103 struct iwl_fw_ini_region_cfg *reg, 1104 void *range_ptr, int idx) 1105 { 1106 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1107 u32 page_size = fwrt->trans->init_dram.paging[idx].size; 1108 1109 range->start_addr = cpu_to_le64(idx); 1110 range->range_data_size = cpu_to_le32(page_size); 1111 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1112 page_size); 1113 1114 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1115 } 1116 1117 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1118 struct iwl_fw_ini_region_cfg *reg, 1119 void *range_ptr, int idx) 1120 { 1121 /* increase idx by 1 since the pages are from 1 to 1122 * fwrt->num_of_paging_blk + 1 1123 */ 1124 struct page *page = fwrt->fw_paging_db[++idx].fw_paging_block; 1125 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1126 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1127 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1128 1129 range->start_addr = cpu_to_le64(idx); 1130 range->range_data_size = cpu_to_le32(page_size); 1131 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1132 DMA_BIDIRECTIONAL); 1133 memcpy(range->data, page_address(page), page_size); 1134 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1135 DMA_BIDIRECTIONAL); 1136 1137 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1138 } 1139 1140 static int 1141 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1142 struct iwl_fw_ini_region_cfg *reg, void *range_ptr, 1143 int idx) 1144 { 1145 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1146 u32 start_addr = iwl_read_umac_prph(fwrt->trans, 1147 MON_BUFF_BASE_ADDR_VER2); 1148 1149 if (start_addr == 0x5a5a5a5a) 1150 return -EBUSY; 1151 1152 range->start_addr = cpu_to_le64(start_addr); 1153 range->range_data_size = cpu_to_le32(fwrt->trans->fw_mon[idx].size); 1154 1155 memcpy(range->data, fwrt->trans->fw_mon[idx].block, 1156 fwrt->trans->fw_mon[idx].size); 1157 1158 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1159 } 1160 1161 struct iwl_ini_txf_iter_data { 1162 int fifo; 1163 int lmac; 1164 u32 fifo_size; 1165 bool internal_txf; 1166 bool init; 1167 }; 1168 1169 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1170 struct iwl_fw_ini_region_cfg *reg) 1171 { 1172 struct iwl_ini_txf_iter_data *iter = fwrt->dump.fifo_iter; 1173 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1174 int txf_num = cfg->num_txfifo_entries; 1175 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1176 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid1); 1177 1178 if (!iter) 1179 return false; 1180 1181 if (iter->init) { 1182 if (le32_to_cpu(reg->offset) && 1183 WARN_ONCE(cfg->num_lmacs == 1, 1184 "Invalid lmac offset: 0x%x\n", 1185 le32_to_cpu(reg->offset))) 1186 return false; 1187 1188 iter->init = false; 1189 iter->internal_txf = false; 1190 iter->fifo_size = 0; 1191 iter->fifo = -1; 1192 if (le32_to_cpu(reg->offset)) 1193 iter->lmac = 1; 1194 else 1195 iter->lmac = 0; 1196 } 1197 1198 if (!iter->internal_txf) 1199 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1200 iter->fifo_size = 1201 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1202 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1203 return true; 1204 } 1205 1206 iter->internal_txf = true; 1207 1208 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1209 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1210 return false; 1211 1212 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1213 iter->fifo_size = 1214 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1215 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1216 return true; 1217 } 1218 1219 return false; 1220 } 1221 1222 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1223 struct iwl_fw_ini_region_cfg *reg, 1224 void *range_ptr, int idx) 1225 { 1226 struct iwl_fw_ini_fifo_error_dump_range *range = range_ptr; 1227 struct iwl_ini_txf_iter_data *iter; 1228 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1229 u32 offs = le32_to_cpu(reg->offset), addr; 1230 u32 registers_size = 1231 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump); 1232 __le32 *data; 1233 unsigned long flags; 1234 int i; 1235 1236 if (!iwl_ini_txf_iter(fwrt, reg)) 1237 return -EIO; 1238 1239 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1240 return -EBUSY; 1241 1242 iter = fwrt->dump.fifo_iter; 1243 1244 range->fifo_num = cpu_to_le32(iter->fifo); 1245 range->num_of_registers = reg->fifos.num_of_registers; 1246 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1247 1248 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1249 1250 /* 1251 * read txf registers. for each register, write to the dump the 1252 * register address and its value 1253 */ 1254 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { 1255 addr = le32_to_cpu(reg->start_addr[i]) + offs; 1256 1257 reg_dump->addr = cpu_to_le32(addr); 1258 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1259 addr)); 1260 1261 reg_dump++; 1262 } 1263 1264 if (reg->fifos.header_only) { 1265 range->range_data_size = cpu_to_le32(registers_size); 1266 goto out; 1267 } 1268 1269 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1270 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1271 TXF_WR_PTR + offs); 1272 1273 /* Dummy-read to advance the read pointer to the head */ 1274 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1275 1276 /* Read FIFO */ 1277 addr = TXF_READ_MODIFY_DATA + offs; 1278 data = (void *)reg_dump; 1279 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1280 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1281 1282 out: 1283 iwl_trans_release_nic_access(fwrt->trans, &flags); 1284 1285 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1286 } 1287 1288 struct iwl_ini_rxf_data { 1289 u32 fifo_num; 1290 u32 size; 1291 u32 offset; 1292 }; 1293 1294 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1295 struct iwl_fw_ini_region_cfg *reg, 1296 struct iwl_ini_rxf_data *data) 1297 { 1298 u32 fid1 = le32_to_cpu(reg->fifos.fid1); 1299 u32 fid2 = le32_to_cpu(reg->fifos.fid2); 1300 u32 fifo_idx; 1301 1302 if (!data) 1303 return; 1304 1305 memset(data, 0, sizeof(*data)); 1306 1307 if (WARN_ON_ONCE((fid1 && fid2) || (!fid1 && !fid2))) 1308 return; 1309 1310 fifo_idx = ffs(fid1) - 1; 1311 if (fid1 && !WARN_ON_ONCE((~BIT(fifo_idx) & fid1) || 1312 fifo_idx >= MAX_NUM_LMAC)) { 1313 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1314 data->fifo_num = fifo_idx; 1315 return; 1316 } 1317 1318 fifo_idx = ffs(fid2) - 1; 1319 if (fid2 && !WARN_ON_ONCE(fifo_idx != 0)) { 1320 data->size = fwrt->smem_cfg.rxfifo2_size; 1321 data->offset = RXF_DIFF_FROM_PREV; 1322 /* use bit 31 to distinguish between umac and lmac rxf while 1323 * parsing the dump 1324 */ 1325 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1326 return; 1327 } 1328 } 1329 1330 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1331 struct iwl_fw_ini_region_cfg *reg, 1332 void *range_ptr, int idx) 1333 { 1334 struct iwl_fw_ini_fifo_error_dump_range *range = range_ptr; 1335 struct iwl_ini_rxf_data rxf_data; 1336 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1337 u32 offs = le32_to_cpu(reg->offset), addr; 1338 u32 registers_size = 1339 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump); 1340 __le32 *data; 1341 unsigned long flags; 1342 int i; 1343 1344 iwl_ini_get_rxf_data(fwrt, reg, &rxf_data); 1345 if (!rxf_data.size) 1346 return -EIO; 1347 1348 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1349 return -EBUSY; 1350 1351 range->fifo_num = cpu_to_le32(rxf_data.fifo_num); 1352 range->num_of_registers = reg->fifos.num_of_registers; 1353 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1354 1355 /* 1356 * read rxf registers. for each register, write to the dump the 1357 * register address and its value 1358 */ 1359 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { 1360 addr = le32_to_cpu(reg->start_addr[i]) + offs; 1361 1362 reg_dump->addr = cpu_to_le32(addr); 1363 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1364 addr)); 1365 1366 reg_dump++; 1367 } 1368 1369 if (reg->fifos.header_only) { 1370 range->range_data_size = cpu_to_le32(registers_size); 1371 goto out; 1372 } 1373 1374 /* 1375 * region register have absolute value so apply rxf offset after 1376 * reading the registers 1377 */ 1378 offs += rxf_data.offset; 1379 1380 /* Lock fence */ 1381 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1382 /* Set fence pointer to the same place like WR pointer */ 1383 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1384 /* Set fence offset */ 1385 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1386 0x0); 1387 1388 /* Read FIFO */ 1389 addr = RXF_FIFO_RD_FENCE_INC + offs; 1390 data = (void *)reg_dump; 1391 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1392 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1393 1394 out: 1395 iwl_trans_release_nic_access(fwrt->trans, &flags); 1396 1397 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1398 } 1399 1400 static void *iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1401 struct iwl_fw_ini_region_cfg *reg, 1402 void *data) 1403 { 1404 struct iwl_fw_ini_error_dump *dump = data; 1405 1406 dump->header.version = cpu_to_le32(IWL_INI_DUMP_MEM_VER); 1407 1408 return dump->ranges; 1409 } 1410 1411 static void 1412 *iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, 1413 struct iwl_fw_ini_region_cfg *reg, 1414 struct iwl_fw_ini_monitor_dump *data, 1415 u32 write_ptr_addr, u32 write_ptr_msk, 1416 u32 cycle_cnt_addr, u32 cycle_cnt_msk) 1417 { 1418 u32 write_ptr, cycle_cnt; 1419 unsigned long flags; 1420 1421 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) { 1422 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1423 return NULL; 1424 } 1425 1426 write_ptr = iwl_read_prph_no_grab(fwrt->trans, write_ptr_addr); 1427 cycle_cnt = iwl_read_prph_no_grab(fwrt->trans, cycle_cnt_addr); 1428 1429 iwl_trans_release_nic_access(fwrt->trans, &flags); 1430 1431 data->header.version = cpu_to_le32(IWL_INI_DUMP_MONITOR_VER); 1432 data->write_ptr = cpu_to_le32(write_ptr & write_ptr_msk); 1433 data->cycle_cnt = cpu_to_le32(cycle_cnt & cycle_cnt_msk); 1434 1435 return data->ranges; 1436 } 1437 1438 static void 1439 *iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1440 struct iwl_fw_ini_region_cfg *reg, 1441 void *data) 1442 { 1443 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1444 u32 write_ptr_addr, write_ptr_msk, cycle_cnt_addr, cycle_cnt_msk; 1445 1446 switch (fwrt->trans->cfg->device_family) { 1447 case IWL_DEVICE_FAMILY_9000: 1448 case IWL_DEVICE_FAMILY_22000: 1449 write_ptr_addr = MON_BUFF_WRPTR_VER2; 1450 write_ptr_msk = -1; 1451 cycle_cnt_addr = MON_BUFF_CYCLE_CNT_VER2; 1452 cycle_cnt_msk = -1; 1453 break; 1454 default: 1455 IWL_ERR(fwrt, "Unsupported device family %d\n", 1456 fwrt->trans->cfg->device_family); 1457 return NULL; 1458 } 1459 1460 return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, write_ptr_addr, 1461 write_ptr_msk, cycle_cnt_addr, 1462 cycle_cnt_msk); 1463 } 1464 1465 static void 1466 *iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1467 struct iwl_fw_ini_region_cfg *reg, 1468 void *data) 1469 { 1470 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1471 const struct iwl_cfg *cfg = fwrt->trans->cfg; 1472 1473 if (fwrt->trans->cfg->device_family != IWL_DEVICE_FAMILY_9000 && 1474 fwrt->trans->cfg->device_family != IWL_DEVICE_FAMILY_22000) { 1475 IWL_ERR(fwrt, "Unsupported device family %d\n", 1476 fwrt->trans->cfg->device_family); 1477 return NULL; 1478 } 1479 1480 return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, 1481 cfg->fw_mon_smem_write_ptr_addr, 1482 cfg->fw_mon_smem_write_ptr_msk, 1483 cfg->fw_mon_smem_cycle_cnt_ptr_addr, 1484 cfg->fw_mon_smem_cycle_cnt_ptr_msk); 1485 1486 } 1487 1488 static void *iwl_dump_ini_fifo_fill_header(struct iwl_fw_runtime *fwrt, 1489 struct iwl_fw_ini_region_cfg *reg, 1490 void *data) 1491 { 1492 struct iwl_fw_ini_fifo_error_dump *dump = data; 1493 1494 dump->header.version = cpu_to_le32(IWL_INI_DUMP_FIFO_VER); 1495 1496 return dump->ranges; 1497 } 1498 1499 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1500 struct iwl_fw_ini_region_cfg *reg) 1501 { 1502 return le32_to_cpu(reg->internal.num_of_ranges); 1503 } 1504 1505 static u32 iwl_dump_ini_paging_gen2_ranges(struct iwl_fw_runtime *fwrt, 1506 struct iwl_fw_ini_region_cfg *reg) 1507 { 1508 return fwrt->trans->init_dram.paging_cnt; 1509 } 1510 1511 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1512 struct iwl_fw_ini_region_cfg *reg) 1513 { 1514 return fwrt->num_of_paging_blk; 1515 } 1516 1517 static u32 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1518 struct iwl_fw_ini_region_cfg *reg) 1519 { 1520 return 1; 1521 } 1522 1523 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1524 struct iwl_fw_ini_region_cfg *reg) 1525 { 1526 struct iwl_ini_txf_iter_data iter = { .init = true }; 1527 void *fifo_iter = fwrt->dump.fifo_iter; 1528 u32 num_of_fifos = 0; 1529 1530 fwrt->dump.fifo_iter = &iter; 1531 while (iwl_ini_txf_iter(fwrt, reg)) 1532 num_of_fifos++; 1533 1534 fwrt->dump.fifo_iter = fifo_iter; 1535 1536 return num_of_fifos; 1537 } 1538 1539 static u32 iwl_dump_ini_rxf_ranges(struct iwl_fw_runtime *fwrt, 1540 struct iwl_fw_ini_region_cfg *reg) 1541 { 1542 /* Each Rx fifo needs a different offset and therefore, it's 1543 * region can contain only one fifo, i.e. 1 memory range. 1544 */ 1545 return 1; 1546 } 1547 1548 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1549 struct iwl_fw_ini_region_cfg *reg) 1550 { 1551 return sizeof(struct iwl_fw_ini_error_dump) + 1552 iwl_dump_ini_mem_ranges(fwrt, reg) * 1553 (sizeof(struct iwl_fw_ini_error_dump_range) + 1554 le32_to_cpu(reg->internal.range_data_size)); 1555 } 1556 1557 static u32 iwl_dump_ini_paging_gen2_get_size(struct iwl_fw_runtime *fwrt, 1558 struct iwl_fw_ini_region_cfg *reg) 1559 { 1560 int i; 1561 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1562 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1563 1564 for (i = 0; i < iwl_dump_ini_paging_gen2_ranges(fwrt, reg); i++) 1565 size += range_header_len + 1566 fwrt->trans->init_dram.paging[i].size; 1567 1568 return size; 1569 } 1570 1571 static u32 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1572 struct iwl_fw_ini_region_cfg *reg) 1573 { 1574 int i; 1575 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1576 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1577 1578 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg); i++) 1579 size += range_header_len + fwrt->fw_paging_db[i].fw_paging_size; 1580 1581 return size; 1582 } 1583 1584 static u32 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 1585 struct iwl_fw_ini_region_cfg *reg) 1586 { 1587 u32 size = sizeof(struct iwl_fw_ini_monitor_dump) + 1588 sizeof(struct iwl_fw_ini_error_dump_range); 1589 1590 if (fwrt->trans->num_blocks) 1591 size += fwrt->trans->fw_mon[0].size; 1592 1593 return size; 1594 } 1595 1596 static u32 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 1597 struct iwl_fw_ini_region_cfg *reg) 1598 { 1599 return sizeof(struct iwl_fw_ini_monitor_dump) + 1600 iwl_dump_ini_mem_ranges(fwrt, reg) * 1601 (sizeof(struct iwl_fw_ini_error_dump_range) + 1602 le32_to_cpu(reg->internal.range_data_size)); 1603 } 1604 1605 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 1606 struct iwl_fw_ini_region_cfg *reg) 1607 { 1608 struct iwl_ini_txf_iter_data iter = { .init = true }; 1609 void *fifo_iter = fwrt->dump.fifo_iter; 1610 u32 size = 0; 1611 u32 fifo_hdr = sizeof(struct iwl_fw_ini_fifo_error_dump_range) + 1612 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(__le32) * 2; 1613 1614 fwrt->dump.fifo_iter = &iter; 1615 while (iwl_ini_txf_iter(fwrt, reg)) { 1616 size += fifo_hdr; 1617 if (!reg->fifos.header_only) 1618 size += iter.fifo_size; 1619 } 1620 1621 if (size) 1622 size += sizeof(struct iwl_fw_ini_fifo_error_dump); 1623 1624 fwrt->dump.fifo_iter = fifo_iter; 1625 1626 return size; 1627 } 1628 1629 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 1630 struct iwl_fw_ini_region_cfg *reg) 1631 { 1632 struct iwl_ini_rxf_data rx_data; 1633 u32 size = sizeof(struct iwl_fw_ini_fifo_error_dump) + 1634 sizeof(struct iwl_fw_ini_fifo_error_dump_range) + 1635 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(__le32) * 2; 1636 1637 if (reg->fifos.header_only) 1638 return size; 1639 1640 iwl_ini_get_rxf_data(fwrt, reg, &rx_data); 1641 size += rx_data.size; 1642 1643 return size; 1644 } 1645 1646 /** 1647 * struct iwl_dump_ini_mem_ops - ini memory dump operations 1648 * @get_num_of_ranges: returns the number of memory ranges in the region. 1649 * @get_size: returns the total size of the region. 1650 * @fill_mem_hdr: fills region type specific headers and returns pointer to 1651 * the first range or NULL if failed to fill headers. 1652 * @fill_range: copies a given memory range into the dump. 1653 * Returns the size of the range or negative error value otherwise. 1654 */ 1655 struct iwl_dump_ini_mem_ops { 1656 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 1657 struct iwl_fw_ini_region_cfg *reg); 1658 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 1659 struct iwl_fw_ini_region_cfg *reg); 1660 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 1661 struct iwl_fw_ini_region_cfg *reg, void *data); 1662 int (*fill_range)(struct iwl_fw_runtime *fwrt, 1663 struct iwl_fw_ini_region_cfg *reg, void *range, 1664 int idx); 1665 }; 1666 1667 /** 1668 * iwl_dump_ini_mem - copy a memory region into the dump 1669 * @fwrt: fw runtime struct. 1670 * @data: dump memory data. 1671 * @reg: region to copy to the dump. 1672 * @ops: memory dump operations. 1673 */ 1674 static void 1675 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, 1676 struct iwl_fw_error_dump_data **data, 1677 struct iwl_fw_ini_region_cfg *reg, 1678 struct iwl_dump_ini_mem_ops *ops) 1679 { 1680 struct iwl_fw_ini_error_dump_header *header = (void *)(*data)->data; 1681 u32 num_of_ranges, i, type = le32_to_cpu(reg->region_type); 1682 void *range; 1683 1684 if (WARN_ON(!ops || !ops->get_num_of_ranges || !ops->get_size || 1685 !ops->fill_mem_hdr || !ops->fill_range)) 1686 return; 1687 1688 num_of_ranges = ops->get_num_of_ranges(fwrt, reg); 1689 1690 (*data)->type = cpu_to_le32(type | INI_DUMP_BIT); 1691 (*data)->len = cpu_to_le32(ops->get_size(fwrt, reg)); 1692 1693 header->region_id = reg->region_id; 1694 header->num_of_ranges = cpu_to_le32(num_of_ranges); 1695 header->name_len = cpu_to_le32(min_t(int, IWL_FW_INI_MAX_NAME, 1696 le32_to_cpu(reg->name_len))); 1697 memcpy(header->name, reg->name, le32_to_cpu(header->name_len)); 1698 1699 range = ops->fill_mem_hdr(fwrt, reg, header); 1700 if (!range) { 1701 IWL_ERR(fwrt, "Failed to fill region header: id=%d, type=%d\n", 1702 le32_to_cpu(reg->region_id), type); 1703 memset(*data, 0, le32_to_cpu((*data)->len)); 1704 return; 1705 } 1706 1707 for (i = 0; i < num_of_ranges; i++) { 1708 int range_size = ops->fill_range(fwrt, reg, range, i); 1709 1710 if (range_size < 0) { 1711 IWL_ERR(fwrt, "Failed to dump region: id=%d, type=%d\n", 1712 le32_to_cpu(reg->region_id), type); 1713 memset(*data, 0, le32_to_cpu((*data)->len)); 1714 return; 1715 } 1716 range = range + range_size; 1717 } 1718 *data = iwl_fw_error_next_data(*data); 1719 } 1720 1721 static int iwl_fw_ini_get_trigger_len(struct iwl_fw_runtime *fwrt, 1722 struct iwl_fw_ini_trigger *trigger) 1723 { 1724 int i, size = 0, hdr_len = sizeof(struct iwl_fw_error_dump_data); 1725 1726 if (!trigger || !trigger->num_regions) 1727 return 0; 1728 1729 for (i = 0; i < le32_to_cpu(trigger->num_regions); i++) { 1730 u32 reg_id = le32_to_cpu(trigger->data[i]); 1731 struct iwl_fw_ini_region_cfg *reg; 1732 1733 if (WARN_ON(reg_id >= ARRAY_SIZE(fwrt->dump.active_regs))) 1734 continue; 1735 1736 reg = fwrt->dump.active_regs[reg_id]; 1737 if (WARN(!reg, "Unassigned region %d\n", reg_id)) 1738 continue; 1739 1740 switch (le32_to_cpu(reg->region_type)) { 1741 case IWL_FW_INI_REGION_DEVICE_MEMORY: 1742 case IWL_FW_INI_REGION_PERIPHERY_MAC: 1743 case IWL_FW_INI_REGION_PERIPHERY_PHY: 1744 case IWL_FW_INI_REGION_PERIPHERY_AUX: 1745 case IWL_FW_INI_REGION_CSR: 1746 size += hdr_len + iwl_dump_ini_mem_get_size(fwrt, reg); 1747 break; 1748 case IWL_FW_INI_REGION_TXF: 1749 size += hdr_len + iwl_dump_ini_txf_get_size(fwrt, reg); 1750 break; 1751 case IWL_FW_INI_REGION_RXF: 1752 size += hdr_len + iwl_dump_ini_rxf_get_size(fwrt, reg); 1753 break; 1754 case IWL_FW_INI_REGION_PAGING: 1755 size += hdr_len; 1756 if (iwl_fw_dbg_is_paging_enabled(fwrt)) { 1757 size += iwl_dump_ini_paging_get_size(fwrt, reg); 1758 } else { 1759 size += iwl_dump_ini_paging_gen2_get_size(fwrt, 1760 reg); 1761 } 1762 break; 1763 case IWL_FW_INI_REGION_DRAM_BUFFER: 1764 if (!fwrt->trans->num_blocks) 1765 break; 1766 size += hdr_len + 1767 iwl_dump_ini_mon_dram_get_size(fwrt, reg); 1768 break; 1769 case IWL_FW_INI_REGION_INTERNAL_BUFFER: 1770 size += hdr_len + 1771 iwl_dump_ini_mon_smem_get_size(fwrt, reg); 1772 break; 1773 case IWL_FW_INI_REGION_DRAM_IMR: 1774 /* Undefined yet */ 1775 default: 1776 break; 1777 } 1778 } 1779 return size; 1780 } 1781 1782 static void iwl_fw_ini_dump_trigger(struct iwl_fw_runtime *fwrt, 1783 struct iwl_fw_ini_trigger *trigger, 1784 struct iwl_fw_error_dump_data **data) 1785 { 1786 int i, num = le32_to_cpu(trigger->num_regions); 1787 1788 for (i = 0; i < num; i++) { 1789 u32 reg_id = le32_to_cpu(trigger->data[i]); 1790 struct iwl_fw_ini_region_cfg *reg; 1791 struct iwl_dump_ini_mem_ops ops; 1792 1793 if (reg_id >= ARRAY_SIZE(fwrt->dump.active_regs)) 1794 continue; 1795 1796 reg = fwrt->dump.active_regs[reg_id]; 1797 /* Don't warn, get_trigger_len already warned */ 1798 if (!reg) 1799 continue; 1800 1801 /* currently the driver supports always on domain only */ 1802 if (le32_to_cpu(reg->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON) 1803 continue; 1804 1805 switch (le32_to_cpu(reg->region_type)) { 1806 case IWL_FW_INI_REGION_DEVICE_MEMORY: 1807 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1808 ops.get_size = iwl_dump_ini_mem_get_size; 1809 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1810 ops.fill_range = iwl_dump_ini_dev_mem_iter; 1811 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1812 break; 1813 case IWL_FW_INI_REGION_PERIPHERY_MAC: 1814 case IWL_FW_INI_REGION_PERIPHERY_PHY: 1815 case IWL_FW_INI_REGION_PERIPHERY_AUX: 1816 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1817 ops.get_size = iwl_dump_ini_mem_get_size; 1818 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1819 ops.fill_range = iwl_dump_ini_prph_iter; 1820 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1821 break; 1822 case IWL_FW_INI_REGION_DRAM_BUFFER: 1823 ops.get_num_of_ranges = iwl_dump_ini_mon_dram_ranges; 1824 ops.get_size = iwl_dump_ini_mon_dram_get_size; 1825 ops.fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header; 1826 ops.fill_range = iwl_dump_ini_mon_dram_iter; 1827 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1828 break; 1829 case IWL_FW_INI_REGION_INTERNAL_BUFFER: 1830 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1831 ops.get_size = iwl_dump_ini_mon_smem_get_size; 1832 ops.fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header; 1833 ops.fill_range = iwl_dump_ini_dev_mem_iter; 1834 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1835 break; 1836 case IWL_FW_INI_REGION_PAGING: 1837 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1838 if (iwl_fw_dbg_is_paging_enabled(fwrt)) { 1839 ops.get_num_of_ranges = 1840 iwl_dump_ini_paging_ranges; 1841 ops.get_size = iwl_dump_ini_paging_get_size; 1842 ops.fill_range = iwl_dump_ini_paging_iter; 1843 } else { 1844 ops.get_num_of_ranges = 1845 iwl_dump_ini_paging_gen2_ranges; 1846 ops.get_size = 1847 iwl_dump_ini_paging_gen2_get_size; 1848 ops.fill_range = iwl_dump_ini_paging_gen2_iter; 1849 } 1850 1851 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1852 break; 1853 case IWL_FW_INI_REGION_TXF: { 1854 struct iwl_ini_txf_iter_data iter = { .init = true }; 1855 void *fifo_iter = fwrt->dump.fifo_iter; 1856 1857 fwrt->dump.fifo_iter = &iter; 1858 ops.get_num_of_ranges = iwl_dump_ini_txf_ranges; 1859 ops.get_size = iwl_dump_ini_txf_get_size; 1860 ops.fill_mem_hdr = iwl_dump_ini_fifo_fill_header; 1861 ops.fill_range = iwl_dump_ini_txf_iter; 1862 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1863 fwrt->dump.fifo_iter = fifo_iter; 1864 break; 1865 } 1866 case IWL_FW_INI_REGION_RXF: 1867 ops.get_num_of_ranges = iwl_dump_ini_rxf_ranges; 1868 ops.get_size = iwl_dump_ini_rxf_get_size; 1869 ops.fill_mem_hdr = iwl_dump_ini_fifo_fill_header; 1870 ops.fill_range = iwl_dump_ini_rxf_iter; 1871 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1872 break; 1873 case IWL_FW_INI_REGION_CSR: 1874 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1875 ops.get_size = iwl_dump_ini_mem_get_size; 1876 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1877 ops.fill_range = iwl_dump_ini_csr_iter; 1878 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1879 break; 1880 case IWL_FW_INI_REGION_DRAM_IMR: 1881 /* This is undefined yet */ 1882 default: 1883 break; 1884 } 1885 } 1886 } 1887 1888 static struct iwl_fw_error_dump_file * 1889 iwl_fw_error_ini_dump_file(struct iwl_fw_runtime *fwrt) 1890 { 1891 int size; 1892 struct iwl_fw_error_dump_data *dump_data; 1893 struct iwl_fw_error_dump_file *dump_file; 1894 struct iwl_fw_ini_trigger *trigger; 1895 enum iwl_fw_ini_trigger_id id = fwrt->dump.ini_trig_id; 1896 1897 if (!iwl_fw_ini_trigger_on(fwrt, id)) 1898 return NULL; 1899 1900 trigger = fwrt->dump.active_trigs[id].trig; 1901 1902 size = iwl_fw_ini_get_trigger_len(fwrt, trigger); 1903 if (!size) 1904 return NULL; 1905 1906 size += sizeof(*dump_file); 1907 1908 dump_file = vzalloc(size); 1909 if (!dump_file) 1910 return NULL; 1911 1912 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 1913 dump_data = (void *)dump_file->data; 1914 dump_file->file_len = cpu_to_le32(size); 1915 1916 iwl_fw_ini_dump_trigger(fwrt, trigger, &dump_data); 1917 1918 return dump_file; 1919 } 1920 1921 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt) 1922 { 1923 struct iwl_fw_dump_ptrs fw_error_dump = {}; 1924 struct iwl_fw_error_dump_file *dump_file; 1925 struct scatterlist *sg_dump_data; 1926 u32 file_len; 1927 u32 dump_mask = fwrt->fw->dbg.dump_mask; 1928 1929 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump); 1930 if (!dump_file) 1931 goto out; 1932 1933 if (!fwrt->trans->ini_valid && fwrt->dump.monitor_only) 1934 dump_mask &= IWL_FW_ERROR_DUMP_FW_MONITOR; 1935 1936 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask); 1937 file_len = le32_to_cpu(dump_file->file_len); 1938 fw_error_dump.fwrt_len = file_len; 1939 1940 if (fw_error_dump.trans_ptr) { 1941 file_len += fw_error_dump.trans_ptr->len; 1942 dump_file->file_len = cpu_to_le32(file_len); 1943 } 1944 1945 sg_dump_data = alloc_sgtable(file_len); 1946 if (sg_dump_data) { 1947 sg_pcopy_from_buffer(sg_dump_data, 1948 sg_nents(sg_dump_data), 1949 fw_error_dump.fwrt_ptr, 1950 fw_error_dump.fwrt_len, 0); 1951 if (fw_error_dump.trans_ptr) 1952 sg_pcopy_from_buffer(sg_dump_data, 1953 sg_nents(sg_dump_data), 1954 fw_error_dump.trans_ptr->data, 1955 fw_error_dump.trans_ptr->len, 1956 fw_error_dump.fwrt_len); 1957 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 1958 GFP_KERNEL); 1959 } 1960 vfree(fw_error_dump.fwrt_ptr); 1961 vfree(fw_error_dump.trans_ptr); 1962 1963 out: 1964 iwl_fw_free_dump_desc(fwrt); 1965 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 1966 } 1967 1968 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt) 1969 { 1970 struct iwl_fw_error_dump_file *dump_file; 1971 struct scatterlist *sg_dump_data; 1972 u32 file_len; 1973 1974 dump_file = iwl_fw_error_ini_dump_file(fwrt); 1975 if (!dump_file) 1976 goto out; 1977 1978 file_len = le32_to_cpu(dump_file->file_len); 1979 1980 sg_dump_data = alloc_sgtable(file_len); 1981 if (sg_dump_data) { 1982 sg_pcopy_from_buffer(sg_dump_data, sg_nents(sg_dump_data), 1983 dump_file, file_len, 0); 1984 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 1985 GFP_KERNEL); 1986 } 1987 vfree(dump_file); 1988 out: 1989 fwrt->dump.ini_trig_id = IWL_FW_TRIGGER_ID_INVALID; 1990 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 1991 } 1992 1993 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 1994 .trig_desc = { 1995 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 1996 }, 1997 }; 1998 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 1999 2000 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2001 const struct iwl_fw_dump_desc *desc, 2002 bool monitor_only, 2003 unsigned int delay) 2004 { 2005 u32 trig_type = le32_to_cpu(desc->trig_desc.type); 2006 int ret; 2007 2008 if (fwrt->trans->ini_valid) { 2009 ret = iwl_fw_dbg_ini_collect(fwrt, trig_type); 2010 if (!ret) 2011 iwl_fw_free_dump_desc(fwrt); 2012 2013 return ret; 2014 } 2015 2016 if (test_and_set_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 2017 return -EBUSY; 2018 2019 if (WARN_ON(fwrt->dump.desc)) 2020 iwl_fw_free_dump_desc(fwrt); 2021 2022 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2023 le32_to_cpu(desc->trig_desc.type)); 2024 2025 fwrt->dump.desc = desc; 2026 fwrt->dump.monitor_only = monitor_only; 2027 2028 schedule_delayed_work(&fwrt->dump.wk, usecs_to_jiffies(delay)); 2029 2030 return 0; 2031 } 2032 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2033 2034 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2035 enum iwl_fw_dbg_trigger trig_type) 2036 { 2037 int ret; 2038 struct iwl_fw_dump_desc *iwl_dump_error_desc = 2039 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2040 2041 if (!iwl_dump_error_desc) 2042 return -ENOMEM; 2043 2044 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2045 iwl_dump_error_desc->len = 0; 2046 2047 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, false, 0); 2048 if (ret) 2049 kfree(iwl_dump_error_desc); 2050 else 2051 iwl_trans_sync_nmi(fwrt->trans); 2052 2053 return ret; 2054 } 2055 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2056 2057 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2058 enum iwl_fw_dbg_trigger trig, 2059 const char *str, size_t len, 2060 struct iwl_fw_dbg_trigger_tlv *trigger) 2061 { 2062 struct iwl_fw_dump_desc *desc; 2063 unsigned int delay = 0; 2064 bool monitor_only = false; 2065 2066 if (trigger) { 2067 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2068 2069 if (!le16_to_cpu(trigger->occurrences)) 2070 return 0; 2071 2072 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2073 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2074 trig); 2075 iwl_force_nmi(fwrt->trans); 2076 return 0; 2077 } 2078 2079 trigger->occurrences = cpu_to_le16(occurrences); 2080 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2081 2082 /* convert msec to usec */ 2083 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2084 } 2085 2086 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 2087 if (!desc) 2088 return -ENOMEM; 2089 2090 2091 desc->len = len; 2092 desc->trig_desc.type = cpu_to_le32(trig); 2093 memcpy(desc->trig_desc.data, str, len); 2094 2095 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2096 } 2097 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2098 2099 int _iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 2100 enum iwl_fw_ini_trigger_id id) 2101 { 2102 struct iwl_fw_ini_active_triggers *active; 2103 u32 occur, delay; 2104 2105 if (WARN_ON(!iwl_fw_ini_trigger_on(fwrt, id))) 2106 return -EINVAL; 2107 2108 if (test_and_set_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 2109 return -EBUSY; 2110 2111 active = &fwrt->dump.active_trigs[id]; 2112 delay = le32_to_cpu(active->trig->dump_delay); 2113 occur = le32_to_cpu(active->trig->occurrences); 2114 if (!occur) 2115 return 0; 2116 2117 active->trig->occurrences = cpu_to_le32(--occur); 2118 2119 if (le32_to_cpu(active->trig->force_restart)) { 2120 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", id); 2121 iwl_force_nmi(fwrt->trans); 2122 return 0; 2123 } 2124 2125 fwrt->dump.ini_trig_id = id; 2126 2127 IWL_WARN(fwrt, "Collecting data: ini trigger %d fired.\n", id); 2128 2129 schedule_delayed_work(&fwrt->dump.wk, usecs_to_jiffies(delay)); 2130 2131 return 0; 2132 } 2133 IWL_EXPORT_SYMBOL(_iwl_fw_dbg_ini_collect); 2134 2135 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, u32 legacy_trigger_id) 2136 { 2137 int id; 2138 2139 switch (legacy_trigger_id) { 2140 case FW_DBG_TRIGGER_FW_ASSERT: 2141 case FW_DBG_TRIGGER_ALIVE_TIMEOUT: 2142 case FW_DBG_TRIGGER_DRIVER: 2143 id = IWL_FW_TRIGGER_ID_FW_ASSERT; 2144 break; 2145 case FW_DBG_TRIGGER_USER: 2146 id = IWL_FW_TRIGGER_ID_USER_TRIGGER; 2147 break; 2148 default: 2149 return -EIO; 2150 } 2151 2152 return _iwl_fw_dbg_ini_collect(fwrt, id); 2153 } 2154 IWL_EXPORT_SYMBOL(iwl_fw_dbg_ini_collect); 2155 2156 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2157 struct iwl_fw_dbg_trigger_tlv *trigger, 2158 const char *fmt, ...) 2159 { 2160 int ret, len = 0; 2161 char buf[64]; 2162 2163 if (fwrt->trans->ini_valid) 2164 return 0; 2165 2166 if (fmt) { 2167 va_list ap; 2168 2169 buf[sizeof(buf) - 1] = '\0'; 2170 2171 va_start(ap, fmt); 2172 vsnprintf(buf, sizeof(buf), fmt, ap); 2173 va_end(ap); 2174 2175 /* check for truncation */ 2176 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2177 buf[sizeof(buf) - 1] = '\0'; 2178 2179 len = strlen(buf) + 1; 2180 } 2181 2182 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2183 trigger); 2184 2185 if (ret) 2186 return ret; 2187 2188 return 0; 2189 } 2190 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2191 2192 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2193 { 2194 u8 *ptr; 2195 int ret; 2196 int i; 2197 2198 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 2199 "Invalid configuration %d\n", conf_id)) 2200 return -EINVAL; 2201 2202 /* EARLY START - firmware's configuration is hard coded */ 2203 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 2204 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 2205 conf_id == FW_DBG_START_FROM_ALIVE) 2206 return 0; 2207 2208 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 2209 return -EINVAL; 2210 2211 if (fwrt->dump.conf != FW_DBG_INVALID) 2212 IWL_WARN(fwrt, "FW already configured (%d) - re-configuring\n", 2213 fwrt->dump.conf); 2214 2215 /* Send all HCMDs for configuring the FW debug */ 2216 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 2217 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 2218 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 2219 struct iwl_host_cmd hcmd = { 2220 .id = cmd->id, 2221 .len = { le16_to_cpu(cmd->len), }, 2222 .data = { cmd->data, }, 2223 }; 2224 2225 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 2226 if (ret) 2227 return ret; 2228 2229 ptr += sizeof(*cmd); 2230 ptr += le16_to_cpu(cmd->len); 2231 } 2232 2233 fwrt->dump.conf = conf_id; 2234 2235 return 0; 2236 } 2237 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 2238 2239 /* this function assumes dump_start was called beforehand and dump_end will be 2240 * called afterwards 2241 */ 2242 void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt) 2243 { 2244 struct iwl_fw_dbg_params params = {0}; 2245 2246 if (!test_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 2247 return; 2248 2249 if (fwrt->ops && fwrt->ops->fw_running && 2250 !fwrt->ops->fw_running(fwrt->ops_ctx)) { 2251 IWL_ERR(fwrt, "Firmware not running - cannot dump error\n"); 2252 iwl_fw_free_dump_desc(fwrt); 2253 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 2254 return; 2255 } 2256 2257 /* there's no point in fw dump if the bus is dead */ 2258 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 2259 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 2260 return; 2261 } 2262 2263 iwl_fw_dbg_stop_recording(fwrt, ¶ms); 2264 2265 IWL_DEBUG_INFO(fwrt, "WRT dump start\n"); 2266 if (fwrt->trans->ini_valid) 2267 iwl_fw_error_ini_dump(fwrt); 2268 else 2269 iwl_fw_error_dump(fwrt); 2270 IWL_DEBUG_INFO(fwrt, "WRT dump done\n"); 2271 2272 /* start recording again if the firmware is not crashed */ 2273 if (!test_bit(STATUS_FW_ERROR, &fwrt->trans->status) && 2274 fwrt->fw->dbg.dest_tlv) { 2275 /* wait before we collect the data till the DBGC stop */ 2276 udelay(500); 2277 iwl_fw_dbg_restart_recording(fwrt, ¶ms); 2278 } 2279 } 2280 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_sync); 2281 2282 void iwl_fw_error_dump_wk(struct work_struct *work) 2283 { 2284 struct iwl_fw_runtime *fwrt = 2285 container_of(work, struct iwl_fw_runtime, dump.wk.work); 2286 2287 if (fwrt->ops && fwrt->ops->dump_start && 2288 fwrt->ops->dump_start(fwrt->ops_ctx)) 2289 return; 2290 2291 iwl_fw_dbg_collect_sync(fwrt); 2292 2293 if (fwrt->ops && fwrt->ops->dump_end) 2294 fwrt->ops->dump_end(fwrt->ops_ctx); 2295 } 2296 2297 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 2298 { 2299 const struct iwl_cfg *cfg = fwrt->trans->cfg; 2300 2301 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 2302 return; 2303 2304 if (!fwrt->dump.d3_debug_data) { 2305 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 2306 GFP_KERNEL); 2307 if (!fwrt->dump.d3_debug_data) { 2308 IWL_ERR(fwrt, 2309 "failed to allocate memory for D3 debug data\n"); 2310 return; 2311 } 2312 } 2313 2314 /* if the buffer holds previous debug data it is overwritten */ 2315 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 2316 fwrt->dump.d3_debug_data, 2317 cfg->d3_debug_data_length); 2318 } 2319 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 2320 2321 static void 2322 iwl_fw_dbg_buffer_allocation(struct iwl_fw_runtime *fwrt, u32 size) 2323 { 2324 struct iwl_trans *trans = fwrt->trans; 2325 void *virtual_addr = NULL; 2326 dma_addr_t phys_addr; 2327 2328 if (WARN_ON_ONCE(trans->num_blocks == ARRAY_SIZE(trans->fw_mon))) 2329 return; 2330 2331 virtual_addr = 2332 dma_alloc_coherent(fwrt->trans->dev, size, &phys_addr, 2333 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO | 2334 __GFP_COMP); 2335 2336 /* TODO: alloc fragments if needed */ 2337 if (!virtual_addr) 2338 IWL_ERR(fwrt, "Failed to allocate debug memory\n"); 2339 2340 trans->fw_mon[trans->num_blocks].block = virtual_addr; 2341 trans->fw_mon[trans->num_blocks].physical = phys_addr; 2342 trans->fw_mon[trans->num_blocks].size = size; 2343 trans->num_blocks++; 2344 2345 IWL_DEBUG_FW(trans, "Allocated debug block of size %d\n", size); 2346 } 2347 2348 static void iwl_fw_dbg_buffer_apply(struct iwl_fw_runtime *fwrt, 2349 struct iwl_fw_ini_allocation_data *alloc, 2350 enum iwl_fw_ini_apply_point pnt) 2351 { 2352 struct iwl_trans *trans = fwrt->trans; 2353 struct iwl_ldbg_config_cmd ldbg_cmd = { 2354 .type = cpu_to_le32(BUFFER_ALLOCATION), 2355 }; 2356 struct iwl_buffer_allocation_cmd *cmd = &ldbg_cmd.buffer_allocation; 2357 struct iwl_host_cmd hcmd = { 2358 .id = LDBG_CONFIG_CMD, 2359 .flags = CMD_ASYNC, 2360 .data[0] = &ldbg_cmd, 2361 .len[0] = sizeof(ldbg_cmd), 2362 }; 2363 int block_idx = trans->num_blocks; 2364 u32 buf_location = le32_to_cpu(alloc->tlv.buffer_location); 2365 2366 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH) { 2367 if (!WARN(pnt != IWL_FW_INI_APPLY_EARLY, 2368 "Invalid apply point %d for SMEM buffer allocation", 2369 pnt)) 2370 /* set sram monitor by enabling bit 7 */ 2371 iwl_set_bit(fwrt->trans, CSR_HW_IF_CONFIG_REG, 2372 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 2373 return; 2374 } 2375 2376 if (buf_location != IWL_FW_INI_LOCATION_DRAM_PATH) 2377 return; 2378 2379 if (!alloc->is_alloc) { 2380 iwl_fw_dbg_buffer_allocation(fwrt, 2381 le32_to_cpu(alloc->tlv.size)); 2382 if (block_idx == trans->num_blocks) 2383 return; 2384 alloc->is_alloc = 1; 2385 } 2386 2387 /* First block is assigned via registers / context info */ 2388 if (trans->num_blocks == 1) 2389 return; 2390 2391 cmd->num_frags = cpu_to_le32(1); 2392 cmd->fragments[0].address = 2393 cpu_to_le64(trans->fw_mon[block_idx].physical); 2394 cmd->fragments[0].size = alloc->tlv.size; 2395 cmd->allocation_id = alloc->tlv.allocation_id; 2396 cmd->buffer_location = alloc->tlv.buffer_location; 2397 2398 iwl_trans_send_cmd(trans, &hcmd); 2399 } 2400 2401 static void iwl_fw_dbg_send_hcmd(struct iwl_fw_runtime *fwrt, 2402 struct iwl_ucode_tlv *tlv) 2403 { 2404 struct iwl_fw_ini_hcmd_tlv *hcmd_tlv = (void *)&tlv->data[0]; 2405 struct iwl_fw_ini_hcmd *data = &hcmd_tlv->hcmd; 2406 u16 len = le32_to_cpu(tlv->length) - sizeof(*hcmd_tlv); 2407 2408 struct iwl_host_cmd hcmd = { 2409 .id = WIDE_ID(data->group, data->id), 2410 .len = { len, }, 2411 .data = { data->data, }, 2412 }; 2413 2414 /* currently the driver supports always on domain only */ 2415 if (le32_to_cpu(hcmd_tlv->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON) 2416 return; 2417 2418 iwl_trans_send_cmd(fwrt->trans, &hcmd); 2419 } 2420 2421 static void iwl_fw_dbg_update_regions(struct iwl_fw_runtime *fwrt, 2422 struct iwl_fw_ini_region_tlv *tlv, 2423 bool ext, enum iwl_fw_ini_apply_point pnt) 2424 { 2425 void *iter = (void *)tlv->region_config; 2426 int i, size = le32_to_cpu(tlv->num_regions); 2427 2428 for (i = 0; i < size; i++) { 2429 struct iwl_fw_ini_region_cfg *reg = iter, **active; 2430 int id = le32_to_cpu(reg->region_id); 2431 u32 type = le32_to_cpu(reg->region_type); 2432 2433 if (WARN(id >= ARRAY_SIZE(fwrt->dump.active_regs), 2434 "Invalid region id %d for apply point %d\n", id, pnt)) 2435 break; 2436 2437 active = &fwrt->dump.active_regs[id]; 2438 2439 if (*active) 2440 IWL_WARN(fwrt->trans, "region TLV %d override\n", id); 2441 2442 IWL_DEBUG_FW(fwrt, 2443 "%s: apply point %d, activating region ID %d\n", 2444 __func__, pnt, id); 2445 2446 *active = reg; 2447 2448 if (type == IWL_FW_INI_REGION_TXF || 2449 type == IWL_FW_INI_REGION_RXF) 2450 iter += le32_to_cpu(reg->fifos.num_of_registers) * 2451 sizeof(__le32); 2452 else if (type != IWL_FW_INI_REGION_DRAM_BUFFER) 2453 iter += le32_to_cpu(reg->internal.num_of_ranges) * 2454 sizeof(__le32); 2455 2456 iter += sizeof(*reg); 2457 } 2458 } 2459 2460 static int iwl_fw_dbg_trig_realloc(struct iwl_fw_runtime *fwrt, 2461 struct iwl_fw_ini_active_triggers *active, 2462 u32 id, int size) 2463 { 2464 void *ptr; 2465 2466 if (size <= active->size) 2467 return 0; 2468 2469 ptr = krealloc(active->trig, size, GFP_KERNEL); 2470 if (!ptr) { 2471 IWL_ERR(fwrt, "Failed to allocate memory for trigger %d\n", id); 2472 return -ENOMEM; 2473 } 2474 active->trig = ptr; 2475 active->size = size; 2476 2477 return 0; 2478 } 2479 2480 static void iwl_fw_dbg_update_triggers(struct iwl_fw_runtime *fwrt, 2481 struct iwl_fw_ini_trigger_tlv *tlv, 2482 bool ext, 2483 enum iwl_fw_ini_apply_point apply_point) 2484 { 2485 int i, size = le32_to_cpu(tlv->num_triggers); 2486 void *iter = (void *)tlv->trigger_config; 2487 2488 for (i = 0; i < size; i++) { 2489 struct iwl_fw_ini_trigger *trig = iter; 2490 struct iwl_fw_ini_active_triggers *active; 2491 int id = le32_to_cpu(trig->trigger_id); 2492 u32 trig_regs_size = le32_to_cpu(trig->num_regions) * 2493 sizeof(__le32); 2494 2495 if (WARN_ON(id >= ARRAY_SIZE(fwrt->dump.active_trigs))) 2496 break; 2497 2498 active = &fwrt->dump.active_trigs[id]; 2499 2500 if (!active->active) { 2501 size_t trig_size = sizeof(*trig) + trig_regs_size; 2502 2503 if (iwl_fw_dbg_trig_realloc(fwrt, active, id, 2504 trig_size)) 2505 goto next; 2506 2507 memcpy(active->trig, trig, trig_size); 2508 2509 } else { 2510 u32 conf_override = 2511 !(le32_to_cpu(trig->override_trig) & 0xff); 2512 u32 region_override = 2513 !(le32_to_cpu(trig->override_trig) & 0xff00); 2514 u32 offset = 0; 2515 u32 active_regs = 2516 le32_to_cpu(active->trig->num_regions); 2517 u32 new_regs = le32_to_cpu(trig->num_regions); 2518 int mem_to_add = trig_regs_size; 2519 2520 if (region_override) { 2521 mem_to_add -= active_regs * sizeof(__le32); 2522 } else { 2523 offset += active_regs; 2524 new_regs += active_regs; 2525 } 2526 2527 if (iwl_fw_dbg_trig_realloc(fwrt, active, id, 2528 active->size + mem_to_add)) 2529 goto next; 2530 2531 if (conf_override) 2532 memcpy(active->trig, trig, sizeof(*trig)); 2533 2534 memcpy(active->trig->data + offset, trig->data, 2535 trig_regs_size); 2536 active->trig->num_regions = cpu_to_le32(new_regs); 2537 } 2538 2539 /* Since zero means infinity - just set to -1 */ 2540 if (!le32_to_cpu(active->trig->occurrences)) 2541 active->trig->occurrences = cpu_to_le32(-1); 2542 2543 active->active = true; 2544 next: 2545 iter += sizeof(*trig) + trig_regs_size; 2546 2547 } 2548 } 2549 2550 static void _iwl_fw_dbg_apply_point(struct iwl_fw_runtime *fwrt, 2551 struct iwl_apply_point_data *data, 2552 enum iwl_fw_ini_apply_point pnt, 2553 bool ext) 2554 { 2555 void *iter = data->data; 2556 2557 while (iter && iter < data->data + data->size) { 2558 struct iwl_ucode_tlv *tlv = iter; 2559 void *ini_tlv = (void *)tlv->data; 2560 u32 type = le32_to_cpu(tlv->type); 2561 2562 switch (type) { 2563 case IWL_UCODE_TLV_TYPE_BUFFER_ALLOCATION: { 2564 struct iwl_fw_ini_allocation_data *buf_alloc = ini_tlv; 2565 2566 iwl_fw_dbg_buffer_apply(fwrt, ini_tlv, pnt); 2567 iter += sizeof(buf_alloc->is_alloc); 2568 break; 2569 } 2570 case IWL_UCODE_TLV_TYPE_HCMD: 2571 if (pnt < IWL_FW_INI_APPLY_AFTER_ALIVE) { 2572 IWL_ERR(fwrt, 2573 "Invalid apply point %x for host command\n", 2574 pnt); 2575 goto next; 2576 } 2577 iwl_fw_dbg_send_hcmd(fwrt, tlv); 2578 break; 2579 case IWL_UCODE_TLV_TYPE_REGIONS: 2580 iwl_fw_dbg_update_regions(fwrt, ini_tlv, ext, pnt); 2581 break; 2582 case IWL_UCODE_TLV_TYPE_TRIGGERS: 2583 iwl_fw_dbg_update_triggers(fwrt, ini_tlv, ext, pnt); 2584 break; 2585 case IWL_UCODE_TLV_TYPE_DEBUG_FLOW: 2586 break; 2587 default: 2588 WARN_ONCE(1, "Invalid TLV %x for apply point\n", type); 2589 break; 2590 } 2591 next: 2592 iter += sizeof(*tlv) + le32_to_cpu(tlv->length); 2593 } 2594 } 2595 2596 void iwl_fw_dbg_apply_point(struct iwl_fw_runtime *fwrt, 2597 enum iwl_fw_ini_apply_point apply_point) 2598 { 2599 void *data = &fwrt->trans->apply_points[apply_point]; 2600 int i; 2601 2602 if (apply_point == IWL_FW_INI_APPLY_EARLY) { 2603 for (i = 0; i < IWL_FW_INI_MAX_REGION_ID; i++) 2604 fwrt->dump.active_regs[i] = NULL; 2605 2606 /* disable the triggers, used in recovery flow */ 2607 for (i = 0; i < IWL_FW_TRIGGER_ID_NUM; i++) 2608 fwrt->dump.active_trigs[i].active = false; 2609 } 2610 2611 _iwl_fw_dbg_apply_point(fwrt, data, apply_point, false); 2612 2613 data = &fwrt->trans->apply_points_ext[apply_point]; 2614 _iwl_fw_dbg_apply_point(fwrt, data, apply_point, true); 2615 } 2616 IWL_EXPORT_SYMBOL(iwl_fw_dbg_apply_point); 2617 2618 void iwl_fwrt_stop_device(struct iwl_fw_runtime *fwrt) 2619 { 2620 iwl_fw_dbg_collect_sync(fwrt); 2621 2622 iwl_trans_stop_device(fwrt->trans); 2623 } 2624 IWL_EXPORT_SYMBOL(iwl_fwrt_stop_device); 2625