1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #include <linux/devcoredump.h> 65 #include "iwl-drv.h" 66 #include "runtime.h" 67 #include "dbg.h" 68 #include "debugfs.h" 69 #include "iwl-io.h" 70 #include "iwl-prph.h" 71 #include "iwl-csr.h" 72 73 /** 74 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 75 * 76 * @fwrt_ptr: pointer to the buffer coming from fwrt 77 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 78 * transport's data. 79 * @trans_len: length of the valid data in trans_ptr 80 * @fwrt_len: length of the valid data in fwrt_ptr 81 */ 82 struct iwl_fw_dump_ptrs { 83 struct iwl_trans_dump_data *trans_ptr; 84 void *fwrt_ptr; 85 u32 fwrt_len; 86 }; 87 88 #define RADIO_REG_MAX_READ 0x2ad 89 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 90 struct iwl_fw_error_dump_data **dump_data) 91 { 92 u8 *pos = (void *)(*dump_data)->data; 93 unsigned long flags; 94 int i; 95 96 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 97 98 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 99 return; 100 101 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 102 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 103 104 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 105 u32 rd_cmd = RADIO_RSP_RD_CMD; 106 107 rd_cmd |= i << RADIO_RSP_ADDR_POS; 108 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 109 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 110 111 pos++; 112 } 113 114 *dump_data = iwl_fw_error_next_data(*dump_data); 115 116 iwl_trans_release_nic_access(fwrt->trans, &flags); 117 } 118 119 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 120 struct iwl_fw_error_dump_data **dump_data, 121 int size, u32 offset, int fifo_num) 122 { 123 struct iwl_fw_error_dump_fifo *fifo_hdr; 124 u32 *fifo_data; 125 u32 fifo_len; 126 int i; 127 128 fifo_hdr = (void *)(*dump_data)->data; 129 fifo_data = (void *)fifo_hdr->data; 130 fifo_len = size; 131 132 /* No need to try to read the data if the length is 0 */ 133 if (fifo_len == 0) 134 return; 135 136 /* Add a TLV for the RXF */ 137 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 138 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 139 140 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 141 fifo_hdr->available_bytes = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 RXF_RD_D_SPACE + offset)); 144 fifo_hdr->wr_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 RXF_RD_WR_PTR + offset)); 147 fifo_hdr->rd_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 RXF_RD_RD_PTR + offset)); 150 fifo_hdr->fence_ptr = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 RXF_RD_FENCE_PTR + offset)); 153 fifo_hdr->fence_mode = 154 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 155 RXF_SET_FENCE_MODE + offset)); 156 157 /* Lock fence */ 158 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 159 /* Set fence pointer to the same place like WR pointer */ 160 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 161 /* Set fence offset */ 162 iwl_trans_write_prph(fwrt->trans, 163 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 164 165 /* Read FIFO */ 166 fifo_len /= sizeof(u32); /* Size in DWORDS */ 167 for (i = 0; i < fifo_len; i++) 168 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 169 RXF_FIFO_RD_FENCE_INC + 170 offset); 171 *dump_data = iwl_fw_error_next_data(*dump_data); 172 } 173 174 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 175 struct iwl_fw_error_dump_data **dump_data, 176 int size, u32 offset, int fifo_num) 177 { 178 struct iwl_fw_error_dump_fifo *fifo_hdr; 179 u32 *fifo_data; 180 u32 fifo_len; 181 int i; 182 183 fifo_hdr = (void *)(*dump_data)->data; 184 fifo_data = (void *)fifo_hdr->data; 185 fifo_len = size; 186 187 /* No need to try to read the data if the length is 0 */ 188 if (fifo_len == 0) 189 return; 190 191 /* Add a TLV for the FIFO */ 192 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 193 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 194 195 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 196 fifo_hdr->available_bytes = 197 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 198 TXF_FIFO_ITEM_CNT + offset)); 199 fifo_hdr->wr_ptr = 200 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 201 TXF_WR_PTR + offset)); 202 fifo_hdr->rd_ptr = 203 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 204 TXF_RD_PTR + offset)); 205 fifo_hdr->fence_ptr = 206 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 207 TXF_FENCE_PTR + offset)); 208 fifo_hdr->fence_mode = 209 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 210 TXF_LOCK_FENCE + offset)); 211 212 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 213 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 214 TXF_WR_PTR + offset); 215 216 /* Dummy-read to advance the read pointer to the head */ 217 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 218 219 /* Read FIFO */ 220 fifo_len /= sizeof(u32); /* Size in DWORDS */ 221 for (i = 0; i < fifo_len; i++) 222 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 223 TXF_READ_MODIFY_DATA + 224 offset); 225 *dump_data = iwl_fw_error_next_data(*dump_data); 226 } 227 228 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 229 struct iwl_fw_error_dump_data **dump_data) 230 { 231 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 232 unsigned long flags; 233 234 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 235 236 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 237 return; 238 239 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 240 /* Pull RXF1 */ 241 iwl_fwrt_dump_rxf(fwrt, dump_data, 242 cfg->lmac[0].rxfifo1_size, 0, 0); 243 /* Pull RXF2 */ 244 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 245 RXF_DIFF_FROM_PREV + 246 fwrt->trans->cfg->umac_prph_offset, 1); 247 /* Pull LMAC2 RXF1 */ 248 if (fwrt->smem_cfg.num_lmacs > 1) 249 iwl_fwrt_dump_rxf(fwrt, dump_data, 250 cfg->lmac[1].rxfifo1_size, 251 LMAC2_PRPH_OFFSET, 2); 252 } 253 254 iwl_trans_release_nic_access(fwrt->trans, &flags); 255 } 256 257 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 258 struct iwl_fw_error_dump_data **dump_data) 259 { 260 struct iwl_fw_error_dump_fifo *fifo_hdr; 261 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 262 u32 *fifo_data; 263 u32 fifo_len; 264 unsigned long flags; 265 int i, j; 266 267 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 268 269 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 270 return; 271 272 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 273 /* Pull TXF data from LMAC1 */ 274 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 275 /* Mark the number of TXF we're pulling now */ 276 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 277 iwl_fwrt_dump_txf(fwrt, dump_data, 278 cfg->lmac[0].txfifo_size[i], 0, i); 279 } 280 281 /* Pull TXF data from LMAC2 */ 282 if (fwrt->smem_cfg.num_lmacs > 1) { 283 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 284 i++) { 285 /* Mark the number of TXF we're pulling now */ 286 iwl_trans_write_prph(fwrt->trans, 287 TXF_LARC_NUM + 288 LMAC2_PRPH_OFFSET, i); 289 iwl_fwrt_dump_txf(fwrt, dump_data, 290 cfg->lmac[1].txfifo_size[i], 291 LMAC2_PRPH_OFFSET, 292 i + cfg->num_txfifo_entries); 293 } 294 } 295 } 296 297 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 298 fw_has_capa(&fwrt->fw->ucode_capa, 299 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 300 /* Pull UMAC internal TXF data from all TXFs */ 301 for (i = 0; 302 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 303 i++) { 304 fifo_hdr = (void *)(*dump_data)->data; 305 fifo_data = (void *)fifo_hdr->data; 306 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 307 308 /* No need to try to read the data if the length is 0 */ 309 if (fifo_len == 0) 310 continue; 311 312 /* Add a TLV for the internal FIFOs */ 313 (*dump_data)->type = 314 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 315 (*dump_data)->len = 316 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 317 318 fifo_hdr->fifo_num = cpu_to_le32(i); 319 320 /* Mark the number of TXF we're pulling now */ 321 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 322 fwrt->smem_cfg.num_txfifo_entries); 323 324 fifo_hdr->available_bytes = 325 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 326 TXF_CPU2_FIFO_ITEM_CNT)); 327 fifo_hdr->wr_ptr = 328 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 329 TXF_CPU2_WR_PTR)); 330 fifo_hdr->rd_ptr = 331 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 332 TXF_CPU2_RD_PTR)); 333 fifo_hdr->fence_ptr = 334 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 335 TXF_CPU2_FENCE_PTR)); 336 fifo_hdr->fence_mode = 337 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 338 TXF_CPU2_LOCK_FENCE)); 339 340 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 341 iwl_trans_write_prph(fwrt->trans, 342 TXF_CPU2_READ_MODIFY_ADDR, 343 TXF_CPU2_WR_PTR); 344 345 /* Dummy-read to advance the read pointer to head */ 346 iwl_trans_read_prph(fwrt->trans, 347 TXF_CPU2_READ_MODIFY_DATA); 348 349 /* Read FIFO */ 350 fifo_len /= sizeof(u32); /* Size in DWORDS */ 351 for (j = 0; j < fifo_len; j++) 352 fifo_data[j] = 353 iwl_trans_read_prph(fwrt->trans, 354 TXF_CPU2_READ_MODIFY_DATA); 355 *dump_data = iwl_fw_error_next_data(*dump_data); 356 } 357 } 358 359 iwl_trans_release_nic_access(fwrt->trans, &flags); 360 } 361 362 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ 363 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ 364 365 struct iwl_prph_range { 366 u32 start, end; 367 }; 368 369 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 370 { .start = 0x00a00000, .end = 0x00a00000 }, 371 { .start = 0x00a0000c, .end = 0x00a00024 }, 372 { .start = 0x00a0002c, .end = 0x00a0003c }, 373 { .start = 0x00a00410, .end = 0x00a00418 }, 374 { .start = 0x00a00420, .end = 0x00a00420 }, 375 { .start = 0x00a00428, .end = 0x00a00428 }, 376 { .start = 0x00a00430, .end = 0x00a0043c }, 377 { .start = 0x00a00444, .end = 0x00a00444 }, 378 { .start = 0x00a004c0, .end = 0x00a004cc }, 379 { .start = 0x00a004d8, .end = 0x00a004d8 }, 380 { .start = 0x00a004e0, .end = 0x00a004f0 }, 381 { .start = 0x00a00840, .end = 0x00a00840 }, 382 { .start = 0x00a00850, .end = 0x00a00858 }, 383 { .start = 0x00a01004, .end = 0x00a01008 }, 384 { .start = 0x00a01010, .end = 0x00a01010 }, 385 { .start = 0x00a01018, .end = 0x00a01018 }, 386 { .start = 0x00a01024, .end = 0x00a01024 }, 387 { .start = 0x00a0102c, .end = 0x00a01034 }, 388 { .start = 0x00a0103c, .end = 0x00a01040 }, 389 { .start = 0x00a01048, .end = 0x00a01094 }, 390 { .start = 0x00a01c00, .end = 0x00a01c20 }, 391 { .start = 0x00a01c58, .end = 0x00a01c58 }, 392 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 393 { .start = 0x00a01c28, .end = 0x00a01c54 }, 394 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 395 { .start = 0x00a01c60, .end = 0x00a01cdc }, 396 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 397 { .start = 0x00a01d18, .end = 0x00a01d20 }, 398 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 399 { .start = 0x00a01d40, .end = 0x00a01d5c }, 400 { .start = 0x00a01d80, .end = 0x00a01d80 }, 401 { .start = 0x00a01d98, .end = 0x00a01d9c }, 402 { .start = 0x00a01da8, .end = 0x00a01da8 }, 403 { .start = 0x00a01db8, .end = 0x00a01df4 }, 404 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 405 { .start = 0x00a01e00, .end = 0x00a01e2c }, 406 { .start = 0x00a01e40, .end = 0x00a01e60 }, 407 { .start = 0x00a01e68, .end = 0x00a01e6c }, 408 { .start = 0x00a01e74, .end = 0x00a01e74 }, 409 { .start = 0x00a01e84, .end = 0x00a01e90 }, 410 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 411 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 412 { .start = 0x00a01f00, .end = 0x00a01f1c }, 413 { .start = 0x00a01f44, .end = 0x00a01ffc }, 414 { .start = 0x00a02000, .end = 0x00a02048 }, 415 { .start = 0x00a02068, .end = 0x00a020f0 }, 416 { .start = 0x00a02100, .end = 0x00a02118 }, 417 { .start = 0x00a02140, .end = 0x00a0214c }, 418 { .start = 0x00a02168, .end = 0x00a0218c }, 419 { .start = 0x00a021c0, .end = 0x00a021c0 }, 420 { .start = 0x00a02400, .end = 0x00a02410 }, 421 { .start = 0x00a02418, .end = 0x00a02420 }, 422 { .start = 0x00a02428, .end = 0x00a0242c }, 423 { .start = 0x00a02434, .end = 0x00a02434 }, 424 { .start = 0x00a02440, .end = 0x00a02460 }, 425 { .start = 0x00a02468, .end = 0x00a024b0 }, 426 { .start = 0x00a024c8, .end = 0x00a024cc }, 427 { .start = 0x00a02500, .end = 0x00a02504 }, 428 { .start = 0x00a0250c, .end = 0x00a02510 }, 429 { .start = 0x00a02540, .end = 0x00a02554 }, 430 { .start = 0x00a02580, .end = 0x00a025f4 }, 431 { .start = 0x00a02600, .end = 0x00a0260c }, 432 { .start = 0x00a02648, .end = 0x00a02650 }, 433 { .start = 0x00a02680, .end = 0x00a02680 }, 434 { .start = 0x00a026c0, .end = 0x00a026d0 }, 435 { .start = 0x00a02700, .end = 0x00a0270c }, 436 { .start = 0x00a02804, .end = 0x00a02804 }, 437 { .start = 0x00a02818, .end = 0x00a0281c }, 438 { .start = 0x00a02c00, .end = 0x00a02db4 }, 439 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 440 { .start = 0x00a03000, .end = 0x00a03014 }, 441 { .start = 0x00a0301c, .end = 0x00a0302c }, 442 { .start = 0x00a03034, .end = 0x00a03038 }, 443 { .start = 0x00a03040, .end = 0x00a03048 }, 444 { .start = 0x00a03060, .end = 0x00a03068 }, 445 { .start = 0x00a03070, .end = 0x00a03074 }, 446 { .start = 0x00a0307c, .end = 0x00a0307c }, 447 { .start = 0x00a03080, .end = 0x00a03084 }, 448 { .start = 0x00a0308c, .end = 0x00a03090 }, 449 { .start = 0x00a03098, .end = 0x00a03098 }, 450 { .start = 0x00a030a0, .end = 0x00a030a0 }, 451 { .start = 0x00a030a8, .end = 0x00a030b4 }, 452 { .start = 0x00a030bc, .end = 0x00a030bc }, 453 { .start = 0x00a030c0, .end = 0x00a0312c }, 454 { .start = 0x00a03c00, .end = 0x00a03c5c }, 455 { .start = 0x00a04400, .end = 0x00a04454 }, 456 { .start = 0x00a04460, .end = 0x00a04474 }, 457 { .start = 0x00a044c0, .end = 0x00a044ec }, 458 { .start = 0x00a04500, .end = 0x00a04504 }, 459 { .start = 0x00a04510, .end = 0x00a04538 }, 460 { .start = 0x00a04540, .end = 0x00a04548 }, 461 { .start = 0x00a04560, .end = 0x00a0457c }, 462 { .start = 0x00a04590, .end = 0x00a04598 }, 463 { .start = 0x00a045c0, .end = 0x00a045f4 }, 464 }; 465 466 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 467 { .start = 0x00a05c00, .end = 0x00a05c18 }, 468 { .start = 0x00a05400, .end = 0x00a056e8 }, 469 { .start = 0x00a08000, .end = 0x00a098bc }, 470 { .start = 0x00a02400, .end = 0x00a02758 }, 471 }; 472 473 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 474 { .start = 0x00a00000, .end = 0x00a00000 }, 475 { .start = 0x00a0000c, .end = 0x00a00024 }, 476 { .start = 0x00a0002c, .end = 0x00a00034 }, 477 { .start = 0x00a0003c, .end = 0x00a0003c }, 478 { .start = 0x00a00410, .end = 0x00a00418 }, 479 { .start = 0x00a00420, .end = 0x00a00420 }, 480 { .start = 0x00a00428, .end = 0x00a00428 }, 481 { .start = 0x00a00430, .end = 0x00a0043c }, 482 { .start = 0x00a00444, .end = 0x00a00444 }, 483 { .start = 0x00a00840, .end = 0x00a00840 }, 484 { .start = 0x00a00850, .end = 0x00a00858 }, 485 { .start = 0x00a01004, .end = 0x00a01008 }, 486 { .start = 0x00a01010, .end = 0x00a01010 }, 487 { .start = 0x00a01018, .end = 0x00a01018 }, 488 { .start = 0x00a01024, .end = 0x00a01024 }, 489 { .start = 0x00a0102c, .end = 0x00a01034 }, 490 { .start = 0x00a0103c, .end = 0x00a01040 }, 491 { .start = 0x00a01048, .end = 0x00a01050 }, 492 { .start = 0x00a01058, .end = 0x00a01058 }, 493 { .start = 0x00a01060, .end = 0x00a01070 }, 494 { .start = 0x00a0108c, .end = 0x00a0108c }, 495 { .start = 0x00a01c20, .end = 0x00a01c28 }, 496 { .start = 0x00a01d10, .end = 0x00a01d10 }, 497 { .start = 0x00a01e28, .end = 0x00a01e2c }, 498 { .start = 0x00a01e60, .end = 0x00a01e60 }, 499 { .start = 0x00a01e80, .end = 0x00a01e80 }, 500 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 501 { .start = 0x00a02000, .end = 0x00a0201c }, 502 { .start = 0x00a02024, .end = 0x00a02024 }, 503 { .start = 0x00a02040, .end = 0x00a02048 }, 504 { .start = 0x00a020c0, .end = 0x00a020e0 }, 505 { .start = 0x00a02400, .end = 0x00a02404 }, 506 { .start = 0x00a0240c, .end = 0x00a02414 }, 507 { .start = 0x00a0241c, .end = 0x00a0243c }, 508 { .start = 0x00a02448, .end = 0x00a024bc }, 509 { .start = 0x00a024c4, .end = 0x00a024cc }, 510 { .start = 0x00a02508, .end = 0x00a02508 }, 511 { .start = 0x00a02510, .end = 0x00a02514 }, 512 { .start = 0x00a0251c, .end = 0x00a0251c }, 513 { .start = 0x00a0252c, .end = 0x00a0255c }, 514 { .start = 0x00a02564, .end = 0x00a025a0 }, 515 { .start = 0x00a025a8, .end = 0x00a025b4 }, 516 { .start = 0x00a025c0, .end = 0x00a025c0 }, 517 { .start = 0x00a025e8, .end = 0x00a025f4 }, 518 { .start = 0x00a02c08, .end = 0x00a02c18 }, 519 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 520 { .start = 0x00a02c68, .end = 0x00a02c78 }, 521 { .start = 0x00a03000, .end = 0x00a03000 }, 522 { .start = 0x00a03010, .end = 0x00a03014 }, 523 { .start = 0x00a0301c, .end = 0x00a0302c }, 524 { .start = 0x00a03034, .end = 0x00a03038 }, 525 { .start = 0x00a03040, .end = 0x00a03044 }, 526 { .start = 0x00a03060, .end = 0x00a03068 }, 527 { .start = 0x00a03070, .end = 0x00a03070 }, 528 { .start = 0x00a0307c, .end = 0x00a03084 }, 529 { .start = 0x00a0308c, .end = 0x00a03090 }, 530 { .start = 0x00a03098, .end = 0x00a03098 }, 531 { .start = 0x00a030a0, .end = 0x00a030a0 }, 532 { .start = 0x00a030a8, .end = 0x00a030b4 }, 533 { .start = 0x00a030bc, .end = 0x00a030c0 }, 534 { .start = 0x00a030c8, .end = 0x00a030f4 }, 535 { .start = 0x00a03100, .end = 0x00a0312c }, 536 { .start = 0x00a03c00, .end = 0x00a03c5c }, 537 { .start = 0x00a04400, .end = 0x00a04454 }, 538 { .start = 0x00a04460, .end = 0x00a04474 }, 539 { .start = 0x00a044c0, .end = 0x00a044ec }, 540 { .start = 0x00a04500, .end = 0x00a04504 }, 541 { .start = 0x00a04510, .end = 0x00a04538 }, 542 { .start = 0x00a04540, .end = 0x00a04548 }, 543 { .start = 0x00a04560, .end = 0x00a04560 }, 544 { .start = 0x00a04570, .end = 0x00a0457c }, 545 { .start = 0x00a04590, .end = 0x00a04590 }, 546 { .start = 0x00a04598, .end = 0x00a04598 }, 547 { .start = 0x00a045c0, .end = 0x00a045f4 }, 548 { .start = 0x00a05c18, .end = 0x00a05c1c }, 549 { .start = 0x00a0c000, .end = 0x00a0c018 }, 550 { .start = 0x00a0c020, .end = 0x00a0c028 }, 551 { .start = 0x00a0c038, .end = 0x00a0c094 }, 552 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 553 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 554 { .start = 0x00a0c150, .end = 0x00a0c174 }, 555 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 556 { .start = 0x00a0c190, .end = 0x00a0c198 }, 557 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 558 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 559 }; 560 561 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 562 { .start = 0x00d03c00, .end = 0x00d03c64 }, 563 { .start = 0x00d05c18, .end = 0x00d05c1c }, 564 { .start = 0x00d0c000, .end = 0x00d0c174 }, 565 }; 566 567 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 568 u32 len_bytes, __le32 *data) 569 { 570 u32 i; 571 572 for (i = 0; i < len_bytes; i += 4) 573 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 574 } 575 576 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 577 const struct iwl_prph_range *iwl_prph_dump_addr, 578 u32 range_len, void *ptr) 579 { 580 struct iwl_fw_error_dump_prph *prph; 581 struct iwl_trans *trans = fwrt->trans; 582 struct iwl_fw_error_dump_data **data = 583 (struct iwl_fw_error_dump_data **)ptr; 584 unsigned long flags; 585 u32 i; 586 587 if (!data) 588 return; 589 590 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 591 592 if (!iwl_trans_grab_nic_access(trans, &flags)) 593 return; 594 595 for (i = 0; i < range_len; i++) { 596 /* The range includes both boundaries */ 597 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 598 iwl_prph_dump_addr[i].start + 4; 599 600 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 601 (*data)->len = cpu_to_le32(sizeof(*prph) + 602 num_bytes_in_chunk); 603 prph = (void *)(*data)->data; 604 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 605 606 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 607 /* our range is inclusive, hence + 4 */ 608 iwl_prph_dump_addr[i].end - 609 iwl_prph_dump_addr[i].start + 4, 610 (void *)prph->data); 611 612 *data = iwl_fw_error_next_data(*data); 613 } 614 615 iwl_trans_release_nic_access(trans, &flags); 616 } 617 618 /* 619 * alloc_sgtable - allocates scallerlist table in the given size, 620 * fills it with pages and returns it 621 * @size: the size (in bytes) of the table 622 */ 623 static struct scatterlist *alloc_sgtable(int size) 624 { 625 int alloc_size, nents, i; 626 struct page *new_page; 627 struct scatterlist *iter; 628 struct scatterlist *table; 629 630 nents = DIV_ROUND_UP(size, PAGE_SIZE); 631 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 632 if (!table) 633 return NULL; 634 sg_init_table(table, nents); 635 iter = table; 636 for_each_sg(table, iter, sg_nents(table), i) { 637 new_page = alloc_page(GFP_KERNEL); 638 if (!new_page) { 639 /* release all previous allocated pages in the table */ 640 iter = table; 641 for_each_sg(table, iter, sg_nents(table), i) { 642 new_page = sg_page(iter); 643 if (new_page) 644 __free_page(new_page); 645 } 646 return NULL; 647 } 648 alloc_size = min_t(int, size, PAGE_SIZE); 649 size -= PAGE_SIZE; 650 sg_set_page(iter, new_page, alloc_size, 0); 651 } 652 return table; 653 } 654 655 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 656 const struct iwl_prph_range *iwl_prph_dump_addr, 657 u32 range_len, void *ptr) 658 { 659 u32 *prph_len = (u32 *)ptr; 660 int i, num_bytes_in_chunk; 661 662 if (!prph_len) 663 return; 664 665 for (i = 0; i < range_len; i++) { 666 /* The range includes both boundaries */ 667 num_bytes_in_chunk = 668 iwl_prph_dump_addr[i].end - 669 iwl_prph_dump_addr[i].start + 4; 670 671 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 672 sizeof(struct iwl_fw_error_dump_prph) + 673 num_bytes_in_chunk; 674 } 675 } 676 677 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 678 void (*handler)(struct iwl_fw_runtime *, 679 const struct iwl_prph_range *, 680 u32, void *)) 681 { 682 u32 range_len; 683 684 if (fwrt->trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 685 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 686 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 687 } else if (fwrt->trans->cfg->device_family >= IWL_DEVICE_FAMILY_22000) { 688 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 689 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 690 } else { 691 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 692 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 693 694 if (fwrt->trans->cfg->mq_rx_supported) { 695 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 696 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 697 } 698 } 699 } 700 701 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 702 struct iwl_fw_error_dump_data **dump_data, 703 u32 len, u32 ofs, u32 type) 704 { 705 struct iwl_fw_error_dump_mem *dump_mem; 706 707 if (!len) 708 return; 709 710 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 711 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 712 dump_mem = (void *)(*dump_data)->data; 713 dump_mem->type = cpu_to_le32(type); 714 dump_mem->offset = cpu_to_le32(ofs); 715 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 716 *dump_data = iwl_fw_error_next_data(*dump_data); 717 718 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 719 } 720 721 #define ADD_LEN(len, item_len, const_len) \ 722 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 723 while (0) 724 725 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 726 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 727 { 728 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 729 sizeof(struct iwl_fw_error_dump_fifo); 730 u32 fifo_len = 0; 731 int i; 732 733 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 734 return 0; 735 736 /* Count RXF2 size */ 737 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 738 739 /* Count RXF1 sizes */ 740 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 741 mem_cfg->num_lmacs = MAX_NUM_LMAC; 742 743 for (i = 0; i < mem_cfg->num_lmacs; i++) 744 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 745 746 return fifo_len; 747 } 748 749 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 750 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 751 { 752 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 753 sizeof(struct iwl_fw_error_dump_fifo); 754 u32 fifo_len = 0; 755 int i; 756 757 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 758 goto dump_internal_txf; 759 760 /* Count TXF sizes */ 761 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 762 mem_cfg->num_lmacs = MAX_NUM_LMAC; 763 764 for (i = 0; i < mem_cfg->num_lmacs; i++) { 765 int j; 766 767 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 768 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 769 hdr_len); 770 } 771 772 dump_internal_txf: 773 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 774 fw_has_capa(&fwrt->fw->ucode_capa, 775 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 776 goto out; 777 778 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 779 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 780 781 out: 782 return fifo_len; 783 } 784 785 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 786 struct iwl_fw_error_dump_data **data) 787 { 788 int i; 789 790 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 791 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 792 struct iwl_fw_error_dump_paging *paging; 793 struct page *pages = 794 fwrt->fw_paging_db[i].fw_paging_block; 795 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 796 797 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 798 (*data)->len = cpu_to_le32(sizeof(*paging) + 799 PAGING_BLOCK_SIZE); 800 paging = (void *)(*data)->data; 801 paging->index = cpu_to_le32(i); 802 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 803 PAGING_BLOCK_SIZE, 804 DMA_BIDIRECTIONAL); 805 memcpy(paging->data, page_address(pages), 806 PAGING_BLOCK_SIZE); 807 dma_sync_single_for_device(fwrt->trans->dev, addr, 808 PAGING_BLOCK_SIZE, 809 DMA_BIDIRECTIONAL); 810 (*data) = iwl_fw_error_next_data(*data); 811 } 812 } 813 814 static struct iwl_fw_error_dump_file * 815 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 816 struct iwl_fw_dump_ptrs *fw_error_dump) 817 { 818 struct iwl_fw_error_dump_file *dump_file; 819 struct iwl_fw_error_dump_data *dump_data; 820 struct iwl_fw_error_dump_info *dump_info; 821 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 822 struct iwl_fw_error_dump_trigger_desc *dump_trig; 823 u32 sram_len, sram_ofs; 824 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 825 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 826 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 827 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 828 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 829 0 : fwrt->trans->cfg->dccm2_len; 830 int i; 831 832 /* SRAM - include stack CCM if driver knows the values for it */ 833 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 834 const struct fw_img *img; 835 836 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 837 return NULL; 838 img = &fwrt->fw->img[fwrt->cur_fw_img]; 839 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 840 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 841 } else { 842 sram_ofs = fwrt->trans->cfg->dccm_offset; 843 sram_len = fwrt->trans->cfg->dccm_len; 844 } 845 846 /* reading RXF/TXF sizes */ 847 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 848 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 849 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 850 851 /* Make room for PRPH registers */ 852 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 853 iwl_fw_prph_handler(fwrt, &prph_len, 854 iwl_fw_get_prph_len); 855 856 if (fwrt->trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 && 857 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 858 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 859 } 860 861 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 862 863 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 864 file_len += sizeof(*dump_data) + sizeof(*dump_info); 865 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 866 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 867 868 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 869 size_t hdr_len = sizeof(*dump_data) + 870 sizeof(struct iwl_fw_error_dump_mem); 871 872 /* Dump SRAM only if no mem_tlvs */ 873 if (!fwrt->fw->dbg.n_mem_tlv) 874 ADD_LEN(file_len, sram_len, hdr_len); 875 876 /* Make room for all mem types that exist */ 877 ADD_LEN(file_len, smem_len, hdr_len); 878 ADD_LEN(file_len, sram2_len, hdr_len); 879 880 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 881 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 882 } 883 884 /* Make room for fw's virtual image pages, if it exists */ 885 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 886 file_len += fwrt->num_of_paging_blk * 887 (sizeof(*dump_data) + 888 sizeof(struct iwl_fw_error_dump_paging) + 889 PAGING_BLOCK_SIZE); 890 891 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 892 file_len += sizeof(*dump_data) + 893 fwrt->trans->cfg->d3_debug_data_length * 2; 894 } 895 896 /* If we only want a monitor dump, reset the file length */ 897 if (fwrt->dump.monitor_only) { 898 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 899 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 900 } 901 902 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 903 fwrt->dump.desc) 904 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 905 fwrt->dump.desc->len; 906 907 dump_file = vzalloc(file_len); 908 if (!dump_file) 909 return NULL; 910 911 fw_error_dump->fwrt_ptr = dump_file; 912 913 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 914 dump_data = (void *)dump_file->data; 915 916 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 917 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 918 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 919 dump_info = (void *)dump_data->data; 920 dump_info->hw_type = 921 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 922 dump_info->hw_step = 923 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 924 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 925 sizeof(dump_info->fw_human_readable)); 926 strncpy(dump_info->dev_human_readable, fwrt->trans->cfg->name, 927 sizeof(dump_info->dev_human_readable) - 1); 928 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 929 sizeof(dump_info->bus_human_readable) - 1); 930 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 931 dump_info->lmac_err_id[0] = 932 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 933 if (fwrt->smem_cfg.num_lmacs > 1) 934 dump_info->lmac_err_id[1] = 935 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 936 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 937 938 dump_data = iwl_fw_error_next_data(dump_data); 939 } 940 941 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 942 /* Dump shared memory configuration */ 943 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 944 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 945 dump_smem_cfg = (void *)dump_data->data; 946 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 947 dump_smem_cfg->num_txfifo_entries = 948 cpu_to_le32(mem_cfg->num_txfifo_entries); 949 for (i = 0; i < MAX_NUM_LMAC; i++) { 950 int j; 951 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 952 953 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 954 dump_smem_cfg->lmac[i].txfifo_size[j] = 955 cpu_to_le32(txf_size[j]); 956 dump_smem_cfg->lmac[i].rxfifo1_size = 957 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 958 } 959 dump_smem_cfg->rxfifo2_size = 960 cpu_to_le32(mem_cfg->rxfifo2_size); 961 dump_smem_cfg->internal_txfifo_addr = 962 cpu_to_le32(mem_cfg->internal_txfifo_addr); 963 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 964 dump_smem_cfg->internal_txfifo_size[i] = 965 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 966 } 967 968 dump_data = iwl_fw_error_next_data(dump_data); 969 } 970 971 /* We only dump the FIFOs if the FW is in error state */ 972 if (fifo_len) { 973 iwl_fw_dump_rxf(fwrt, &dump_data); 974 iwl_fw_dump_txf(fwrt, &dump_data); 975 } 976 977 if (radio_len) 978 iwl_read_radio_regs(fwrt, &dump_data); 979 980 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 981 fwrt->dump.desc) { 982 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 983 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 984 fwrt->dump.desc->len); 985 dump_trig = (void *)dump_data->data; 986 memcpy(dump_trig, &fwrt->dump.desc->trig_desc, 987 sizeof(*dump_trig) + fwrt->dump.desc->len); 988 989 dump_data = iwl_fw_error_next_data(dump_data); 990 } 991 992 /* In case we only want monitor dump, skip to dump trasport data */ 993 if (fwrt->dump.monitor_only) 994 goto out; 995 996 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 997 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 998 fwrt->fw->dbg.mem_tlv; 999 1000 if (!fwrt->fw->dbg.n_mem_tlv) 1001 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 1002 IWL_FW_ERROR_DUMP_MEM_SRAM); 1003 1004 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 1005 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 1006 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 1007 1008 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 1009 le32_to_cpu(fw_dbg_mem[i].data_type)); 1010 } 1011 1012 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 1013 fwrt->trans->cfg->smem_offset, 1014 IWL_FW_ERROR_DUMP_MEM_SMEM); 1015 1016 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 1017 fwrt->trans->cfg->dccm2_offset, 1018 IWL_FW_ERROR_DUMP_MEM_SRAM); 1019 } 1020 1021 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 1022 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 1023 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 1024 1025 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 1026 dump_data->len = cpu_to_le32(data_size * 2); 1027 1028 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 1029 1030 kfree(fwrt->dump.d3_debug_data); 1031 fwrt->dump.d3_debug_data = NULL; 1032 1033 iwl_trans_read_mem_bytes(fwrt->trans, addr, 1034 dump_data->data + data_size, 1035 data_size); 1036 1037 dump_data = iwl_fw_error_next_data(dump_data); 1038 } 1039 1040 /* Dump fw's virtual image */ 1041 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1042 iwl_dump_paging(fwrt, &dump_data); 1043 1044 if (prph_len) 1045 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1046 1047 out: 1048 dump_file->file_len = cpu_to_le32(file_len); 1049 return dump_file; 1050 } 1051 1052 static int iwl_dump_ini_prph_iter(struct iwl_fw_runtime *fwrt, 1053 struct iwl_fw_ini_region_cfg *reg, 1054 void *range_ptr, int idx) 1055 { 1056 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1057 __le32 *val = range->data; 1058 u32 prph_val; 1059 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1060 int i; 1061 1062 range->start_addr = cpu_to_le64(addr); 1063 range->range_data_size = reg->internal.range_data_size; 1064 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) { 1065 prph_val = iwl_read_prph(fwrt->trans, addr + i); 1066 if (prph_val == 0x5a5a5a5a) 1067 return -EBUSY; 1068 *val++ = cpu_to_le32(prph_val); 1069 } 1070 1071 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1072 } 1073 1074 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1075 struct iwl_fw_ini_region_cfg *reg, 1076 void *range_ptr, int idx) 1077 { 1078 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1079 __le32 *val = range->data; 1080 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1081 int i; 1082 1083 range->start_addr = cpu_to_le64(addr); 1084 range->range_data_size = reg->internal.range_data_size; 1085 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) 1086 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1087 1088 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1089 } 1090 1091 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1092 struct iwl_fw_ini_region_cfg *reg, 1093 void *range_ptr, int idx) 1094 { 1095 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1096 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1097 1098 range->start_addr = cpu_to_le64(addr); 1099 range->range_data_size = reg->internal.range_data_size; 1100 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1101 le32_to_cpu(reg->internal.range_data_size)); 1102 1103 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1104 } 1105 1106 static int 1107 iwl_dump_ini_paging_gen2_iter(struct iwl_fw_runtime *fwrt, 1108 struct iwl_fw_ini_region_cfg *reg, 1109 void *range_ptr, int idx) 1110 { 1111 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1112 u32 page_size = fwrt->trans->init_dram.paging[idx].size; 1113 1114 range->start_addr = cpu_to_le64(idx); 1115 range->range_data_size = cpu_to_le32(page_size); 1116 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1117 page_size); 1118 1119 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1120 } 1121 1122 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1123 struct iwl_fw_ini_region_cfg *reg, 1124 void *range_ptr, int idx) 1125 { 1126 /* increase idx by 1 since the pages are from 1 to 1127 * fwrt->num_of_paging_blk + 1 1128 */ 1129 struct page *page = fwrt->fw_paging_db[++idx].fw_paging_block; 1130 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1131 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1132 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1133 1134 range->start_addr = cpu_to_le64(idx); 1135 range->range_data_size = cpu_to_le32(page_size); 1136 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1137 DMA_BIDIRECTIONAL); 1138 memcpy(range->data, page_address(page), page_size); 1139 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1140 DMA_BIDIRECTIONAL); 1141 1142 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1143 } 1144 1145 static int 1146 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1147 struct iwl_fw_ini_region_cfg *reg, void *range_ptr, 1148 int idx) 1149 { 1150 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1151 u32 start_addr = iwl_read_umac_prph(fwrt->trans, 1152 MON_BUFF_BASE_ADDR_VER2); 1153 1154 if (start_addr == 0x5a5a5a5a) 1155 return -EBUSY; 1156 1157 range->start_addr = cpu_to_le64(start_addr); 1158 range->range_data_size = cpu_to_le32(fwrt->trans->fw_mon[idx].size); 1159 1160 memcpy(range->data, fwrt->trans->fw_mon[idx].block, 1161 fwrt->trans->fw_mon[idx].size); 1162 1163 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1164 } 1165 1166 struct iwl_ini_txf_iter_data { 1167 int fifo; 1168 int lmac; 1169 u32 fifo_size; 1170 bool internal_txf; 1171 bool init; 1172 }; 1173 1174 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1175 struct iwl_fw_ini_region_cfg *reg) 1176 { 1177 struct iwl_ini_txf_iter_data *iter = fwrt->dump.fifo_iter; 1178 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1179 int txf_num = cfg->num_txfifo_entries; 1180 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1181 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid1); 1182 1183 if (!iter) 1184 return false; 1185 1186 if (iter->init) { 1187 if (le32_to_cpu(reg->offset) && 1188 WARN_ONCE(cfg->num_lmacs == 1, 1189 "Invalid lmac offset: 0x%x\n", 1190 le32_to_cpu(reg->offset))) 1191 return false; 1192 1193 iter->init = false; 1194 iter->internal_txf = false; 1195 iter->fifo_size = 0; 1196 iter->fifo = -1; 1197 if (le32_to_cpu(reg->offset)) 1198 iter->lmac = 1; 1199 else 1200 iter->lmac = 0; 1201 } 1202 1203 if (!iter->internal_txf) 1204 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1205 iter->fifo_size = 1206 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1207 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1208 return true; 1209 } 1210 1211 iter->internal_txf = true; 1212 1213 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1214 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1215 return false; 1216 1217 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1218 iter->fifo_size = 1219 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1220 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1221 return true; 1222 } 1223 1224 return false; 1225 } 1226 1227 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1228 struct iwl_fw_ini_region_cfg *reg, 1229 void *range_ptr, int idx) 1230 { 1231 struct iwl_fw_ini_fifo_error_dump_range *range = range_ptr; 1232 struct iwl_ini_txf_iter_data *iter; 1233 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1234 u32 offs = le32_to_cpu(reg->offset), addr; 1235 u32 registers_size = 1236 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump); 1237 __le32 *data; 1238 unsigned long flags; 1239 int i; 1240 1241 if (!iwl_ini_txf_iter(fwrt, reg)) 1242 return -EIO; 1243 1244 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1245 return -EBUSY; 1246 1247 iter = fwrt->dump.fifo_iter; 1248 1249 range->fifo_num = cpu_to_le32(iter->fifo); 1250 range->num_of_registers = reg->fifos.num_of_registers; 1251 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1252 1253 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1254 1255 /* 1256 * read txf registers. for each register, write to the dump the 1257 * register address and its value 1258 */ 1259 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { 1260 addr = le32_to_cpu(reg->start_addr[i]) + offs; 1261 1262 reg_dump->addr = cpu_to_le32(addr); 1263 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1264 addr)); 1265 1266 reg_dump++; 1267 } 1268 1269 if (reg->fifos.header_only) { 1270 range->range_data_size = cpu_to_le32(registers_size); 1271 goto out; 1272 } 1273 1274 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1275 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1276 TXF_WR_PTR + offs); 1277 1278 /* Dummy-read to advance the read pointer to the head */ 1279 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1280 1281 /* Read FIFO */ 1282 addr = TXF_READ_MODIFY_DATA + offs; 1283 data = (void *)reg_dump; 1284 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1285 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1286 1287 out: 1288 iwl_trans_release_nic_access(fwrt->trans, &flags); 1289 1290 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1291 } 1292 1293 struct iwl_ini_rxf_data { 1294 u32 fifo_num; 1295 u32 size; 1296 u32 offset; 1297 }; 1298 1299 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1300 struct iwl_fw_ini_region_cfg *reg, 1301 struct iwl_ini_rxf_data *data) 1302 { 1303 u32 fid1 = le32_to_cpu(reg->fifos.fid1); 1304 u32 fid2 = le32_to_cpu(reg->fifos.fid2); 1305 u32 fifo_idx; 1306 1307 if (!data) 1308 return; 1309 1310 memset(data, 0, sizeof(*data)); 1311 1312 if (WARN_ON_ONCE((fid1 && fid2) || (!fid1 && !fid2))) 1313 return; 1314 1315 fifo_idx = ffs(fid1) - 1; 1316 if (fid1 && !WARN_ON_ONCE((~BIT(fifo_idx) & fid1) || 1317 fifo_idx >= MAX_NUM_LMAC)) { 1318 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1319 data->fifo_num = fifo_idx; 1320 return; 1321 } 1322 1323 fifo_idx = ffs(fid2) - 1; 1324 if (fid2 && !WARN_ON_ONCE(fifo_idx != 0)) { 1325 data->size = fwrt->smem_cfg.rxfifo2_size; 1326 data->offset = RXF_DIFF_FROM_PREV; 1327 /* use bit 31 to distinguish between umac and lmac rxf while 1328 * parsing the dump 1329 */ 1330 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1331 return; 1332 } 1333 } 1334 1335 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1336 struct iwl_fw_ini_region_cfg *reg, 1337 void *range_ptr, int idx) 1338 { 1339 struct iwl_fw_ini_fifo_error_dump_range *range = range_ptr; 1340 struct iwl_ini_rxf_data rxf_data; 1341 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1342 u32 offs = le32_to_cpu(reg->offset), addr; 1343 u32 registers_size = 1344 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump); 1345 __le32 *data; 1346 unsigned long flags; 1347 int i; 1348 1349 iwl_ini_get_rxf_data(fwrt, reg, &rxf_data); 1350 if (!rxf_data.size) 1351 return -EIO; 1352 1353 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1354 return -EBUSY; 1355 1356 range->fifo_num = cpu_to_le32(rxf_data.fifo_num); 1357 range->num_of_registers = reg->fifos.num_of_registers; 1358 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1359 1360 /* 1361 * read rxf registers. for each register, write to the dump the 1362 * register address and its value 1363 */ 1364 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { 1365 addr = le32_to_cpu(reg->start_addr[i]) + offs; 1366 1367 reg_dump->addr = cpu_to_le32(addr); 1368 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1369 addr)); 1370 1371 reg_dump++; 1372 } 1373 1374 if (reg->fifos.header_only) { 1375 range->range_data_size = cpu_to_le32(registers_size); 1376 goto out; 1377 } 1378 1379 /* 1380 * region register have absolute value so apply rxf offset after 1381 * reading the registers 1382 */ 1383 offs += rxf_data.offset; 1384 1385 /* Lock fence */ 1386 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1387 /* Set fence pointer to the same place like WR pointer */ 1388 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1389 /* Set fence offset */ 1390 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1391 0x0); 1392 1393 /* Read FIFO */ 1394 addr = RXF_FIFO_RD_FENCE_INC + offs; 1395 data = (void *)reg_dump; 1396 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1397 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1398 1399 out: 1400 iwl_trans_release_nic_access(fwrt->trans, &flags); 1401 1402 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1403 } 1404 1405 static void *iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1406 struct iwl_fw_ini_region_cfg *reg, 1407 void *data) 1408 { 1409 struct iwl_fw_ini_error_dump *dump = data; 1410 1411 dump->header.version = cpu_to_le32(IWL_INI_DUMP_MEM_VER); 1412 1413 return dump->ranges; 1414 } 1415 1416 static void 1417 *iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, 1418 struct iwl_fw_ini_region_cfg *reg, 1419 struct iwl_fw_ini_monitor_dump *data, 1420 u32 write_ptr_addr, u32 write_ptr_msk, 1421 u32 cycle_cnt_addr, u32 cycle_cnt_msk) 1422 { 1423 u32 write_ptr, cycle_cnt; 1424 unsigned long flags; 1425 1426 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) { 1427 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1428 return NULL; 1429 } 1430 1431 write_ptr = iwl_read_prph_no_grab(fwrt->trans, write_ptr_addr); 1432 cycle_cnt = iwl_read_prph_no_grab(fwrt->trans, cycle_cnt_addr); 1433 1434 iwl_trans_release_nic_access(fwrt->trans, &flags); 1435 1436 data->header.version = cpu_to_le32(IWL_INI_DUMP_MONITOR_VER); 1437 data->write_ptr = cpu_to_le32(write_ptr & write_ptr_msk); 1438 data->cycle_cnt = cpu_to_le32(cycle_cnt & cycle_cnt_msk); 1439 1440 return data->ranges; 1441 } 1442 1443 static void 1444 *iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1445 struct iwl_fw_ini_region_cfg *reg, 1446 void *data) 1447 { 1448 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1449 u32 write_ptr_addr, write_ptr_msk, cycle_cnt_addr, cycle_cnt_msk; 1450 1451 switch (fwrt->trans->cfg->device_family) { 1452 case IWL_DEVICE_FAMILY_9000: 1453 case IWL_DEVICE_FAMILY_22000: 1454 write_ptr_addr = MON_BUFF_WRPTR_VER2; 1455 write_ptr_msk = -1; 1456 cycle_cnt_addr = MON_BUFF_CYCLE_CNT_VER2; 1457 cycle_cnt_msk = -1; 1458 break; 1459 default: 1460 IWL_ERR(fwrt, "Unsupported device family %d\n", 1461 fwrt->trans->cfg->device_family); 1462 return NULL; 1463 } 1464 1465 return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, write_ptr_addr, 1466 write_ptr_msk, cycle_cnt_addr, 1467 cycle_cnt_msk); 1468 } 1469 1470 static void 1471 *iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1472 struct iwl_fw_ini_region_cfg *reg, 1473 void *data) 1474 { 1475 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1476 const struct iwl_cfg *cfg = fwrt->trans->cfg; 1477 1478 if (fwrt->trans->cfg->device_family != IWL_DEVICE_FAMILY_9000 && 1479 fwrt->trans->cfg->device_family != IWL_DEVICE_FAMILY_22000) { 1480 IWL_ERR(fwrt, "Unsupported device family %d\n", 1481 fwrt->trans->cfg->device_family); 1482 return NULL; 1483 } 1484 1485 return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, 1486 cfg->fw_mon_smem_write_ptr_addr, 1487 cfg->fw_mon_smem_write_ptr_msk, 1488 cfg->fw_mon_smem_cycle_cnt_ptr_addr, 1489 cfg->fw_mon_smem_cycle_cnt_ptr_msk); 1490 1491 } 1492 1493 static void *iwl_dump_ini_fifo_fill_header(struct iwl_fw_runtime *fwrt, 1494 struct iwl_fw_ini_region_cfg *reg, 1495 void *data) 1496 { 1497 struct iwl_fw_ini_fifo_error_dump *dump = data; 1498 1499 dump->header.version = cpu_to_le32(IWL_INI_DUMP_FIFO_VER); 1500 1501 return dump->ranges; 1502 } 1503 1504 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1505 struct iwl_fw_ini_region_cfg *reg) 1506 { 1507 return le32_to_cpu(reg->internal.num_of_ranges); 1508 } 1509 1510 static u32 iwl_dump_ini_paging_gen2_ranges(struct iwl_fw_runtime *fwrt, 1511 struct iwl_fw_ini_region_cfg *reg) 1512 { 1513 return fwrt->trans->init_dram.paging_cnt; 1514 } 1515 1516 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1517 struct iwl_fw_ini_region_cfg *reg) 1518 { 1519 return fwrt->num_of_paging_blk; 1520 } 1521 1522 static u32 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1523 struct iwl_fw_ini_region_cfg *reg) 1524 { 1525 return 1; 1526 } 1527 1528 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1529 struct iwl_fw_ini_region_cfg *reg) 1530 { 1531 struct iwl_ini_txf_iter_data iter = { .init = true }; 1532 void *fifo_iter = fwrt->dump.fifo_iter; 1533 u32 num_of_fifos = 0; 1534 1535 fwrt->dump.fifo_iter = &iter; 1536 while (iwl_ini_txf_iter(fwrt, reg)) 1537 num_of_fifos++; 1538 1539 fwrt->dump.fifo_iter = fifo_iter; 1540 1541 return num_of_fifos; 1542 } 1543 1544 static u32 iwl_dump_ini_rxf_ranges(struct iwl_fw_runtime *fwrt, 1545 struct iwl_fw_ini_region_cfg *reg) 1546 { 1547 /* Each Rx fifo needs a different offset and therefore, it's 1548 * region can contain only one fifo, i.e. 1 memory range. 1549 */ 1550 return 1; 1551 } 1552 1553 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1554 struct iwl_fw_ini_region_cfg *reg) 1555 { 1556 return sizeof(struct iwl_fw_ini_error_dump) + 1557 iwl_dump_ini_mem_ranges(fwrt, reg) * 1558 (sizeof(struct iwl_fw_ini_error_dump_range) + 1559 le32_to_cpu(reg->internal.range_data_size)); 1560 } 1561 1562 static u32 iwl_dump_ini_paging_gen2_get_size(struct iwl_fw_runtime *fwrt, 1563 struct iwl_fw_ini_region_cfg *reg) 1564 { 1565 int i; 1566 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1567 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1568 1569 for (i = 0; i < iwl_dump_ini_paging_gen2_ranges(fwrt, reg); i++) 1570 size += range_header_len + 1571 fwrt->trans->init_dram.paging[i].size; 1572 1573 return size; 1574 } 1575 1576 static u32 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1577 struct iwl_fw_ini_region_cfg *reg) 1578 { 1579 int i; 1580 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1581 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1582 1583 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg); i++) 1584 size += range_header_len + fwrt->fw_paging_db[i].fw_paging_size; 1585 1586 return size; 1587 } 1588 1589 static u32 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 1590 struct iwl_fw_ini_region_cfg *reg) 1591 { 1592 u32 size = sizeof(struct iwl_fw_ini_monitor_dump) + 1593 sizeof(struct iwl_fw_ini_error_dump_range); 1594 1595 if (fwrt->trans->num_blocks) 1596 size += fwrt->trans->fw_mon[0].size; 1597 1598 return size; 1599 } 1600 1601 static u32 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 1602 struct iwl_fw_ini_region_cfg *reg) 1603 { 1604 return sizeof(struct iwl_fw_ini_monitor_dump) + 1605 iwl_dump_ini_mem_ranges(fwrt, reg) * 1606 (sizeof(struct iwl_fw_ini_error_dump_range) + 1607 le32_to_cpu(reg->internal.range_data_size)); 1608 } 1609 1610 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 1611 struct iwl_fw_ini_region_cfg *reg) 1612 { 1613 struct iwl_ini_txf_iter_data iter = { .init = true }; 1614 void *fifo_iter = fwrt->dump.fifo_iter; 1615 u32 size = 0; 1616 u32 fifo_hdr = sizeof(struct iwl_fw_ini_fifo_error_dump_range) + 1617 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(__le32) * 2; 1618 1619 fwrt->dump.fifo_iter = &iter; 1620 while (iwl_ini_txf_iter(fwrt, reg)) { 1621 size += fifo_hdr; 1622 if (!reg->fifos.header_only) 1623 size += iter.fifo_size; 1624 } 1625 1626 if (size) 1627 size += sizeof(struct iwl_fw_ini_fifo_error_dump); 1628 1629 fwrt->dump.fifo_iter = fifo_iter; 1630 1631 return size; 1632 } 1633 1634 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 1635 struct iwl_fw_ini_region_cfg *reg) 1636 { 1637 struct iwl_ini_rxf_data rx_data; 1638 u32 size = sizeof(struct iwl_fw_ini_fifo_error_dump) + 1639 sizeof(struct iwl_fw_ini_fifo_error_dump_range) + 1640 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(__le32) * 2; 1641 1642 if (reg->fifos.header_only) 1643 return size; 1644 1645 iwl_ini_get_rxf_data(fwrt, reg, &rx_data); 1646 size += rx_data.size; 1647 1648 return size; 1649 } 1650 1651 /** 1652 * struct iwl_dump_ini_mem_ops - ini memory dump operations 1653 * @get_num_of_ranges: returns the number of memory ranges in the region. 1654 * @get_size: returns the total size of the region. 1655 * @fill_mem_hdr: fills region type specific headers and returns pointer to 1656 * the first range or NULL if failed to fill headers. 1657 * @fill_range: copies a given memory range into the dump. 1658 * Returns the size of the range or negative error value otherwise. 1659 */ 1660 struct iwl_dump_ini_mem_ops { 1661 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 1662 struct iwl_fw_ini_region_cfg *reg); 1663 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 1664 struct iwl_fw_ini_region_cfg *reg); 1665 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 1666 struct iwl_fw_ini_region_cfg *reg, void *data); 1667 int (*fill_range)(struct iwl_fw_runtime *fwrt, 1668 struct iwl_fw_ini_region_cfg *reg, void *range, 1669 int idx); 1670 }; 1671 1672 /** 1673 * iwl_dump_ini_mem - copy a memory region into the dump 1674 * @fwrt: fw runtime struct. 1675 * @data: dump memory data. 1676 * @reg: region to copy to the dump. 1677 * @ops: memory dump operations. 1678 */ 1679 static void 1680 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, 1681 struct iwl_fw_error_dump_data **data, 1682 struct iwl_fw_ini_region_cfg *reg, 1683 struct iwl_dump_ini_mem_ops *ops) 1684 { 1685 struct iwl_fw_ini_error_dump_header *header = (void *)(*data)->data; 1686 u32 num_of_ranges, i, type = le32_to_cpu(reg->region_type); 1687 void *range; 1688 1689 if (WARN_ON(!ops || !ops->get_num_of_ranges || !ops->get_size || 1690 !ops->fill_mem_hdr || !ops->fill_range)) 1691 return; 1692 1693 IWL_DEBUG_FW(fwrt, "WRT: collecting region: id=%d, type=%d\n", 1694 le32_to_cpu(reg->region_id), type); 1695 1696 num_of_ranges = ops->get_num_of_ranges(fwrt, reg); 1697 1698 (*data)->type = cpu_to_le32(type | INI_DUMP_BIT); 1699 (*data)->len = cpu_to_le32(ops->get_size(fwrt, reg)); 1700 1701 header->region_id = reg->region_id; 1702 header->num_of_ranges = cpu_to_le32(num_of_ranges); 1703 header->name_len = cpu_to_le32(min_t(int, IWL_FW_INI_MAX_NAME, 1704 le32_to_cpu(reg->name_len))); 1705 memcpy(header->name, reg->name, le32_to_cpu(header->name_len)); 1706 1707 range = ops->fill_mem_hdr(fwrt, reg, header); 1708 if (!range) { 1709 IWL_ERR(fwrt, 1710 "WRT: failed to fill region header: id=%d, type=%d\n", 1711 le32_to_cpu(reg->region_id), type); 1712 memset(*data, 0, le32_to_cpu((*data)->len)); 1713 return; 1714 } 1715 1716 for (i = 0; i < num_of_ranges; i++) { 1717 int range_size = ops->fill_range(fwrt, reg, range, i); 1718 1719 if (range_size < 0) { 1720 IWL_ERR(fwrt, 1721 "WRT: failed to dump region: id=%d, type=%d\n", 1722 le32_to_cpu(reg->region_id), type); 1723 memset(*data, 0, le32_to_cpu((*data)->len)); 1724 return; 1725 } 1726 range = range + range_size; 1727 } 1728 *data = iwl_fw_error_next_data(*data); 1729 } 1730 1731 static int iwl_fw_ini_get_trigger_len(struct iwl_fw_runtime *fwrt, 1732 struct iwl_fw_ini_trigger *trigger) 1733 { 1734 int i, size = 0, hdr_len = sizeof(struct iwl_fw_error_dump_data); 1735 1736 if (!trigger || !trigger->num_regions) 1737 return 0; 1738 1739 for (i = 0; i < le32_to_cpu(trigger->num_regions); i++) { 1740 u32 reg_id = le32_to_cpu(trigger->data[i]); 1741 struct iwl_fw_ini_region_cfg *reg; 1742 1743 if (WARN_ON(reg_id >= ARRAY_SIZE(fwrt->dump.active_regs))) 1744 continue; 1745 1746 reg = fwrt->dump.active_regs[reg_id]; 1747 if (!reg) { 1748 IWL_WARN(fwrt, 1749 "WRT: unassigned region id %d, skipping\n", 1750 reg_id); 1751 continue; 1752 } 1753 1754 /* currently the driver supports always on domain only */ 1755 if (le32_to_cpu(reg->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON) 1756 continue; 1757 1758 switch (le32_to_cpu(reg->region_type)) { 1759 case IWL_FW_INI_REGION_DEVICE_MEMORY: 1760 case IWL_FW_INI_REGION_PERIPHERY_MAC: 1761 case IWL_FW_INI_REGION_PERIPHERY_PHY: 1762 case IWL_FW_INI_REGION_PERIPHERY_AUX: 1763 case IWL_FW_INI_REGION_CSR: 1764 case IWL_FW_INI_REGION_LMAC_ERROR_TABLE: 1765 case IWL_FW_INI_REGION_UMAC_ERROR_TABLE: 1766 size += hdr_len + iwl_dump_ini_mem_get_size(fwrt, reg); 1767 break; 1768 case IWL_FW_INI_REGION_TXF: 1769 size += hdr_len + iwl_dump_ini_txf_get_size(fwrt, reg); 1770 break; 1771 case IWL_FW_INI_REGION_RXF: 1772 size += hdr_len + iwl_dump_ini_rxf_get_size(fwrt, reg); 1773 break; 1774 case IWL_FW_INI_REGION_PAGING: 1775 size += hdr_len; 1776 if (iwl_fw_dbg_is_paging_enabled(fwrt)) { 1777 size += iwl_dump_ini_paging_get_size(fwrt, reg); 1778 } else { 1779 size += iwl_dump_ini_paging_gen2_get_size(fwrt, 1780 reg); 1781 } 1782 break; 1783 case IWL_FW_INI_REGION_DRAM_BUFFER: 1784 if (!fwrt->trans->num_blocks) 1785 break; 1786 size += hdr_len + 1787 iwl_dump_ini_mon_dram_get_size(fwrt, reg); 1788 break; 1789 case IWL_FW_INI_REGION_INTERNAL_BUFFER: 1790 size += hdr_len + 1791 iwl_dump_ini_mon_smem_get_size(fwrt, reg); 1792 break; 1793 case IWL_FW_INI_REGION_DRAM_IMR: 1794 /* Undefined yet */ 1795 default: 1796 break; 1797 } 1798 } 1799 return size; 1800 } 1801 1802 static void iwl_fw_ini_dump_trigger(struct iwl_fw_runtime *fwrt, 1803 struct iwl_fw_ini_trigger *trigger, 1804 struct iwl_fw_error_dump_data **data) 1805 { 1806 int i, num = le32_to_cpu(trigger->num_regions); 1807 1808 for (i = 0; i < num; i++) { 1809 u32 reg_id = le32_to_cpu(trigger->data[i]); 1810 struct iwl_fw_ini_region_cfg *reg; 1811 struct iwl_dump_ini_mem_ops ops; 1812 1813 if (reg_id >= ARRAY_SIZE(fwrt->dump.active_regs)) 1814 continue; 1815 1816 reg = fwrt->dump.active_regs[reg_id]; 1817 /* Don't warn, get_trigger_len already warned */ 1818 if (!reg) 1819 continue; 1820 1821 /* currently the driver supports always on domain only */ 1822 if (le32_to_cpu(reg->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON) 1823 continue; 1824 1825 switch (le32_to_cpu(reg->region_type)) { 1826 case IWL_FW_INI_REGION_DEVICE_MEMORY: 1827 case IWL_FW_INI_REGION_LMAC_ERROR_TABLE: 1828 case IWL_FW_INI_REGION_UMAC_ERROR_TABLE: 1829 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1830 ops.get_size = iwl_dump_ini_mem_get_size; 1831 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1832 ops.fill_range = iwl_dump_ini_dev_mem_iter; 1833 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1834 break; 1835 case IWL_FW_INI_REGION_PERIPHERY_MAC: 1836 case IWL_FW_INI_REGION_PERIPHERY_PHY: 1837 case IWL_FW_INI_REGION_PERIPHERY_AUX: 1838 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1839 ops.get_size = iwl_dump_ini_mem_get_size; 1840 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1841 ops.fill_range = iwl_dump_ini_prph_iter; 1842 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1843 break; 1844 case IWL_FW_INI_REGION_DRAM_BUFFER: 1845 ops.get_num_of_ranges = iwl_dump_ini_mon_dram_ranges; 1846 ops.get_size = iwl_dump_ini_mon_dram_get_size; 1847 ops.fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header; 1848 ops.fill_range = iwl_dump_ini_mon_dram_iter; 1849 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1850 break; 1851 case IWL_FW_INI_REGION_INTERNAL_BUFFER: 1852 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1853 ops.get_size = iwl_dump_ini_mon_smem_get_size; 1854 ops.fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header; 1855 ops.fill_range = iwl_dump_ini_dev_mem_iter; 1856 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1857 break; 1858 case IWL_FW_INI_REGION_PAGING: 1859 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1860 if (iwl_fw_dbg_is_paging_enabled(fwrt)) { 1861 ops.get_num_of_ranges = 1862 iwl_dump_ini_paging_ranges; 1863 ops.get_size = iwl_dump_ini_paging_get_size; 1864 ops.fill_range = iwl_dump_ini_paging_iter; 1865 } else { 1866 ops.get_num_of_ranges = 1867 iwl_dump_ini_paging_gen2_ranges; 1868 ops.get_size = 1869 iwl_dump_ini_paging_gen2_get_size; 1870 ops.fill_range = iwl_dump_ini_paging_gen2_iter; 1871 } 1872 1873 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1874 break; 1875 case IWL_FW_INI_REGION_TXF: { 1876 struct iwl_ini_txf_iter_data iter = { .init = true }; 1877 void *fifo_iter = fwrt->dump.fifo_iter; 1878 1879 fwrt->dump.fifo_iter = &iter; 1880 ops.get_num_of_ranges = iwl_dump_ini_txf_ranges; 1881 ops.get_size = iwl_dump_ini_txf_get_size; 1882 ops.fill_mem_hdr = iwl_dump_ini_fifo_fill_header; 1883 ops.fill_range = iwl_dump_ini_txf_iter; 1884 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1885 fwrt->dump.fifo_iter = fifo_iter; 1886 break; 1887 } 1888 case IWL_FW_INI_REGION_RXF: 1889 ops.get_num_of_ranges = iwl_dump_ini_rxf_ranges; 1890 ops.get_size = iwl_dump_ini_rxf_get_size; 1891 ops.fill_mem_hdr = iwl_dump_ini_fifo_fill_header; 1892 ops.fill_range = iwl_dump_ini_rxf_iter; 1893 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1894 break; 1895 case IWL_FW_INI_REGION_CSR: 1896 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1897 ops.get_size = iwl_dump_ini_mem_get_size; 1898 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1899 ops.fill_range = iwl_dump_ini_csr_iter; 1900 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1901 break; 1902 case IWL_FW_INI_REGION_DRAM_IMR: 1903 /* This is undefined yet */ 1904 default: 1905 break; 1906 } 1907 } 1908 } 1909 1910 static struct iwl_fw_error_dump_file * 1911 iwl_fw_error_ini_dump_file(struct iwl_fw_runtime *fwrt) 1912 { 1913 int size; 1914 struct iwl_fw_error_dump_data *dump_data; 1915 struct iwl_fw_error_dump_file *dump_file; 1916 struct iwl_fw_ini_trigger *trigger; 1917 enum iwl_fw_ini_trigger_id id = fwrt->dump.ini_trig_id; 1918 1919 if (!iwl_fw_ini_trigger_on(fwrt, id)) 1920 return NULL; 1921 1922 trigger = fwrt->dump.active_trigs[id].trig; 1923 1924 size = iwl_fw_ini_get_trigger_len(fwrt, trigger); 1925 if (!size) 1926 return NULL; 1927 1928 size += sizeof(*dump_file); 1929 1930 dump_file = vzalloc(size); 1931 if (!dump_file) 1932 return NULL; 1933 1934 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 1935 dump_data = (void *)dump_file->data; 1936 dump_file->file_len = cpu_to_le32(size); 1937 1938 iwl_fw_ini_dump_trigger(fwrt, trigger, &dump_data); 1939 1940 return dump_file; 1941 } 1942 1943 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt) 1944 { 1945 struct iwl_fw_dump_ptrs fw_error_dump = {}; 1946 struct iwl_fw_error_dump_file *dump_file; 1947 struct scatterlist *sg_dump_data; 1948 u32 file_len; 1949 u32 dump_mask = fwrt->fw->dbg.dump_mask; 1950 1951 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump); 1952 if (!dump_file) 1953 goto out; 1954 1955 if (!fwrt->trans->ini_valid && fwrt->dump.monitor_only) 1956 dump_mask &= IWL_FW_ERROR_DUMP_FW_MONITOR; 1957 1958 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask); 1959 file_len = le32_to_cpu(dump_file->file_len); 1960 fw_error_dump.fwrt_len = file_len; 1961 1962 if (fw_error_dump.trans_ptr) { 1963 file_len += fw_error_dump.trans_ptr->len; 1964 dump_file->file_len = cpu_to_le32(file_len); 1965 } 1966 1967 sg_dump_data = alloc_sgtable(file_len); 1968 if (sg_dump_data) { 1969 sg_pcopy_from_buffer(sg_dump_data, 1970 sg_nents(sg_dump_data), 1971 fw_error_dump.fwrt_ptr, 1972 fw_error_dump.fwrt_len, 0); 1973 if (fw_error_dump.trans_ptr) 1974 sg_pcopy_from_buffer(sg_dump_data, 1975 sg_nents(sg_dump_data), 1976 fw_error_dump.trans_ptr->data, 1977 fw_error_dump.trans_ptr->len, 1978 fw_error_dump.fwrt_len); 1979 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 1980 GFP_KERNEL); 1981 } 1982 vfree(fw_error_dump.fwrt_ptr); 1983 vfree(fw_error_dump.trans_ptr); 1984 1985 out: 1986 iwl_fw_free_dump_desc(fwrt); 1987 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 1988 } 1989 1990 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt) 1991 { 1992 struct iwl_fw_error_dump_file *dump_file; 1993 struct scatterlist *sg_dump_data; 1994 u32 file_len; 1995 1996 dump_file = iwl_fw_error_ini_dump_file(fwrt); 1997 if (!dump_file) 1998 goto out; 1999 2000 file_len = le32_to_cpu(dump_file->file_len); 2001 2002 sg_dump_data = alloc_sgtable(file_len); 2003 if (sg_dump_data) { 2004 sg_pcopy_from_buffer(sg_dump_data, sg_nents(sg_dump_data), 2005 dump_file, file_len, 0); 2006 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2007 GFP_KERNEL); 2008 } 2009 vfree(dump_file); 2010 out: 2011 fwrt->dump.ini_trig_id = IWL_FW_TRIGGER_ID_INVALID; 2012 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 2013 } 2014 2015 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2016 .trig_desc = { 2017 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2018 }, 2019 }; 2020 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2021 2022 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2023 const struct iwl_fw_dump_desc *desc, 2024 bool monitor_only, 2025 unsigned int delay) 2026 { 2027 u32 trig_type = le32_to_cpu(desc->trig_desc.type); 2028 int ret; 2029 2030 if (fwrt->trans->ini_valid) { 2031 ret = iwl_fw_dbg_ini_collect(fwrt, trig_type); 2032 if (!ret) 2033 iwl_fw_free_dump_desc(fwrt); 2034 2035 return ret; 2036 } 2037 2038 if (test_and_set_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 2039 return -EBUSY; 2040 2041 if (WARN_ON(fwrt->dump.desc)) 2042 iwl_fw_free_dump_desc(fwrt); 2043 2044 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2045 le32_to_cpu(desc->trig_desc.type)); 2046 2047 fwrt->dump.desc = desc; 2048 fwrt->dump.monitor_only = monitor_only; 2049 2050 schedule_delayed_work(&fwrt->dump.wk, usecs_to_jiffies(delay)); 2051 2052 return 0; 2053 } 2054 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2055 2056 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2057 enum iwl_fw_dbg_trigger trig_type) 2058 { 2059 int ret; 2060 struct iwl_fw_dump_desc *iwl_dump_error_desc = 2061 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2062 2063 if (!iwl_dump_error_desc) 2064 return -ENOMEM; 2065 2066 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2067 iwl_dump_error_desc->len = 0; 2068 2069 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, false, 0); 2070 if (ret) 2071 kfree(iwl_dump_error_desc); 2072 else 2073 iwl_trans_sync_nmi(fwrt->trans); 2074 2075 return ret; 2076 } 2077 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2078 2079 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2080 enum iwl_fw_dbg_trigger trig, 2081 const char *str, size_t len, 2082 struct iwl_fw_dbg_trigger_tlv *trigger) 2083 { 2084 struct iwl_fw_dump_desc *desc; 2085 unsigned int delay = 0; 2086 bool monitor_only = false; 2087 2088 if (trigger) { 2089 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2090 2091 if (!le16_to_cpu(trigger->occurrences)) 2092 return 0; 2093 2094 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2095 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2096 trig); 2097 iwl_force_nmi(fwrt->trans); 2098 return 0; 2099 } 2100 2101 trigger->occurrences = cpu_to_le16(occurrences); 2102 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2103 2104 /* convert msec to usec */ 2105 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2106 } 2107 2108 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 2109 if (!desc) 2110 return -ENOMEM; 2111 2112 2113 desc->len = len; 2114 desc->trig_desc.type = cpu_to_le32(trig); 2115 memcpy(desc->trig_desc.data, str, len); 2116 2117 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2118 } 2119 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2120 2121 int _iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 2122 enum iwl_fw_ini_trigger_id id) 2123 { 2124 struct iwl_fw_ini_active_triggers *active; 2125 u32 occur, delay; 2126 2127 if (WARN_ON(!iwl_fw_ini_trigger_on(fwrt, id))) 2128 return -EINVAL; 2129 2130 if (test_and_set_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 2131 return -EBUSY; 2132 2133 if (!iwl_fw_ini_trigger_on(fwrt, id)) { 2134 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 2135 id); 2136 return -EINVAL; 2137 } 2138 2139 active = &fwrt->dump.active_trigs[id]; 2140 delay = le32_to_cpu(active->trig->dump_delay); 2141 occur = le32_to_cpu(active->trig->occurrences); 2142 if (!occur) 2143 return 0; 2144 2145 active->trig->occurrences = cpu_to_le32(--occur); 2146 2147 if (le32_to_cpu(active->trig->force_restart)) { 2148 IWL_WARN(fwrt, "WRT: force restart: trigger %d fired.\n", id); 2149 iwl_force_nmi(fwrt->trans); 2150 return 0; 2151 } 2152 2153 if (test_and_set_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 2154 return -EBUSY; 2155 2156 fwrt->dump.ini_trig_id = id; 2157 2158 IWL_WARN(fwrt, "WRT: collecting data: ini trigger %d fired.\n", id); 2159 2160 schedule_delayed_work(&fwrt->dump.wk, usecs_to_jiffies(delay)); 2161 2162 return 0; 2163 } 2164 IWL_EXPORT_SYMBOL(_iwl_fw_dbg_ini_collect); 2165 2166 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, u32 legacy_trigger_id) 2167 { 2168 int id; 2169 2170 switch (legacy_trigger_id) { 2171 case FW_DBG_TRIGGER_FW_ASSERT: 2172 case FW_DBG_TRIGGER_ALIVE_TIMEOUT: 2173 case FW_DBG_TRIGGER_DRIVER: 2174 id = IWL_FW_TRIGGER_ID_FW_ASSERT; 2175 break; 2176 case FW_DBG_TRIGGER_USER: 2177 id = IWL_FW_TRIGGER_ID_USER_TRIGGER; 2178 break; 2179 default: 2180 return -EIO; 2181 } 2182 2183 return _iwl_fw_dbg_ini_collect(fwrt, id); 2184 } 2185 IWL_EXPORT_SYMBOL(iwl_fw_dbg_ini_collect); 2186 2187 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2188 struct iwl_fw_dbg_trigger_tlv *trigger, 2189 const char *fmt, ...) 2190 { 2191 int ret, len = 0; 2192 char buf[64]; 2193 2194 if (fwrt->trans->ini_valid) 2195 return 0; 2196 2197 if (fmt) { 2198 va_list ap; 2199 2200 buf[sizeof(buf) - 1] = '\0'; 2201 2202 va_start(ap, fmt); 2203 vsnprintf(buf, sizeof(buf), fmt, ap); 2204 va_end(ap); 2205 2206 /* check for truncation */ 2207 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2208 buf[sizeof(buf) - 1] = '\0'; 2209 2210 len = strlen(buf) + 1; 2211 } 2212 2213 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2214 trigger); 2215 2216 if (ret) 2217 return ret; 2218 2219 return 0; 2220 } 2221 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2222 2223 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2224 { 2225 u8 *ptr; 2226 int ret; 2227 int i; 2228 2229 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 2230 "Invalid configuration %d\n", conf_id)) 2231 return -EINVAL; 2232 2233 /* EARLY START - firmware's configuration is hard coded */ 2234 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 2235 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 2236 conf_id == FW_DBG_START_FROM_ALIVE) 2237 return 0; 2238 2239 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 2240 return -EINVAL; 2241 2242 if (fwrt->dump.conf != FW_DBG_INVALID) 2243 IWL_WARN(fwrt, "FW already configured (%d) - re-configuring\n", 2244 fwrt->dump.conf); 2245 2246 /* Send all HCMDs for configuring the FW debug */ 2247 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 2248 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 2249 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 2250 struct iwl_host_cmd hcmd = { 2251 .id = cmd->id, 2252 .len = { le16_to_cpu(cmd->len), }, 2253 .data = { cmd->data, }, 2254 }; 2255 2256 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 2257 if (ret) 2258 return ret; 2259 2260 ptr += sizeof(*cmd); 2261 ptr += le16_to_cpu(cmd->len); 2262 } 2263 2264 fwrt->dump.conf = conf_id; 2265 2266 return 0; 2267 } 2268 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 2269 2270 /* this function assumes dump_start was called beforehand and dump_end will be 2271 * called afterwards 2272 */ 2273 void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt) 2274 { 2275 struct iwl_fw_dbg_params params = {0}; 2276 2277 if (!test_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 2278 return; 2279 2280 if (fwrt->ops && fwrt->ops->fw_running && 2281 !fwrt->ops->fw_running(fwrt->ops_ctx)) { 2282 IWL_ERR(fwrt, "Firmware not running - cannot dump error\n"); 2283 iwl_fw_free_dump_desc(fwrt); 2284 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 2285 return; 2286 } 2287 2288 /* there's no point in fw dump if the bus is dead */ 2289 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 2290 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 2291 return; 2292 } 2293 2294 iwl_fw_dbg_stop_recording(fwrt, ¶ms); 2295 2296 IWL_DEBUG_FW_INFO(fwrt, "WRT: data collection start\n"); 2297 if (fwrt->trans->ini_valid) 2298 iwl_fw_error_ini_dump(fwrt); 2299 else 2300 iwl_fw_error_dump(fwrt); 2301 IWL_DEBUG_FW_INFO(fwrt, "WRT: data collection done\n"); 2302 2303 /* start recording again if the firmware is not crashed */ 2304 if (!test_bit(STATUS_FW_ERROR, &fwrt->trans->status) && 2305 fwrt->fw->dbg.dest_tlv) { 2306 /* wait before we collect the data till the DBGC stop */ 2307 udelay(500); 2308 iwl_fw_dbg_restart_recording(fwrt, ¶ms); 2309 } 2310 } 2311 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_sync); 2312 2313 void iwl_fw_error_dump_wk(struct work_struct *work) 2314 { 2315 struct iwl_fw_runtime *fwrt = 2316 container_of(work, struct iwl_fw_runtime, dump.wk.work); 2317 2318 if (fwrt->ops && fwrt->ops->dump_start && 2319 fwrt->ops->dump_start(fwrt->ops_ctx)) 2320 return; 2321 2322 iwl_fw_dbg_collect_sync(fwrt); 2323 2324 if (fwrt->ops && fwrt->ops->dump_end) 2325 fwrt->ops->dump_end(fwrt->ops_ctx); 2326 } 2327 2328 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 2329 { 2330 const struct iwl_cfg *cfg = fwrt->trans->cfg; 2331 2332 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 2333 return; 2334 2335 if (!fwrt->dump.d3_debug_data) { 2336 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 2337 GFP_KERNEL); 2338 if (!fwrt->dump.d3_debug_data) { 2339 IWL_ERR(fwrt, 2340 "failed to allocate memory for D3 debug data\n"); 2341 return; 2342 } 2343 } 2344 2345 /* if the buffer holds previous debug data it is overwritten */ 2346 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 2347 fwrt->dump.d3_debug_data, 2348 cfg->d3_debug_data_length); 2349 } 2350 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 2351 2352 static void 2353 iwl_fw_dbg_buffer_allocation(struct iwl_fw_runtime *fwrt, u32 size) 2354 { 2355 struct iwl_trans *trans = fwrt->trans; 2356 void *virtual_addr = NULL; 2357 dma_addr_t phys_addr; 2358 2359 if (WARN_ON_ONCE(trans->num_blocks == ARRAY_SIZE(trans->fw_mon))) 2360 return; 2361 2362 virtual_addr = 2363 dma_alloc_coherent(fwrt->trans->dev, size, &phys_addr, 2364 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO | 2365 __GFP_COMP); 2366 2367 /* TODO: alloc fragments if needed */ 2368 if (!virtual_addr) 2369 IWL_ERR(fwrt, "Failed to allocate debug memory\n"); 2370 2371 IWL_DEBUG_FW(trans, 2372 "Allocated DRAM buffer[%d], size=0x%x\n", 2373 trans->num_blocks, size); 2374 2375 trans->fw_mon[trans->num_blocks].block = virtual_addr; 2376 trans->fw_mon[trans->num_blocks].physical = phys_addr; 2377 trans->fw_mon[trans->num_blocks].size = size; 2378 trans->num_blocks++; 2379 } 2380 2381 static void iwl_fw_dbg_buffer_apply(struct iwl_fw_runtime *fwrt, 2382 struct iwl_fw_ini_allocation_data *alloc, 2383 enum iwl_fw_ini_apply_point pnt) 2384 { 2385 struct iwl_trans *trans = fwrt->trans; 2386 struct iwl_ldbg_config_cmd ldbg_cmd = { 2387 .type = cpu_to_le32(BUFFER_ALLOCATION), 2388 }; 2389 struct iwl_buffer_allocation_cmd *cmd = &ldbg_cmd.buffer_allocation; 2390 struct iwl_host_cmd hcmd = { 2391 .id = LDBG_CONFIG_CMD, 2392 .flags = CMD_ASYNC, 2393 .data[0] = &ldbg_cmd, 2394 .len[0] = sizeof(ldbg_cmd), 2395 }; 2396 int block_idx = trans->num_blocks; 2397 u32 buf_location = le32_to_cpu(alloc->tlv.buffer_location); 2398 2399 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH) { 2400 if (!WARN(pnt != IWL_FW_INI_APPLY_EARLY, 2401 "WRT: Invalid apply point %d for SMEM buffer allocation, aborting\n", 2402 pnt)) { 2403 IWL_DEBUG_FW(trans, 2404 "WRT: applying SMEM buffer destination\n"); 2405 2406 /* set sram monitor by enabling bit 7 */ 2407 iwl_set_bit(fwrt->trans, CSR_HW_IF_CONFIG_REG, 2408 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 2409 } 2410 return; 2411 } 2412 2413 if (buf_location != IWL_FW_INI_LOCATION_DRAM_PATH) 2414 return; 2415 2416 if (!alloc->is_alloc) { 2417 iwl_fw_dbg_buffer_allocation(fwrt, 2418 le32_to_cpu(alloc->tlv.size)); 2419 if (block_idx == trans->num_blocks) 2420 return; 2421 alloc->is_alloc = 1; 2422 } 2423 2424 /* First block is assigned via registers / context info */ 2425 if (trans->num_blocks == 1) 2426 return; 2427 2428 IWL_DEBUG_FW(trans, 2429 "WRT: applying DRAM buffer[%d] destination\n", block_idx); 2430 2431 cmd->num_frags = cpu_to_le32(1); 2432 cmd->fragments[0].address = 2433 cpu_to_le64(trans->fw_mon[block_idx].physical); 2434 cmd->fragments[0].size = alloc->tlv.size; 2435 cmd->allocation_id = alloc->tlv.allocation_id; 2436 cmd->buffer_location = alloc->tlv.buffer_location; 2437 2438 iwl_trans_send_cmd(trans, &hcmd); 2439 } 2440 2441 static void iwl_fw_dbg_send_hcmd(struct iwl_fw_runtime *fwrt, 2442 struct iwl_ucode_tlv *tlv, 2443 bool ext) 2444 { 2445 struct iwl_fw_ini_hcmd_tlv *hcmd_tlv = (void *)&tlv->data[0]; 2446 struct iwl_fw_ini_hcmd *data = &hcmd_tlv->hcmd; 2447 u16 len = le32_to_cpu(tlv->length) - sizeof(*hcmd_tlv); 2448 2449 struct iwl_host_cmd hcmd = { 2450 .id = WIDE_ID(data->group, data->id), 2451 .len = { len, }, 2452 .data = { data->data, }, 2453 }; 2454 2455 /* currently the driver supports always on domain only */ 2456 if (le32_to_cpu(hcmd_tlv->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON) 2457 return; 2458 2459 IWL_DEBUG_FW(fwrt, 2460 "WRT: ext=%d. Sending host command id=0x%x, group=0x%x\n", 2461 ext, data->id, data->group); 2462 2463 iwl_trans_send_cmd(fwrt->trans, &hcmd); 2464 } 2465 2466 static void iwl_fw_dbg_update_regions(struct iwl_fw_runtime *fwrt, 2467 struct iwl_fw_ini_region_tlv *tlv, 2468 bool ext, enum iwl_fw_ini_apply_point pnt) 2469 { 2470 void *iter = (void *)tlv->region_config; 2471 int i, size = le32_to_cpu(tlv->num_regions); 2472 const char *err_st = 2473 "WRT: ext=%d. Invalid region %s %d for apply point %d\n"; 2474 2475 for (i = 0; i < size; i++) { 2476 struct iwl_fw_ini_region_cfg *reg = iter, **active; 2477 int id = le32_to_cpu(reg->region_id); 2478 u32 type = le32_to_cpu(reg->region_type); 2479 2480 if (WARN(id >= ARRAY_SIZE(fwrt->dump.active_regs), err_st, ext, 2481 "id", id, pnt)) 2482 break; 2483 2484 if (WARN(type == 0 || type >= IWL_FW_INI_REGION_NUM, err_st, 2485 ext, "type", type, pnt)) 2486 break; 2487 2488 active = &fwrt->dump.active_regs[id]; 2489 2490 if (*active) 2491 IWL_WARN(fwrt->trans, 2492 "WRT: ext=%d. Region id %d override\n", 2493 ext, id); 2494 2495 IWL_DEBUG_FW(fwrt, 2496 "WRT: ext=%d. Activating region id %d\n", 2497 ext, id); 2498 2499 *active = reg; 2500 2501 if (type == IWL_FW_INI_REGION_TXF || 2502 type == IWL_FW_INI_REGION_RXF) 2503 iter += le32_to_cpu(reg->fifos.num_of_registers) * 2504 sizeof(__le32); 2505 else if (type == IWL_FW_INI_REGION_DEVICE_MEMORY || 2506 type == IWL_FW_INI_REGION_PERIPHERY_MAC || 2507 type == IWL_FW_INI_REGION_PERIPHERY_PHY || 2508 type == IWL_FW_INI_REGION_PERIPHERY_AUX || 2509 type == IWL_FW_INI_REGION_INTERNAL_BUFFER || 2510 type == IWL_FW_INI_REGION_PAGING || 2511 type == IWL_FW_INI_REGION_CSR || 2512 type == IWL_FW_INI_REGION_LMAC_ERROR_TABLE || 2513 type == IWL_FW_INI_REGION_UMAC_ERROR_TABLE) 2514 iter += le32_to_cpu(reg->internal.num_of_ranges) * 2515 sizeof(__le32); 2516 2517 iter += sizeof(*reg); 2518 } 2519 } 2520 2521 static int iwl_fw_dbg_trig_realloc(struct iwl_fw_runtime *fwrt, 2522 struct iwl_fw_ini_active_triggers *active, 2523 u32 id, int size) 2524 { 2525 void *ptr; 2526 2527 if (size <= active->size) 2528 return 0; 2529 2530 ptr = krealloc(active->trig, size, GFP_KERNEL); 2531 if (!ptr) { 2532 IWL_ERR(fwrt, "WRT: Failed to allocate memory for trigger %d\n", 2533 id); 2534 return -ENOMEM; 2535 } 2536 active->trig = ptr; 2537 active->size = size; 2538 2539 return 0; 2540 } 2541 2542 static void iwl_fw_dbg_update_triggers(struct iwl_fw_runtime *fwrt, 2543 struct iwl_fw_ini_trigger_tlv *tlv, 2544 bool ext, 2545 enum iwl_fw_ini_apply_point apply_point) 2546 { 2547 int i, size = le32_to_cpu(tlv->num_triggers); 2548 void *iter = (void *)tlv->trigger_config; 2549 2550 for (i = 0; i < size; i++) { 2551 struct iwl_fw_ini_trigger *trig = iter; 2552 struct iwl_fw_ini_active_triggers *active; 2553 int id = le32_to_cpu(trig->trigger_id); 2554 u32 trig_regs_size = le32_to_cpu(trig->num_regions) * 2555 sizeof(__le32); 2556 2557 if (WARN(id >= ARRAY_SIZE(fwrt->dump.active_trigs), 2558 "WRT: ext=%d. Invalid trigger id %d for apply point %d\n", 2559 ext, id, apply_point)) 2560 break; 2561 2562 active = &fwrt->dump.active_trigs[id]; 2563 2564 if (!active->active) { 2565 size_t trig_size = sizeof(*trig) + trig_regs_size; 2566 2567 IWL_DEBUG_FW(fwrt, 2568 "WRT: ext=%d. Activating trigger %d\n", 2569 ext, id); 2570 2571 if (iwl_fw_dbg_trig_realloc(fwrt, active, id, 2572 trig_size)) 2573 goto next; 2574 2575 memcpy(active->trig, trig, trig_size); 2576 2577 } else { 2578 u32 conf_override = 2579 !(le32_to_cpu(trig->override_trig) & 0xff); 2580 u32 region_override = 2581 !(le32_to_cpu(trig->override_trig) & 0xff00); 2582 u32 offset = 0; 2583 u32 active_regs = 2584 le32_to_cpu(active->trig->num_regions); 2585 u32 new_regs = le32_to_cpu(trig->num_regions); 2586 int mem_to_add = trig_regs_size; 2587 2588 if (region_override) { 2589 IWL_DEBUG_FW(fwrt, 2590 "WRT: ext=%d. Trigger %d regions override\n", 2591 ext, id); 2592 2593 mem_to_add -= active_regs * sizeof(__le32); 2594 } else { 2595 IWL_DEBUG_FW(fwrt, 2596 "WRT: ext=%d. Trigger %d regions appending\n", 2597 ext, id); 2598 2599 offset += active_regs; 2600 new_regs += active_regs; 2601 } 2602 2603 if (iwl_fw_dbg_trig_realloc(fwrt, active, id, 2604 active->size + mem_to_add)) 2605 goto next; 2606 2607 if (conf_override) { 2608 IWL_DEBUG_FW(fwrt, 2609 "WRT: ext=%d. Trigger %d configuration override\n", 2610 ext, id); 2611 2612 memcpy(active->trig, trig, sizeof(*trig)); 2613 } 2614 2615 memcpy(active->trig->data + offset, trig->data, 2616 trig_regs_size); 2617 active->trig->num_regions = cpu_to_le32(new_regs); 2618 } 2619 2620 /* Since zero means infinity - just set to -1 */ 2621 if (!le32_to_cpu(active->trig->occurrences)) 2622 active->trig->occurrences = cpu_to_le32(-1); 2623 2624 active->active = true; 2625 2626 if (id == IWL_FW_TRIGGER_ID_PERIODIC_TRIGGER) { 2627 u32 collect_interval = le32_to_cpu(trig->trigger_data); 2628 2629 /* the minimum allowed interval is 50ms */ 2630 if (collect_interval < 50) { 2631 collect_interval = 50; 2632 trig->trigger_data = 2633 cpu_to_le32(collect_interval); 2634 } 2635 2636 mod_timer(&fwrt->dump.periodic_trig, 2637 jiffies + msecs_to_jiffies(collect_interval)); 2638 } 2639 next: 2640 iter += sizeof(*trig) + trig_regs_size; 2641 2642 } 2643 } 2644 2645 static void _iwl_fw_dbg_apply_point(struct iwl_fw_runtime *fwrt, 2646 struct iwl_apply_point_data *data, 2647 enum iwl_fw_ini_apply_point pnt, 2648 bool ext) 2649 { 2650 void *iter = data->data; 2651 2652 while (iter && iter < data->data + data->size) { 2653 struct iwl_ucode_tlv *tlv = iter; 2654 void *ini_tlv = (void *)tlv->data; 2655 u32 type = le32_to_cpu(tlv->type); 2656 2657 switch (type) { 2658 case IWL_UCODE_TLV_TYPE_BUFFER_ALLOCATION: { 2659 struct iwl_fw_ini_allocation_data *buf_alloc = ini_tlv; 2660 2661 iwl_fw_dbg_buffer_apply(fwrt, ini_tlv, pnt); 2662 iter += sizeof(buf_alloc->is_alloc); 2663 break; 2664 } 2665 case IWL_UCODE_TLV_TYPE_HCMD: 2666 if (pnt < IWL_FW_INI_APPLY_AFTER_ALIVE) { 2667 IWL_ERR(fwrt, 2668 "WRT: ext=%d. Invalid apply point %d for host command\n", 2669 ext, pnt); 2670 goto next; 2671 } 2672 iwl_fw_dbg_send_hcmd(fwrt, tlv, ext); 2673 break; 2674 case IWL_UCODE_TLV_TYPE_REGIONS: 2675 iwl_fw_dbg_update_regions(fwrt, ini_tlv, ext, pnt); 2676 break; 2677 case IWL_UCODE_TLV_TYPE_TRIGGERS: 2678 iwl_fw_dbg_update_triggers(fwrt, ini_tlv, ext, pnt); 2679 break; 2680 case IWL_UCODE_TLV_TYPE_DEBUG_FLOW: 2681 break; 2682 default: 2683 WARN_ONCE(1, 2684 "WRT: ext=%d. Invalid TLV 0x%x for apply point\n", 2685 ext, type); 2686 break; 2687 } 2688 next: 2689 iter += sizeof(*tlv) + le32_to_cpu(tlv->length); 2690 } 2691 } 2692 2693 void iwl_fw_dbg_apply_point(struct iwl_fw_runtime *fwrt, 2694 enum iwl_fw_ini_apply_point apply_point) 2695 { 2696 void *data = &fwrt->trans->apply_points[apply_point]; 2697 int i; 2698 2699 IWL_DEBUG_FW(fwrt, "WRT: enabling apply point %d\n", apply_point); 2700 2701 if (apply_point == IWL_FW_INI_APPLY_EARLY) { 2702 for (i = 0; i < IWL_FW_INI_MAX_REGION_ID; i++) 2703 fwrt->dump.active_regs[i] = NULL; 2704 2705 /* disable the triggers, used in recovery flow */ 2706 for (i = 0; i < IWL_FW_TRIGGER_ID_NUM; i++) 2707 fwrt->dump.active_trigs[i].active = false; 2708 } 2709 2710 _iwl_fw_dbg_apply_point(fwrt, data, apply_point, false); 2711 2712 data = &fwrt->trans->apply_points_ext[apply_point]; 2713 _iwl_fw_dbg_apply_point(fwrt, data, apply_point, true); 2714 } 2715 IWL_EXPORT_SYMBOL(iwl_fw_dbg_apply_point); 2716 2717 void iwl_fwrt_stop_device(struct iwl_fw_runtime *fwrt) 2718 { 2719 del_timer(&fwrt->dump.periodic_trig); 2720 iwl_fw_dbg_collect_sync(fwrt); 2721 2722 iwl_trans_stop_device(fwrt->trans); 2723 } 2724 IWL_EXPORT_SYMBOL(iwl_fwrt_stop_device); 2725 2726 void iwl_fw_dbg_periodic_trig_handler(struct timer_list *t) 2727 { 2728 struct iwl_fw_runtime *fwrt; 2729 enum iwl_fw_ini_trigger_id id = IWL_FW_TRIGGER_ID_PERIODIC_TRIGGER; 2730 int ret; 2731 typeof(fwrt->dump) *dump_ptr = container_of(t, typeof(fwrt->dump), 2732 periodic_trig); 2733 2734 fwrt = container_of(dump_ptr, typeof(*fwrt), dump); 2735 2736 ret = _iwl_fw_dbg_ini_collect(fwrt, id); 2737 if (!ret || ret == -EBUSY) { 2738 struct iwl_fw_ini_trigger *trig = 2739 fwrt->dump.active_trigs[id].trig; 2740 u32 occur = le32_to_cpu(trig->occurrences); 2741 u32 collect_interval = le32_to_cpu(trig->trigger_data); 2742 2743 if (!occur) 2744 return; 2745 2746 mod_timer(&fwrt->dump.periodic_trig, 2747 jiffies + msecs_to_jiffies(collect_interval)); 2748 } 2749 } 2750 2751 #define FSEQ_REG(x) { .addr = (x), .str = #x, } 2752 2753 void iwl_fw_error_print_fseq_regs(struct iwl_fw_runtime *fwrt) 2754 { 2755 struct iwl_trans *trans = fwrt->trans; 2756 unsigned long flags; 2757 int i; 2758 struct { 2759 u32 addr; 2760 const char *str; 2761 } fseq_regs[] = { 2762 FSEQ_REG(FSEQ_ERROR_CODE), 2763 FSEQ_REG(FSEQ_TOP_INIT_VERSION), 2764 FSEQ_REG(FSEQ_CNVIO_INIT_VERSION), 2765 FSEQ_REG(FSEQ_OTP_VERSION), 2766 FSEQ_REG(FSEQ_TOP_CONTENT_VERSION), 2767 FSEQ_REG(FSEQ_ALIVE_TOKEN), 2768 FSEQ_REG(FSEQ_CNVI_ID), 2769 FSEQ_REG(FSEQ_CNVR_ID), 2770 FSEQ_REG(CNVI_AUX_MISC_CHIP), 2771 FSEQ_REG(CNVR_AUX_MISC_CHIP), 2772 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM), 2773 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR), 2774 }; 2775 2776 if (!iwl_trans_grab_nic_access(trans, &flags)) 2777 return; 2778 2779 IWL_ERR(fwrt, "Fseq Registers:\n"); 2780 2781 for (i = 0; i < ARRAY_SIZE(fseq_regs); i++) 2782 IWL_ERR(fwrt, "0x%08X | %s\n", 2783 iwl_read_prph_no_grab(trans, fseq_regs[i].addr), 2784 fseq_regs[i].str); 2785 2786 iwl_trans_release_nic_access(trans, &flags); 2787 } 2788 IWL_EXPORT_SYMBOL(iwl_fw_error_print_fseq_regs); 2789