1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #include <linux/devcoredump.h> 65 #include "iwl-drv.h" 66 #include "runtime.h" 67 #include "dbg.h" 68 #include "debugfs.h" 69 #include "iwl-io.h" 70 #include "iwl-prph.h" 71 #include "iwl-csr.h" 72 73 /** 74 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 75 * 76 * @fwrt_ptr: pointer to the buffer coming from fwrt 77 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 78 * transport's data. 79 * @trans_len: length of the valid data in trans_ptr 80 * @fwrt_len: length of the valid data in fwrt_ptr 81 */ 82 struct iwl_fw_dump_ptrs { 83 struct iwl_trans_dump_data *trans_ptr; 84 void *fwrt_ptr; 85 u32 fwrt_len; 86 }; 87 88 #define RADIO_REG_MAX_READ 0x2ad 89 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 90 struct iwl_fw_error_dump_data **dump_data) 91 { 92 u8 *pos = (void *)(*dump_data)->data; 93 unsigned long flags; 94 int i; 95 96 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 97 98 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 99 return; 100 101 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 102 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 103 104 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 105 u32 rd_cmd = RADIO_RSP_RD_CMD; 106 107 rd_cmd |= i << RADIO_RSP_ADDR_POS; 108 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 109 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 110 111 pos++; 112 } 113 114 *dump_data = iwl_fw_error_next_data(*dump_data); 115 116 iwl_trans_release_nic_access(fwrt->trans, &flags); 117 } 118 119 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 120 struct iwl_fw_error_dump_data **dump_data, 121 int size, u32 offset, int fifo_num) 122 { 123 struct iwl_fw_error_dump_fifo *fifo_hdr; 124 u32 *fifo_data; 125 u32 fifo_len; 126 int i; 127 128 fifo_hdr = (void *)(*dump_data)->data; 129 fifo_data = (void *)fifo_hdr->data; 130 fifo_len = size; 131 132 /* No need to try to read the data if the length is 0 */ 133 if (fifo_len == 0) 134 return; 135 136 /* Add a TLV for the RXF */ 137 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 138 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 139 140 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 141 fifo_hdr->available_bytes = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 RXF_RD_D_SPACE + offset)); 144 fifo_hdr->wr_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 RXF_RD_WR_PTR + offset)); 147 fifo_hdr->rd_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 RXF_RD_RD_PTR + offset)); 150 fifo_hdr->fence_ptr = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 RXF_RD_FENCE_PTR + offset)); 153 fifo_hdr->fence_mode = 154 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 155 RXF_SET_FENCE_MODE + offset)); 156 157 /* Lock fence */ 158 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 159 /* Set fence pointer to the same place like WR pointer */ 160 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 161 /* Set fence offset */ 162 iwl_trans_write_prph(fwrt->trans, 163 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 164 165 /* Read FIFO */ 166 fifo_len /= sizeof(u32); /* Size in DWORDS */ 167 for (i = 0; i < fifo_len; i++) 168 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 169 RXF_FIFO_RD_FENCE_INC + 170 offset); 171 *dump_data = iwl_fw_error_next_data(*dump_data); 172 } 173 174 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 175 struct iwl_fw_error_dump_data **dump_data, 176 int size, u32 offset, int fifo_num) 177 { 178 struct iwl_fw_error_dump_fifo *fifo_hdr; 179 u32 *fifo_data; 180 u32 fifo_len; 181 int i; 182 183 fifo_hdr = (void *)(*dump_data)->data; 184 fifo_data = (void *)fifo_hdr->data; 185 fifo_len = size; 186 187 /* No need to try to read the data if the length is 0 */ 188 if (fifo_len == 0) 189 return; 190 191 /* Add a TLV for the FIFO */ 192 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 193 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 194 195 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 196 fifo_hdr->available_bytes = 197 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 198 TXF_FIFO_ITEM_CNT + offset)); 199 fifo_hdr->wr_ptr = 200 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 201 TXF_WR_PTR + offset)); 202 fifo_hdr->rd_ptr = 203 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 204 TXF_RD_PTR + offset)); 205 fifo_hdr->fence_ptr = 206 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 207 TXF_FENCE_PTR + offset)); 208 fifo_hdr->fence_mode = 209 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 210 TXF_LOCK_FENCE + offset)); 211 212 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 213 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 214 TXF_WR_PTR + offset); 215 216 /* Dummy-read to advance the read pointer to the head */ 217 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 218 219 /* Read FIFO */ 220 fifo_len /= sizeof(u32); /* Size in DWORDS */ 221 for (i = 0; i < fifo_len; i++) 222 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 223 TXF_READ_MODIFY_DATA + 224 offset); 225 *dump_data = iwl_fw_error_next_data(*dump_data); 226 } 227 228 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 229 struct iwl_fw_error_dump_data **dump_data) 230 { 231 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 232 unsigned long flags; 233 234 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 235 236 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 237 return; 238 239 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 240 /* Pull RXF1 */ 241 iwl_fwrt_dump_rxf(fwrt, dump_data, 242 cfg->lmac[0].rxfifo1_size, 0, 0); 243 /* Pull RXF2 */ 244 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 245 RXF_DIFF_FROM_PREV + 246 fwrt->trans->cfg->umac_prph_offset, 1); 247 /* Pull LMAC2 RXF1 */ 248 if (fwrt->smem_cfg.num_lmacs > 1) 249 iwl_fwrt_dump_rxf(fwrt, dump_data, 250 cfg->lmac[1].rxfifo1_size, 251 LMAC2_PRPH_OFFSET, 2); 252 } 253 254 iwl_trans_release_nic_access(fwrt->trans, &flags); 255 } 256 257 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 258 struct iwl_fw_error_dump_data **dump_data) 259 { 260 struct iwl_fw_error_dump_fifo *fifo_hdr; 261 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 262 u32 *fifo_data; 263 u32 fifo_len; 264 unsigned long flags; 265 int i, j; 266 267 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 268 269 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 270 return; 271 272 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 273 /* Pull TXF data from LMAC1 */ 274 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 275 /* Mark the number of TXF we're pulling now */ 276 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 277 iwl_fwrt_dump_txf(fwrt, dump_data, 278 cfg->lmac[0].txfifo_size[i], 0, i); 279 } 280 281 /* Pull TXF data from LMAC2 */ 282 if (fwrt->smem_cfg.num_lmacs > 1) { 283 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 284 i++) { 285 /* Mark the number of TXF we're pulling now */ 286 iwl_trans_write_prph(fwrt->trans, 287 TXF_LARC_NUM + 288 LMAC2_PRPH_OFFSET, i); 289 iwl_fwrt_dump_txf(fwrt, dump_data, 290 cfg->lmac[1].txfifo_size[i], 291 LMAC2_PRPH_OFFSET, 292 i + cfg->num_txfifo_entries); 293 } 294 } 295 } 296 297 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 298 fw_has_capa(&fwrt->fw->ucode_capa, 299 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 300 /* Pull UMAC internal TXF data from all TXFs */ 301 for (i = 0; 302 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 303 i++) { 304 fifo_hdr = (void *)(*dump_data)->data; 305 fifo_data = (void *)fifo_hdr->data; 306 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 307 308 /* No need to try to read the data if the length is 0 */ 309 if (fifo_len == 0) 310 continue; 311 312 /* Add a TLV for the internal FIFOs */ 313 (*dump_data)->type = 314 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 315 (*dump_data)->len = 316 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 317 318 fifo_hdr->fifo_num = cpu_to_le32(i); 319 320 /* Mark the number of TXF we're pulling now */ 321 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 322 fwrt->smem_cfg.num_txfifo_entries); 323 324 fifo_hdr->available_bytes = 325 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 326 TXF_CPU2_FIFO_ITEM_CNT)); 327 fifo_hdr->wr_ptr = 328 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 329 TXF_CPU2_WR_PTR)); 330 fifo_hdr->rd_ptr = 331 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 332 TXF_CPU2_RD_PTR)); 333 fifo_hdr->fence_ptr = 334 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 335 TXF_CPU2_FENCE_PTR)); 336 fifo_hdr->fence_mode = 337 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 338 TXF_CPU2_LOCK_FENCE)); 339 340 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 341 iwl_trans_write_prph(fwrt->trans, 342 TXF_CPU2_READ_MODIFY_ADDR, 343 TXF_CPU2_WR_PTR); 344 345 /* Dummy-read to advance the read pointer to head */ 346 iwl_trans_read_prph(fwrt->trans, 347 TXF_CPU2_READ_MODIFY_DATA); 348 349 /* Read FIFO */ 350 fifo_len /= sizeof(u32); /* Size in DWORDS */ 351 for (j = 0; j < fifo_len; j++) 352 fifo_data[j] = 353 iwl_trans_read_prph(fwrt->trans, 354 TXF_CPU2_READ_MODIFY_DATA); 355 *dump_data = iwl_fw_error_next_data(*dump_data); 356 } 357 } 358 359 iwl_trans_release_nic_access(fwrt->trans, &flags); 360 } 361 362 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ 363 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ 364 365 struct iwl_prph_range { 366 u32 start, end; 367 }; 368 369 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 370 { .start = 0x00a00000, .end = 0x00a00000 }, 371 { .start = 0x00a0000c, .end = 0x00a00024 }, 372 { .start = 0x00a0002c, .end = 0x00a0003c }, 373 { .start = 0x00a00410, .end = 0x00a00418 }, 374 { .start = 0x00a00420, .end = 0x00a00420 }, 375 { .start = 0x00a00428, .end = 0x00a00428 }, 376 { .start = 0x00a00430, .end = 0x00a0043c }, 377 { .start = 0x00a00444, .end = 0x00a00444 }, 378 { .start = 0x00a004c0, .end = 0x00a004cc }, 379 { .start = 0x00a004d8, .end = 0x00a004d8 }, 380 { .start = 0x00a004e0, .end = 0x00a004f0 }, 381 { .start = 0x00a00840, .end = 0x00a00840 }, 382 { .start = 0x00a00850, .end = 0x00a00858 }, 383 { .start = 0x00a01004, .end = 0x00a01008 }, 384 { .start = 0x00a01010, .end = 0x00a01010 }, 385 { .start = 0x00a01018, .end = 0x00a01018 }, 386 { .start = 0x00a01024, .end = 0x00a01024 }, 387 { .start = 0x00a0102c, .end = 0x00a01034 }, 388 { .start = 0x00a0103c, .end = 0x00a01040 }, 389 { .start = 0x00a01048, .end = 0x00a01094 }, 390 { .start = 0x00a01c00, .end = 0x00a01c20 }, 391 { .start = 0x00a01c58, .end = 0x00a01c58 }, 392 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 393 { .start = 0x00a01c28, .end = 0x00a01c54 }, 394 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 395 { .start = 0x00a01c60, .end = 0x00a01cdc }, 396 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 397 { .start = 0x00a01d18, .end = 0x00a01d20 }, 398 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 399 { .start = 0x00a01d40, .end = 0x00a01d5c }, 400 { .start = 0x00a01d80, .end = 0x00a01d80 }, 401 { .start = 0x00a01d98, .end = 0x00a01d9c }, 402 { .start = 0x00a01da8, .end = 0x00a01da8 }, 403 { .start = 0x00a01db8, .end = 0x00a01df4 }, 404 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 405 { .start = 0x00a01e00, .end = 0x00a01e2c }, 406 { .start = 0x00a01e40, .end = 0x00a01e60 }, 407 { .start = 0x00a01e68, .end = 0x00a01e6c }, 408 { .start = 0x00a01e74, .end = 0x00a01e74 }, 409 { .start = 0x00a01e84, .end = 0x00a01e90 }, 410 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 411 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 412 { .start = 0x00a01f00, .end = 0x00a01f1c }, 413 { .start = 0x00a01f44, .end = 0x00a01ffc }, 414 { .start = 0x00a02000, .end = 0x00a02048 }, 415 { .start = 0x00a02068, .end = 0x00a020f0 }, 416 { .start = 0x00a02100, .end = 0x00a02118 }, 417 { .start = 0x00a02140, .end = 0x00a0214c }, 418 { .start = 0x00a02168, .end = 0x00a0218c }, 419 { .start = 0x00a021c0, .end = 0x00a021c0 }, 420 { .start = 0x00a02400, .end = 0x00a02410 }, 421 { .start = 0x00a02418, .end = 0x00a02420 }, 422 { .start = 0x00a02428, .end = 0x00a0242c }, 423 { .start = 0x00a02434, .end = 0x00a02434 }, 424 { .start = 0x00a02440, .end = 0x00a02460 }, 425 { .start = 0x00a02468, .end = 0x00a024b0 }, 426 { .start = 0x00a024c8, .end = 0x00a024cc }, 427 { .start = 0x00a02500, .end = 0x00a02504 }, 428 { .start = 0x00a0250c, .end = 0x00a02510 }, 429 { .start = 0x00a02540, .end = 0x00a02554 }, 430 { .start = 0x00a02580, .end = 0x00a025f4 }, 431 { .start = 0x00a02600, .end = 0x00a0260c }, 432 { .start = 0x00a02648, .end = 0x00a02650 }, 433 { .start = 0x00a02680, .end = 0x00a02680 }, 434 { .start = 0x00a026c0, .end = 0x00a026d0 }, 435 { .start = 0x00a02700, .end = 0x00a0270c }, 436 { .start = 0x00a02804, .end = 0x00a02804 }, 437 { .start = 0x00a02818, .end = 0x00a0281c }, 438 { .start = 0x00a02c00, .end = 0x00a02db4 }, 439 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 440 { .start = 0x00a03000, .end = 0x00a03014 }, 441 { .start = 0x00a0301c, .end = 0x00a0302c }, 442 { .start = 0x00a03034, .end = 0x00a03038 }, 443 { .start = 0x00a03040, .end = 0x00a03048 }, 444 { .start = 0x00a03060, .end = 0x00a03068 }, 445 { .start = 0x00a03070, .end = 0x00a03074 }, 446 { .start = 0x00a0307c, .end = 0x00a0307c }, 447 { .start = 0x00a03080, .end = 0x00a03084 }, 448 { .start = 0x00a0308c, .end = 0x00a03090 }, 449 { .start = 0x00a03098, .end = 0x00a03098 }, 450 { .start = 0x00a030a0, .end = 0x00a030a0 }, 451 { .start = 0x00a030a8, .end = 0x00a030b4 }, 452 { .start = 0x00a030bc, .end = 0x00a030bc }, 453 { .start = 0x00a030c0, .end = 0x00a0312c }, 454 { .start = 0x00a03c00, .end = 0x00a03c5c }, 455 { .start = 0x00a04400, .end = 0x00a04454 }, 456 { .start = 0x00a04460, .end = 0x00a04474 }, 457 { .start = 0x00a044c0, .end = 0x00a044ec }, 458 { .start = 0x00a04500, .end = 0x00a04504 }, 459 { .start = 0x00a04510, .end = 0x00a04538 }, 460 { .start = 0x00a04540, .end = 0x00a04548 }, 461 { .start = 0x00a04560, .end = 0x00a0457c }, 462 { .start = 0x00a04590, .end = 0x00a04598 }, 463 { .start = 0x00a045c0, .end = 0x00a045f4 }, 464 }; 465 466 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 467 { .start = 0x00a05c00, .end = 0x00a05c18 }, 468 { .start = 0x00a05400, .end = 0x00a056e8 }, 469 { .start = 0x00a08000, .end = 0x00a098bc }, 470 { .start = 0x00a02400, .end = 0x00a02758 }, 471 }; 472 473 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 474 { .start = 0x00a00000, .end = 0x00a00000 }, 475 { .start = 0x00a0000c, .end = 0x00a00024 }, 476 { .start = 0x00a0002c, .end = 0x00a00034 }, 477 { .start = 0x00a0003c, .end = 0x00a0003c }, 478 { .start = 0x00a00410, .end = 0x00a00418 }, 479 { .start = 0x00a00420, .end = 0x00a00420 }, 480 { .start = 0x00a00428, .end = 0x00a00428 }, 481 { .start = 0x00a00430, .end = 0x00a0043c }, 482 { .start = 0x00a00444, .end = 0x00a00444 }, 483 { .start = 0x00a00840, .end = 0x00a00840 }, 484 { .start = 0x00a00850, .end = 0x00a00858 }, 485 { .start = 0x00a01004, .end = 0x00a01008 }, 486 { .start = 0x00a01010, .end = 0x00a01010 }, 487 { .start = 0x00a01018, .end = 0x00a01018 }, 488 { .start = 0x00a01024, .end = 0x00a01024 }, 489 { .start = 0x00a0102c, .end = 0x00a01034 }, 490 { .start = 0x00a0103c, .end = 0x00a01040 }, 491 { .start = 0x00a01048, .end = 0x00a01050 }, 492 { .start = 0x00a01058, .end = 0x00a01058 }, 493 { .start = 0x00a01060, .end = 0x00a01070 }, 494 { .start = 0x00a0108c, .end = 0x00a0108c }, 495 { .start = 0x00a01c20, .end = 0x00a01c28 }, 496 { .start = 0x00a01d10, .end = 0x00a01d10 }, 497 { .start = 0x00a01e28, .end = 0x00a01e2c }, 498 { .start = 0x00a01e60, .end = 0x00a01e60 }, 499 { .start = 0x00a01e80, .end = 0x00a01e80 }, 500 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 501 { .start = 0x00a02000, .end = 0x00a0201c }, 502 { .start = 0x00a02024, .end = 0x00a02024 }, 503 { .start = 0x00a02040, .end = 0x00a02048 }, 504 { .start = 0x00a020c0, .end = 0x00a020e0 }, 505 { .start = 0x00a02400, .end = 0x00a02404 }, 506 { .start = 0x00a0240c, .end = 0x00a02414 }, 507 { .start = 0x00a0241c, .end = 0x00a0243c }, 508 { .start = 0x00a02448, .end = 0x00a024bc }, 509 { .start = 0x00a024c4, .end = 0x00a024cc }, 510 { .start = 0x00a02508, .end = 0x00a02508 }, 511 { .start = 0x00a02510, .end = 0x00a02514 }, 512 { .start = 0x00a0251c, .end = 0x00a0251c }, 513 { .start = 0x00a0252c, .end = 0x00a0255c }, 514 { .start = 0x00a02564, .end = 0x00a025a0 }, 515 { .start = 0x00a025a8, .end = 0x00a025b4 }, 516 { .start = 0x00a025c0, .end = 0x00a025c0 }, 517 { .start = 0x00a025e8, .end = 0x00a025f4 }, 518 { .start = 0x00a02c08, .end = 0x00a02c18 }, 519 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 520 { .start = 0x00a02c68, .end = 0x00a02c78 }, 521 { .start = 0x00a03000, .end = 0x00a03000 }, 522 { .start = 0x00a03010, .end = 0x00a03014 }, 523 { .start = 0x00a0301c, .end = 0x00a0302c }, 524 { .start = 0x00a03034, .end = 0x00a03038 }, 525 { .start = 0x00a03040, .end = 0x00a03044 }, 526 { .start = 0x00a03060, .end = 0x00a03068 }, 527 { .start = 0x00a03070, .end = 0x00a03070 }, 528 { .start = 0x00a0307c, .end = 0x00a03084 }, 529 { .start = 0x00a0308c, .end = 0x00a03090 }, 530 { .start = 0x00a03098, .end = 0x00a03098 }, 531 { .start = 0x00a030a0, .end = 0x00a030a0 }, 532 { .start = 0x00a030a8, .end = 0x00a030b4 }, 533 { .start = 0x00a030bc, .end = 0x00a030c0 }, 534 { .start = 0x00a030c8, .end = 0x00a030f4 }, 535 { .start = 0x00a03100, .end = 0x00a0312c }, 536 { .start = 0x00a03c00, .end = 0x00a03c5c }, 537 { .start = 0x00a04400, .end = 0x00a04454 }, 538 { .start = 0x00a04460, .end = 0x00a04474 }, 539 { .start = 0x00a044c0, .end = 0x00a044ec }, 540 { .start = 0x00a04500, .end = 0x00a04504 }, 541 { .start = 0x00a04510, .end = 0x00a04538 }, 542 { .start = 0x00a04540, .end = 0x00a04548 }, 543 { .start = 0x00a04560, .end = 0x00a04560 }, 544 { .start = 0x00a04570, .end = 0x00a0457c }, 545 { .start = 0x00a04590, .end = 0x00a04590 }, 546 { .start = 0x00a04598, .end = 0x00a04598 }, 547 { .start = 0x00a045c0, .end = 0x00a045f4 }, 548 { .start = 0x00a05c18, .end = 0x00a05c1c }, 549 { .start = 0x00a0c000, .end = 0x00a0c018 }, 550 { .start = 0x00a0c020, .end = 0x00a0c028 }, 551 { .start = 0x00a0c038, .end = 0x00a0c094 }, 552 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 553 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 554 { .start = 0x00a0c150, .end = 0x00a0c174 }, 555 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 556 { .start = 0x00a0c190, .end = 0x00a0c198 }, 557 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 558 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 559 }; 560 561 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 562 { .start = 0x00d03c00, .end = 0x00d03c64 }, 563 { .start = 0x00d05c18, .end = 0x00d05c1c }, 564 { .start = 0x00d0c000, .end = 0x00d0c174 }, 565 }; 566 567 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 568 u32 len_bytes, __le32 *data) 569 { 570 u32 i; 571 572 for (i = 0; i < len_bytes; i += 4) 573 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 574 } 575 576 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 577 const struct iwl_prph_range *iwl_prph_dump_addr, 578 u32 range_len, void *ptr) 579 { 580 struct iwl_fw_error_dump_prph *prph; 581 struct iwl_trans *trans = fwrt->trans; 582 struct iwl_fw_error_dump_data **data = 583 (struct iwl_fw_error_dump_data **)ptr; 584 unsigned long flags; 585 u32 i; 586 587 if (!data) 588 return; 589 590 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 591 592 if (!iwl_trans_grab_nic_access(trans, &flags)) 593 return; 594 595 for (i = 0; i < range_len; i++) { 596 /* The range includes both boundaries */ 597 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 598 iwl_prph_dump_addr[i].start + 4; 599 600 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 601 (*data)->len = cpu_to_le32(sizeof(*prph) + 602 num_bytes_in_chunk); 603 prph = (void *)(*data)->data; 604 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 605 606 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 607 /* our range is inclusive, hence + 4 */ 608 iwl_prph_dump_addr[i].end - 609 iwl_prph_dump_addr[i].start + 4, 610 (void *)prph->data); 611 612 *data = iwl_fw_error_next_data(*data); 613 } 614 615 iwl_trans_release_nic_access(trans, &flags); 616 } 617 618 /* 619 * alloc_sgtable - allocates scallerlist table in the given size, 620 * fills it with pages and returns it 621 * @size: the size (in bytes) of the table 622 */ 623 static struct scatterlist *alloc_sgtable(int size) 624 { 625 int alloc_size, nents, i; 626 struct page *new_page; 627 struct scatterlist *iter; 628 struct scatterlist *table; 629 630 nents = DIV_ROUND_UP(size, PAGE_SIZE); 631 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 632 if (!table) 633 return NULL; 634 sg_init_table(table, nents); 635 iter = table; 636 for_each_sg(table, iter, sg_nents(table), i) { 637 new_page = alloc_page(GFP_KERNEL); 638 if (!new_page) { 639 /* release all previous allocated pages in the table */ 640 iter = table; 641 for_each_sg(table, iter, sg_nents(table), i) { 642 new_page = sg_page(iter); 643 if (new_page) 644 __free_page(new_page); 645 } 646 return NULL; 647 } 648 alloc_size = min_t(int, size, PAGE_SIZE); 649 size -= PAGE_SIZE; 650 sg_set_page(iter, new_page, alloc_size, 0); 651 } 652 return table; 653 } 654 655 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 656 const struct iwl_prph_range *iwl_prph_dump_addr, 657 u32 range_len, void *ptr) 658 { 659 u32 *prph_len = (u32 *)ptr; 660 int i, num_bytes_in_chunk; 661 662 if (!prph_len) 663 return; 664 665 for (i = 0; i < range_len; i++) { 666 /* The range includes both boundaries */ 667 num_bytes_in_chunk = 668 iwl_prph_dump_addr[i].end - 669 iwl_prph_dump_addr[i].start + 4; 670 671 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 672 sizeof(struct iwl_fw_error_dump_prph) + 673 num_bytes_in_chunk; 674 } 675 } 676 677 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 678 void (*handler)(struct iwl_fw_runtime *, 679 const struct iwl_prph_range *, 680 u32, void *)) 681 { 682 u32 range_len; 683 684 if (fwrt->trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 685 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 686 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 687 } else if (fwrt->trans->cfg->device_family >= IWL_DEVICE_FAMILY_22000) { 688 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 689 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 690 } else { 691 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 692 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 693 694 if (fwrt->trans->cfg->mq_rx_supported) { 695 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 696 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 697 } 698 } 699 } 700 701 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 702 struct iwl_fw_error_dump_data **dump_data, 703 u32 len, u32 ofs, u32 type) 704 { 705 struct iwl_fw_error_dump_mem *dump_mem; 706 707 if (!len) 708 return; 709 710 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 711 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 712 dump_mem = (void *)(*dump_data)->data; 713 dump_mem->type = cpu_to_le32(type); 714 dump_mem->offset = cpu_to_le32(ofs); 715 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 716 *dump_data = iwl_fw_error_next_data(*dump_data); 717 718 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 719 } 720 721 #define ADD_LEN(len, item_len, const_len) \ 722 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 723 while (0) 724 725 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 726 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 727 { 728 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 729 sizeof(struct iwl_fw_error_dump_fifo); 730 u32 fifo_len = 0; 731 int i; 732 733 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 734 return 0; 735 736 /* Count RXF2 size */ 737 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 738 739 /* Count RXF1 sizes */ 740 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 741 mem_cfg->num_lmacs = MAX_NUM_LMAC; 742 743 for (i = 0; i < mem_cfg->num_lmacs; i++) 744 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 745 746 return fifo_len; 747 } 748 749 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 750 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 751 { 752 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 753 sizeof(struct iwl_fw_error_dump_fifo); 754 u32 fifo_len = 0; 755 int i; 756 757 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 758 goto dump_internal_txf; 759 760 /* Count TXF sizes */ 761 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 762 mem_cfg->num_lmacs = MAX_NUM_LMAC; 763 764 for (i = 0; i < mem_cfg->num_lmacs; i++) { 765 int j; 766 767 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 768 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 769 hdr_len); 770 } 771 772 dump_internal_txf: 773 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 774 fw_has_capa(&fwrt->fw->ucode_capa, 775 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 776 goto out; 777 778 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 779 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 780 781 out: 782 return fifo_len; 783 } 784 785 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 786 struct iwl_fw_error_dump_data **data) 787 { 788 int i; 789 790 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 791 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 792 struct iwl_fw_error_dump_paging *paging; 793 struct page *pages = 794 fwrt->fw_paging_db[i].fw_paging_block; 795 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 796 797 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 798 (*data)->len = cpu_to_le32(sizeof(*paging) + 799 PAGING_BLOCK_SIZE); 800 paging = (void *)(*data)->data; 801 paging->index = cpu_to_le32(i); 802 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 803 PAGING_BLOCK_SIZE, 804 DMA_BIDIRECTIONAL); 805 memcpy(paging->data, page_address(pages), 806 PAGING_BLOCK_SIZE); 807 dma_sync_single_for_device(fwrt->trans->dev, addr, 808 PAGING_BLOCK_SIZE, 809 DMA_BIDIRECTIONAL); 810 (*data) = iwl_fw_error_next_data(*data); 811 } 812 } 813 814 static struct iwl_fw_error_dump_file * 815 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 816 struct iwl_fw_dump_ptrs *fw_error_dump) 817 { 818 struct iwl_fw_error_dump_file *dump_file; 819 struct iwl_fw_error_dump_data *dump_data; 820 struct iwl_fw_error_dump_info *dump_info; 821 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 822 struct iwl_fw_error_dump_trigger_desc *dump_trig; 823 u32 sram_len, sram_ofs; 824 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 825 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 826 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 827 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 828 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 829 0 : fwrt->trans->cfg->dccm2_len; 830 int i; 831 832 /* SRAM - include stack CCM if driver knows the values for it */ 833 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 834 const struct fw_img *img; 835 836 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 837 return NULL; 838 img = &fwrt->fw->img[fwrt->cur_fw_img]; 839 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 840 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 841 } else { 842 sram_ofs = fwrt->trans->cfg->dccm_offset; 843 sram_len = fwrt->trans->cfg->dccm_len; 844 } 845 846 /* reading RXF/TXF sizes */ 847 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 848 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 849 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 850 851 /* Make room for PRPH registers */ 852 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 853 iwl_fw_prph_handler(fwrt, &prph_len, 854 iwl_fw_get_prph_len); 855 856 if (fwrt->trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 && 857 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 858 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 859 } 860 861 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 862 863 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 864 file_len += sizeof(*dump_data) + sizeof(*dump_info); 865 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 866 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 867 868 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 869 size_t hdr_len = sizeof(*dump_data) + 870 sizeof(struct iwl_fw_error_dump_mem); 871 872 /* Dump SRAM only if no mem_tlvs */ 873 if (!fwrt->fw->dbg.n_mem_tlv) 874 ADD_LEN(file_len, sram_len, hdr_len); 875 876 /* Make room for all mem types that exist */ 877 ADD_LEN(file_len, smem_len, hdr_len); 878 ADD_LEN(file_len, sram2_len, hdr_len); 879 880 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 881 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 882 } 883 884 /* Make room for fw's virtual image pages, if it exists */ 885 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 886 file_len += fwrt->num_of_paging_blk * 887 (sizeof(*dump_data) + 888 sizeof(struct iwl_fw_error_dump_paging) + 889 PAGING_BLOCK_SIZE); 890 891 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 892 file_len += sizeof(*dump_data) + 893 fwrt->trans->cfg->d3_debug_data_length * 2; 894 } 895 896 /* If we only want a monitor dump, reset the file length */ 897 if (fwrt->dump.monitor_only) { 898 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 899 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 900 } 901 902 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 903 fwrt->dump.desc) 904 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 905 fwrt->dump.desc->len; 906 907 dump_file = vzalloc(file_len); 908 if (!dump_file) 909 return NULL; 910 911 fw_error_dump->fwrt_ptr = dump_file; 912 913 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 914 dump_data = (void *)dump_file->data; 915 916 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 917 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 918 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 919 dump_info = (void *)dump_data->data; 920 dump_info->device_family = 921 fwrt->trans->cfg->device_family == 922 IWL_DEVICE_FAMILY_7000 ? 923 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_7) : 924 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_8); 925 dump_info->hw_step = 926 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 927 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 928 sizeof(dump_info->fw_human_readable)); 929 strncpy(dump_info->dev_human_readable, fwrt->trans->cfg->name, 930 sizeof(dump_info->dev_human_readable) - 1); 931 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 932 sizeof(dump_info->bus_human_readable) - 1); 933 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 934 dump_info->lmac_err_id[0] = 935 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 936 if (fwrt->smem_cfg.num_lmacs > 1) 937 dump_info->lmac_err_id[1] = 938 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 939 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 940 941 dump_data = iwl_fw_error_next_data(dump_data); 942 } 943 944 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 945 /* Dump shared memory configuration */ 946 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 947 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 948 dump_smem_cfg = (void *)dump_data->data; 949 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 950 dump_smem_cfg->num_txfifo_entries = 951 cpu_to_le32(mem_cfg->num_txfifo_entries); 952 for (i = 0; i < MAX_NUM_LMAC; i++) { 953 int j; 954 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 955 956 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 957 dump_smem_cfg->lmac[i].txfifo_size[j] = 958 cpu_to_le32(txf_size[j]); 959 dump_smem_cfg->lmac[i].rxfifo1_size = 960 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 961 } 962 dump_smem_cfg->rxfifo2_size = 963 cpu_to_le32(mem_cfg->rxfifo2_size); 964 dump_smem_cfg->internal_txfifo_addr = 965 cpu_to_le32(mem_cfg->internal_txfifo_addr); 966 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 967 dump_smem_cfg->internal_txfifo_size[i] = 968 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 969 } 970 971 dump_data = iwl_fw_error_next_data(dump_data); 972 } 973 974 /* We only dump the FIFOs if the FW is in error state */ 975 if (fifo_len) { 976 iwl_fw_dump_rxf(fwrt, &dump_data); 977 iwl_fw_dump_txf(fwrt, &dump_data); 978 } 979 980 if (radio_len) 981 iwl_read_radio_regs(fwrt, &dump_data); 982 983 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 984 fwrt->dump.desc) { 985 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 986 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 987 fwrt->dump.desc->len); 988 dump_trig = (void *)dump_data->data; 989 memcpy(dump_trig, &fwrt->dump.desc->trig_desc, 990 sizeof(*dump_trig) + fwrt->dump.desc->len); 991 992 dump_data = iwl_fw_error_next_data(dump_data); 993 } 994 995 /* In case we only want monitor dump, skip to dump trasport data */ 996 if (fwrt->dump.monitor_only) 997 goto out; 998 999 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 1000 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 1001 fwrt->fw->dbg.mem_tlv; 1002 1003 if (!fwrt->fw->dbg.n_mem_tlv) 1004 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 1005 IWL_FW_ERROR_DUMP_MEM_SRAM); 1006 1007 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 1008 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 1009 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 1010 1011 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 1012 le32_to_cpu(fw_dbg_mem[i].data_type)); 1013 } 1014 1015 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 1016 fwrt->trans->cfg->smem_offset, 1017 IWL_FW_ERROR_DUMP_MEM_SMEM); 1018 1019 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 1020 fwrt->trans->cfg->dccm2_offset, 1021 IWL_FW_ERROR_DUMP_MEM_SRAM); 1022 } 1023 1024 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 1025 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 1026 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 1027 1028 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 1029 dump_data->len = cpu_to_le32(data_size * 2); 1030 1031 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 1032 1033 kfree(fwrt->dump.d3_debug_data); 1034 fwrt->dump.d3_debug_data = NULL; 1035 1036 iwl_trans_read_mem_bytes(fwrt->trans, addr, 1037 dump_data->data + data_size, 1038 data_size); 1039 1040 dump_data = iwl_fw_error_next_data(dump_data); 1041 } 1042 1043 /* Dump fw's virtual image */ 1044 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1045 iwl_dump_paging(fwrt, &dump_data); 1046 1047 if (prph_len) 1048 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1049 1050 out: 1051 dump_file->file_len = cpu_to_le32(file_len); 1052 return dump_file; 1053 } 1054 1055 static int iwl_dump_ini_prph_iter(struct iwl_fw_runtime *fwrt, 1056 struct iwl_fw_ini_region_cfg *reg, 1057 void *range_ptr, int idx) 1058 { 1059 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1060 __le32 *val = range->data; 1061 u32 prph_val; 1062 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1063 int i; 1064 1065 range->start_addr = cpu_to_le64(addr); 1066 range->range_data_size = reg->internal.range_data_size; 1067 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) { 1068 prph_val = iwl_read_prph(fwrt->trans, addr + i); 1069 if (prph_val == 0x5a5a5a5a) 1070 return -EBUSY; 1071 *val++ = cpu_to_le32(prph_val); 1072 } 1073 1074 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1075 } 1076 1077 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1078 struct iwl_fw_ini_region_cfg *reg, 1079 void *range_ptr, int idx) 1080 { 1081 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1082 __le32 *val = range->data; 1083 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1084 int i; 1085 1086 range->start_addr = cpu_to_le64(addr); 1087 range->range_data_size = reg->internal.range_data_size; 1088 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) 1089 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1090 1091 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1092 } 1093 1094 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1095 struct iwl_fw_ini_region_cfg *reg, 1096 void *range_ptr, int idx) 1097 { 1098 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1099 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1100 1101 range->start_addr = cpu_to_le64(addr); 1102 range->range_data_size = reg->internal.range_data_size; 1103 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1104 le32_to_cpu(reg->internal.range_data_size)); 1105 1106 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1107 } 1108 1109 static int 1110 iwl_dump_ini_paging_gen2_iter(struct iwl_fw_runtime *fwrt, 1111 struct iwl_fw_ini_region_cfg *reg, 1112 void *range_ptr, int idx) 1113 { 1114 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1115 u32 page_size = fwrt->trans->init_dram.paging[idx].size; 1116 1117 range->start_addr = cpu_to_le64(idx); 1118 range->range_data_size = cpu_to_le32(page_size); 1119 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1120 page_size); 1121 1122 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1123 } 1124 1125 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1126 struct iwl_fw_ini_region_cfg *reg, 1127 void *range_ptr, int idx) 1128 { 1129 /* increase idx by 1 since the pages are from 1 to 1130 * fwrt->num_of_paging_blk + 1 1131 */ 1132 struct page *page = fwrt->fw_paging_db[++idx].fw_paging_block; 1133 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1134 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1135 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1136 1137 range->start_addr = cpu_to_le64(idx); 1138 range->range_data_size = cpu_to_le32(page_size); 1139 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1140 DMA_BIDIRECTIONAL); 1141 memcpy(range->data, page_address(page), page_size); 1142 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1143 DMA_BIDIRECTIONAL); 1144 1145 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1146 } 1147 1148 static int 1149 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1150 struct iwl_fw_ini_region_cfg *reg, void *range_ptr, 1151 int idx) 1152 { 1153 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1154 u32 start_addr = iwl_read_umac_prph(fwrt->trans, 1155 MON_BUFF_BASE_ADDR_VER2); 1156 1157 if (start_addr == 0x5a5a5a5a) 1158 return -EBUSY; 1159 1160 range->start_addr = cpu_to_le64(start_addr); 1161 range->range_data_size = cpu_to_le32(fwrt->trans->fw_mon[idx].size); 1162 1163 memcpy(range->data, fwrt->trans->fw_mon[idx].block, 1164 fwrt->trans->fw_mon[idx].size); 1165 1166 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1167 } 1168 1169 struct iwl_ini_txf_iter_data { 1170 int fifo; 1171 int lmac; 1172 u32 fifo_size; 1173 bool internal_txf; 1174 bool init; 1175 }; 1176 1177 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1178 struct iwl_fw_ini_region_cfg *reg) 1179 { 1180 struct iwl_ini_txf_iter_data *iter = fwrt->dump.fifo_iter; 1181 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1182 int txf_num = cfg->num_txfifo_entries; 1183 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1184 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid1); 1185 1186 if (!iter) 1187 return false; 1188 1189 if (iter->init) { 1190 if (le32_to_cpu(reg->offset) && 1191 WARN_ONCE(cfg->num_lmacs == 1, 1192 "Invalid lmac offset: 0x%x\n", 1193 le32_to_cpu(reg->offset))) 1194 return false; 1195 1196 iter->init = false; 1197 iter->internal_txf = false; 1198 iter->fifo_size = 0; 1199 iter->fifo = -1; 1200 if (le32_to_cpu(reg->offset)) 1201 iter->lmac = 1; 1202 else 1203 iter->lmac = 0; 1204 } 1205 1206 if (!iter->internal_txf) 1207 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1208 iter->fifo_size = 1209 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1210 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1211 return true; 1212 } 1213 1214 iter->internal_txf = true; 1215 1216 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1217 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1218 return false; 1219 1220 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1221 iter->fifo_size = 1222 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1223 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1224 return true; 1225 } 1226 1227 return false; 1228 } 1229 1230 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1231 struct iwl_fw_ini_region_cfg *reg, 1232 void *range_ptr, int idx) 1233 { 1234 struct iwl_fw_ini_fifo_error_dump_range *range = range_ptr; 1235 struct iwl_ini_txf_iter_data *iter; 1236 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1237 u32 offs = le32_to_cpu(reg->offset), addr; 1238 u32 registers_size = 1239 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump); 1240 __le32 *data; 1241 unsigned long flags; 1242 int i; 1243 1244 if (!iwl_ini_txf_iter(fwrt, reg)) 1245 return -EIO; 1246 1247 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1248 return -EBUSY; 1249 1250 iter = fwrt->dump.fifo_iter; 1251 1252 range->fifo_num = cpu_to_le32(iter->fifo); 1253 range->num_of_registers = reg->fifos.num_of_registers; 1254 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1255 1256 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1257 1258 /* 1259 * read txf registers. for each register, write to the dump the 1260 * register address and its value 1261 */ 1262 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { 1263 addr = le32_to_cpu(reg->start_addr[i]) + offs; 1264 1265 reg_dump->addr = cpu_to_le32(addr); 1266 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1267 addr)); 1268 1269 reg_dump++; 1270 } 1271 1272 if (reg->fifos.header_only) { 1273 range->range_data_size = cpu_to_le32(registers_size); 1274 goto out; 1275 } 1276 1277 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1278 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1279 TXF_WR_PTR + offs); 1280 1281 /* Dummy-read to advance the read pointer to the head */ 1282 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1283 1284 /* Read FIFO */ 1285 addr = TXF_READ_MODIFY_DATA + offs; 1286 data = (void *)reg_dump; 1287 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1288 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1289 1290 out: 1291 iwl_trans_release_nic_access(fwrt->trans, &flags); 1292 1293 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1294 } 1295 1296 struct iwl_ini_rxf_data { 1297 u32 fifo_num; 1298 u32 size; 1299 u32 offset; 1300 }; 1301 1302 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1303 struct iwl_fw_ini_region_cfg *reg, 1304 struct iwl_ini_rxf_data *data) 1305 { 1306 u32 fid1 = le32_to_cpu(reg->fifos.fid1); 1307 u32 fid2 = le32_to_cpu(reg->fifos.fid2); 1308 u32 fifo_idx; 1309 1310 if (!data) 1311 return; 1312 1313 memset(data, 0, sizeof(*data)); 1314 1315 if (WARN_ON_ONCE((fid1 && fid2) || (!fid1 && !fid2))) 1316 return; 1317 1318 fifo_idx = ffs(fid1) - 1; 1319 if (fid1 && !WARN_ON_ONCE((~BIT(fifo_idx) & fid1) || 1320 fifo_idx >= MAX_NUM_LMAC)) { 1321 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1322 data->fifo_num = fifo_idx; 1323 return; 1324 } 1325 1326 fifo_idx = ffs(fid2) - 1; 1327 if (fid2 && !WARN_ON_ONCE(fifo_idx != 0)) { 1328 data->size = fwrt->smem_cfg.rxfifo2_size; 1329 data->offset = RXF_DIFF_FROM_PREV; 1330 /* use bit 31 to distinguish between umac and lmac rxf while 1331 * parsing the dump 1332 */ 1333 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1334 return; 1335 } 1336 } 1337 1338 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1339 struct iwl_fw_ini_region_cfg *reg, 1340 void *range_ptr, int idx) 1341 { 1342 struct iwl_fw_ini_fifo_error_dump_range *range = range_ptr; 1343 struct iwl_ini_rxf_data rxf_data; 1344 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1345 u32 offs = le32_to_cpu(reg->offset), addr; 1346 u32 registers_size = 1347 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump); 1348 __le32 *data; 1349 unsigned long flags; 1350 int i; 1351 1352 iwl_ini_get_rxf_data(fwrt, reg, &rxf_data); 1353 if (!rxf_data.size) 1354 return -EIO; 1355 1356 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1357 return -EBUSY; 1358 1359 range->fifo_num = cpu_to_le32(rxf_data.fifo_num); 1360 range->num_of_registers = reg->fifos.num_of_registers; 1361 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1362 1363 /* 1364 * read rxf registers. for each register, write to the dump the 1365 * register address and its value 1366 */ 1367 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { 1368 addr = le32_to_cpu(reg->start_addr[i]) + offs; 1369 1370 reg_dump->addr = cpu_to_le32(addr); 1371 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1372 addr)); 1373 1374 reg_dump++; 1375 } 1376 1377 if (reg->fifos.header_only) { 1378 range->range_data_size = cpu_to_le32(registers_size); 1379 goto out; 1380 } 1381 1382 /* 1383 * region register have absolute value so apply rxf offset after 1384 * reading the registers 1385 */ 1386 offs += rxf_data.offset; 1387 1388 /* Lock fence */ 1389 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1390 /* Set fence pointer to the same place like WR pointer */ 1391 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1392 /* Set fence offset */ 1393 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1394 0x0); 1395 1396 /* Read FIFO */ 1397 addr = RXF_FIFO_RD_FENCE_INC + offs; 1398 data = (void *)reg_dump; 1399 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1400 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1401 1402 out: 1403 iwl_trans_release_nic_access(fwrt->trans, &flags); 1404 1405 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1406 } 1407 1408 static void *iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1409 struct iwl_fw_ini_region_cfg *reg, 1410 void *data) 1411 { 1412 struct iwl_fw_ini_error_dump *dump = data; 1413 1414 dump->header.version = cpu_to_le32(IWL_INI_DUMP_MEM_VER); 1415 1416 return dump->ranges; 1417 } 1418 1419 static void 1420 *iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, 1421 struct iwl_fw_ini_region_cfg *reg, 1422 struct iwl_fw_ini_monitor_dump *data, 1423 u32 write_ptr_addr, u32 write_ptr_msk, 1424 u32 cycle_cnt_addr, u32 cycle_cnt_msk) 1425 { 1426 u32 write_ptr, cycle_cnt; 1427 unsigned long flags; 1428 1429 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) { 1430 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1431 return NULL; 1432 } 1433 1434 write_ptr = iwl_read_prph_no_grab(fwrt->trans, write_ptr_addr); 1435 cycle_cnt = iwl_read_prph_no_grab(fwrt->trans, cycle_cnt_addr); 1436 1437 iwl_trans_release_nic_access(fwrt->trans, &flags); 1438 1439 data->header.version = cpu_to_le32(IWL_INI_DUMP_MONITOR_VER); 1440 data->write_ptr = cpu_to_le32(write_ptr & write_ptr_msk); 1441 data->cycle_cnt = cpu_to_le32(cycle_cnt & cycle_cnt_msk); 1442 1443 return data->ranges; 1444 } 1445 1446 static void 1447 *iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1448 struct iwl_fw_ini_region_cfg *reg, 1449 void *data) 1450 { 1451 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1452 u32 write_ptr_addr, write_ptr_msk, cycle_cnt_addr, cycle_cnt_msk; 1453 1454 switch (fwrt->trans->cfg->device_family) { 1455 case IWL_DEVICE_FAMILY_9000: 1456 case IWL_DEVICE_FAMILY_22000: 1457 write_ptr_addr = MON_BUFF_WRPTR_VER2; 1458 write_ptr_msk = -1; 1459 cycle_cnt_addr = MON_BUFF_CYCLE_CNT_VER2; 1460 cycle_cnt_msk = -1; 1461 break; 1462 default: 1463 IWL_ERR(fwrt, "Unsupported device family %d\n", 1464 fwrt->trans->cfg->device_family); 1465 return NULL; 1466 } 1467 1468 return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, write_ptr_addr, 1469 write_ptr_msk, cycle_cnt_addr, 1470 cycle_cnt_msk); 1471 } 1472 1473 static void 1474 *iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1475 struct iwl_fw_ini_region_cfg *reg, 1476 void *data) 1477 { 1478 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1479 const struct iwl_cfg *cfg = fwrt->trans->cfg; 1480 1481 if (fwrt->trans->cfg->device_family != IWL_DEVICE_FAMILY_9000 && 1482 fwrt->trans->cfg->device_family != IWL_DEVICE_FAMILY_22000) { 1483 IWL_ERR(fwrt, "Unsupported device family %d\n", 1484 fwrt->trans->cfg->device_family); 1485 return NULL; 1486 } 1487 1488 return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, 1489 cfg->fw_mon_smem_write_ptr_addr, 1490 cfg->fw_mon_smem_write_ptr_msk, 1491 cfg->fw_mon_smem_cycle_cnt_ptr_addr, 1492 cfg->fw_mon_smem_cycle_cnt_ptr_msk); 1493 1494 } 1495 1496 static void *iwl_dump_ini_fifo_fill_header(struct iwl_fw_runtime *fwrt, 1497 struct iwl_fw_ini_region_cfg *reg, 1498 void *data) 1499 { 1500 struct iwl_fw_ini_fifo_error_dump *dump = data; 1501 1502 dump->header.version = cpu_to_le32(IWL_INI_DUMP_FIFO_VER); 1503 1504 return dump->ranges; 1505 } 1506 1507 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1508 struct iwl_fw_ini_region_cfg *reg) 1509 { 1510 return le32_to_cpu(reg->internal.num_of_ranges); 1511 } 1512 1513 static u32 iwl_dump_ini_paging_gen2_ranges(struct iwl_fw_runtime *fwrt, 1514 struct iwl_fw_ini_region_cfg *reg) 1515 { 1516 return fwrt->trans->init_dram.paging_cnt; 1517 } 1518 1519 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1520 struct iwl_fw_ini_region_cfg *reg) 1521 { 1522 return fwrt->num_of_paging_blk; 1523 } 1524 1525 static u32 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1526 struct iwl_fw_ini_region_cfg *reg) 1527 { 1528 return 1; 1529 } 1530 1531 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1532 struct iwl_fw_ini_region_cfg *reg) 1533 { 1534 struct iwl_ini_txf_iter_data iter = { .init = true }; 1535 void *fifo_iter = fwrt->dump.fifo_iter; 1536 u32 num_of_fifos = 0; 1537 1538 fwrt->dump.fifo_iter = &iter; 1539 while (iwl_ini_txf_iter(fwrt, reg)) 1540 num_of_fifos++; 1541 1542 fwrt->dump.fifo_iter = fifo_iter; 1543 1544 return num_of_fifos; 1545 } 1546 1547 static u32 iwl_dump_ini_rxf_ranges(struct iwl_fw_runtime *fwrt, 1548 struct iwl_fw_ini_region_cfg *reg) 1549 { 1550 /* Each Rx fifo needs a different offset and therefore, it's 1551 * region can contain only one fifo, i.e. 1 memory range. 1552 */ 1553 return 1; 1554 } 1555 1556 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1557 struct iwl_fw_ini_region_cfg *reg) 1558 { 1559 return sizeof(struct iwl_fw_ini_error_dump) + 1560 iwl_dump_ini_mem_ranges(fwrt, reg) * 1561 (sizeof(struct iwl_fw_ini_error_dump_range) + 1562 le32_to_cpu(reg->internal.range_data_size)); 1563 } 1564 1565 static u32 iwl_dump_ini_paging_gen2_get_size(struct iwl_fw_runtime *fwrt, 1566 struct iwl_fw_ini_region_cfg *reg) 1567 { 1568 int i; 1569 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1570 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1571 1572 for (i = 0; i < iwl_dump_ini_paging_gen2_ranges(fwrt, reg); i++) 1573 size += range_header_len + 1574 fwrt->trans->init_dram.paging[i].size; 1575 1576 return size; 1577 } 1578 1579 static u32 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1580 struct iwl_fw_ini_region_cfg *reg) 1581 { 1582 int i; 1583 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1584 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1585 1586 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg); i++) 1587 size += range_header_len + fwrt->fw_paging_db[i].fw_paging_size; 1588 1589 return size; 1590 } 1591 1592 static u32 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 1593 struct iwl_fw_ini_region_cfg *reg) 1594 { 1595 u32 size = sizeof(struct iwl_fw_ini_monitor_dump) + 1596 sizeof(struct iwl_fw_ini_error_dump_range); 1597 1598 if (fwrt->trans->num_blocks) 1599 size += fwrt->trans->fw_mon[0].size; 1600 1601 return size; 1602 } 1603 1604 static u32 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 1605 struct iwl_fw_ini_region_cfg *reg) 1606 { 1607 return sizeof(struct iwl_fw_ini_monitor_dump) + 1608 iwl_dump_ini_mem_ranges(fwrt, reg) * 1609 (sizeof(struct iwl_fw_ini_error_dump_range) + 1610 le32_to_cpu(reg->internal.range_data_size)); 1611 } 1612 1613 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 1614 struct iwl_fw_ini_region_cfg *reg) 1615 { 1616 struct iwl_ini_txf_iter_data iter = { .init = true }; 1617 void *fifo_iter = fwrt->dump.fifo_iter; 1618 u32 size = 0; 1619 u32 fifo_hdr = sizeof(struct iwl_fw_ini_fifo_error_dump_range) + 1620 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(__le32) * 2; 1621 1622 fwrt->dump.fifo_iter = &iter; 1623 while (iwl_ini_txf_iter(fwrt, reg)) { 1624 size += fifo_hdr; 1625 if (!reg->fifos.header_only) 1626 size += iter.fifo_size; 1627 } 1628 1629 if (size) 1630 size += sizeof(struct iwl_fw_ini_fifo_error_dump); 1631 1632 fwrt->dump.fifo_iter = fifo_iter; 1633 1634 return size; 1635 } 1636 1637 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 1638 struct iwl_fw_ini_region_cfg *reg) 1639 { 1640 struct iwl_ini_rxf_data rx_data; 1641 u32 size = sizeof(struct iwl_fw_ini_fifo_error_dump) + 1642 sizeof(struct iwl_fw_ini_fifo_error_dump_range) + 1643 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(__le32) * 2; 1644 1645 if (reg->fifos.header_only) 1646 return size; 1647 1648 iwl_ini_get_rxf_data(fwrt, reg, &rx_data); 1649 size += rx_data.size; 1650 1651 return size; 1652 } 1653 1654 /** 1655 * struct iwl_dump_ini_mem_ops - ini memory dump operations 1656 * @get_num_of_ranges: returns the number of memory ranges in the region. 1657 * @get_size: returns the total size of the region. 1658 * @fill_mem_hdr: fills region type specific headers and returns pointer to 1659 * the first range or NULL if failed to fill headers. 1660 * @fill_range: copies a given memory range into the dump. 1661 * Returns the size of the range or negative error value otherwise. 1662 */ 1663 struct iwl_dump_ini_mem_ops { 1664 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 1665 struct iwl_fw_ini_region_cfg *reg); 1666 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 1667 struct iwl_fw_ini_region_cfg *reg); 1668 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 1669 struct iwl_fw_ini_region_cfg *reg, void *data); 1670 int (*fill_range)(struct iwl_fw_runtime *fwrt, 1671 struct iwl_fw_ini_region_cfg *reg, void *range, 1672 int idx); 1673 }; 1674 1675 /** 1676 * iwl_dump_ini_mem - copy a memory region into the dump 1677 * @fwrt: fw runtime struct. 1678 * @data: dump memory data. 1679 * @reg: region to copy to the dump. 1680 * @ops: memory dump operations. 1681 */ 1682 static void 1683 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, 1684 struct iwl_fw_error_dump_data **data, 1685 struct iwl_fw_ini_region_cfg *reg, 1686 struct iwl_dump_ini_mem_ops *ops) 1687 { 1688 struct iwl_fw_ini_error_dump_header *header = (void *)(*data)->data; 1689 u32 num_of_ranges, i, type = le32_to_cpu(reg->region_type); 1690 void *range; 1691 1692 if (WARN_ON(!ops || !ops->get_num_of_ranges || !ops->get_size || 1693 !ops->fill_mem_hdr || !ops->fill_range)) 1694 return; 1695 1696 IWL_DEBUG_FW(fwrt, "WRT: collecting region: id=%d, type=%d\n", 1697 le32_to_cpu(reg->region_id), type); 1698 1699 num_of_ranges = ops->get_num_of_ranges(fwrt, reg); 1700 1701 (*data)->type = cpu_to_le32(type | INI_DUMP_BIT); 1702 (*data)->len = cpu_to_le32(ops->get_size(fwrt, reg)); 1703 1704 header->region_id = reg->region_id; 1705 header->num_of_ranges = cpu_to_le32(num_of_ranges); 1706 header->name_len = cpu_to_le32(min_t(int, IWL_FW_INI_MAX_NAME, 1707 le32_to_cpu(reg->name_len))); 1708 memcpy(header->name, reg->name, le32_to_cpu(header->name_len)); 1709 1710 range = ops->fill_mem_hdr(fwrt, reg, header); 1711 if (!range) { 1712 IWL_ERR(fwrt, 1713 "WRT: failed to fill region header: id=%d, type=%d\n", 1714 le32_to_cpu(reg->region_id), type); 1715 memset(*data, 0, le32_to_cpu((*data)->len)); 1716 return; 1717 } 1718 1719 for (i = 0; i < num_of_ranges; i++) { 1720 int range_size = ops->fill_range(fwrt, reg, range, i); 1721 1722 if (range_size < 0) { 1723 IWL_ERR(fwrt, 1724 "WRT: failed to dump region: id=%d, type=%d\n", 1725 le32_to_cpu(reg->region_id), type); 1726 memset(*data, 0, le32_to_cpu((*data)->len)); 1727 return; 1728 } 1729 range = range + range_size; 1730 } 1731 *data = iwl_fw_error_next_data(*data); 1732 } 1733 1734 static int iwl_fw_ini_get_trigger_len(struct iwl_fw_runtime *fwrt, 1735 struct iwl_fw_ini_trigger *trigger) 1736 { 1737 int i, size = 0, hdr_len = sizeof(struct iwl_fw_error_dump_data); 1738 1739 if (!trigger || !trigger->num_regions) 1740 return 0; 1741 1742 for (i = 0; i < le32_to_cpu(trigger->num_regions); i++) { 1743 u32 reg_id = le32_to_cpu(trigger->data[i]); 1744 struct iwl_fw_ini_region_cfg *reg; 1745 1746 if (WARN_ON(reg_id >= ARRAY_SIZE(fwrt->dump.active_regs))) 1747 continue; 1748 1749 reg = fwrt->dump.active_regs[reg_id]; 1750 if (!reg) { 1751 IWL_WARN(fwrt, 1752 "WRT: unassigned region id %d, skipping\n", 1753 reg_id); 1754 continue; 1755 } 1756 1757 switch (le32_to_cpu(reg->region_type)) { 1758 case IWL_FW_INI_REGION_DEVICE_MEMORY: 1759 case IWL_FW_INI_REGION_PERIPHERY_MAC: 1760 case IWL_FW_INI_REGION_PERIPHERY_PHY: 1761 case IWL_FW_INI_REGION_PERIPHERY_AUX: 1762 case IWL_FW_INI_REGION_CSR: 1763 size += hdr_len + iwl_dump_ini_mem_get_size(fwrt, reg); 1764 break; 1765 case IWL_FW_INI_REGION_TXF: 1766 size += hdr_len + iwl_dump_ini_txf_get_size(fwrt, reg); 1767 break; 1768 case IWL_FW_INI_REGION_RXF: 1769 size += hdr_len + iwl_dump_ini_rxf_get_size(fwrt, reg); 1770 break; 1771 case IWL_FW_INI_REGION_PAGING: 1772 size += hdr_len; 1773 if (iwl_fw_dbg_is_paging_enabled(fwrt)) { 1774 size += iwl_dump_ini_paging_get_size(fwrt, reg); 1775 } else { 1776 size += iwl_dump_ini_paging_gen2_get_size(fwrt, 1777 reg); 1778 } 1779 break; 1780 case IWL_FW_INI_REGION_DRAM_BUFFER: 1781 if (!fwrt->trans->num_blocks) 1782 break; 1783 size += hdr_len + 1784 iwl_dump_ini_mon_dram_get_size(fwrt, reg); 1785 break; 1786 case IWL_FW_INI_REGION_INTERNAL_BUFFER: 1787 size += hdr_len + 1788 iwl_dump_ini_mon_smem_get_size(fwrt, reg); 1789 break; 1790 case IWL_FW_INI_REGION_DRAM_IMR: 1791 /* Undefined yet */ 1792 default: 1793 break; 1794 } 1795 } 1796 return size; 1797 } 1798 1799 static void iwl_fw_ini_dump_trigger(struct iwl_fw_runtime *fwrt, 1800 struct iwl_fw_ini_trigger *trigger, 1801 struct iwl_fw_error_dump_data **data) 1802 { 1803 int i, num = le32_to_cpu(trigger->num_regions); 1804 1805 for (i = 0; i < num; i++) { 1806 u32 reg_id = le32_to_cpu(trigger->data[i]); 1807 struct iwl_fw_ini_region_cfg *reg; 1808 struct iwl_dump_ini_mem_ops ops; 1809 1810 if (reg_id >= ARRAY_SIZE(fwrt->dump.active_regs)) 1811 continue; 1812 1813 reg = fwrt->dump.active_regs[reg_id]; 1814 /* Don't warn, get_trigger_len already warned */ 1815 if (!reg) 1816 continue; 1817 1818 /* currently the driver supports always on domain only */ 1819 if (le32_to_cpu(reg->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON) 1820 continue; 1821 1822 switch (le32_to_cpu(reg->region_type)) { 1823 case IWL_FW_INI_REGION_DEVICE_MEMORY: 1824 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1825 ops.get_size = iwl_dump_ini_mem_get_size; 1826 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1827 ops.fill_range = iwl_dump_ini_dev_mem_iter; 1828 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1829 break; 1830 case IWL_FW_INI_REGION_PERIPHERY_MAC: 1831 case IWL_FW_INI_REGION_PERIPHERY_PHY: 1832 case IWL_FW_INI_REGION_PERIPHERY_AUX: 1833 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1834 ops.get_size = iwl_dump_ini_mem_get_size; 1835 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1836 ops.fill_range = iwl_dump_ini_prph_iter; 1837 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1838 break; 1839 case IWL_FW_INI_REGION_DRAM_BUFFER: 1840 ops.get_num_of_ranges = iwl_dump_ini_mon_dram_ranges; 1841 ops.get_size = iwl_dump_ini_mon_dram_get_size; 1842 ops.fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header; 1843 ops.fill_range = iwl_dump_ini_mon_dram_iter; 1844 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1845 break; 1846 case IWL_FW_INI_REGION_INTERNAL_BUFFER: 1847 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1848 ops.get_size = iwl_dump_ini_mon_smem_get_size; 1849 ops.fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header; 1850 ops.fill_range = iwl_dump_ini_dev_mem_iter; 1851 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1852 break; 1853 case IWL_FW_INI_REGION_PAGING: 1854 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1855 if (iwl_fw_dbg_is_paging_enabled(fwrt)) { 1856 ops.get_num_of_ranges = 1857 iwl_dump_ini_paging_ranges; 1858 ops.get_size = iwl_dump_ini_paging_get_size; 1859 ops.fill_range = iwl_dump_ini_paging_iter; 1860 } else { 1861 ops.get_num_of_ranges = 1862 iwl_dump_ini_paging_gen2_ranges; 1863 ops.get_size = 1864 iwl_dump_ini_paging_gen2_get_size; 1865 ops.fill_range = iwl_dump_ini_paging_gen2_iter; 1866 } 1867 1868 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1869 break; 1870 case IWL_FW_INI_REGION_TXF: { 1871 struct iwl_ini_txf_iter_data iter = { .init = true }; 1872 void *fifo_iter = fwrt->dump.fifo_iter; 1873 1874 fwrt->dump.fifo_iter = &iter; 1875 ops.get_num_of_ranges = iwl_dump_ini_txf_ranges; 1876 ops.get_size = iwl_dump_ini_txf_get_size; 1877 ops.fill_mem_hdr = iwl_dump_ini_fifo_fill_header; 1878 ops.fill_range = iwl_dump_ini_txf_iter; 1879 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1880 fwrt->dump.fifo_iter = fifo_iter; 1881 break; 1882 } 1883 case IWL_FW_INI_REGION_RXF: 1884 ops.get_num_of_ranges = iwl_dump_ini_rxf_ranges; 1885 ops.get_size = iwl_dump_ini_rxf_get_size; 1886 ops.fill_mem_hdr = iwl_dump_ini_fifo_fill_header; 1887 ops.fill_range = iwl_dump_ini_rxf_iter; 1888 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1889 break; 1890 case IWL_FW_INI_REGION_CSR: 1891 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1892 ops.get_size = iwl_dump_ini_mem_get_size; 1893 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1894 ops.fill_range = iwl_dump_ini_csr_iter; 1895 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1896 break; 1897 case IWL_FW_INI_REGION_DRAM_IMR: 1898 /* This is undefined yet */ 1899 default: 1900 break; 1901 } 1902 } 1903 } 1904 1905 static struct iwl_fw_error_dump_file * 1906 iwl_fw_error_ini_dump_file(struct iwl_fw_runtime *fwrt) 1907 { 1908 int size; 1909 struct iwl_fw_error_dump_data *dump_data; 1910 struct iwl_fw_error_dump_file *dump_file; 1911 struct iwl_fw_ini_trigger *trigger; 1912 enum iwl_fw_ini_trigger_id id = fwrt->dump.ini_trig_id; 1913 1914 if (!iwl_fw_ini_trigger_on(fwrt, id)) 1915 return NULL; 1916 1917 trigger = fwrt->dump.active_trigs[id].trig; 1918 1919 size = iwl_fw_ini_get_trigger_len(fwrt, trigger); 1920 if (!size) 1921 return NULL; 1922 1923 size += sizeof(*dump_file); 1924 1925 dump_file = vzalloc(size); 1926 if (!dump_file) 1927 return NULL; 1928 1929 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 1930 dump_data = (void *)dump_file->data; 1931 dump_file->file_len = cpu_to_le32(size); 1932 1933 iwl_fw_ini_dump_trigger(fwrt, trigger, &dump_data); 1934 1935 return dump_file; 1936 } 1937 1938 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt) 1939 { 1940 struct iwl_fw_dump_ptrs fw_error_dump = {}; 1941 struct iwl_fw_error_dump_file *dump_file; 1942 struct scatterlist *sg_dump_data; 1943 u32 file_len; 1944 u32 dump_mask = fwrt->fw->dbg.dump_mask; 1945 1946 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump); 1947 if (!dump_file) 1948 goto out; 1949 1950 if (!fwrt->trans->ini_valid && fwrt->dump.monitor_only) 1951 dump_mask &= IWL_FW_ERROR_DUMP_FW_MONITOR; 1952 1953 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask); 1954 file_len = le32_to_cpu(dump_file->file_len); 1955 fw_error_dump.fwrt_len = file_len; 1956 1957 if (fw_error_dump.trans_ptr) { 1958 file_len += fw_error_dump.trans_ptr->len; 1959 dump_file->file_len = cpu_to_le32(file_len); 1960 } 1961 1962 sg_dump_data = alloc_sgtable(file_len); 1963 if (sg_dump_data) { 1964 sg_pcopy_from_buffer(sg_dump_data, 1965 sg_nents(sg_dump_data), 1966 fw_error_dump.fwrt_ptr, 1967 fw_error_dump.fwrt_len, 0); 1968 if (fw_error_dump.trans_ptr) 1969 sg_pcopy_from_buffer(sg_dump_data, 1970 sg_nents(sg_dump_data), 1971 fw_error_dump.trans_ptr->data, 1972 fw_error_dump.trans_ptr->len, 1973 fw_error_dump.fwrt_len); 1974 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 1975 GFP_KERNEL); 1976 } 1977 vfree(fw_error_dump.fwrt_ptr); 1978 vfree(fw_error_dump.trans_ptr); 1979 1980 out: 1981 iwl_fw_free_dump_desc(fwrt); 1982 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 1983 } 1984 1985 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt) 1986 { 1987 struct iwl_fw_error_dump_file *dump_file; 1988 struct scatterlist *sg_dump_data; 1989 u32 file_len; 1990 1991 dump_file = iwl_fw_error_ini_dump_file(fwrt); 1992 if (!dump_file) 1993 goto out; 1994 1995 file_len = le32_to_cpu(dump_file->file_len); 1996 1997 sg_dump_data = alloc_sgtable(file_len); 1998 if (sg_dump_data) { 1999 sg_pcopy_from_buffer(sg_dump_data, sg_nents(sg_dump_data), 2000 dump_file, file_len, 0); 2001 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2002 GFP_KERNEL); 2003 } 2004 vfree(dump_file); 2005 out: 2006 fwrt->dump.ini_trig_id = IWL_FW_TRIGGER_ID_INVALID; 2007 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 2008 } 2009 2010 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2011 .trig_desc = { 2012 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2013 }, 2014 }; 2015 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2016 2017 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2018 const struct iwl_fw_dump_desc *desc, 2019 bool monitor_only, 2020 unsigned int delay) 2021 { 2022 u32 trig_type = le32_to_cpu(desc->trig_desc.type); 2023 int ret; 2024 2025 if (fwrt->trans->ini_valid) { 2026 ret = iwl_fw_dbg_ini_collect(fwrt, trig_type); 2027 if (!ret) 2028 iwl_fw_free_dump_desc(fwrt); 2029 2030 return ret; 2031 } 2032 2033 if (test_and_set_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 2034 return -EBUSY; 2035 2036 if (WARN_ON(fwrt->dump.desc)) 2037 iwl_fw_free_dump_desc(fwrt); 2038 2039 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2040 le32_to_cpu(desc->trig_desc.type)); 2041 2042 fwrt->dump.desc = desc; 2043 fwrt->dump.monitor_only = monitor_only; 2044 2045 schedule_delayed_work(&fwrt->dump.wk, usecs_to_jiffies(delay)); 2046 2047 return 0; 2048 } 2049 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2050 2051 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2052 enum iwl_fw_dbg_trigger trig_type) 2053 { 2054 int ret; 2055 struct iwl_fw_dump_desc *iwl_dump_error_desc = 2056 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2057 2058 if (!iwl_dump_error_desc) 2059 return -ENOMEM; 2060 2061 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2062 iwl_dump_error_desc->len = 0; 2063 2064 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, false, 0); 2065 if (ret) 2066 kfree(iwl_dump_error_desc); 2067 else 2068 iwl_trans_sync_nmi(fwrt->trans); 2069 2070 return ret; 2071 } 2072 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2073 2074 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2075 enum iwl_fw_dbg_trigger trig, 2076 const char *str, size_t len, 2077 struct iwl_fw_dbg_trigger_tlv *trigger) 2078 { 2079 struct iwl_fw_dump_desc *desc; 2080 unsigned int delay = 0; 2081 bool monitor_only = false; 2082 2083 if (trigger) { 2084 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2085 2086 if (!le16_to_cpu(trigger->occurrences)) 2087 return 0; 2088 2089 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2090 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2091 trig); 2092 iwl_force_nmi(fwrt->trans); 2093 return 0; 2094 } 2095 2096 trigger->occurrences = cpu_to_le16(occurrences); 2097 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2098 2099 /* convert msec to usec */ 2100 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2101 } 2102 2103 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 2104 if (!desc) 2105 return -ENOMEM; 2106 2107 2108 desc->len = len; 2109 desc->trig_desc.type = cpu_to_le32(trig); 2110 memcpy(desc->trig_desc.data, str, len); 2111 2112 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2113 } 2114 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2115 2116 int _iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 2117 enum iwl_fw_ini_trigger_id id) 2118 { 2119 struct iwl_fw_ini_active_triggers *active; 2120 u32 occur, delay; 2121 2122 if (WARN_ON(!iwl_fw_ini_trigger_on(fwrt, id))) 2123 return -EINVAL; 2124 2125 if (test_and_set_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 2126 return -EBUSY; 2127 2128 if (!iwl_fw_ini_trigger_on(fwrt, id)) { 2129 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 2130 id); 2131 return -EINVAL; 2132 } 2133 2134 active = &fwrt->dump.active_trigs[id]; 2135 delay = le32_to_cpu(active->trig->dump_delay); 2136 occur = le32_to_cpu(active->trig->occurrences); 2137 if (!occur) 2138 return 0; 2139 2140 active->trig->occurrences = cpu_to_le32(--occur); 2141 2142 if (le32_to_cpu(active->trig->force_restart)) { 2143 IWL_WARN(fwrt, "WRT: force restart: trigger %d fired.\n", id); 2144 iwl_force_nmi(fwrt->trans); 2145 return 0; 2146 } 2147 2148 if (test_and_set_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 2149 return -EBUSY; 2150 2151 fwrt->dump.ini_trig_id = id; 2152 2153 IWL_WARN(fwrt, "WRT: collecting data: ini trigger %d fired.\n", id); 2154 2155 schedule_delayed_work(&fwrt->dump.wk, usecs_to_jiffies(delay)); 2156 2157 return 0; 2158 } 2159 IWL_EXPORT_SYMBOL(_iwl_fw_dbg_ini_collect); 2160 2161 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, u32 legacy_trigger_id) 2162 { 2163 int id; 2164 2165 switch (legacy_trigger_id) { 2166 case FW_DBG_TRIGGER_FW_ASSERT: 2167 case FW_DBG_TRIGGER_ALIVE_TIMEOUT: 2168 case FW_DBG_TRIGGER_DRIVER: 2169 id = IWL_FW_TRIGGER_ID_FW_ASSERT; 2170 break; 2171 case FW_DBG_TRIGGER_USER: 2172 id = IWL_FW_TRIGGER_ID_USER_TRIGGER; 2173 break; 2174 default: 2175 return -EIO; 2176 } 2177 2178 return _iwl_fw_dbg_ini_collect(fwrt, id); 2179 } 2180 IWL_EXPORT_SYMBOL(iwl_fw_dbg_ini_collect); 2181 2182 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2183 struct iwl_fw_dbg_trigger_tlv *trigger, 2184 const char *fmt, ...) 2185 { 2186 int ret, len = 0; 2187 char buf[64]; 2188 2189 if (fwrt->trans->ini_valid) 2190 return 0; 2191 2192 if (fmt) { 2193 va_list ap; 2194 2195 buf[sizeof(buf) - 1] = '\0'; 2196 2197 va_start(ap, fmt); 2198 vsnprintf(buf, sizeof(buf), fmt, ap); 2199 va_end(ap); 2200 2201 /* check for truncation */ 2202 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2203 buf[sizeof(buf) - 1] = '\0'; 2204 2205 len = strlen(buf) + 1; 2206 } 2207 2208 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2209 trigger); 2210 2211 if (ret) 2212 return ret; 2213 2214 return 0; 2215 } 2216 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2217 2218 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2219 { 2220 u8 *ptr; 2221 int ret; 2222 int i; 2223 2224 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 2225 "Invalid configuration %d\n", conf_id)) 2226 return -EINVAL; 2227 2228 /* EARLY START - firmware's configuration is hard coded */ 2229 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 2230 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 2231 conf_id == FW_DBG_START_FROM_ALIVE) 2232 return 0; 2233 2234 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 2235 return -EINVAL; 2236 2237 if (fwrt->dump.conf != FW_DBG_INVALID) 2238 IWL_WARN(fwrt, "FW already configured (%d) - re-configuring\n", 2239 fwrt->dump.conf); 2240 2241 /* Send all HCMDs for configuring the FW debug */ 2242 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 2243 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 2244 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 2245 struct iwl_host_cmd hcmd = { 2246 .id = cmd->id, 2247 .len = { le16_to_cpu(cmd->len), }, 2248 .data = { cmd->data, }, 2249 }; 2250 2251 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 2252 if (ret) 2253 return ret; 2254 2255 ptr += sizeof(*cmd); 2256 ptr += le16_to_cpu(cmd->len); 2257 } 2258 2259 fwrt->dump.conf = conf_id; 2260 2261 return 0; 2262 } 2263 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 2264 2265 /* this function assumes dump_start was called beforehand and dump_end will be 2266 * called afterwards 2267 */ 2268 void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt) 2269 { 2270 struct iwl_fw_dbg_params params = {0}; 2271 2272 if (!test_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 2273 return; 2274 2275 if (fwrt->ops && fwrt->ops->fw_running && 2276 !fwrt->ops->fw_running(fwrt->ops_ctx)) { 2277 IWL_ERR(fwrt, "Firmware not running - cannot dump error\n"); 2278 iwl_fw_free_dump_desc(fwrt); 2279 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 2280 return; 2281 } 2282 2283 /* there's no point in fw dump if the bus is dead */ 2284 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 2285 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 2286 return; 2287 } 2288 2289 iwl_fw_dbg_stop_recording(fwrt, ¶ms); 2290 2291 IWL_DEBUG_FW_INFO(fwrt, "WRT: data collection start\n"); 2292 if (fwrt->trans->ini_valid) 2293 iwl_fw_error_ini_dump(fwrt); 2294 else 2295 iwl_fw_error_dump(fwrt); 2296 IWL_DEBUG_FW_INFO(fwrt, "WRT: data collection done\n"); 2297 2298 /* start recording again if the firmware is not crashed */ 2299 if (!test_bit(STATUS_FW_ERROR, &fwrt->trans->status) && 2300 fwrt->fw->dbg.dest_tlv) { 2301 /* wait before we collect the data till the DBGC stop */ 2302 udelay(500); 2303 iwl_fw_dbg_restart_recording(fwrt, ¶ms); 2304 } 2305 } 2306 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_sync); 2307 2308 void iwl_fw_error_dump_wk(struct work_struct *work) 2309 { 2310 struct iwl_fw_runtime *fwrt = 2311 container_of(work, struct iwl_fw_runtime, dump.wk.work); 2312 2313 if (fwrt->ops && fwrt->ops->dump_start && 2314 fwrt->ops->dump_start(fwrt->ops_ctx)) 2315 return; 2316 2317 iwl_fw_dbg_collect_sync(fwrt); 2318 2319 if (fwrt->ops && fwrt->ops->dump_end) 2320 fwrt->ops->dump_end(fwrt->ops_ctx); 2321 } 2322 2323 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 2324 { 2325 const struct iwl_cfg *cfg = fwrt->trans->cfg; 2326 2327 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 2328 return; 2329 2330 if (!fwrt->dump.d3_debug_data) { 2331 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 2332 GFP_KERNEL); 2333 if (!fwrt->dump.d3_debug_data) { 2334 IWL_ERR(fwrt, 2335 "failed to allocate memory for D3 debug data\n"); 2336 return; 2337 } 2338 } 2339 2340 /* if the buffer holds previous debug data it is overwritten */ 2341 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 2342 fwrt->dump.d3_debug_data, 2343 cfg->d3_debug_data_length); 2344 } 2345 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 2346 2347 static void 2348 iwl_fw_dbg_buffer_allocation(struct iwl_fw_runtime *fwrt, u32 size) 2349 { 2350 struct iwl_trans *trans = fwrt->trans; 2351 void *virtual_addr = NULL; 2352 dma_addr_t phys_addr; 2353 2354 if (WARN_ON_ONCE(trans->num_blocks == ARRAY_SIZE(trans->fw_mon))) 2355 return; 2356 2357 virtual_addr = 2358 dma_alloc_coherent(fwrt->trans->dev, size, &phys_addr, 2359 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO | 2360 __GFP_COMP); 2361 2362 /* TODO: alloc fragments if needed */ 2363 if (!virtual_addr) 2364 IWL_ERR(fwrt, "Failed to allocate debug memory\n"); 2365 2366 IWL_DEBUG_FW(trans, 2367 "Allocated DRAM buffer[%d], size=0x%x\n", 2368 trans->num_blocks, size); 2369 2370 trans->fw_mon[trans->num_blocks].block = virtual_addr; 2371 trans->fw_mon[trans->num_blocks].physical = phys_addr; 2372 trans->fw_mon[trans->num_blocks].size = size; 2373 trans->num_blocks++; 2374 } 2375 2376 static void iwl_fw_dbg_buffer_apply(struct iwl_fw_runtime *fwrt, 2377 struct iwl_fw_ini_allocation_data *alloc, 2378 enum iwl_fw_ini_apply_point pnt) 2379 { 2380 struct iwl_trans *trans = fwrt->trans; 2381 struct iwl_ldbg_config_cmd ldbg_cmd = { 2382 .type = cpu_to_le32(BUFFER_ALLOCATION), 2383 }; 2384 struct iwl_buffer_allocation_cmd *cmd = &ldbg_cmd.buffer_allocation; 2385 struct iwl_host_cmd hcmd = { 2386 .id = LDBG_CONFIG_CMD, 2387 .flags = CMD_ASYNC, 2388 .data[0] = &ldbg_cmd, 2389 .len[0] = sizeof(ldbg_cmd), 2390 }; 2391 int block_idx = trans->num_blocks; 2392 u32 buf_location = le32_to_cpu(alloc->tlv.buffer_location); 2393 2394 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH) { 2395 if (!WARN(pnt != IWL_FW_INI_APPLY_EARLY, 2396 "WRT: Invalid apply point %d for SMEM buffer allocation, aborting\n", 2397 pnt)) { 2398 IWL_DEBUG_FW(trans, 2399 "WRT: applying SMEM buffer destination\n"); 2400 2401 /* set sram monitor by enabling bit 7 */ 2402 iwl_set_bit(fwrt->trans, CSR_HW_IF_CONFIG_REG, 2403 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 2404 } 2405 return; 2406 } 2407 2408 if (buf_location != IWL_FW_INI_LOCATION_DRAM_PATH) 2409 return; 2410 2411 if (!alloc->is_alloc) { 2412 iwl_fw_dbg_buffer_allocation(fwrt, 2413 le32_to_cpu(alloc->tlv.size)); 2414 if (block_idx == trans->num_blocks) 2415 return; 2416 alloc->is_alloc = 1; 2417 } 2418 2419 /* First block is assigned via registers / context info */ 2420 if (trans->num_blocks == 1) 2421 return; 2422 2423 IWL_DEBUG_FW(trans, 2424 "WRT: applying DRAM buffer[%d] destination\n", block_idx); 2425 2426 cmd->num_frags = cpu_to_le32(1); 2427 cmd->fragments[0].address = 2428 cpu_to_le64(trans->fw_mon[block_idx].physical); 2429 cmd->fragments[0].size = alloc->tlv.size; 2430 cmd->allocation_id = alloc->tlv.allocation_id; 2431 cmd->buffer_location = alloc->tlv.buffer_location; 2432 2433 iwl_trans_send_cmd(trans, &hcmd); 2434 } 2435 2436 static void iwl_fw_dbg_send_hcmd(struct iwl_fw_runtime *fwrt, 2437 struct iwl_ucode_tlv *tlv, 2438 bool ext) 2439 { 2440 struct iwl_fw_ini_hcmd_tlv *hcmd_tlv = (void *)&tlv->data[0]; 2441 struct iwl_fw_ini_hcmd *data = &hcmd_tlv->hcmd; 2442 u16 len = le32_to_cpu(tlv->length) - sizeof(*hcmd_tlv); 2443 2444 struct iwl_host_cmd hcmd = { 2445 .id = WIDE_ID(data->group, data->id), 2446 .len = { len, }, 2447 .data = { data->data, }, 2448 }; 2449 2450 /* currently the driver supports always on domain only */ 2451 if (le32_to_cpu(hcmd_tlv->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON) 2452 return; 2453 2454 IWL_DEBUG_FW(fwrt, 2455 "WRT: ext=%d. Sending host command id=0x%x, group=0x%x\n", 2456 ext, data->id, data->group); 2457 2458 iwl_trans_send_cmd(fwrt->trans, &hcmd); 2459 } 2460 2461 static void iwl_fw_dbg_update_regions(struct iwl_fw_runtime *fwrt, 2462 struct iwl_fw_ini_region_tlv *tlv, 2463 bool ext, enum iwl_fw_ini_apply_point pnt) 2464 { 2465 void *iter = (void *)tlv->region_config; 2466 int i, size = le32_to_cpu(tlv->num_regions); 2467 2468 for (i = 0; i < size; i++) { 2469 struct iwl_fw_ini_region_cfg *reg = iter, **active; 2470 int id = le32_to_cpu(reg->region_id); 2471 u32 type = le32_to_cpu(reg->region_type); 2472 2473 if (WARN(id >= ARRAY_SIZE(fwrt->dump.active_regs), 2474 "WRT: ext=%d. Invalid region id %d for apply point %d\n", 2475 ext, id, pnt)) 2476 break; 2477 2478 active = &fwrt->dump.active_regs[id]; 2479 2480 if (*active) 2481 IWL_WARN(fwrt->trans, 2482 "WRT: ext=%d. Region id %d override\n", 2483 ext, id); 2484 2485 IWL_DEBUG_FW(fwrt, 2486 "WRT: ext=%d. Activating region id %d\n", 2487 ext, id); 2488 2489 *active = reg; 2490 2491 if (type == IWL_FW_INI_REGION_TXF || 2492 type == IWL_FW_INI_REGION_RXF) 2493 iter += le32_to_cpu(reg->fifos.num_of_registers) * 2494 sizeof(__le32); 2495 else if (type == IWL_FW_INI_REGION_DEVICE_MEMORY || 2496 type == IWL_FW_INI_REGION_PERIPHERY_MAC || 2497 type == IWL_FW_INI_REGION_PERIPHERY_PHY || 2498 type == IWL_FW_INI_REGION_PERIPHERY_AUX || 2499 type == IWL_FW_INI_REGION_INTERNAL_BUFFER || 2500 type == IWL_FW_INI_REGION_PAGING || 2501 type == IWL_FW_INI_REGION_CSR) 2502 iter += le32_to_cpu(reg->internal.num_of_ranges) * 2503 sizeof(__le32); 2504 2505 iter += sizeof(*reg); 2506 } 2507 } 2508 2509 static int iwl_fw_dbg_trig_realloc(struct iwl_fw_runtime *fwrt, 2510 struct iwl_fw_ini_active_triggers *active, 2511 u32 id, int size) 2512 { 2513 void *ptr; 2514 2515 if (size <= active->size) 2516 return 0; 2517 2518 ptr = krealloc(active->trig, size, GFP_KERNEL); 2519 if (!ptr) { 2520 IWL_ERR(fwrt, "WRT: Failed to allocate memory for trigger %d\n", 2521 id); 2522 return -ENOMEM; 2523 } 2524 active->trig = ptr; 2525 active->size = size; 2526 2527 return 0; 2528 } 2529 2530 static void iwl_fw_dbg_update_triggers(struct iwl_fw_runtime *fwrt, 2531 struct iwl_fw_ini_trigger_tlv *tlv, 2532 bool ext, 2533 enum iwl_fw_ini_apply_point apply_point) 2534 { 2535 int i, size = le32_to_cpu(tlv->num_triggers); 2536 void *iter = (void *)tlv->trigger_config; 2537 2538 for (i = 0; i < size; i++) { 2539 struct iwl_fw_ini_trigger *trig = iter; 2540 struct iwl_fw_ini_active_triggers *active; 2541 int id = le32_to_cpu(trig->trigger_id); 2542 u32 trig_regs_size = le32_to_cpu(trig->num_regions) * 2543 sizeof(__le32); 2544 2545 if (WARN(id >= ARRAY_SIZE(fwrt->dump.active_trigs), 2546 "WRT: ext=%d. Invalid trigger id %d for apply point %d\n", 2547 ext, id, apply_point)) 2548 break; 2549 2550 active = &fwrt->dump.active_trigs[id]; 2551 2552 if (!active->active) { 2553 size_t trig_size = sizeof(*trig) + trig_regs_size; 2554 2555 IWL_DEBUG_FW(fwrt, 2556 "WRT: ext=%d. Activating trigger %d\n", 2557 ext, id); 2558 2559 if (iwl_fw_dbg_trig_realloc(fwrt, active, id, 2560 trig_size)) 2561 goto next; 2562 2563 memcpy(active->trig, trig, trig_size); 2564 2565 } else { 2566 u32 conf_override = 2567 !(le32_to_cpu(trig->override_trig) & 0xff); 2568 u32 region_override = 2569 !(le32_to_cpu(trig->override_trig) & 0xff00); 2570 u32 offset = 0; 2571 u32 active_regs = 2572 le32_to_cpu(active->trig->num_regions); 2573 u32 new_regs = le32_to_cpu(trig->num_regions); 2574 int mem_to_add = trig_regs_size; 2575 2576 if (region_override) { 2577 IWL_DEBUG_FW(fwrt, 2578 "WRT: ext=%d. Trigger %d regions override\n", 2579 ext, id); 2580 2581 mem_to_add -= active_regs * sizeof(__le32); 2582 } else { 2583 IWL_DEBUG_FW(fwrt, 2584 "WRT: ext=%d. Trigger %d regions appending\n", 2585 ext, id); 2586 2587 offset += active_regs; 2588 new_regs += active_regs; 2589 } 2590 2591 if (iwl_fw_dbg_trig_realloc(fwrt, active, id, 2592 active->size + mem_to_add)) 2593 goto next; 2594 2595 if (conf_override) { 2596 IWL_DEBUG_FW(fwrt, 2597 "WRT: ext=%d. Trigger %d configuration override\n", 2598 ext, id); 2599 2600 memcpy(active->trig, trig, sizeof(*trig)); 2601 } 2602 2603 memcpy(active->trig->data + offset, trig->data, 2604 trig_regs_size); 2605 active->trig->num_regions = cpu_to_le32(new_regs); 2606 } 2607 2608 /* Since zero means infinity - just set to -1 */ 2609 if (!le32_to_cpu(active->trig->occurrences)) 2610 active->trig->occurrences = cpu_to_le32(-1); 2611 2612 active->active = true; 2613 next: 2614 iter += sizeof(*trig) + trig_regs_size; 2615 2616 } 2617 } 2618 2619 static void _iwl_fw_dbg_apply_point(struct iwl_fw_runtime *fwrt, 2620 struct iwl_apply_point_data *data, 2621 enum iwl_fw_ini_apply_point pnt, 2622 bool ext) 2623 { 2624 void *iter = data->data; 2625 2626 while (iter && iter < data->data + data->size) { 2627 struct iwl_ucode_tlv *tlv = iter; 2628 void *ini_tlv = (void *)tlv->data; 2629 u32 type = le32_to_cpu(tlv->type); 2630 2631 switch (type) { 2632 case IWL_UCODE_TLV_TYPE_BUFFER_ALLOCATION: { 2633 struct iwl_fw_ini_allocation_data *buf_alloc = ini_tlv; 2634 2635 iwl_fw_dbg_buffer_apply(fwrt, ini_tlv, pnt); 2636 iter += sizeof(buf_alloc->is_alloc); 2637 break; 2638 } 2639 case IWL_UCODE_TLV_TYPE_HCMD: 2640 if (pnt < IWL_FW_INI_APPLY_AFTER_ALIVE) { 2641 IWL_ERR(fwrt, 2642 "WRT: ext=%d. Invalid apply point %d for host command\n", 2643 ext, pnt); 2644 goto next; 2645 } 2646 iwl_fw_dbg_send_hcmd(fwrt, tlv, ext); 2647 break; 2648 case IWL_UCODE_TLV_TYPE_REGIONS: 2649 iwl_fw_dbg_update_regions(fwrt, ini_tlv, ext, pnt); 2650 break; 2651 case IWL_UCODE_TLV_TYPE_TRIGGERS: 2652 iwl_fw_dbg_update_triggers(fwrt, ini_tlv, ext, pnt); 2653 break; 2654 case IWL_UCODE_TLV_TYPE_DEBUG_FLOW: 2655 break; 2656 default: 2657 WARN_ONCE(1, 2658 "WRT: ext=%d. Invalid TLV 0x%x for apply point\n", 2659 ext, type); 2660 break; 2661 } 2662 next: 2663 iter += sizeof(*tlv) + le32_to_cpu(tlv->length); 2664 } 2665 } 2666 2667 void iwl_fw_dbg_apply_point(struct iwl_fw_runtime *fwrt, 2668 enum iwl_fw_ini_apply_point apply_point) 2669 { 2670 void *data = &fwrt->trans->apply_points[apply_point]; 2671 int i; 2672 2673 IWL_DEBUG_FW(fwrt, "WRT: enabling apply point %d\n", apply_point); 2674 2675 if (apply_point == IWL_FW_INI_APPLY_EARLY) { 2676 for (i = 0; i < IWL_FW_INI_MAX_REGION_ID; i++) 2677 fwrt->dump.active_regs[i] = NULL; 2678 2679 /* disable the triggers, used in recovery flow */ 2680 for (i = 0; i < IWL_FW_TRIGGER_ID_NUM; i++) 2681 fwrt->dump.active_trigs[i].active = false; 2682 } 2683 2684 _iwl_fw_dbg_apply_point(fwrt, data, apply_point, false); 2685 2686 data = &fwrt->trans->apply_points_ext[apply_point]; 2687 _iwl_fw_dbg_apply_point(fwrt, data, apply_point, true); 2688 } 2689 IWL_EXPORT_SYMBOL(iwl_fw_dbg_apply_point); 2690 2691 void iwl_fwrt_stop_device(struct iwl_fw_runtime *fwrt) 2692 { 2693 iwl_fw_dbg_collect_sync(fwrt); 2694 2695 iwl_trans_stop_device(fwrt->trans); 2696 } 2697 IWL_EXPORT_SYMBOL(iwl_fwrt_stop_device); 2698