1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #include <linux/devcoredump.h> 65 #include "iwl-drv.h" 66 #include "runtime.h" 67 #include "dbg.h" 68 #include "debugfs.h" 69 #include "iwl-io.h" 70 #include "iwl-prph.h" 71 #include "iwl-csr.h" 72 73 /** 74 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 75 * 76 * @fwrt_ptr: pointer to the buffer coming from fwrt 77 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 78 * transport's data. 79 * @trans_len: length of the valid data in trans_ptr 80 * @fwrt_len: length of the valid data in fwrt_ptr 81 */ 82 struct iwl_fw_dump_ptrs { 83 struct iwl_trans_dump_data *trans_ptr; 84 void *fwrt_ptr; 85 u32 fwrt_len; 86 }; 87 88 #define RADIO_REG_MAX_READ 0x2ad 89 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 90 struct iwl_fw_error_dump_data **dump_data) 91 { 92 u8 *pos = (void *)(*dump_data)->data; 93 unsigned long flags; 94 int i; 95 96 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 97 98 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 99 return; 100 101 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 102 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 103 104 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 105 u32 rd_cmd = RADIO_RSP_RD_CMD; 106 107 rd_cmd |= i << RADIO_RSP_ADDR_POS; 108 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 109 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 110 111 pos++; 112 } 113 114 *dump_data = iwl_fw_error_next_data(*dump_data); 115 116 iwl_trans_release_nic_access(fwrt->trans, &flags); 117 } 118 119 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 120 struct iwl_fw_error_dump_data **dump_data, 121 int size, u32 offset, int fifo_num) 122 { 123 struct iwl_fw_error_dump_fifo *fifo_hdr; 124 u32 *fifo_data; 125 u32 fifo_len; 126 int i; 127 128 fifo_hdr = (void *)(*dump_data)->data; 129 fifo_data = (void *)fifo_hdr->data; 130 fifo_len = size; 131 132 /* No need to try to read the data if the length is 0 */ 133 if (fifo_len == 0) 134 return; 135 136 /* Add a TLV for the RXF */ 137 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 138 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 139 140 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 141 fifo_hdr->available_bytes = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 RXF_RD_D_SPACE + offset)); 144 fifo_hdr->wr_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 RXF_RD_WR_PTR + offset)); 147 fifo_hdr->rd_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 RXF_RD_RD_PTR + offset)); 150 fifo_hdr->fence_ptr = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 RXF_RD_FENCE_PTR + offset)); 153 fifo_hdr->fence_mode = 154 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 155 RXF_SET_FENCE_MODE + offset)); 156 157 /* Lock fence */ 158 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 159 /* Set fence pointer to the same place like WR pointer */ 160 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 161 /* Set fence offset */ 162 iwl_trans_write_prph(fwrt->trans, 163 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 164 165 /* Read FIFO */ 166 fifo_len /= sizeof(u32); /* Size in DWORDS */ 167 for (i = 0; i < fifo_len; i++) 168 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 169 RXF_FIFO_RD_FENCE_INC + 170 offset); 171 *dump_data = iwl_fw_error_next_data(*dump_data); 172 } 173 174 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 175 struct iwl_fw_error_dump_data **dump_data, 176 int size, u32 offset, int fifo_num) 177 { 178 struct iwl_fw_error_dump_fifo *fifo_hdr; 179 u32 *fifo_data; 180 u32 fifo_len; 181 int i; 182 183 fifo_hdr = (void *)(*dump_data)->data; 184 fifo_data = (void *)fifo_hdr->data; 185 fifo_len = size; 186 187 /* No need to try to read the data if the length is 0 */ 188 if (fifo_len == 0) 189 return; 190 191 /* Add a TLV for the FIFO */ 192 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 193 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 194 195 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 196 fifo_hdr->available_bytes = 197 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 198 TXF_FIFO_ITEM_CNT + offset)); 199 fifo_hdr->wr_ptr = 200 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 201 TXF_WR_PTR + offset)); 202 fifo_hdr->rd_ptr = 203 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 204 TXF_RD_PTR + offset)); 205 fifo_hdr->fence_ptr = 206 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 207 TXF_FENCE_PTR + offset)); 208 fifo_hdr->fence_mode = 209 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 210 TXF_LOCK_FENCE + offset)); 211 212 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 213 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 214 TXF_WR_PTR + offset); 215 216 /* Dummy-read to advance the read pointer to the head */ 217 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 218 219 /* Read FIFO */ 220 fifo_len /= sizeof(u32); /* Size in DWORDS */ 221 for (i = 0; i < fifo_len; i++) 222 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 223 TXF_READ_MODIFY_DATA + 224 offset); 225 *dump_data = iwl_fw_error_next_data(*dump_data); 226 } 227 228 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 229 struct iwl_fw_error_dump_data **dump_data) 230 { 231 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 232 unsigned long flags; 233 234 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 235 236 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 237 return; 238 239 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 240 /* Pull RXF1 */ 241 iwl_fwrt_dump_rxf(fwrt, dump_data, 242 cfg->lmac[0].rxfifo1_size, 0, 0); 243 /* Pull RXF2 */ 244 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 245 RXF_DIFF_FROM_PREV + 246 fwrt->trans->cfg->umac_prph_offset, 1); 247 /* Pull LMAC2 RXF1 */ 248 if (fwrt->smem_cfg.num_lmacs > 1) 249 iwl_fwrt_dump_rxf(fwrt, dump_data, 250 cfg->lmac[1].rxfifo1_size, 251 LMAC2_PRPH_OFFSET, 2); 252 } 253 254 iwl_trans_release_nic_access(fwrt->trans, &flags); 255 } 256 257 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 258 struct iwl_fw_error_dump_data **dump_data) 259 { 260 struct iwl_fw_error_dump_fifo *fifo_hdr; 261 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 262 u32 *fifo_data; 263 u32 fifo_len; 264 unsigned long flags; 265 int i, j; 266 267 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 268 269 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 270 return; 271 272 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 273 /* Pull TXF data from LMAC1 */ 274 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 275 /* Mark the number of TXF we're pulling now */ 276 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 277 iwl_fwrt_dump_txf(fwrt, dump_data, 278 cfg->lmac[0].txfifo_size[i], 0, i); 279 } 280 281 /* Pull TXF data from LMAC2 */ 282 if (fwrt->smem_cfg.num_lmacs > 1) { 283 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 284 i++) { 285 /* Mark the number of TXF we're pulling now */ 286 iwl_trans_write_prph(fwrt->trans, 287 TXF_LARC_NUM + 288 LMAC2_PRPH_OFFSET, i); 289 iwl_fwrt_dump_txf(fwrt, dump_data, 290 cfg->lmac[1].txfifo_size[i], 291 LMAC2_PRPH_OFFSET, 292 i + cfg->num_txfifo_entries); 293 } 294 } 295 } 296 297 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 298 fw_has_capa(&fwrt->fw->ucode_capa, 299 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 300 /* Pull UMAC internal TXF data from all TXFs */ 301 for (i = 0; 302 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 303 i++) { 304 fifo_hdr = (void *)(*dump_data)->data; 305 fifo_data = (void *)fifo_hdr->data; 306 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 307 308 /* No need to try to read the data if the length is 0 */ 309 if (fifo_len == 0) 310 continue; 311 312 /* Add a TLV for the internal FIFOs */ 313 (*dump_data)->type = 314 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 315 (*dump_data)->len = 316 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 317 318 fifo_hdr->fifo_num = cpu_to_le32(i); 319 320 /* Mark the number of TXF we're pulling now */ 321 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 322 fwrt->smem_cfg.num_txfifo_entries); 323 324 fifo_hdr->available_bytes = 325 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 326 TXF_CPU2_FIFO_ITEM_CNT)); 327 fifo_hdr->wr_ptr = 328 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 329 TXF_CPU2_WR_PTR)); 330 fifo_hdr->rd_ptr = 331 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 332 TXF_CPU2_RD_PTR)); 333 fifo_hdr->fence_ptr = 334 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 335 TXF_CPU2_FENCE_PTR)); 336 fifo_hdr->fence_mode = 337 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 338 TXF_CPU2_LOCK_FENCE)); 339 340 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 341 iwl_trans_write_prph(fwrt->trans, 342 TXF_CPU2_READ_MODIFY_ADDR, 343 TXF_CPU2_WR_PTR); 344 345 /* Dummy-read to advance the read pointer to head */ 346 iwl_trans_read_prph(fwrt->trans, 347 TXF_CPU2_READ_MODIFY_DATA); 348 349 /* Read FIFO */ 350 fifo_len /= sizeof(u32); /* Size in DWORDS */ 351 for (j = 0; j < fifo_len; j++) 352 fifo_data[j] = 353 iwl_trans_read_prph(fwrt->trans, 354 TXF_CPU2_READ_MODIFY_DATA); 355 *dump_data = iwl_fw_error_next_data(*dump_data); 356 } 357 } 358 359 iwl_trans_release_nic_access(fwrt->trans, &flags); 360 } 361 362 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ 363 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ 364 365 struct iwl_prph_range { 366 u32 start, end; 367 }; 368 369 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 370 { .start = 0x00a00000, .end = 0x00a00000 }, 371 { .start = 0x00a0000c, .end = 0x00a00024 }, 372 { .start = 0x00a0002c, .end = 0x00a0003c }, 373 { .start = 0x00a00410, .end = 0x00a00418 }, 374 { .start = 0x00a00420, .end = 0x00a00420 }, 375 { .start = 0x00a00428, .end = 0x00a00428 }, 376 { .start = 0x00a00430, .end = 0x00a0043c }, 377 { .start = 0x00a00444, .end = 0x00a00444 }, 378 { .start = 0x00a004c0, .end = 0x00a004cc }, 379 { .start = 0x00a004d8, .end = 0x00a004d8 }, 380 { .start = 0x00a004e0, .end = 0x00a004f0 }, 381 { .start = 0x00a00840, .end = 0x00a00840 }, 382 { .start = 0x00a00850, .end = 0x00a00858 }, 383 { .start = 0x00a01004, .end = 0x00a01008 }, 384 { .start = 0x00a01010, .end = 0x00a01010 }, 385 { .start = 0x00a01018, .end = 0x00a01018 }, 386 { .start = 0x00a01024, .end = 0x00a01024 }, 387 { .start = 0x00a0102c, .end = 0x00a01034 }, 388 { .start = 0x00a0103c, .end = 0x00a01040 }, 389 { .start = 0x00a01048, .end = 0x00a01094 }, 390 { .start = 0x00a01c00, .end = 0x00a01c20 }, 391 { .start = 0x00a01c58, .end = 0x00a01c58 }, 392 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 393 { .start = 0x00a01c28, .end = 0x00a01c54 }, 394 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 395 { .start = 0x00a01c60, .end = 0x00a01cdc }, 396 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 397 { .start = 0x00a01d18, .end = 0x00a01d20 }, 398 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 399 { .start = 0x00a01d40, .end = 0x00a01d5c }, 400 { .start = 0x00a01d80, .end = 0x00a01d80 }, 401 { .start = 0x00a01d98, .end = 0x00a01d9c }, 402 { .start = 0x00a01da8, .end = 0x00a01da8 }, 403 { .start = 0x00a01db8, .end = 0x00a01df4 }, 404 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 405 { .start = 0x00a01e00, .end = 0x00a01e2c }, 406 { .start = 0x00a01e40, .end = 0x00a01e60 }, 407 { .start = 0x00a01e68, .end = 0x00a01e6c }, 408 { .start = 0x00a01e74, .end = 0x00a01e74 }, 409 { .start = 0x00a01e84, .end = 0x00a01e90 }, 410 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 411 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 412 { .start = 0x00a01f00, .end = 0x00a01f1c }, 413 { .start = 0x00a01f44, .end = 0x00a01ffc }, 414 { .start = 0x00a02000, .end = 0x00a02048 }, 415 { .start = 0x00a02068, .end = 0x00a020f0 }, 416 { .start = 0x00a02100, .end = 0x00a02118 }, 417 { .start = 0x00a02140, .end = 0x00a0214c }, 418 { .start = 0x00a02168, .end = 0x00a0218c }, 419 { .start = 0x00a021c0, .end = 0x00a021c0 }, 420 { .start = 0x00a02400, .end = 0x00a02410 }, 421 { .start = 0x00a02418, .end = 0x00a02420 }, 422 { .start = 0x00a02428, .end = 0x00a0242c }, 423 { .start = 0x00a02434, .end = 0x00a02434 }, 424 { .start = 0x00a02440, .end = 0x00a02460 }, 425 { .start = 0x00a02468, .end = 0x00a024b0 }, 426 { .start = 0x00a024c8, .end = 0x00a024cc }, 427 { .start = 0x00a02500, .end = 0x00a02504 }, 428 { .start = 0x00a0250c, .end = 0x00a02510 }, 429 { .start = 0x00a02540, .end = 0x00a02554 }, 430 { .start = 0x00a02580, .end = 0x00a025f4 }, 431 { .start = 0x00a02600, .end = 0x00a0260c }, 432 { .start = 0x00a02648, .end = 0x00a02650 }, 433 { .start = 0x00a02680, .end = 0x00a02680 }, 434 { .start = 0x00a026c0, .end = 0x00a026d0 }, 435 { .start = 0x00a02700, .end = 0x00a0270c }, 436 { .start = 0x00a02804, .end = 0x00a02804 }, 437 { .start = 0x00a02818, .end = 0x00a0281c }, 438 { .start = 0x00a02c00, .end = 0x00a02db4 }, 439 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 440 { .start = 0x00a03000, .end = 0x00a03014 }, 441 { .start = 0x00a0301c, .end = 0x00a0302c }, 442 { .start = 0x00a03034, .end = 0x00a03038 }, 443 { .start = 0x00a03040, .end = 0x00a03048 }, 444 { .start = 0x00a03060, .end = 0x00a03068 }, 445 { .start = 0x00a03070, .end = 0x00a03074 }, 446 { .start = 0x00a0307c, .end = 0x00a0307c }, 447 { .start = 0x00a03080, .end = 0x00a03084 }, 448 { .start = 0x00a0308c, .end = 0x00a03090 }, 449 { .start = 0x00a03098, .end = 0x00a03098 }, 450 { .start = 0x00a030a0, .end = 0x00a030a0 }, 451 { .start = 0x00a030a8, .end = 0x00a030b4 }, 452 { .start = 0x00a030bc, .end = 0x00a030bc }, 453 { .start = 0x00a030c0, .end = 0x00a0312c }, 454 { .start = 0x00a03c00, .end = 0x00a03c5c }, 455 { .start = 0x00a04400, .end = 0x00a04454 }, 456 { .start = 0x00a04460, .end = 0x00a04474 }, 457 { .start = 0x00a044c0, .end = 0x00a044ec }, 458 { .start = 0x00a04500, .end = 0x00a04504 }, 459 { .start = 0x00a04510, .end = 0x00a04538 }, 460 { .start = 0x00a04540, .end = 0x00a04548 }, 461 { .start = 0x00a04560, .end = 0x00a0457c }, 462 { .start = 0x00a04590, .end = 0x00a04598 }, 463 { .start = 0x00a045c0, .end = 0x00a045f4 }, 464 }; 465 466 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 467 { .start = 0x00a05c00, .end = 0x00a05c18 }, 468 { .start = 0x00a05400, .end = 0x00a056e8 }, 469 { .start = 0x00a08000, .end = 0x00a098bc }, 470 { .start = 0x00a02400, .end = 0x00a02758 }, 471 }; 472 473 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 474 { .start = 0x00a00000, .end = 0x00a00000 }, 475 { .start = 0x00a0000c, .end = 0x00a00024 }, 476 { .start = 0x00a0002c, .end = 0x00a00034 }, 477 { .start = 0x00a0003c, .end = 0x00a0003c }, 478 { .start = 0x00a00410, .end = 0x00a00418 }, 479 { .start = 0x00a00420, .end = 0x00a00420 }, 480 { .start = 0x00a00428, .end = 0x00a00428 }, 481 { .start = 0x00a00430, .end = 0x00a0043c }, 482 { .start = 0x00a00444, .end = 0x00a00444 }, 483 { .start = 0x00a00840, .end = 0x00a00840 }, 484 { .start = 0x00a00850, .end = 0x00a00858 }, 485 { .start = 0x00a01004, .end = 0x00a01008 }, 486 { .start = 0x00a01010, .end = 0x00a01010 }, 487 { .start = 0x00a01018, .end = 0x00a01018 }, 488 { .start = 0x00a01024, .end = 0x00a01024 }, 489 { .start = 0x00a0102c, .end = 0x00a01034 }, 490 { .start = 0x00a0103c, .end = 0x00a01040 }, 491 { .start = 0x00a01048, .end = 0x00a01050 }, 492 { .start = 0x00a01058, .end = 0x00a01058 }, 493 { .start = 0x00a01060, .end = 0x00a01070 }, 494 { .start = 0x00a0108c, .end = 0x00a0108c }, 495 { .start = 0x00a01c20, .end = 0x00a01c28 }, 496 { .start = 0x00a01d10, .end = 0x00a01d10 }, 497 { .start = 0x00a01e28, .end = 0x00a01e2c }, 498 { .start = 0x00a01e60, .end = 0x00a01e60 }, 499 { .start = 0x00a01e80, .end = 0x00a01e80 }, 500 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 501 { .start = 0x00a02000, .end = 0x00a0201c }, 502 { .start = 0x00a02024, .end = 0x00a02024 }, 503 { .start = 0x00a02040, .end = 0x00a02048 }, 504 { .start = 0x00a020c0, .end = 0x00a020e0 }, 505 { .start = 0x00a02400, .end = 0x00a02404 }, 506 { .start = 0x00a0240c, .end = 0x00a02414 }, 507 { .start = 0x00a0241c, .end = 0x00a0243c }, 508 { .start = 0x00a02448, .end = 0x00a024bc }, 509 { .start = 0x00a024c4, .end = 0x00a024cc }, 510 { .start = 0x00a02508, .end = 0x00a02508 }, 511 { .start = 0x00a02510, .end = 0x00a02514 }, 512 { .start = 0x00a0251c, .end = 0x00a0251c }, 513 { .start = 0x00a0252c, .end = 0x00a0255c }, 514 { .start = 0x00a02564, .end = 0x00a025a0 }, 515 { .start = 0x00a025a8, .end = 0x00a025b4 }, 516 { .start = 0x00a025c0, .end = 0x00a025c0 }, 517 { .start = 0x00a025e8, .end = 0x00a025f4 }, 518 { .start = 0x00a02c08, .end = 0x00a02c18 }, 519 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 520 { .start = 0x00a02c68, .end = 0x00a02c78 }, 521 { .start = 0x00a03000, .end = 0x00a03000 }, 522 { .start = 0x00a03010, .end = 0x00a03014 }, 523 { .start = 0x00a0301c, .end = 0x00a0302c }, 524 { .start = 0x00a03034, .end = 0x00a03038 }, 525 { .start = 0x00a03040, .end = 0x00a03044 }, 526 { .start = 0x00a03060, .end = 0x00a03068 }, 527 { .start = 0x00a03070, .end = 0x00a03070 }, 528 { .start = 0x00a0307c, .end = 0x00a03084 }, 529 { .start = 0x00a0308c, .end = 0x00a03090 }, 530 { .start = 0x00a03098, .end = 0x00a03098 }, 531 { .start = 0x00a030a0, .end = 0x00a030a0 }, 532 { .start = 0x00a030a8, .end = 0x00a030b4 }, 533 { .start = 0x00a030bc, .end = 0x00a030c0 }, 534 { .start = 0x00a030c8, .end = 0x00a030f4 }, 535 { .start = 0x00a03100, .end = 0x00a0312c }, 536 { .start = 0x00a03c00, .end = 0x00a03c5c }, 537 { .start = 0x00a04400, .end = 0x00a04454 }, 538 { .start = 0x00a04460, .end = 0x00a04474 }, 539 { .start = 0x00a044c0, .end = 0x00a044ec }, 540 { .start = 0x00a04500, .end = 0x00a04504 }, 541 { .start = 0x00a04510, .end = 0x00a04538 }, 542 { .start = 0x00a04540, .end = 0x00a04548 }, 543 { .start = 0x00a04560, .end = 0x00a04560 }, 544 { .start = 0x00a04570, .end = 0x00a0457c }, 545 { .start = 0x00a04590, .end = 0x00a04590 }, 546 { .start = 0x00a04598, .end = 0x00a04598 }, 547 { .start = 0x00a045c0, .end = 0x00a045f4 }, 548 { .start = 0x00a0c000, .end = 0x00a0c018 }, 549 { .start = 0x00a0c020, .end = 0x00a0c028 }, 550 { .start = 0x00a0c038, .end = 0x00a0c094 }, 551 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 552 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 553 { .start = 0x00a0c150, .end = 0x00a0c174 }, 554 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 555 { .start = 0x00a0c190, .end = 0x00a0c198 }, 556 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 557 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 558 }; 559 560 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 561 u32 len_bytes, __le32 *data) 562 { 563 u32 i; 564 565 for (i = 0; i < len_bytes; i += 4) 566 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 567 } 568 569 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 570 const struct iwl_prph_range *iwl_prph_dump_addr, 571 u32 range_len, void *ptr) 572 { 573 struct iwl_fw_error_dump_prph *prph; 574 struct iwl_trans *trans = fwrt->trans; 575 struct iwl_fw_error_dump_data **data = 576 (struct iwl_fw_error_dump_data **)ptr; 577 unsigned long flags; 578 u32 i; 579 580 if (!data) 581 return; 582 583 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 584 585 if (!iwl_trans_grab_nic_access(trans, &flags)) 586 return; 587 588 for (i = 0; i < range_len; i++) { 589 /* The range includes both boundaries */ 590 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 591 iwl_prph_dump_addr[i].start + 4; 592 593 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 594 (*data)->len = cpu_to_le32(sizeof(*prph) + 595 num_bytes_in_chunk); 596 prph = (void *)(*data)->data; 597 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 598 599 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 600 /* our range is inclusive, hence + 4 */ 601 iwl_prph_dump_addr[i].end - 602 iwl_prph_dump_addr[i].start + 4, 603 (void *)prph->data); 604 605 *data = iwl_fw_error_next_data(*data); 606 } 607 608 iwl_trans_release_nic_access(trans, &flags); 609 } 610 611 /* 612 * alloc_sgtable - allocates scallerlist table in the given size, 613 * fills it with pages and returns it 614 * @size: the size (in bytes) of the table 615 */ 616 static struct scatterlist *alloc_sgtable(int size) 617 { 618 int alloc_size, nents, i; 619 struct page *new_page; 620 struct scatterlist *iter; 621 struct scatterlist *table; 622 623 nents = DIV_ROUND_UP(size, PAGE_SIZE); 624 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 625 if (!table) 626 return NULL; 627 sg_init_table(table, nents); 628 iter = table; 629 for_each_sg(table, iter, sg_nents(table), i) { 630 new_page = alloc_page(GFP_KERNEL); 631 if (!new_page) { 632 /* release all previous allocated pages in the table */ 633 iter = table; 634 for_each_sg(table, iter, sg_nents(table), i) { 635 new_page = sg_page(iter); 636 if (new_page) 637 __free_page(new_page); 638 } 639 return NULL; 640 } 641 alloc_size = min_t(int, size, PAGE_SIZE); 642 size -= PAGE_SIZE; 643 sg_set_page(iter, new_page, alloc_size, 0); 644 } 645 return table; 646 } 647 648 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 649 const struct iwl_prph_range *iwl_prph_dump_addr, 650 u32 range_len, void *ptr) 651 { 652 u32 *prph_len = (u32 *)ptr; 653 int i, num_bytes_in_chunk; 654 655 if (!prph_len) 656 return; 657 658 for (i = 0; i < range_len; i++) { 659 /* The range includes both boundaries */ 660 num_bytes_in_chunk = 661 iwl_prph_dump_addr[i].end - 662 iwl_prph_dump_addr[i].start + 4; 663 664 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 665 sizeof(struct iwl_fw_error_dump_prph) + 666 num_bytes_in_chunk; 667 } 668 } 669 670 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 671 void (*handler)(struct iwl_fw_runtime *, 672 const struct iwl_prph_range *, 673 u32, void *)) 674 { 675 u32 range_len; 676 677 if (fwrt->trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 678 /* TODO */ 679 } else if (fwrt->trans->cfg->device_family >= IWL_DEVICE_FAMILY_22000) { 680 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 681 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 682 } else { 683 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 684 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 685 686 if (fwrt->trans->cfg->mq_rx_supported) { 687 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 688 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 689 } 690 } 691 } 692 693 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 694 struct iwl_fw_error_dump_data **dump_data, 695 u32 len, u32 ofs, u32 type) 696 { 697 struct iwl_fw_error_dump_mem *dump_mem; 698 699 if (!len) 700 return; 701 702 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 703 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 704 dump_mem = (void *)(*dump_data)->data; 705 dump_mem->type = cpu_to_le32(type); 706 dump_mem->offset = cpu_to_le32(ofs); 707 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 708 *dump_data = iwl_fw_error_next_data(*dump_data); 709 710 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 711 } 712 713 #define ADD_LEN(len, item_len, const_len) \ 714 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 715 while (0) 716 717 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 718 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 719 { 720 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 721 sizeof(struct iwl_fw_error_dump_fifo); 722 u32 fifo_len = 0; 723 int i; 724 725 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 726 return 0; 727 728 /* Count RXF2 size */ 729 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 730 731 /* Count RXF1 sizes */ 732 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 733 mem_cfg->num_lmacs = MAX_NUM_LMAC; 734 735 for (i = 0; i < mem_cfg->num_lmacs; i++) 736 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 737 738 return fifo_len; 739 } 740 741 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 742 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 743 { 744 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 745 sizeof(struct iwl_fw_error_dump_fifo); 746 u32 fifo_len = 0; 747 int i; 748 749 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 750 goto dump_internal_txf; 751 752 /* Count TXF sizes */ 753 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 754 mem_cfg->num_lmacs = MAX_NUM_LMAC; 755 756 for (i = 0; i < mem_cfg->num_lmacs; i++) { 757 int j; 758 759 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 760 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 761 hdr_len); 762 } 763 764 dump_internal_txf: 765 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 766 fw_has_capa(&fwrt->fw->ucode_capa, 767 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 768 goto out; 769 770 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 771 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 772 773 out: 774 return fifo_len; 775 } 776 777 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 778 struct iwl_fw_error_dump_data **data) 779 { 780 int i; 781 782 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 783 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 784 struct iwl_fw_error_dump_paging *paging; 785 struct page *pages = 786 fwrt->fw_paging_db[i].fw_paging_block; 787 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 788 789 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 790 (*data)->len = cpu_to_le32(sizeof(*paging) + 791 PAGING_BLOCK_SIZE); 792 paging = (void *)(*data)->data; 793 paging->index = cpu_to_le32(i); 794 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 795 PAGING_BLOCK_SIZE, 796 DMA_BIDIRECTIONAL); 797 memcpy(paging->data, page_address(pages), 798 PAGING_BLOCK_SIZE); 799 dma_sync_single_for_device(fwrt->trans->dev, addr, 800 PAGING_BLOCK_SIZE, 801 DMA_BIDIRECTIONAL); 802 (*data) = iwl_fw_error_next_data(*data); 803 } 804 } 805 806 static struct iwl_fw_error_dump_file * 807 _iwl_fw_error_dump(struct iwl_fw_runtime *fwrt, 808 struct iwl_fw_dump_ptrs *fw_error_dump) 809 { 810 struct iwl_fw_error_dump_file *dump_file; 811 struct iwl_fw_error_dump_data *dump_data; 812 struct iwl_fw_error_dump_info *dump_info; 813 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 814 struct iwl_fw_error_dump_trigger_desc *dump_trig; 815 u32 sram_len, sram_ofs; 816 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 817 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 818 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 819 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 820 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 821 0 : fwrt->trans->cfg->dccm2_len; 822 int i; 823 824 /* SRAM - include stack CCM if driver knows the values for it */ 825 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 826 const struct fw_img *img; 827 828 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 829 return NULL; 830 img = &fwrt->fw->img[fwrt->cur_fw_img]; 831 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 832 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 833 } else { 834 sram_ofs = fwrt->trans->cfg->dccm_offset; 835 sram_len = fwrt->trans->cfg->dccm_len; 836 } 837 838 /* reading RXF/TXF sizes */ 839 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 840 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 841 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 842 843 /* Make room for PRPH registers */ 844 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 845 iwl_fw_prph_handler(fwrt, &prph_len, 846 iwl_fw_get_prph_len); 847 848 if (fwrt->trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 && 849 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 850 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 851 } 852 853 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 854 855 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 856 file_len += sizeof(*dump_data) + sizeof(*dump_info); 857 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 858 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 859 860 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 861 size_t hdr_len = sizeof(*dump_data) + 862 sizeof(struct iwl_fw_error_dump_mem); 863 864 /* Dump SRAM only if no mem_tlvs */ 865 if (!fwrt->fw->dbg.n_mem_tlv) 866 ADD_LEN(file_len, sram_len, hdr_len); 867 868 /* Make room for all mem types that exist */ 869 ADD_LEN(file_len, smem_len, hdr_len); 870 ADD_LEN(file_len, sram2_len, hdr_len); 871 872 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 873 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 874 } 875 876 /* Make room for fw's virtual image pages, if it exists */ 877 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 878 file_len += fwrt->num_of_paging_blk * 879 (sizeof(*dump_data) + 880 sizeof(struct iwl_fw_error_dump_paging) + 881 PAGING_BLOCK_SIZE); 882 883 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 884 file_len += sizeof(*dump_data) + 885 fwrt->trans->cfg->d3_debug_data_length * 2; 886 } 887 888 /* If we only want a monitor dump, reset the file length */ 889 if (fwrt->dump.monitor_only) { 890 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 891 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 892 } 893 894 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 895 fwrt->dump.desc) 896 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 897 fwrt->dump.desc->len; 898 899 dump_file = vzalloc(file_len); 900 if (!dump_file) 901 return NULL; 902 903 fw_error_dump->fwrt_ptr = dump_file; 904 905 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 906 dump_data = (void *)dump_file->data; 907 908 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 909 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 910 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 911 dump_info = (void *)dump_data->data; 912 dump_info->device_family = 913 fwrt->trans->cfg->device_family == 914 IWL_DEVICE_FAMILY_7000 ? 915 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_7) : 916 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_8); 917 dump_info->hw_step = 918 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 919 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 920 sizeof(dump_info->fw_human_readable)); 921 strncpy(dump_info->dev_human_readable, fwrt->trans->cfg->name, 922 sizeof(dump_info->dev_human_readable) - 1); 923 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 924 sizeof(dump_info->bus_human_readable) - 1); 925 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 926 dump_info->lmac_err_id[0] = 927 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 928 if (fwrt->smem_cfg.num_lmacs > 1) 929 dump_info->lmac_err_id[1] = 930 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 931 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 932 933 dump_data = iwl_fw_error_next_data(dump_data); 934 } 935 936 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 937 /* Dump shared memory configuration */ 938 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 939 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 940 dump_smem_cfg = (void *)dump_data->data; 941 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 942 dump_smem_cfg->num_txfifo_entries = 943 cpu_to_le32(mem_cfg->num_txfifo_entries); 944 for (i = 0; i < MAX_NUM_LMAC; i++) { 945 int j; 946 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 947 948 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 949 dump_smem_cfg->lmac[i].txfifo_size[j] = 950 cpu_to_le32(txf_size[j]); 951 dump_smem_cfg->lmac[i].rxfifo1_size = 952 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 953 } 954 dump_smem_cfg->rxfifo2_size = 955 cpu_to_le32(mem_cfg->rxfifo2_size); 956 dump_smem_cfg->internal_txfifo_addr = 957 cpu_to_le32(mem_cfg->internal_txfifo_addr); 958 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 959 dump_smem_cfg->internal_txfifo_size[i] = 960 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 961 } 962 963 dump_data = iwl_fw_error_next_data(dump_data); 964 } 965 966 /* We only dump the FIFOs if the FW is in error state */ 967 if (fifo_len) { 968 iwl_fw_dump_rxf(fwrt, &dump_data); 969 iwl_fw_dump_txf(fwrt, &dump_data); 970 if (radio_len) 971 iwl_read_radio_regs(fwrt, &dump_data); 972 } 973 974 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 975 fwrt->dump.desc) { 976 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 977 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 978 fwrt->dump.desc->len); 979 dump_trig = (void *)dump_data->data; 980 memcpy(dump_trig, &fwrt->dump.desc->trig_desc, 981 sizeof(*dump_trig) + fwrt->dump.desc->len); 982 983 dump_data = iwl_fw_error_next_data(dump_data); 984 } 985 986 /* In case we only want monitor dump, skip to dump trasport data */ 987 if (fwrt->dump.monitor_only) 988 goto out; 989 990 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 991 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 992 fwrt->fw->dbg.mem_tlv; 993 994 if (!fwrt->fw->dbg.n_mem_tlv) 995 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 996 IWL_FW_ERROR_DUMP_MEM_SRAM); 997 998 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 999 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 1000 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 1001 1002 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 1003 le32_to_cpu(fw_dbg_mem[i].data_type)); 1004 } 1005 1006 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 1007 fwrt->trans->cfg->smem_offset, 1008 IWL_FW_ERROR_DUMP_MEM_SMEM); 1009 1010 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 1011 fwrt->trans->cfg->dccm2_offset, 1012 IWL_FW_ERROR_DUMP_MEM_SRAM); 1013 } 1014 1015 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 1016 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 1017 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 1018 1019 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 1020 dump_data->len = cpu_to_le32(data_size * 2); 1021 1022 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 1023 1024 kfree(fwrt->dump.d3_debug_data); 1025 fwrt->dump.d3_debug_data = NULL; 1026 1027 iwl_trans_read_mem_bytes(fwrt->trans, addr, 1028 dump_data->data + data_size, 1029 data_size); 1030 1031 dump_data = iwl_fw_error_next_data(dump_data); 1032 } 1033 1034 /* Dump fw's virtual image */ 1035 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1036 iwl_dump_paging(fwrt, &dump_data); 1037 1038 if (prph_len) 1039 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1040 1041 out: 1042 dump_file->file_len = cpu_to_le32(file_len); 1043 return dump_file; 1044 } 1045 1046 static int iwl_dump_ini_prph_iter(struct iwl_fw_runtime *fwrt, 1047 struct iwl_fw_ini_region_cfg *reg, 1048 void *range_ptr, int idx) 1049 { 1050 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1051 __le32 *val = range->data; 1052 u32 addr, prph_val, offset = le32_to_cpu(reg->offset); 1053 int i; 1054 1055 range->start_addr = reg->start_addr[idx]; 1056 range->range_data_size = reg->internal.range_data_size; 1057 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) { 1058 addr = le32_to_cpu(range->start_addr) + i; 1059 prph_val = iwl_read_prph(fwrt->trans, addr + offset); 1060 if (prph_val == 0x5a5a5a5a) 1061 return -EBUSY; 1062 *val++ = cpu_to_le32(prph_val); 1063 } 1064 1065 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1066 } 1067 1068 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1069 struct iwl_fw_ini_region_cfg *reg, 1070 void *range_ptr, int idx) 1071 { 1072 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1073 __le32 *val = range->data; 1074 u32 addr, offset = le32_to_cpu(reg->offset); 1075 int i; 1076 1077 range->start_addr = reg->start_addr[idx]; 1078 range->range_data_size = reg->internal.range_data_size; 1079 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) { 1080 addr = le32_to_cpu(range->start_addr) + i; 1081 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, 1082 addr + offset)); 1083 } 1084 1085 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1086 } 1087 1088 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1089 struct iwl_fw_ini_region_cfg *reg, 1090 void *range_ptr, int idx) 1091 { 1092 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1093 u32 addr = le32_to_cpu(range->start_addr); 1094 u32 offset = le32_to_cpu(reg->offset); 1095 1096 range->start_addr = reg->start_addr[idx]; 1097 range->range_data_size = reg->internal.range_data_size; 1098 iwl_trans_read_mem_bytes(fwrt->trans, addr + offset, range->data, 1099 le32_to_cpu(reg->internal.range_data_size)); 1100 1101 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1102 } 1103 1104 static int 1105 iwl_dump_ini_paging_gen2_iter(struct iwl_fw_runtime *fwrt, 1106 struct iwl_fw_ini_region_cfg *reg, 1107 void *range_ptr, int idx) 1108 { 1109 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1110 u32 page_size = fwrt->trans->init_dram.paging[idx].size; 1111 1112 range->start_addr = cpu_to_le32(idx); 1113 range->range_data_size = cpu_to_le32(page_size); 1114 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1115 page_size); 1116 1117 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1118 } 1119 1120 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1121 struct iwl_fw_ini_region_cfg *reg, 1122 void *range_ptr, int idx) 1123 { 1124 /* increase idx by 1 since the pages are from 1 to 1125 * fwrt->num_of_paging_blk + 1 1126 */ 1127 struct page *page = fwrt->fw_paging_db[++idx].fw_paging_block; 1128 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1129 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1130 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1131 1132 range->start_addr = cpu_to_le32(idx); 1133 range->range_data_size = cpu_to_le32(page_size); 1134 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1135 DMA_BIDIRECTIONAL); 1136 memcpy(range->data, page_address(page), page_size); 1137 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1138 DMA_BIDIRECTIONAL); 1139 1140 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1141 } 1142 1143 static int 1144 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1145 struct iwl_fw_ini_region_cfg *reg, void *range_ptr, 1146 int idx) 1147 { 1148 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1149 u32 start_addr = iwl_read_umac_prph(fwrt->trans, 1150 MON_BUFF_BASE_ADDR_VER2); 1151 1152 if (start_addr == 0x5a5a5a5a) 1153 return -EBUSY; 1154 1155 range->start_addr = cpu_to_le32(start_addr); 1156 range->range_data_size = cpu_to_le32(fwrt->trans->fw_mon[idx].size); 1157 1158 memcpy(range->data, fwrt->trans->fw_mon[idx].block, 1159 fwrt->trans->fw_mon[idx].size); 1160 1161 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1162 } 1163 1164 struct iwl_ini_txf_iter_data { 1165 int fifo; 1166 int lmac; 1167 u32 fifo_size; 1168 bool internal_txf; 1169 bool init; 1170 }; 1171 1172 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1173 struct iwl_fw_ini_region_cfg *reg) 1174 { 1175 struct iwl_ini_txf_iter_data *iter = fwrt->dump.fifo_iter; 1176 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1177 int txf_num = cfg->num_txfifo_entries; 1178 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1179 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid1); 1180 1181 if (!iter) 1182 return false; 1183 1184 if (iter->init) { 1185 if (le32_to_cpu(reg->offset) && 1186 WARN_ONCE(cfg->num_lmacs == 1, 1187 "Invalid lmac offset: 0x%x\n", 1188 le32_to_cpu(reg->offset))) 1189 return false; 1190 1191 iter->init = false; 1192 iter->internal_txf = false; 1193 iter->fifo_size = 0; 1194 iter->fifo = -1; 1195 if (le32_to_cpu(reg->offset)) 1196 iter->lmac = 1; 1197 else 1198 iter->lmac = 0; 1199 } 1200 1201 if (!iter->internal_txf) 1202 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1203 iter->fifo_size = 1204 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1205 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1206 return true; 1207 } 1208 1209 iter->internal_txf = true; 1210 1211 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1212 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1213 return false; 1214 1215 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1216 iter->fifo_size = 1217 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1218 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1219 return true; 1220 } 1221 1222 return false; 1223 } 1224 1225 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1226 struct iwl_fw_ini_region_cfg *reg, 1227 void *range_ptr, int idx) 1228 { 1229 struct iwl_fw_ini_fifo_error_dump_range *range = range_ptr; 1230 struct iwl_ini_txf_iter_data *iter; 1231 u32 offs = le32_to_cpu(reg->offset), addr; 1232 u32 registers_size = 1233 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(__le32); 1234 __le32 *val = range->data; 1235 unsigned long flags; 1236 int i; 1237 1238 if (!iwl_ini_txf_iter(fwrt, reg)) 1239 return -EIO; 1240 1241 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1242 return -EBUSY; 1243 1244 iter = fwrt->dump.fifo_iter; 1245 1246 range->fifo_num = cpu_to_le32(iter->fifo); 1247 range->num_of_registers = reg->fifos.num_of_registers; 1248 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1249 1250 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1251 1252 /* read txf registers */ 1253 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { 1254 addr = le32_to_cpu(reg->start_addr[i]) + offs; 1255 1256 *val++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1257 } 1258 1259 if (reg->fifos.header_only) { 1260 range->range_data_size = cpu_to_le32(registers_size); 1261 goto out; 1262 } 1263 1264 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1265 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1266 TXF_WR_PTR + offs); 1267 1268 /* Dummy-read to advance the read pointer to the head */ 1269 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1270 1271 /* Read FIFO */ 1272 addr = TXF_READ_MODIFY_DATA + offs; 1273 for (i = 0; i < iter->fifo_size; i += sizeof(__le32)) 1274 *val++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1275 1276 out: 1277 iwl_trans_release_nic_access(fwrt->trans, &flags); 1278 1279 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1280 } 1281 1282 struct iwl_ini_rxf_data { 1283 u32 fifo_num; 1284 u32 size; 1285 u32 offset; 1286 }; 1287 1288 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1289 struct iwl_fw_ini_region_cfg *reg, 1290 struct iwl_ini_rxf_data *data) 1291 { 1292 u32 fid1 = le32_to_cpu(reg->fifos.fid1); 1293 u32 fid2 = le32_to_cpu(reg->fifos.fid2); 1294 u32 fifo_idx; 1295 1296 if (!data) 1297 return; 1298 1299 memset(data, 0, sizeof(*data)); 1300 1301 if (WARN_ON_ONCE((fid1 && fid2) || (!fid1 && !fid2))) 1302 return; 1303 1304 fifo_idx = ffs(fid1) - 1; 1305 if (fid1 && !WARN_ON_ONCE((~BIT(fifo_idx) & fid1) || 1306 fifo_idx >= MAX_NUM_LMAC)) { 1307 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1308 data->fifo_num = fifo_idx; 1309 return; 1310 } 1311 1312 fifo_idx = ffs(fid2) - 1; 1313 if (fid2 && !WARN_ON_ONCE(fifo_idx != 0)) { 1314 data->size = fwrt->smem_cfg.rxfifo2_size; 1315 data->offset = RXF_DIFF_FROM_PREV; 1316 /* use bit 31 to distinguish between umac and lmac rxf while 1317 * parsing the dump 1318 */ 1319 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1320 return; 1321 } 1322 } 1323 1324 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1325 struct iwl_fw_ini_region_cfg *reg, 1326 void *range_ptr, int idx) 1327 { 1328 struct iwl_fw_ini_fifo_error_dump_range *range = range_ptr; 1329 struct iwl_ini_rxf_data rxf_data; 1330 u32 offs = le32_to_cpu(reg->offset), addr; 1331 u32 registers_size = 1332 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(__le32); 1333 __le32 *val = range->data; 1334 unsigned long flags; 1335 int i; 1336 1337 iwl_ini_get_rxf_data(fwrt, reg, &rxf_data); 1338 if (!rxf_data.size) 1339 return -EIO; 1340 1341 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1342 return -EBUSY; 1343 1344 offs += rxf_data.offset; 1345 1346 range->fifo_num = cpu_to_le32(rxf_data.fifo_num); 1347 range->num_of_registers = reg->fifos.num_of_registers; 1348 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1349 1350 /* read rxf registers */ 1351 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { 1352 addr = le32_to_cpu(reg->start_addr[i]) + offs; 1353 1354 *val++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1355 } 1356 1357 if (reg->fifos.header_only) { 1358 range->range_data_size = cpu_to_le32(registers_size); 1359 goto out; 1360 } 1361 1362 /* Lock fence */ 1363 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1364 /* Set fence pointer to the same place like WR pointer */ 1365 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1366 /* Set fence offset */ 1367 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1368 0x0); 1369 1370 /* Read FIFO */ 1371 addr = RXF_FIFO_RD_FENCE_INC + offs; 1372 for (i = 0; i < rxf_data.size; i += sizeof(__le32)) 1373 *val++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1374 1375 out: 1376 iwl_trans_release_nic_access(fwrt->trans, &flags); 1377 1378 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1379 } 1380 1381 static void *iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1382 struct iwl_fw_ini_region_cfg *reg, 1383 void *data) 1384 { 1385 struct iwl_fw_ini_error_dump *dump = data; 1386 1387 return dump->ranges; 1388 } 1389 1390 static void 1391 *iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1392 struct iwl_fw_ini_region_cfg *reg, 1393 void *data) 1394 { 1395 struct iwl_fw_ini_monitor_dram_dump *mon_dump = (void *)data; 1396 u32 write_ptr, cycle_cnt; 1397 unsigned long flags; 1398 1399 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) { 1400 IWL_ERR(fwrt, "Failed to get DRAM monitor header\n"); 1401 return NULL; 1402 } 1403 write_ptr = iwl_read_umac_prph_no_grab(fwrt->trans, 1404 MON_BUFF_WRPTR_VER2); 1405 cycle_cnt = iwl_read_umac_prph_no_grab(fwrt->trans, 1406 MON_BUFF_CYCLE_CNT_VER2); 1407 iwl_trans_release_nic_access(fwrt->trans, &flags); 1408 1409 mon_dump->write_ptr = cpu_to_le32(write_ptr); 1410 mon_dump->cycle_cnt = cpu_to_le32(cycle_cnt); 1411 1412 return mon_dump->ranges; 1413 } 1414 1415 static void *iwl_dump_ini_fifo_fill_header(struct iwl_fw_runtime *fwrt, 1416 struct iwl_fw_ini_region_cfg *reg, 1417 void *data) 1418 { 1419 struct iwl_fw_ini_fifo_error_dump *dump = data; 1420 1421 return dump->ranges; 1422 } 1423 1424 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1425 struct iwl_fw_ini_region_cfg *reg) 1426 { 1427 return le32_to_cpu(reg->internal.num_of_ranges); 1428 } 1429 1430 static u32 iwl_dump_ini_paging_gen2_ranges(struct iwl_fw_runtime *fwrt, 1431 struct iwl_fw_ini_region_cfg *reg) 1432 { 1433 return fwrt->trans->init_dram.paging_cnt; 1434 } 1435 1436 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1437 struct iwl_fw_ini_region_cfg *reg) 1438 { 1439 return fwrt->num_of_paging_blk; 1440 } 1441 1442 static u32 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1443 struct iwl_fw_ini_region_cfg *reg) 1444 { 1445 return 1; 1446 } 1447 1448 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1449 struct iwl_fw_ini_region_cfg *reg) 1450 { 1451 struct iwl_ini_txf_iter_data iter = { .init = true }; 1452 void *fifo_iter = fwrt->dump.fifo_iter; 1453 u32 num_of_fifos = 0; 1454 1455 fwrt->dump.fifo_iter = &iter; 1456 while (iwl_ini_txf_iter(fwrt, reg)) 1457 num_of_fifos++; 1458 1459 fwrt->dump.fifo_iter = fifo_iter; 1460 1461 return num_of_fifos; 1462 } 1463 1464 static u32 iwl_dump_ini_rxf_ranges(struct iwl_fw_runtime *fwrt, 1465 struct iwl_fw_ini_region_cfg *reg) 1466 { 1467 /* Each Rx fifo needs a different offset and therefore, it's 1468 * region can contain only one fifo, i.e. 1 memory range. 1469 */ 1470 return 1; 1471 } 1472 1473 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1474 struct iwl_fw_ini_region_cfg *reg) 1475 { 1476 return sizeof(struct iwl_fw_ini_error_dump) + 1477 iwl_dump_ini_mem_ranges(fwrt, reg) * 1478 (sizeof(struct iwl_fw_ini_error_dump_range) + 1479 le32_to_cpu(reg->internal.range_data_size)); 1480 } 1481 1482 static u32 iwl_dump_ini_paging_gen2_get_size(struct iwl_fw_runtime *fwrt, 1483 struct iwl_fw_ini_region_cfg *reg) 1484 { 1485 int i; 1486 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1487 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1488 1489 for (i = 0; i < iwl_dump_ini_paging_gen2_ranges(fwrt, reg); i++) 1490 size += range_header_len + 1491 fwrt->trans->init_dram.paging[i].size; 1492 1493 return size; 1494 } 1495 1496 static u32 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1497 struct iwl_fw_ini_region_cfg *reg) 1498 { 1499 int i; 1500 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1501 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1502 1503 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg); i++) 1504 size += range_header_len + fwrt->fw_paging_db[i].fw_paging_size; 1505 1506 return size; 1507 } 1508 1509 static u32 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 1510 struct iwl_fw_ini_region_cfg *reg) 1511 { 1512 u32 size = sizeof(struct iwl_fw_ini_monitor_dram_dump); 1513 1514 if (fwrt->trans->num_blocks) 1515 size += fwrt->trans->fw_mon[0].size; 1516 1517 return size; 1518 } 1519 1520 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 1521 struct iwl_fw_ini_region_cfg *reg) 1522 { 1523 struct iwl_ini_txf_iter_data iter = { .init = true }; 1524 void *fifo_iter = fwrt->dump.fifo_iter; 1525 u32 size = 0; 1526 u32 fifo_hdr = sizeof(struct iwl_fw_ini_fifo_error_dump_range) + 1527 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(__le32); 1528 1529 fwrt->dump.fifo_iter = &iter; 1530 while (iwl_ini_txf_iter(fwrt, reg)) { 1531 size += fifo_hdr; 1532 if (!reg->fifos.header_only) 1533 size += iter.fifo_size; 1534 } 1535 1536 if (size) 1537 size += sizeof(struct iwl_fw_ini_fifo_error_dump); 1538 1539 fwrt->dump.fifo_iter = fifo_iter; 1540 1541 return size; 1542 } 1543 1544 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 1545 struct iwl_fw_ini_region_cfg *reg) 1546 { 1547 struct iwl_ini_rxf_data rx_data; 1548 u32 size = sizeof(struct iwl_fw_ini_fifo_error_dump) + 1549 sizeof(struct iwl_fw_ini_fifo_error_dump_range) + 1550 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(__le32); 1551 1552 if (reg->fifos.header_only) 1553 return size; 1554 1555 iwl_ini_get_rxf_data(fwrt, reg, &rx_data); 1556 size += rx_data.size; 1557 1558 return size; 1559 } 1560 1561 /** 1562 * struct iwl_dump_ini_mem_ops - ini memory dump operations 1563 * @get_num_of_ranges: returns the number of memory ranges in the region. 1564 * @get_size: returns the total size of the region. 1565 * @fill_mem_hdr: fills region type specific headers and returns pointer to 1566 * the first range or NULL if failed to fill headers. 1567 * @fill_range: copies a given memory range into the dump. 1568 * Returns the size of the range or negative error value otherwise. 1569 */ 1570 struct iwl_dump_ini_mem_ops { 1571 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 1572 struct iwl_fw_ini_region_cfg *reg); 1573 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 1574 struct iwl_fw_ini_region_cfg *reg); 1575 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 1576 struct iwl_fw_ini_region_cfg *reg, void *data); 1577 int (*fill_range)(struct iwl_fw_runtime *fwrt, 1578 struct iwl_fw_ini_region_cfg *reg, void *range, 1579 int idx); 1580 }; 1581 1582 /** 1583 * iwl_dump_ini_mem - copy a memory region into the dump 1584 * @fwrt: fw runtime struct. 1585 * @data: dump memory data. 1586 * @reg: region to copy to the dump. 1587 */ 1588 static void 1589 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, 1590 enum iwl_fw_ini_region_type type, 1591 struct iwl_fw_error_dump_data **data, 1592 struct iwl_fw_ini_region_cfg *reg, 1593 struct iwl_dump_ini_mem_ops *ops) 1594 { 1595 struct iwl_fw_ini_error_dump_header *header = (void *)(*data)->data; 1596 void *range; 1597 u32 num_of_ranges, i; 1598 1599 if (WARN_ON(!ops || !ops->get_num_of_ranges || !ops->get_size || 1600 !ops->fill_mem_hdr || !ops->fill_range)) 1601 return; 1602 1603 num_of_ranges = ops->get_num_of_ranges(fwrt, reg); 1604 1605 (*data)->type = cpu_to_le32(type | INI_DUMP_BIT); 1606 (*data)->len = cpu_to_le32(ops->get_size(fwrt, reg)); 1607 1608 header->num_of_ranges = cpu_to_le32(num_of_ranges); 1609 header->name_len = cpu_to_le32(min_t(int, IWL_FW_INI_MAX_NAME, 1610 le32_to_cpu(reg->name_len))); 1611 memcpy(header->name, reg->name, le32_to_cpu(header->name_len)); 1612 1613 range = ops->fill_mem_hdr(fwrt, reg, header); 1614 if (!range) { 1615 IWL_ERR(fwrt, "Failed to fill region header: id=%d, type=%d\n", 1616 le32_to_cpu(reg->region_id), type); 1617 return; 1618 } 1619 1620 for (i = 0; i < num_of_ranges; i++) { 1621 int range_size = ops->fill_range(fwrt, reg, range, i); 1622 1623 if (range_size < 0) { 1624 IWL_ERR(fwrt, "Failed to dump region: id=%d, type=%d\n", 1625 le32_to_cpu(reg->region_id), type); 1626 return; 1627 } 1628 range = range + range_size; 1629 } 1630 *data = iwl_fw_error_next_data(*data); 1631 } 1632 1633 static int iwl_fw_ini_get_trigger_len(struct iwl_fw_runtime *fwrt, 1634 struct iwl_fw_ini_trigger *trigger) 1635 { 1636 int i, size = 0, hdr_len = sizeof(struct iwl_fw_error_dump_data); 1637 1638 if (!trigger || !trigger->num_regions) 1639 return 0; 1640 1641 for (i = 0; i < le32_to_cpu(trigger->num_regions); i++) { 1642 u32 reg_id = le32_to_cpu(trigger->data[i]); 1643 struct iwl_fw_ini_region_cfg *reg; 1644 enum iwl_fw_ini_region_type type; 1645 1646 if (WARN_ON(reg_id >= ARRAY_SIZE(fwrt->dump.active_regs))) 1647 continue; 1648 1649 reg = fwrt->dump.active_regs[reg_id]; 1650 if (WARN(!reg, "Unassigned region %d\n", reg_id)) 1651 continue; 1652 1653 type = le32_to_cpu(reg->region_type); 1654 switch (type) { 1655 case IWL_FW_INI_REGION_DEVICE_MEMORY: 1656 case IWL_FW_INI_REGION_PERIPHERY_MAC: 1657 case IWL_FW_INI_REGION_PERIPHERY_PHY: 1658 case IWL_FW_INI_REGION_PERIPHERY_AUX: 1659 case IWL_FW_INI_REGION_INTERNAL_BUFFER: 1660 case IWL_FW_INI_REGION_CSR: 1661 size += hdr_len + iwl_dump_ini_mem_get_size(fwrt, reg); 1662 break; 1663 case IWL_FW_INI_REGION_TXF: 1664 size += hdr_len + iwl_dump_ini_txf_get_size(fwrt, reg); 1665 break; 1666 case IWL_FW_INI_REGION_RXF: 1667 size += hdr_len + iwl_dump_ini_rxf_get_size(fwrt, reg); 1668 break; 1669 case IWL_FW_INI_REGION_PAGING: { 1670 size += hdr_len; 1671 if (iwl_fw_dbg_is_paging_enabled(fwrt)) { 1672 size += iwl_dump_ini_paging_get_size(fwrt, reg); 1673 } else { 1674 size += iwl_dump_ini_paging_gen2_get_size(fwrt, 1675 reg); 1676 } 1677 break; 1678 } 1679 case IWL_FW_INI_REGION_DRAM_BUFFER: 1680 if (!fwrt->trans->num_blocks) 1681 break; 1682 size += hdr_len + 1683 iwl_dump_ini_mon_dram_get_size(fwrt, reg); 1684 break; 1685 case IWL_FW_INI_REGION_DRAM_IMR: 1686 /* Undefined yet */ 1687 default: 1688 break; 1689 } 1690 } 1691 return size; 1692 } 1693 1694 static void iwl_fw_ini_dump_trigger(struct iwl_fw_runtime *fwrt, 1695 struct iwl_fw_ini_trigger *trigger, 1696 struct iwl_fw_error_dump_data **data) 1697 { 1698 int i, num = le32_to_cpu(trigger->num_regions); 1699 1700 for (i = 0; i < num; i++) { 1701 u32 reg_id = le32_to_cpu(trigger->data[i]); 1702 enum iwl_fw_ini_region_type type; 1703 struct iwl_fw_ini_region_cfg *reg; 1704 struct iwl_dump_ini_mem_ops ops; 1705 1706 if (reg_id >= ARRAY_SIZE(fwrt->dump.active_regs)) 1707 continue; 1708 1709 reg = fwrt->dump.active_regs[reg_id]; 1710 /* Don't warn, get_trigger_len already warned */ 1711 if (!reg) 1712 continue; 1713 1714 type = le32_to_cpu(reg->region_type); 1715 switch (type) { 1716 case IWL_FW_INI_REGION_DEVICE_MEMORY: 1717 case IWL_FW_INI_REGION_INTERNAL_BUFFER: 1718 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1719 ops.get_size = iwl_dump_ini_mem_get_size; 1720 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1721 ops.fill_range = iwl_dump_ini_dev_mem_iter; 1722 iwl_dump_ini_mem(fwrt, type, data, reg, &ops); 1723 break; 1724 case IWL_FW_INI_REGION_PERIPHERY_MAC: 1725 case IWL_FW_INI_REGION_PERIPHERY_PHY: 1726 case IWL_FW_INI_REGION_PERIPHERY_AUX: 1727 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1728 ops.get_size = iwl_dump_ini_mem_get_size; 1729 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1730 ops.fill_range = iwl_dump_ini_prph_iter; 1731 iwl_dump_ini_mem(fwrt, type, data, reg, &ops); 1732 break; 1733 case IWL_FW_INI_REGION_DRAM_BUFFER: 1734 ops.get_num_of_ranges = iwl_dump_ini_mon_dram_ranges; 1735 ops.get_size = iwl_dump_ini_mon_dram_get_size; 1736 ops.fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header; 1737 ops.fill_range = iwl_dump_ini_mon_dram_iter; 1738 iwl_dump_ini_mem(fwrt, type, data, reg, &ops); 1739 break; 1740 case IWL_FW_INI_REGION_PAGING: { 1741 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1742 if (iwl_fw_dbg_is_paging_enabled(fwrt)) { 1743 ops.get_num_of_ranges = 1744 iwl_dump_ini_paging_ranges; 1745 ops.get_size = iwl_dump_ini_paging_get_size; 1746 ops.fill_range = iwl_dump_ini_paging_iter; 1747 } else { 1748 ops.get_num_of_ranges = 1749 iwl_dump_ini_paging_gen2_ranges; 1750 ops.get_size = 1751 iwl_dump_ini_paging_gen2_get_size; 1752 ops.fill_range = iwl_dump_ini_paging_gen2_iter; 1753 } 1754 1755 iwl_dump_ini_mem(fwrt, type, data, reg, &ops); 1756 break; 1757 } 1758 case IWL_FW_INI_REGION_TXF: { 1759 struct iwl_ini_txf_iter_data iter = { .init = true }; 1760 void *fifo_iter = fwrt->dump.fifo_iter; 1761 1762 fwrt->dump.fifo_iter = &iter; 1763 ops.get_num_of_ranges = iwl_dump_ini_txf_ranges; 1764 ops.get_size = iwl_dump_ini_txf_get_size; 1765 ops.fill_mem_hdr = iwl_dump_ini_fifo_fill_header; 1766 ops.fill_range = iwl_dump_ini_txf_iter; 1767 iwl_dump_ini_mem(fwrt, type, data, reg, &ops); 1768 fwrt->dump.fifo_iter = fifo_iter; 1769 break; 1770 } 1771 case IWL_FW_INI_REGION_RXF: 1772 ops.get_num_of_ranges = iwl_dump_ini_rxf_ranges; 1773 ops.get_size = iwl_dump_ini_rxf_get_size; 1774 ops.fill_mem_hdr = iwl_dump_ini_fifo_fill_header; 1775 ops.fill_range = iwl_dump_ini_rxf_iter; 1776 iwl_dump_ini_mem(fwrt, type, data, reg, &ops); 1777 break; 1778 case IWL_FW_INI_REGION_CSR: 1779 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1780 ops.get_size = iwl_dump_ini_mem_get_size; 1781 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1782 ops.fill_range = iwl_dump_ini_csr_iter; 1783 iwl_dump_ini_mem(fwrt, type, data, reg, &ops); 1784 break; 1785 case IWL_FW_INI_REGION_DRAM_IMR: 1786 /* This is undefined yet */ 1787 default: 1788 break; 1789 } 1790 } 1791 } 1792 1793 static struct iwl_fw_error_dump_file * 1794 _iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, 1795 struct iwl_fw_dump_ptrs *fw_error_dump) 1796 { 1797 int size, id = le32_to_cpu(fwrt->dump.desc->trig_desc.type); 1798 struct iwl_fw_error_dump_data *dump_data; 1799 struct iwl_fw_error_dump_file *dump_file; 1800 struct iwl_fw_ini_trigger *trigger; 1801 1802 if (id == FW_DBG_TRIGGER_FW_ASSERT) 1803 id = IWL_FW_TRIGGER_ID_FW_ASSERT; 1804 1805 if (!iwl_fw_ini_trigger_on(fwrt, id)) 1806 return NULL; 1807 1808 trigger = fwrt->dump.active_trigs[id].trig; 1809 1810 size = sizeof(*dump_file); 1811 size += iwl_fw_ini_get_trigger_len(fwrt, trigger); 1812 1813 if (!size) 1814 return NULL; 1815 1816 dump_file = vzalloc(size); 1817 if (!dump_file) 1818 return NULL; 1819 1820 fw_error_dump->fwrt_ptr = dump_file; 1821 1822 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 1823 dump_data = (void *)dump_file->data; 1824 dump_file->file_len = cpu_to_le32(size); 1825 1826 iwl_fw_ini_dump_trigger(fwrt, trigger, &dump_data); 1827 1828 return dump_file; 1829 } 1830 1831 void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt) 1832 { 1833 struct iwl_fw_dump_ptrs *fw_error_dump; 1834 struct iwl_fw_error_dump_file *dump_file; 1835 struct scatterlist *sg_dump_data; 1836 u32 file_len; 1837 u32 dump_mask = fwrt->fw->dbg.dump_mask; 1838 1839 IWL_DEBUG_INFO(fwrt, "WRT dump start\n"); 1840 1841 /* there's no point in fw dump if the bus is dead */ 1842 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 1843 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 1844 goto out; 1845 } 1846 1847 fw_error_dump = kzalloc(sizeof(*fw_error_dump), GFP_KERNEL); 1848 if (!fw_error_dump) 1849 goto out; 1850 1851 if (fwrt->trans->ini_valid) 1852 dump_file = _iwl_fw_error_ini_dump(fwrt, fw_error_dump); 1853 else 1854 dump_file = _iwl_fw_error_dump(fwrt, fw_error_dump); 1855 1856 if (!dump_file) { 1857 kfree(fw_error_dump); 1858 goto out; 1859 } 1860 1861 if (!fwrt->trans->ini_valid && fwrt->dump.monitor_only) 1862 dump_mask &= IWL_FW_ERROR_DUMP_FW_MONITOR; 1863 1864 if (!fwrt->trans->ini_valid) 1865 fw_error_dump->trans_ptr = 1866 iwl_trans_dump_data(fwrt->trans, dump_mask); 1867 1868 file_len = le32_to_cpu(dump_file->file_len); 1869 fw_error_dump->fwrt_len = file_len; 1870 if (fw_error_dump->trans_ptr) { 1871 file_len += fw_error_dump->trans_ptr->len; 1872 dump_file->file_len = cpu_to_le32(file_len); 1873 } 1874 1875 sg_dump_data = alloc_sgtable(file_len); 1876 if (sg_dump_data) { 1877 sg_pcopy_from_buffer(sg_dump_data, 1878 sg_nents(sg_dump_data), 1879 fw_error_dump->fwrt_ptr, 1880 fw_error_dump->fwrt_len, 0); 1881 if (fw_error_dump->trans_ptr) 1882 sg_pcopy_from_buffer(sg_dump_data, 1883 sg_nents(sg_dump_data), 1884 fw_error_dump->trans_ptr->data, 1885 fw_error_dump->trans_ptr->len, 1886 fw_error_dump->fwrt_len); 1887 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 1888 GFP_KERNEL); 1889 } 1890 vfree(fw_error_dump->fwrt_ptr); 1891 vfree(fw_error_dump->trans_ptr); 1892 kfree(fw_error_dump); 1893 1894 out: 1895 iwl_fw_free_dump_desc(fwrt); 1896 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 1897 IWL_DEBUG_INFO(fwrt, "WRT dump done\n"); 1898 } 1899 IWL_EXPORT_SYMBOL(iwl_fw_error_dump); 1900 1901 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 1902 .trig_desc = { 1903 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 1904 }, 1905 }; 1906 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 1907 1908 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 1909 const struct iwl_fw_dump_desc *desc, 1910 bool monitor_only, 1911 unsigned int delay) 1912 { 1913 if (test_and_set_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 1914 return -EBUSY; 1915 1916 if (WARN_ON(fwrt->dump.desc)) 1917 iwl_fw_free_dump_desc(fwrt); 1918 1919 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 1920 le32_to_cpu(desc->trig_desc.type)); 1921 1922 fwrt->dump.desc = desc; 1923 fwrt->dump.monitor_only = monitor_only; 1924 1925 schedule_delayed_work(&fwrt->dump.wk, usecs_to_jiffies(delay)); 1926 1927 return 0; 1928 } 1929 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 1930 1931 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 1932 enum iwl_fw_dbg_trigger trig_type) 1933 { 1934 int ret; 1935 struct iwl_fw_dump_desc *iwl_dump_error_desc = 1936 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 1937 1938 if (!iwl_dump_error_desc) 1939 return -ENOMEM; 1940 1941 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 1942 iwl_dump_error_desc->len = 0; 1943 1944 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, false, 0); 1945 if (ret) { 1946 kfree(iwl_dump_error_desc); 1947 } else { 1948 set_bit(STATUS_FW_WAIT_DUMP, &fwrt->trans->status); 1949 1950 /* trigger nmi to halt the fw */ 1951 iwl_force_nmi(fwrt->trans); 1952 } 1953 1954 return ret; 1955 } 1956 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 1957 1958 int _iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 1959 enum iwl_fw_dbg_trigger trig, 1960 const char *str, size_t len, 1961 struct iwl_fw_dbg_trigger_tlv *trigger) 1962 { 1963 struct iwl_fw_dump_desc *desc; 1964 unsigned int delay = 0; 1965 bool monitor_only = false; 1966 1967 if (trigger) { 1968 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 1969 1970 if (!le16_to_cpu(trigger->occurrences)) 1971 return 0; 1972 1973 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 1974 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 1975 trig); 1976 iwl_force_nmi(fwrt->trans); 1977 return 0; 1978 } 1979 1980 trigger->occurrences = cpu_to_le16(occurrences); 1981 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 1982 1983 /* convert msec to usec */ 1984 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 1985 } 1986 1987 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 1988 if (!desc) 1989 return -ENOMEM; 1990 1991 1992 desc->len = len; 1993 desc->trig_desc.type = cpu_to_le32(trig); 1994 memcpy(desc->trig_desc.data, str, len); 1995 1996 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 1997 } 1998 IWL_EXPORT_SYMBOL(_iwl_fw_dbg_collect); 1999 2000 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2001 u32 id, const char *str, size_t len) 2002 { 2003 struct iwl_fw_dump_desc *desc; 2004 struct iwl_fw_ini_active_triggers *active; 2005 u32 occur, delay; 2006 2007 if (!fwrt->trans->ini_valid) 2008 return _iwl_fw_dbg_collect(fwrt, id, str, len, NULL); 2009 2010 if (id == FW_DBG_TRIGGER_USER) 2011 id = IWL_FW_TRIGGER_ID_USER_TRIGGER; 2012 2013 active = &fwrt->dump.active_trigs[id]; 2014 2015 if (WARN_ON(!active->active)) 2016 return -EINVAL; 2017 2018 delay = le32_to_cpu(active->trig->dump_delay); 2019 occur = le32_to_cpu(active->trig->occurrences); 2020 if (!occur) 2021 return 0; 2022 2023 if (le32_to_cpu(active->trig->force_restart)) { 2024 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", id); 2025 iwl_force_nmi(fwrt->trans); 2026 return 0; 2027 } 2028 2029 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 2030 if (!desc) 2031 return -ENOMEM; 2032 2033 active->trig->occurrences = cpu_to_le32(--occur); 2034 2035 desc->len = len; 2036 desc->trig_desc.type = cpu_to_le32(id); 2037 memcpy(desc->trig_desc.data, str, len); 2038 2039 return iwl_fw_dbg_collect_desc(fwrt, desc, true, delay); 2040 } 2041 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2042 2043 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2044 struct iwl_fw_dbg_trigger_tlv *trigger, 2045 const char *fmt, ...) 2046 { 2047 int ret, len = 0; 2048 char buf[64]; 2049 2050 if (fwrt->trans->ini_valid) 2051 return 0; 2052 2053 if (fmt) { 2054 va_list ap; 2055 2056 buf[sizeof(buf) - 1] = '\0'; 2057 2058 va_start(ap, fmt); 2059 vsnprintf(buf, sizeof(buf), fmt, ap); 2060 va_end(ap); 2061 2062 /* check for truncation */ 2063 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2064 buf[sizeof(buf) - 1] = '\0'; 2065 2066 len = strlen(buf) + 1; 2067 } 2068 2069 ret = _iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2070 trigger); 2071 2072 if (ret) 2073 return ret; 2074 2075 return 0; 2076 } 2077 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2078 2079 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2080 { 2081 u8 *ptr; 2082 int ret; 2083 int i; 2084 2085 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 2086 "Invalid configuration %d\n", conf_id)) 2087 return -EINVAL; 2088 2089 /* EARLY START - firmware's configuration is hard coded */ 2090 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 2091 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 2092 conf_id == FW_DBG_START_FROM_ALIVE) 2093 return 0; 2094 2095 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 2096 return -EINVAL; 2097 2098 if (fwrt->dump.conf != FW_DBG_INVALID) 2099 IWL_WARN(fwrt, "FW already configured (%d) - re-configuring\n", 2100 fwrt->dump.conf); 2101 2102 /* Send all HCMDs for configuring the FW debug */ 2103 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 2104 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 2105 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 2106 struct iwl_host_cmd hcmd = { 2107 .id = cmd->id, 2108 .len = { le16_to_cpu(cmd->len), }, 2109 .data = { cmd->data, }, 2110 }; 2111 2112 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 2113 if (ret) 2114 return ret; 2115 2116 ptr += sizeof(*cmd); 2117 ptr += le16_to_cpu(cmd->len); 2118 } 2119 2120 fwrt->dump.conf = conf_id; 2121 2122 return 0; 2123 } 2124 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 2125 2126 /* this function assumes dump_start was called beforehand and dump_end will be 2127 * called afterwards 2128 */ 2129 void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt) 2130 { 2131 struct iwl_fw_dbg_params params = {0}; 2132 2133 if (!test_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 2134 return; 2135 2136 if (fwrt->ops && fwrt->ops->fw_running && 2137 !fwrt->ops->fw_running(fwrt->ops_ctx)) { 2138 IWL_ERR(fwrt, "Firmware not running - cannot dump error\n"); 2139 iwl_fw_free_dump_desc(fwrt); 2140 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 2141 return; 2142 } 2143 2144 iwl_fw_dbg_stop_recording(fwrt, ¶ms); 2145 2146 iwl_fw_error_dump(fwrt); 2147 2148 /* start recording again if the firmware is not crashed */ 2149 if (!test_bit(STATUS_FW_ERROR, &fwrt->trans->status) && 2150 fwrt->fw->dbg.dest_tlv) { 2151 /* wait before we collect the data till the DBGC stop */ 2152 udelay(500); 2153 iwl_fw_dbg_restart_recording(fwrt, ¶ms); 2154 } 2155 } 2156 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_sync); 2157 2158 void iwl_fw_error_dump_wk(struct work_struct *work) 2159 { 2160 struct iwl_fw_runtime *fwrt = 2161 container_of(work, struct iwl_fw_runtime, dump.wk.work); 2162 2163 if (fwrt->ops && fwrt->ops->dump_start && 2164 fwrt->ops->dump_start(fwrt->ops_ctx)) 2165 return; 2166 2167 iwl_fw_dbg_collect_sync(fwrt); 2168 2169 if (fwrt->ops && fwrt->ops->dump_end) 2170 fwrt->ops->dump_end(fwrt->ops_ctx); 2171 } 2172 2173 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 2174 { 2175 const struct iwl_cfg *cfg = fwrt->trans->cfg; 2176 2177 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 2178 return; 2179 2180 if (!fwrt->dump.d3_debug_data) { 2181 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 2182 GFP_KERNEL); 2183 if (!fwrt->dump.d3_debug_data) { 2184 IWL_ERR(fwrt, 2185 "failed to allocate memory for D3 debug data\n"); 2186 return; 2187 } 2188 } 2189 2190 /* if the buffer holds previous debug data it is overwritten */ 2191 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 2192 fwrt->dump.d3_debug_data, 2193 cfg->d3_debug_data_length); 2194 } 2195 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 2196 2197 static void 2198 iwl_fw_dbg_buffer_allocation(struct iwl_fw_runtime *fwrt, u32 size) 2199 { 2200 struct iwl_trans *trans = fwrt->trans; 2201 void *virtual_addr = NULL; 2202 dma_addr_t phys_addr; 2203 2204 if (WARN_ON_ONCE(trans->num_blocks == ARRAY_SIZE(trans->fw_mon))) 2205 return; 2206 2207 virtual_addr = 2208 dma_alloc_coherent(fwrt->trans->dev, size, &phys_addr, 2209 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO | 2210 __GFP_COMP); 2211 2212 /* TODO: alloc fragments if needed */ 2213 if (!virtual_addr) 2214 IWL_ERR(fwrt, "Failed to allocate debug memory\n"); 2215 2216 trans->fw_mon[trans->num_blocks].block = virtual_addr; 2217 trans->fw_mon[trans->num_blocks].physical = phys_addr; 2218 trans->fw_mon[trans->num_blocks].size = size; 2219 trans->num_blocks++; 2220 2221 IWL_DEBUG_FW(trans, "Allocated debug block of size %d\n", size); 2222 } 2223 2224 static void iwl_fw_dbg_buffer_apply(struct iwl_fw_runtime *fwrt, 2225 struct iwl_fw_ini_allocation_data *alloc, 2226 enum iwl_fw_ini_apply_point pnt) 2227 { 2228 struct iwl_trans *trans = fwrt->trans; 2229 struct iwl_ldbg_config_cmd ldbg_cmd = { 2230 .type = cpu_to_le32(BUFFER_ALLOCATION), 2231 }; 2232 struct iwl_buffer_allocation_cmd *cmd = &ldbg_cmd.buffer_allocation; 2233 struct iwl_host_cmd hcmd = { 2234 .id = LDBG_CONFIG_CMD, 2235 .flags = CMD_ASYNC, 2236 .data[0] = &ldbg_cmd, 2237 .len[0] = sizeof(ldbg_cmd), 2238 }; 2239 int block_idx = trans->num_blocks; 2240 u32 buf_location = le32_to_cpu(alloc->tlv.buffer_location); 2241 2242 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH) { 2243 if (!WARN(pnt != IWL_FW_INI_APPLY_EARLY, 2244 "Invalid apply point %d for SMEM buffer allocation", 2245 pnt)) 2246 /* set sram monitor by enabling bit 7 */ 2247 iwl_set_bit(fwrt->trans, CSR_HW_IF_CONFIG_REG, 2248 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 2249 return; 2250 } 2251 2252 if (buf_location != IWL_FW_INI_LOCATION_DRAM_PATH) 2253 return; 2254 2255 if (!alloc->is_alloc) { 2256 iwl_fw_dbg_buffer_allocation(fwrt, 2257 le32_to_cpu(alloc->tlv.size)); 2258 if (block_idx == trans->num_blocks) 2259 return; 2260 alloc->is_alloc = 1; 2261 } 2262 2263 /* First block is assigned via registers / context info */ 2264 if (trans->num_blocks == 1) 2265 return; 2266 2267 cmd->num_frags = cpu_to_le32(1); 2268 cmd->fragments[0].address = 2269 cpu_to_le64(trans->fw_mon[block_idx].physical); 2270 cmd->fragments[0].size = alloc->tlv.size; 2271 cmd->allocation_id = alloc->tlv.allocation_id; 2272 cmd->buffer_location = alloc->tlv.buffer_location; 2273 2274 iwl_trans_send_cmd(trans, &hcmd); 2275 } 2276 2277 static void iwl_fw_dbg_send_hcmd(struct iwl_fw_runtime *fwrt, 2278 struct iwl_ucode_tlv *tlv) 2279 { 2280 struct iwl_fw_ini_hcmd_tlv *hcmd_tlv = (void *)&tlv->data[0]; 2281 struct iwl_fw_ini_hcmd *data = &hcmd_tlv->hcmd; 2282 u16 len = le32_to_cpu(tlv->length) - sizeof(*hcmd_tlv); 2283 2284 struct iwl_host_cmd hcmd = { 2285 .id = WIDE_ID(data->group, data->id), 2286 .len = { len, }, 2287 .data = { data->data, }, 2288 }; 2289 2290 iwl_trans_send_cmd(fwrt->trans, &hcmd); 2291 } 2292 2293 static void iwl_fw_dbg_update_regions(struct iwl_fw_runtime *fwrt, 2294 struct iwl_fw_ini_region_tlv *tlv, 2295 bool ext, enum iwl_fw_ini_apply_point pnt) 2296 { 2297 void *iter = (void *)tlv->region_config; 2298 int i, size = le32_to_cpu(tlv->num_regions); 2299 2300 for (i = 0; i < size; i++) { 2301 struct iwl_fw_ini_region_cfg *reg = iter, **active; 2302 int id = le32_to_cpu(reg->region_id); 2303 u32 type = le32_to_cpu(reg->region_type); 2304 2305 if (WARN(id >= ARRAY_SIZE(fwrt->dump.active_regs), 2306 "Invalid region id %d for apply point %d\n", id, pnt)) 2307 break; 2308 2309 active = &fwrt->dump.active_regs[id]; 2310 2311 if (*active) 2312 IWL_WARN(fwrt->trans, "region TLV %d override\n", id); 2313 2314 IWL_DEBUG_FW(fwrt, 2315 "%s: apply point %d, activating region ID %d\n", 2316 __func__, pnt, id); 2317 2318 *active = reg; 2319 2320 if (type == IWL_FW_INI_REGION_TXF || 2321 type == IWL_FW_INI_REGION_RXF) 2322 iter += le32_to_cpu(reg->fifos.num_of_registers) * 2323 sizeof(__le32); 2324 else if (type != IWL_FW_INI_REGION_DRAM_BUFFER) 2325 iter += le32_to_cpu(reg->internal.num_of_ranges) * 2326 sizeof(__le32); 2327 2328 iter += sizeof(*reg); 2329 } 2330 } 2331 2332 static int iwl_fw_dbg_trig_realloc(struct iwl_fw_runtime *fwrt, 2333 struct iwl_fw_ini_active_triggers *active, 2334 u32 id, int size) 2335 { 2336 void *ptr; 2337 2338 if (size <= active->size) 2339 return 0; 2340 2341 ptr = krealloc(active->trig, size, GFP_KERNEL); 2342 if (!ptr) { 2343 IWL_ERR(fwrt, "Failed to allocate memory for trigger %d\n", id); 2344 return -ENOMEM; 2345 } 2346 active->trig = ptr; 2347 active->size = size; 2348 2349 return 0; 2350 } 2351 2352 static void iwl_fw_dbg_update_triggers(struct iwl_fw_runtime *fwrt, 2353 struct iwl_fw_ini_trigger_tlv *tlv, 2354 bool ext, 2355 enum iwl_fw_ini_apply_point apply_point) 2356 { 2357 int i, size = le32_to_cpu(tlv->num_triggers); 2358 void *iter = (void *)tlv->trigger_config; 2359 2360 for (i = 0; i < size; i++) { 2361 struct iwl_fw_ini_trigger *trig = iter; 2362 struct iwl_fw_ini_active_triggers *active; 2363 int id = le32_to_cpu(trig->trigger_id); 2364 u32 trig_regs_size = le32_to_cpu(trig->num_regions) * 2365 sizeof(__le32); 2366 2367 if (WARN_ON(id >= ARRAY_SIZE(fwrt->dump.active_trigs))) 2368 break; 2369 2370 active = &fwrt->dump.active_trigs[id]; 2371 2372 if (!active->active) { 2373 size_t trig_size = sizeof(*trig) + trig_regs_size; 2374 2375 if (iwl_fw_dbg_trig_realloc(fwrt, active, id, 2376 trig_size)) 2377 goto next; 2378 2379 memcpy(active->trig, trig, trig_size); 2380 2381 } else { 2382 u32 conf_override = 2383 !(le32_to_cpu(trig->override_trig) & 0xff); 2384 u32 region_override = 2385 !(le32_to_cpu(trig->override_trig) & 0xff00); 2386 u32 offset = 0; 2387 u32 active_regs = 2388 le32_to_cpu(active->trig->num_regions); 2389 u32 new_regs = le32_to_cpu(trig->num_regions); 2390 int mem_to_add = trig_regs_size; 2391 2392 if (region_override) { 2393 mem_to_add -= active_regs * sizeof(__le32); 2394 } else { 2395 offset += active_regs; 2396 new_regs += active_regs; 2397 } 2398 2399 if (iwl_fw_dbg_trig_realloc(fwrt, active, id, 2400 active->size + mem_to_add)) 2401 goto next; 2402 2403 if (conf_override) 2404 memcpy(active->trig, trig, sizeof(*trig)); 2405 2406 memcpy(active->trig->data + offset, trig->data, 2407 trig_regs_size); 2408 active->trig->num_regions = cpu_to_le32(new_regs); 2409 } 2410 2411 /* Since zero means infinity - just set to -1 */ 2412 if (!le32_to_cpu(active->trig->occurrences)) 2413 active->trig->occurrences = cpu_to_le32(-1); 2414 2415 active->active = true; 2416 next: 2417 iter += sizeof(*trig) + trig_regs_size; 2418 2419 } 2420 } 2421 2422 static void _iwl_fw_dbg_apply_point(struct iwl_fw_runtime *fwrt, 2423 struct iwl_apply_point_data *data, 2424 enum iwl_fw_ini_apply_point pnt, 2425 bool ext) 2426 { 2427 void *iter = data->data; 2428 2429 while (iter && iter < data->data + data->size) { 2430 struct iwl_ucode_tlv *tlv = iter; 2431 void *ini_tlv = (void *)tlv->data; 2432 u32 type = le32_to_cpu(tlv->type); 2433 2434 switch (type) { 2435 case IWL_UCODE_TLV_TYPE_BUFFER_ALLOCATION: { 2436 struct iwl_fw_ini_allocation_data *buf_alloc = ini_tlv; 2437 2438 iwl_fw_dbg_buffer_apply(fwrt, ini_tlv, pnt); 2439 iter += sizeof(buf_alloc->is_alloc); 2440 break; 2441 } 2442 case IWL_UCODE_TLV_TYPE_HCMD: 2443 if (pnt < IWL_FW_INI_APPLY_AFTER_ALIVE) { 2444 IWL_ERR(fwrt, 2445 "Invalid apply point %x for host command\n", 2446 pnt); 2447 goto next; 2448 } 2449 iwl_fw_dbg_send_hcmd(fwrt, tlv); 2450 break; 2451 case IWL_UCODE_TLV_TYPE_REGIONS: 2452 iwl_fw_dbg_update_regions(fwrt, ini_tlv, ext, pnt); 2453 break; 2454 case IWL_UCODE_TLV_TYPE_TRIGGERS: 2455 iwl_fw_dbg_update_triggers(fwrt, ini_tlv, ext, pnt); 2456 break; 2457 case IWL_UCODE_TLV_TYPE_DEBUG_FLOW: 2458 break; 2459 default: 2460 WARN_ONCE(1, "Invalid TLV %x for apply point\n", type); 2461 break; 2462 } 2463 next: 2464 iter += sizeof(*tlv) + le32_to_cpu(tlv->length); 2465 } 2466 } 2467 2468 void iwl_fw_dbg_apply_point(struct iwl_fw_runtime *fwrt, 2469 enum iwl_fw_ini_apply_point apply_point) 2470 { 2471 void *data = &fwrt->trans->apply_points[apply_point]; 2472 int i; 2473 2474 if (apply_point == IWL_FW_INI_APPLY_EARLY) { 2475 for (i = 0; i < IWL_FW_INI_MAX_REGION_ID; i++) 2476 fwrt->dump.active_regs[i] = NULL; 2477 2478 /* disable the triggers, used in recovery flow */ 2479 for (i = 0; i < IWL_FW_TRIGGER_ID_NUM; i++) 2480 fwrt->dump.active_trigs[i].active = false; 2481 } 2482 2483 _iwl_fw_dbg_apply_point(fwrt, data, apply_point, false); 2484 2485 data = &fwrt->trans->apply_points_ext[apply_point]; 2486 _iwl_fw_dbg_apply_point(fwrt, data, apply_point, true); 2487 } 2488 IWL_EXPORT_SYMBOL(iwl_fw_dbg_apply_point); 2489 2490 void iwl_fwrt_stop_device(struct iwl_fw_runtime *fwrt) 2491 { 2492 /* if the wait event timeout elapses instead of wake up then 2493 * the driver did not receive NMI interrupt and can not assume the FW 2494 * is halted 2495 */ 2496 int ret = wait_event_timeout(fwrt->trans->fw_halt_waitq, 2497 !test_bit(STATUS_FW_WAIT_DUMP, 2498 &fwrt->trans->status), 2499 msecs_to_jiffies(2000)); 2500 if (!ret) { 2501 /* failed to receive NMI interrupt, assuming the FW is stuck */ 2502 set_bit(STATUS_FW_ERROR, &fwrt->trans->status); 2503 2504 clear_bit(STATUS_FW_WAIT_DUMP, &fwrt->trans->status); 2505 } 2506 2507 /* Assuming the op mode mutex is held at this point */ 2508 iwl_fw_dbg_collect_sync(fwrt); 2509 2510 iwl_trans_stop_device(fwrt->trans); 2511 } 2512 IWL_EXPORT_SYMBOL(iwl_fwrt_stop_device); 2513