1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2005-2014, 2019-2020 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_fw_api_txq_h__ 8 #define __iwl_fw_api_txq_h__ 9 10 /* 11 * DQA queue numbers 12 * 13 * @IWL_MVM_DQA_CMD_QUEUE: a queue reserved for sending HCMDs to the FW 14 * @IWL_MVM_DQA_AUX_QUEUE: a queue reserved for aux frames 15 * @IWL_MVM_DQA_P2P_DEVICE_QUEUE: a queue reserved for P2P device frames 16 * @IWL_MVM_DQA_INJECT_MONITOR_QUEUE: a queue reserved for injection using 17 * monitor mode. Note this queue is the same as the queue for P2P device 18 * but we can't have active monitor mode along with P2P device anyway. 19 * @IWL_MVM_DQA_GCAST_QUEUE: a queue reserved for P2P GO/SoftAP GCAST frames 20 * @IWL_MVM_DQA_BSS_CLIENT_QUEUE: a queue reserved for BSS activity, to ensure 21 * that we are never left without the possibility to connect to an AP. 22 * @IWL_MVM_DQA_MIN_MGMT_QUEUE: first TXQ in pool for MGMT and non-QOS frames. 23 * Each MGMT queue is mapped to a single STA 24 * MGMT frames are frames that return true on ieee80211_is_mgmt() 25 * @IWL_MVM_DQA_MAX_MGMT_QUEUE: last TXQ in pool for MGMT frames 26 * @IWL_MVM_DQA_AP_PROBE_RESP_QUEUE: a queue reserved for P2P GO/SoftAP probe 27 * responses 28 * @IWL_MVM_DQA_MIN_DATA_QUEUE: first TXQ in pool for DATA frames. 29 * DATA frames are intended for !ieee80211_is_mgmt() frames, but if 30 * the MGMT TXQ pool is exhausted, mgmt frames can be sent on DATA queues 31 * as well 32 * @IWL_MVM_DQA_MAX_DATA_QUEUE: last TXQ in pool for DATA frames 33 */ 34 enum iwl_mvm_dqa_txq { 35 IWL_MVM_DQA_CMD_QUEUE = 0, 36 IWL_MVM_DQA_AUX_QUEUE = 1, 37 IWL_MVM_DQA_P2P_DEVICE_QUEUE = 2, 38 IWL_MVM_DQA_INJECT_MONITOR_QUEUE = 2, 39 IWL_MVM_DQA_GCAST_QUEUE = 3, 40 IWL_MVM_DQA_BSS_CLIENT_QUEUE = 4, 41 IWL_MVM_DQA_MIN_MGMT_QUEUE = 5, 42 IWL_MVM_DQA_MAX_MGMT_QUEUE = 8, 43 IWL_MVM_DQA_AP_PROBE_RESP_QUEUE = 9, 44 IWL_MVM_DQA_MIN_DATA_QUEUE = 10, 45 IWL_MVM_DQA_MAX_DATA_QUEUE = 30, 46 }; 47 48 enum iwl_mvm_tx_fifo { 49 IWL_MVM_TX_FIFO_BK = 0, 50 IWL_MVM_TX_FIFO_BE, 51 IWL_MVM_TX_FIFO_VI, 52 IWL_MVM_TX_FIFO_VO, 53 IWL_MVM_TX_FIFO_MCAST = 5, 54 IWL_MVM_TX_FIFO_CMD = 7, 55 }; 56 57 enum iwl_gen2_tx_fifo { 58 IWL_GEN2_TX_FIFO_CMD = 0, 59 IWL_GEN2_EDCA_TX_FIFO_BK, 60 IWL_GEN2_EDCA_TX_FIFO_BE, 61 IWL_GEN2_EDCA_TX_FIFO_VI, 62 IWL_GEN2_EDCA_TX_FIFO_VO, 63 IWL_GEN2_TRIG_TX_FIFO_BK, 64 IWL_GEN2_TRIG_TX_FIFO_BE, 65 IWL_GEN2_TRIG_TX_FIFO_VI, 66 IWL_GEN2_TRIG_TX_FIFO_VO, 67 }; 68 69 /** 70 * enum iwl_tx_queue_cfg_actions - TXQ config options 71 * @TX_QUEUE_CFG_ENABLE_QUEUE: enable a queue 72 * @TX_QUEUE_CFG_TFD_SHORT_FORMAT: use short TFD format 73 */ 74 enum iwl_tx_queue_cfg_actions { 75 TX_QUEUE_CFG_ENABLE_QUEUE = BIT(0), 76 TX_QUEUE_CFG_TFD_SHORT_FORMAT = BIT(1), 77 }; 78 79 #define IWL_DEFAULT_QUEUE_SIZE 256 80 #define IWL_MGMT_QUEUE_SIZE 16 81 #define IWL_CMD_QUEUE_SIZE 32 82 /** 83 * struct iwl_tx_queue_cfg_cmd - txq hw scheduler config command 84 * @sta_id: station id 85 * @tid: tid of the queue 86 * @flags: see &enum iwl_tx_queue_cfg_actions 87 * @cb_size: size of TFD cyclic buffer. Value is exponent - 3. 88 * Minimum value 0 (8 TFDs), maximum value 5 (256 TFDs) 89 * @byte_cnt_addr: address of byte count table 90 * @tfdq_addr: address of TFD circular buffer 91 */ 92 struct iwl_tx_queue_cfg_cmd { 93 u8 sta_id; 94 u8 tid; 95 __le16 flags; 96 __le32 cb_size; 97 __le64 byte_cnt_addr; 98 __le64 tfdq_addr; 99 } __packed; /* TX_QUEUE_CFG_CMD_API_S_VER_2 */ 100 101 /** 102 * struct iwl_tx_queue_cfg_rsp - response to txq hw scheduler config 103 * @queue_number: queue number assigned to this RA -TID 104 * @flags: set on failure 105 * @write_pointer: initial value for write pointer 106 * @reserved: reserved 107 */ 108 struct iwl_tx_queue_cfg_rsp { 109 __le16 queue_number; 110 __le16 flags; 111 __le16 write_pointer; 112 __le16 reserved; 113 } __packed; /* TX_QUEUE_CFG_RSP_API_S_VER_2 */ 114 115 #endif /* __iwl_fw_api_txq_h__ */ 116