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62 #ifndef __iwl_fw_api_txq_h__
63 #define __iwl_fw_api_txq_h__
64 
65 /*
66  * DQA queue numbers
67  *
68  * @IWL_MVM_DQA_CMD_QUEUE: a queue reserved for sending HCMDs to the FW
69  * @IWL_MVM_DQA_AUX_QUEUE: a queue reserved for aux frames
70  * @IWL_MVM_DQA_P2P_DEVICE_QUEUE: a queue reserved for P2P device frames
71  * @IWL_MVM_DQA_GCAST_QUEUE: a queue reserved for P2P GO/SoftAP GCAST frames
72  * @IWL_MVM_DQA_BSS_CLIENT_QUEUE: a queue reserved for BSS activity, to ensure
73  *	that we are never left without the possibility to connect to an AP.
74  * @IWL_MVM_DQA_MIN_MGMT_QUEUE: first TXQ in pool for MGMT and non-QOS frames.
75  *	Each MGMT queue is mapped to a single STA
76  *	MGMT frames are frames that return true on ieee80211_is_mgmt()
77  * @IWL_MVM_DQA_MAX_MGMT_QUEUE: last TXQ in pool for MGMT frames
78  * @IWL_MVM_DQA_AP_PROBE_RESP_QUEUE: a queue reserved for P2P GO/SoftAP probe
79  *	responses
80  * @IWL_MVM_DQA_MIN_DATA_QUEUE: first TXQ in pool for DATA frames.
81  *	DATA frames are intended for !ieee80211_is_mgmt() frames, but if
82  *	the MGMT TXQ pool is exhausted, mgmt frames can be sent on DATA queues
83  *	as well
84  * @IWL_MVM_DQA_MAX_DATA_QUEUE: last TXQ in pool for DATA frames
85  */
86 enum iwl_mvm_dqa_txq {
87 	IWL_MVM_DQA_CMD_QUEUE = 0,
88 	IWL_MVM_DQA_AUX_QUEUE = 1,
89 	IWL_MVM_DQA_P2P_DEVICE_QUEUE = 2,
90 	IWL_MVM_DQA_GCAST_QUEUE = 3,
91 	IWL_MVM_DQA_BSS_CLIENT_QUEUE = 4,
92 	IWL_MVM_DQA_MIN_MGMT_QUEUE = 5,
93 	IWL_MVM_DQA_MAX_MGMT_QUEUE = 8,
94 	IWL_MVM_DQA_AP_PROBE_RESP_QUEUE = 9,
95 	IWL_MVM_DQA_MIN_DATA_QUEUE = 10,
96 	IWL_MVM_DQA_MAX_DATA_QUEUE = 31,
97 };
98 
99 enum iwl_mvm_tx_fifo {
100 	IWL_MVM_TX_FIFO_BK = 0,
101 	IWL_MVM_TX_FIFO_BE,
102 	IWL_MVM_TX_FIFO_VI,
103 	IWL_MVM_TX_FIFO_VO,
104 	IWL_MVM_TX_FIFO_MCAST = 5,
105 	IWL_MVM_TX_FIFO_CMD = 7,
106 };
107 
108 enum iwl_gen2_tx_fifo {
109 	IWL_GEN2_TX_FIFO_CMD = 0,
110 	IWL_GEN2_EDCA_TX_FIFO_BK,
111 	IWL_GEN2_EDCA_TX_FIFO_BE,
112 	IWL_GEN2_EDCA_TX_FIFO_VI,
113 	IWL_GEN2_EDCA_TX_FIFO_VO,
114 	IWL_GEN2_TRIG_TX_FIFO_BK,
115 	IWL_GEN2_TRIG_TX_FIFO_BE,
116 	IWL_GEN2_TRIG_TX_FIFO_VI,
117 	IWL_GEN2_TRIG_TX_FIFO_VO,
118 };
119 
120 /**
121  * enum iwl_tx_queue_cfg_actions - TXQ config options
122  * @TX_QUEUE_CFG_ENABLE_QUEUE: enable a queue
123  * @TX_QUEUE_CFG_TFD_SHORT_FORMAT: use short TFD format
124  */
125 enum iwl_tx_queue_cfg_actions {
126 	TX_QUEUE_CFG_ENABLE_QUEUE		= BIT(0),
127 	TX_QUEUE_CFG_TFD_SHORT_FORMAT		= BIT(1),
128 };
129 
130 /**
131  * struct iwl_tx_queue_cfg_cmd - txq hw scheduler config command
132  * @sta_id: station id
133  * @tid: tid of the queue
134  * @flags: see &enum iwl_tx_queue_cfg_actions
135  * @cb_size: size of TFD cyclic buffer. Value is exponent - 3.
136  *	Minimum value 0 (8 TFDs), maximum value 5 (256 TFDs)
137  * @byte_cnt_addr: address of byte count table
138  * @tfdq_addr: address of TFD circular buffer
139  */
140 struct iwl_tx_queue_cfg_cmd {
141 	u8 sta_id;
142 	u8 tid;
143 	__le16 flags;
144 	__le32 cb_size;
145 	__le64 byte_cnt_addr;
146 	__le64 tfdq_addr;
147 } __packed; /* TX_QUEUE_CFG_CMD_API_S_VER_2 */
148 
149 /**
150  * struct iwl_tx_queue_cfg_rsp - response to txq hw scheduler config
151  * @queue_number: queue number assigned to this RA -TID
152  * @flags: set on failure
153  * @write_pointer: initial value for write pointer
154  * @reserved: reserved
155  */
156 struct iwl_tx_queue_cfg_rsp {
157 	__le16 queue_number;
158 	__le16 flags;
159 	__le16 write_pointer;
160 	__le16 reserved;
161 } __packed; /* TX_QUEUE_CFG_RSP_API_S_VER_2 */
162 
163 #endif /* __iwl_fw_api_txq_h__ */
164