1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /*
3  * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5  * Copyright (C) 2015-2017 Intel Deutschland GmbH
6  */
7 #ifndef __iwl_fw_api_rx_h__
8 #define __iwl_fw_api_rx_h__
9 
10 /* API for pre-9000 hardware */
11 
12 #define IWL_RX_INFO_PHY_CNT 8
13 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1
14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0
17 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8
18 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16
19 
20 enum iwl_mac_context_info {
21 	MAC_CONTEXT_INFO_NONE,
22 	MAC_CONTEXT_INFO_GSCAN,
23 };
24 
25 /**
26  * struct iwl_rx_phy_info - phy info
27  * (REPLY_RX_PHY_CMD = 0xc0)
28  * @non_cfg_phy_cnt: non configurable DSP phy data byte count
29  * @cfg_phy_cnt: configurable DSP phy data byte count
30  * @stat_id: configurable DSP phy data set ID
31  * @reserved1: reserved
32  * @system_timestamp: GP2  at on air rise
33  * @timestamp: TSF at on air rise
34  * @beacon_time_stamp: beacon at on-air rise
35  * @phy_flags: general phy flags: band, modulation, ...
36  * @channel: channel number
37  * @non_cfg_phy: for various implementations of non_cfg_phy
38  * @rate_n_flags: RATE_MCS_*
39  * @byte_count: frame's byte-count
40  * @frame_time: frame's time on the air, based on byte count and frame rate
41  *	calculation
42  * @mac_active_msk: what MACs were active when the frame was received
43  * @mac_context_info: additional info on the context in which the frame was
44  *	received as defined in &enum iwl_mac_context_info
45  *
46  * Before each Rx, the device sends this data. It contains PHY information
47  * about the reception of the packet.
48  */
49 struct iwl_rx_phy_info {
50 	u8 non_cfg_phy_cnt;
51 	u8 cfg_phy_cnt;
52 	u8 stat_id;
53 	u8 reserved1;
54 	__le32 system_timestamp;
55 	__le64 timestamp;
56 	__le32 beacon_time_stamp;
57 	__le16 phy_flags;
58 	__le16 channel;
59 	__le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT];
60 	__le32 rate_n_flags;
61 	__le32 byte_count;
62 	u8 mac_active_msk;
63 	u8 mac_context_info;
64 	__le16 frame_time;
65 } __packed;
66 
67 /*
68  * TCP offload Rx assist info
69  *
70  * bits 0:3 - reserved
71  * bits 4:7 - MIC CRC length
72  * bits 8:12 - MAC header length
73  * bit 13 - Padding indication
74  * bit 14 - A-AMSDU indication
75  * bit 15 - Offload enabled
76  */
77 enum iwl_csum_rx_assist_info {
78 	CSUM_RXA_RESERVED_MASK	= 0x000f,
79 	CSUM_RXA_MICSIZE_MASK	= 0x00f0,
80 	CSUM_RXA_HEADERLEN_MASK	= 0x1f00,
81 	CSUM_RXA_PADD		= BIT(13),
82 	CSUM_RXA_AMSDU		= BIT(14),
83 	CSUM_RXA_ENA		= BIT(15)
84 };
85 
86 /**
87  * struct iwl_rx_mpdu_res_start - phy info
88  * @byte_count: byte count of the frame
89  * @assist: see &enum iwl_csum_rx_assist_info
90  */
91 struct iwl_rx_mpdu_res_start {
92 	__le16 byte_count;
93 	__le16 assist;
94 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */
95 
96 /**
97  * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags
98  * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
99  * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK
100  * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
101  * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive
102  * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
103  * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position
104  * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
105  * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
106  * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
107  * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
108  */
109 enum iwl_rx_phy_flags {
110 	RX_RES_PHY_FLAGS_BAND_24	= BIT(0),
111 	RX_RES_PHY_FLAGS_MOD_CCK	= BIT(1),
112 	RX_RES_PHY_FLAGS_SHORT_PREAMBLE	= BIT(2),
113 	RX_RES_PHY_FLAGS_NARROW_BAND	= BIT(3),
114 	RX_RES_PHY_FLAGS_ANTENNA	= (0x7 << 4),
115 	RX_RES_PHY_FLAGS_ANTENNA_POS	= 4,
116 	RX_RES_PHY_FLAGS_AGG		= BIT(7),
117 	RX_RES_PHY_FLAGS_OFDM_HT	= BIT(8),
118 	RX_RES_PHY_FLAGS_OFDM_GF	= BIT(9),
119 	RX_RES_PHY_FLAGS_OFDM_VHT	= BIT(10),
120 };
121 
122 /**
123  * enum iwl_mvm_rx_status - written by fw for each Rx packet
124  * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
125  * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
126  * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found
127  * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid
128  * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
129  * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
130  *	in the driver.
131  * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
132  * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR:  valid for alg = CCM_CMAC or
133  *	alg = CCM only. Checks replay attack for 11w frames.
134  * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
135  * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
136  * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
137  * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
138  * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension
139  *	algorithm
140  * @RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC: this frame is protected using
141  *	CMAC or GMAC
142  * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
143  * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
144  * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
145  * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw
146  * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors
147  * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask
148  * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift
149  */
150 enum iwl_mvm_rx_status {
151 	RX_MPDU_RES_STATUS_CRC_OK			= BIT(0),
152 	RX_MPDU_RES_STATUS_OVERRUN_OK			= BIT(1),
153 	RX_MPDU_RES_STATUS_SRC_STA_FOUND		= BIT(2),
154 	RX_MPDU_RES_STATUS_KEY_VALID			= BIT(3),
155 	RX_MPDU_RES_STATUS_ICV_OK			= BIT(5),
156 	RX_MPDU_RES_STATUS_MIC_OK			= BIT(6),
157 	RX_MPDU_RES_STATUS_TTAK_OK			= BIT(7),
158 	RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR		= BIT(7),
159 	RX_MPDU_RES_STATUS_SEC_NO_ENC			= (0 << 8),
160 	RX_MPDU_RES_STATUS_SEC_WEP_ENC			= (1 << 8),
161 	RX_MPDU_RES_STATUS_SEC_CCM_ENC			= (2 << 8),
162 	RX_MPDU_RES_STATUS_SEC_TKIP_ENC			= (3 << 8),
163 	RX_MPDU_RES_STATUS_SEC_EXT_ENC			= (4 << 8),
164 	RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC		= (6 << 8),
165 	RX_MPDU_RES_STATUS_SEC_ENC_ERR			= (7 << 8),
166 	RX_MPDU_RES_STATUS_SEC_ENC_MSK			= (7 << 8),
167 	RX_MPDU_RES_STATUS_DEC_DONE			= BIT(11),
168 	RX_MPDU_RES_STATUS_CSUM_DONE			= BIT(16),
169 	RX_MPDU_RES_STATUS_CSUM_OK			= BIT(17),
170 	RX_MDPU_RES_STATUS_STA_ID_SHIFT			= 24,
171 	RX_MPDU_RES_STATUS_STA_ID_MSK			= 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT,
172 };
173 
174 /* 9000 series API */
175 enum iwl_rx_mpdu_mac_flags1 {
176 	IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK		= 0x03,
177 	IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK	= 0xf0,
178 	/* shift should be 4, but the length is measured in 2-byte
179 	 * words, so shifting only by 3 gives a byte result
180 	 */
181 	IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT	= 3,
182 };
183 
184 enum iwl_rx_mpdu_mac_flags2 {
185 	/* in 2-byte words */
186 	IWL_RX_MPDU_MFLG2_HDR_LEN_MASK		= 0x1f,
187 	IWL_RX_MPDU_MFLG2_PAD			= 0x20,
188 	IWL_RX_MPDU_MFLG2_AMSDU			= 0x40,
189 };
190 
191 enum iwl_rx_mpdu_amsdu_info {
192 	IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK	= 0x7f,
193 	IWL_RX_MPDU_AMSDU_LAST_SUBFRAME		= 0x80,
194 };
195 
196 #define RX_MPDU_BAND_POS 6
197 #define RX_MPDU_BAND_MASK 0xC0
198 #define BAND_IN_RX_STATUS(_val) \
199 	(((_val) & RX_MPDU_BAND_MASK) >> RX_MPDU_BAND_POS)
200 
201 enum iwl_rx_l3_proto_values {
202 	IWL_RX_L3_TYPE_NONE,
203 	IWL_RX_L3_TYPE_IPV4,
204 	IWL_RX_L3_TYPE_IPV4_FRAG,
205 	IWL_RX_L3_TYPE_IPV6_FRAG,
206 	IWL_RX_L3_TYPE_IPV6,
207 	IWL_RX_L3_TYPE_IPV6_IN_IPV4,
208 	IWL_RX_L3_TYPE_ARP,
209 	IWL_RX_L3_TYPE_EAPOL,
210 };
211 
212 #define IWL_RX_L3_PROTO_POS 4
213 
214 enum iwl_rx_l3l4_flags {
215 	IWL_RX_L3L4_IP_HDR_CSUM_OK		= BIT(0),
216 	IWL_RX_L3L4_TCP_UDP_CSUM_OK		= BIT(1),
217 	IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH		= BIT(2),
218 	IWL_RX_L3L4_TCP_ACK			= BIT(3),
219 	IWL_RX_L3L4_L3_PROTO_MASK		= 0xf << IWL_RX_L3_PROTO_POS,
220 	IWL_RX_L3L4_L4_PROTO_MASK		= 0xf << 8,
221 	IWL_RX_L3L4_RSS_HASH_MASK		= 0xf << 12,
222 };
223 
224 enum iwl_rx_mpdu_status {
225 	IWL_RX_MPDU_STATUS_CRC_OK		= BIT(0),
226 	IWL_RX_MPDU_STATUS_OVERRUN_OK		= BIT(1),
227 	IWL_RX_MPDU_STATUS_SRC_STA_FOUND	= BIT(2),
228 	IWL_RX_MPDU_STATUS_KEY_VALID		= BIT(3),
229 	IWL_RX_MPDU_STATUS_ICV_OK		= BIT(5),
230 	IWL_RX_MPDU_STATUS_MIC_OK		= BIT(6),
231 	IWL_RX_MPDU_RES_STATUS_TTAK_OK		= BIT(7),
232 	/* overlayed since IWL_UCODE_TLV_API_DEPRECATE_TTAK */
233 	IWL_RX_MPDU_STATUS_REPLAY_ERROR		= BIT(7),
234 	IWL_RX_MPDU_STATUS_SEC_MASK		= 0x7 << 8,
235 	IWL_RX_MPDU_STATUS_SEC_UNKNOWN		= IWL_RX_MPDU_STATUS_SEC_MASK,
236 	IWL_RX_MPDU_STATUS_SEC_NONE		= 0x0 << 8,
237 	IWL_RX_MPDU_STATUS_SEC_WEP		= 0x1 << 8,
238 	IWL_RX_MPDU_STATUS_SEC_CCM		= 0x2 << 8,
239 	IWL_RX_MPDU_STATUS_SEC_TKIP		= 0x3 << 8,
240 	IWL_RX_MPDU_STATUS_SEC_EXT_ENC		= 0x4 << 8,
241 	IWL_RX_MPDU_STATUS_SEC_GCM		= 0x5 << 8,
242 	IWL_RX_MPDU_STATUS_DECRYPTED		= BIT(11),
243 	IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME	= BIT(15),
244 
245 	IWL_RX_MPDU_STATUS_DUPLICATE		= BIT(22),
246 
247 	IWL_RX_MPDU_STATUS_STA_ID		= 0x1f000000,
248 };
249 
250 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f
251 
252 enum iwl_rx_mpdu_reorder_data {
253 	IWL_RX_MPDU_REORDER_NSSN_MASK		= 0x00000fff,
254 	IWL_RX_MPDU_REORDER_SN_MASK		= 0x00fff000,
255 	IWL_RX_MPDU_REORDER_SN_SHIFT		= 12,
256 	IWL_RX_MPDU_REORDER_BAID_MASK		= 0x7f000000,
257 	IWL_RX_MPDU_REORDER_BAID_SHIFT		= 24,
258 	IWL_RX_MPDU_REORDER_BA_OLD_SN		= 0x80000000,
259 };
260 
261 enum iwl_rx_mpdu_phy_info {
262 	IWL_RX_MPDU_PHY_AMPDU		= BIT(5),
263 	IWL_RX_MPDU_PHY_AMPDU_TOGGLE	= BIT(6),
264 	IWL_RX_MPDU_PHY_SHORT_PREAMBLE	= BIT(7),
265 	/* short preamble is only for CCK, for non-CCK overridden by this */
266 	IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY	= BIT(7),
267 	IWL_RX_MPDU_PHY_TSF_OVERLOAD	= BIT(8),
268 };
269 
270 enum iwl_rx_mpdu_mac_info {
271 	IWL_RX_MPDU_PHY_MAC_INDEX_MASK		= 0x0f,
272 	IWL_RX_MPDU_PHY_PHY_INDEX_MASK		= 0xf0,
273 };
274 
275 /* TSF overload low dword */
276 enum iwl_rx_phy_data0 {
277 	/* info type: HE any */
278 	IWL_RX_PHY_DATA0_HE_BEAM_CHNG				= 0x00000001,
279 	IWL_RX_PHY_DATA0_HE_UPLINK				= 0x00000002,
280 	IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK			= 0x000000fc,
281 	IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK			= 0x00000f00,
282 	/* 1 bit reserved */
283 	IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK			= 0x000fe000,
284 	IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM			= 0x00100000,
285 	IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK			= 0x00600000,
286 	IWL_RX_PHY_DATA0_HE_PE_DISAMBIG				= 0x00800000,
287 	IWL_RX_PHY_DATA0_HE_DOPPLER				= 0x01000000,
288 	/* 6 bits reserved */
289 	IWL_RX_PHY_DATA0_HE_DELIM_EOF				= 0x80000000,
290 };
291 
292 enum iwl_rx_phy_info_type {
293 	IWL_RX_PHY_INFO_TYPE_NONE				= 0,
294 	IWL_RX_PHY_INFO_TYPE_CCK				= 1,
295 	IWL_RX_PHY_INFO_TYPE_OFDM_LGCY				= 2,
296 	IWL_RX_PHY_INFO_TYPE_HT					= 3,
297 	IWL_RX_PHY_INFO_TYPE_VHT_SU				= 4,
298 	IWL_RX_PHY_INFO_TYPE_VHT_MU				= 5,
299 	IWL_RX_PHY_INFO_TYPE_HE_SU				= 6,
300 	IWL_RX_PHY_INFO_TYPE_HE_MU				= 7,
301 	IWL_RX_PHY_INFO_TYPE_HE_TB				= 8,
302 	IWL_RX_PHY_INFO_TYPE_HE_MU_EXT				= 9,
303 	IWL_RX_PHY_INFO_TYPE_HE_TB_EXT				= 10,
304 };
305 
306 /* TSF overload high dword */
307 enum iwl_rx_phy_data1 {
308 	/*
309 	 * check this first - if TSF overload is set,
310 	 * see &enum iwl_rx_phy_info_type
311 	 */
312 	IWL_RX_PHY_DATA1_INFO_TYPE_MASK				= 0xf0000000,
313 
314 	/* info type: HT/VHT/HE any */
315 	IWL_RX_PHY_DATA1_LSIG_LEN_MASK				= 0x0fff0000,
316 
317 	/* info type: HE MU/MU-EXT */
318 	IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION			= 0x00000001,
319 	IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK	= 0x0000001e,
320 
321 	/* info type: HE any */
322 	IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK			= 0x000000e0,
323 	IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80			= 0x00000100,
324 	/* trigger encoded */
325 	IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK			= 0x0000fe00,
326 
327 	/* info type: HE TB/TX-EXT */
328 	IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE			= 0x00000001,
329 	IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK			= 0x0000000e,
330 };
331 
332 /* goes into Metadata DW 7 */
333 enum iwl_rx_phy_data2 {
334 	/* info type: HE MU-EXT */
335 	/* the a1/a2/... is what the PHY/firmware calls the values */
336 	IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0		= 0x000000ff, /* a1 */
337 	IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2		= 0x0000ff00, /* a2 */
338 	IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0		= 0x00ff0000, /* b1 */
339 	IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2		= 0xff000000, /* b2 */
340 
341 	/* info type: HE TB-EXT */
342 	IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1		= 0x0000000f,
343 	IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2		= 0x000000f0,
344 	IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3		= 0x00000f00,
345 	IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4		= 0x0000f000,
346 };
347 
348 /* goes into Metadata DW 8 */
349 enum iwl_rx_phy_data3 {
350 	/* info type: HE MU-EXT */
351 	IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1		= 0x000000ff, /* c1 */
352 	IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3		= 0x0000ff00, /* c2 */
353 	IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1		= 0x00ff0000, /* d1 */
354 	IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3		= 0xff000000, /* d2 */
355 };
356 
357 /* goes into Metadata DW 4 high 16 bits */
358 enum iwl_rx_phy_data4 {
359 	/* info type: HE MU-EXT */
360 	IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU			= 0x0001,
361 	IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU			= 0x0002,
362 	IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK			= 0x0004,
363 	IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK			= 0x0008,
364 	IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK		= 0x00f0,
365 	IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM			= 0x0100,
366 	IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK	= 0x0600,
367 };
368 
369 /**
370  * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor
371  */
372 struct iwl_rx_mpdu_desc_v1 {
373 	/* DW7 - carries rss_hash only when rpa_en == 1 */
374 	union {
375 		/**
376 		 * @rss_hash: RSS hash value
377 		 */
378 		__le32 rss_hash;
379 
380 		/**
381 		 * @phy_data2: depends on info type (see @phy_data1)
382 		 */
383 		__le32 phy_data2;
384 	};
385 
386 	/* DW8 - carries filter_match only when rpa_en == 1 */
387 	union {
388 		/**
389 		 * @filter_match: filter match value
390 		 */
391 		__le32 filter_match;
392 
393 		/**
394 		 * @phy_data3: depends on info type (see @phy_data1)
395 		 */
396 		__le32 phy_data3;
397 	};
398 
399 	/* DW9 */
400 	/**
401 	 * @rate_n_flags: RX rate/flags encoding
402 	 */
403 	__le32 rate_n_flags;
404 	/* DW10 */
405 	/**
406 	 * @energy_a: energy chain A
407 	 */
408 	u8 energy_a;
409 	/**
410 	 * @energy_b: energy chain B
411 	 */
412 	u8 energy_b;
413 	/**
414 	 * @channel: channel number
415 	 */
416 	u8 channel;
417 	/**
418 	 * @mac_context: MAC context mask
419 	 */
420 	u8 mac_context;
421 	/* DW11 */
422 	/**
423 	 * @gp2_on_air_rise: GP2 timer value on air rise (INA)
424 	 */
425 	__le32 gp2_on_air_rise;
426 	/* DW12 & DW13 */
427 	union {
428 		/**
429 		 * @tsf_on_air_rise:
430 		 * TSF value on air rise (INA), only valid if
431 		 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set
432 		 */
433 		__le64 tsf_on_air_rise;
434 
435 		struct {
436 			/**
437 			 * @phy_data0: depends on info_type, see @phy_data1
438 			 */
439 			__le32 phy_data0;
440 			/**
441 			 * @phy_data1: valid only if
442 			 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set,
443 			 * see &enum iwl_rx_phy_data1.
444 			 */
445 			__le32 phy_data1;
446 		};
447 	};
448 } __packed; /* RX_MPDU_RES_START_API_S_VER_4 */
449 
450 /**
451  * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor
452  */
453 struct iwl_rx_mpdu_desc_v3 {
454 	/* DW7 - carries filter_match only when rpa_en == 1 */
455 	union {
456 		/**
457 		 * @filter_match: filter match value
458 		 */
459 		__le32 filter_match;
460 
461 		/**
462 		 * @phy_data3: depends on info type (see @phy_data1)
463 		 */
464 		__le32 phy_data3;
465 	};
466 
467 	/* DW8 - carries rss_hash only when rpa_en == 1 */
468 	union {
469 		/**
470 		 * @rss_hash: RSS hash value
471 		 */
472 		__le32 rss_hash;
473 
474 		/**
475 		 * @phy_data2: depends on info type (see @phy_data1)
476 		 */
477 		__le32 phy_data2;
478 	};
479 	/* DW9 */
480 	/**
481 	 * @partial_hash: 31:0 ip/tcp header hash
482 	 *	w/o some fields (such as IP SRC addr)
483 	 */
484 	__le32 partial_hash;
485 	/* DW10 */
486 	/**
487 	 * @raw_xsum: raw xsum value
488 	 */
489 	__be16 raw_xsum;
490 	/**
491 	 * @reserved_xsum: reserved high bits in the raw checksum
492 	 */
493 	__le16 reserved_xsum;
494 	/* DW11 */
495 	/**
496 	 * @rate_n_flags: RX rate/flags encoding
497 	 */
498 	__le32 rate_n_flags;
499 	/* DW12 */
500 	/**
501 	 * @energy_a: energy chain A
502 	 */
503 	u8 energy_a;
504 	/**
505 	 * @energy_b: energy chain B
506 	 */
507 	u8 energy_b;
508 	/**
509 	 * @channel: channel number
510 	 */
511 	u8 channel;
512 	/**
513 	 * @mac_context: MAC context mask
514 	 */
515 	u8 mac_context;
516 	/* DW13 */
517 	/**
518 	 * @gp2_on_air_rise: GP2 timer value on air rise (INA)
519 	 */
520 	__le32 gp2_on_air_rise;
521 	/* DW14 & DW15 */
522 	union {
523 		/**
524 		 * @tsf_on_air_rise:
525 		 * TSF value on air rise (INA), only valid if
526 		 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set
527 		 */
528 		__le64 tsf_on_air_rise;
529 
530 		struct {
531 			/**
532 			 * @phy_data0: depends on info_type, see @phy_data1
533 			 */
534 			__le32 phy_data0;
535 			/**
536 			 * @phy_data1: valid only if
537 			 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set,
538 			 * see &enum iwl_rx_phy_data1.
539 			 */
540 			__le32 phy_data1;
541 		};
542 	};
543 	/* DW16 & DW17 */
544 	/**
545 	 * @reserved: reserved
546 	 */
547 	__le32 reserved[2];
548 } __packed; /* RX_MPDU_RES_START_API_S_VER_3,
549 	       RX_MPDU_RES_START_API_S_VER_5 */
550 
551 /**
552  * struct iwl_rx_mpdu_desc - RX MPDU descriptor
553  */
554 struct iwl_rx_mpdu_desc {
555 	/* DW2 */
556 	/**
557 	 * @mpdu_len: MPDU length
558 	 */
559 	__le16 mpdu_len;
560 	/**
561 	 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1
562 	 */
563 	u8 mac_flags1;
564 	/**
565 	 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2
566 	 */
567 	u8 mac_flags2;
568 	/* DW3 */
569 	/**
570 	 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info
571 	 */
572 	u8 amsdu_info;
573 	/**
574 	 * @phy_info: &enum iwl_rx_mpdu_phy_info
575 	 */
576 	__le16 phy_info;
577 	/**
578 	 * @mac_phy_idx: MAC/PHY index
579 	 */
580 	u8 mac_phy_idx;
581 	/* DW4 - carries csum data only when rpa_en == 1 */
582 	/**
583 	 * @raw_csum: raw checksum (alledgedly unreliable)
584 	 */
585 	__le16 raw_csum;
586 
587 	union {
588 		/**
589 		 * @l3l4_flags: &enum iwl_rx_l3l4_flags
590 		 */
591 		__le16 l3l4_flags;
592 
593 		/**
594 		 * @phy_data4: depends on info type, see phy_data1
595 		 */
596 		__le16 phy_data4;
597 	};
598 	/* DW5 */
599 	/**
600 	 * @status: &enum iwl_rx_mpdu_status
601 	 */
602 	__le32 status;
603 
604 	/* DW6 */
605 	/**
606 	 * @reorder_data: &enum iwl_rx_mpdu_reorder_data
607 	 */
608 	__le32 reorder_data;
609 
610 	union {
611 		struct iwl_rx_mpdu_desc_v1 v1;
612 		struct iwl_rx_mpdu_desc_v3 v3;
613 	};
614 } __packed; /* RX_MPDU_RES_START_API_S_VER_3,
615 	       RX_MPDU_RES_START_API_S_VER_4,
616 	       RX_MPDU_RES_START_API_S_VER_5 */
617 
618 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1)
619 
620 #define RX_NO_DATA_CHAIN_A_POS		0
621 #define RX_NO_DATA_CHAIN_A_MSK		(0xff << RX_NO_DATA_CHAIN_A_POS)
622 #define RX_NO_DATA_CHAIN_B_POS		8
623 #define RX_NO_DATA_CHAIN_B_MSK		(0xff << RX_NO_DATA_CHAIN_B_POS)
624 #define RX_NO_DATA_CHANNEL_POS		16
625 #define RX_NO_DATA_CHANNEL_MSK		(0xff << RX_NO_DATA_CHANNEL_POS)
626 
627 #define RX_NO_DATA_INFO_TYPE_POS	0
628 #define RX_NO_DATA_INFO_TYPE_MSK	(0xff << RX_NO_DATA_INFO_TYPE_POS)
629 #define RX_NO_DATA_INFO_TYPE_NONE	0
630 #define RX_NO_DATA_INFO_TYPE_RX_ERR	1
631 #define RX_NO_DATA_INFO_TYPE_NDP	2
632 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED	3
633 #define RX_NO_DATA_INFO_TYPE_HE_TB_UNMATCHED	4
634 
635 #define RX_NO_DATA_INFO_ERR_POS		8
636 #define RX_NO_DATA_INFO_ERR_MSK		(0xff << RX_NO_DATA_INFO_ERR_POS)
637 #define RX_NO_DATA_INFO_ERR_NONE	0
638 #define RX_NO_DATA_INFO_ERR_BAD_PLCP	1
639 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE	2
640 #define RX_NO_DATA_INFO_ERR_NO_DELIM		3
641 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR	4
642 
643 #define RX_NO_DATA_FRAME_TIME_POS	0
644 #define RX_NO_DATA_FRAME_TIME_MSK	(0xfffff << RX_NO_DATA_FRAME_TIME_POS)
645 
646 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK	0x03800000
647 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK	0x38000000
648 
649 /**
650  * struct iwl_rx_no_data - RX no data descriptor
651  * @info: 7:0 frame type, 15:8 RX error type
652  * @rssi: 7:0 energy chain-A,
653  *	15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel
654  * @on_air_rise_time: GP2 during on air rise
655  * @fr_time: frame time
656  * @rate: rate/mcs of frame
657  * @phy_info: &enum iwl_rx_phy_data0 and &enum iwl_rx_phy_info_type
658  * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type.
659  *	for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT
660  *	for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT
661  */
662 struct iwl_rx_no_data {
663 	__le32 info;
664 	__le32 rssi;
665 	__le32 on_air_rise_time;
666 	__le32 fr_time;
667 	__le32 rate;
668 	__le32 phy_info[2];
669 	__le32 rx_vec[2];
670 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1,
671 	       RX_NO_DATA_NTFY_API_S_VER_2 */
672 
673 struct iwl_frame_release {
674 	u8 baid;
675 	u8 reserved;
676 	__le16 nssn;
677 };
678 
679 /**
680  * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release
681  * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask
682  * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask
683  */
684 enum iwl_bar_frame_release_sta_tid {
685 	IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f,
686 	IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0,
687 };
688 
689 /**
690  * enum iwl_bar_frame_release_ba_info - BA information for BAR release
691  * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask
692  * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver)
693  * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask
694  */
695 enum iwl_bar_frame_release_ba_info {
696 	IWL_BAR_FRAME_RELEASE_NSSN_MASK	= 0x00000fff,
697 	IWL_BAR_FRAME_RELEASE_SN_MASK	= 0x00fff000,
698 	IWL_BAR_FRAME_RELEASE_BAID_MASK	= 0x3f000000,
699 };
700 
701 /**
702  * struct iwl_bar_frame_release - frame release from BAR info
703  * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid.
704  * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info.
705  */
706 struct iwl_bar_frame_release {
707 	__le32 sta_tid;
708 	__le32 ba_info;
709 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */
710 
711 enum iwl_rss_hash_func_en {
712 	IWL_RSS_HASH_TYPE_IPV4_TCP,
713 	IWL_RSS_HASH_TYPE_IPV4_UDP,
714 	IWL_RSS_HASH_TYPE_IPV4_PAYLOAD,
715 	IWL_RSS_HASH_TYPE_IPV6_TCP,
716 	IWL_RSS_HASH_TYPE_IPV6_UDP,
717 	IWL_RSS_HASH_TYPE_IPV6_PAYLOAD,
718 };
719 
720 #define IWL_RSS_HASH_KEY_CNT 10
721 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128
722 #define IWL_RSS_ENABLE 1
723 
724 /**
725  * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration
726  *
727  * @flags: 1 - enable, 0 - disable
728  * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en
729  * @reserved: reserved
730  * @secret_key: 320 bit input of random key configuration from driver
731  * @indirection_table: indirection table
732  */
733 struct iwl_rss_config_cmd {
734 	__le32 flags;
735 	u8 hash_mask;
736 	u8 reserved[3];
737 	__le32 secret_key[IWL_RSS_HASH_KEY_CNT];
738 	u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE];
739 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */
740 
741 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0
742 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf
743 
744 /**
745  * struct iwl_rxq_sync_cmd - RXQ notification trigger
746  *
747  * @flags: flags of the notification. bit 0:3 are the sender queue
748  * @rxq_mask: rx queues to send the notification on
749  * @count: number of bytes in payload, should be DWORD aligned
750  * @payload: data to send to rx queues
751  */
752 struct iwl_rxq_sync_cmd {
753 	__le32 flags;
754 	__le32 rxq_mask;
755 	__le32 count;
756 	u8 payload[];
757 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */
758 
759 /**
760  * struct iwl_rxq_sync_notification - Notification triggered by RXQ
761  * sync command
762  *
763  * @count: number of bytes in payload
764  * @payload: data to send to rx queues
765  */
766 struct iwl_rxq_sync_notification {
767 	__le32 count;
768 	u8 payload[];
769 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */
770 
771 /**
772  * enum iwl_mvm_pm_event - type of station PM event
773  * @IWL_MVM_PM_EVENT_AWAKE: station woke up
774  * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep
775  * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger
776  * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll
777  */
778 enum iwl_mvm_pm_event {
779 	IWL_MVM_PM_EVENT_AWAKE,
780 	IWL_MVM_PM_EVENT_ASLEEP,
781 	IWL_MVM_PM_EVENT_UAPSD,
782 	IWL_MVM_PM_EVENT_PS_POLL,
783 }; /* PEER_PM_NTFY_API_E_VER_1 */
784 
785 /**
786  * struct iwl_mvm_pm_state_notification - station PM state notification
787  * @sta_id: station ID of the station changing state
788  * @type: the new powersave state, see &enum iwl_mvm_pm_event
789  */
790 struct iwl_mvm_pm_state_notification {
791 	u8 sta_id;
792 	u8 type;
793 	/* private: */
794 	__le16 reserved;
795 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */
796 
797 #define BA_WINDOW_STREAMS_MAX		16
798 #define BA_WINDOW_STATUS_TID_MSK	0x000F
799 #define BA_WINDOW_STATUS_STA_ID_POS	4
800 #define BA_WINDOW_STATUS_STA_ID_MSK	0x01F0
801 #define BA_WINDOW_STATUS_VALID_MSK	BIT(9)
802 
803 /**
804  * struct iwl_ba_window_status_notif - reordering window's status notification
805  * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63]
806  * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid
807  * @start_seq_num: the start sequence number of the bitmap
808  * @mpdu_rx_count: the number of received MPDUs since entering D0i3
809  */
810 struct iwl_ba_window_status_notif {
811 	__le64 bitmap[BA_WINDOW_STREAMS_MAX];
812 	__le16 ra_tid[BA_WINDOW_STREAMS_MAX];
813 	__le32 start_seq_num[BA_WINDOW_STREAMS_MAX];
814 	__le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX];
815 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */
816 
817 /**
818  * struct iwl_rfh_queue_config - RX queue configuration
819  * @q_num: Q num
820  * @enable: enable queue
821  * @reserved: alignment
822  * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr
823  * @fr_bd_cb: DMA address of freeRB table
824  * @ur_bd_cb: DMA address of used RB table
825  * @fr_bd_wid: Initial index of the free table
826  */
827 struct iwl_rfh_queue_data {
828 	u8 q_num;
829 	u8 enable;
830 	__le16 reserved;
831 	__le64 urbd_stts_wrptr;
832 	__le64 fr_bd_cb;
833 	__le64 ur_bd_cb;
834 	__le32 fr_bd_wid;
835 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */
836 
837 /**
838  * struct iwl_rfh_queue_config - RX queue configuration
839  * @num_queues: number of queues configured
840  * @reserved: alignment
841  * @data: DMA addresses per-queue
842  */
843 struct iwl_rfh_queue_config {
844 	u8 num_queues;
845 	u8 reserved[3];
846 	struct iwl_rfh_queue_data data[];
847 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */
848 
849 #endif /* __iwl_fw_api_rx_h__ */
850