1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 65 #ifndef __iwl_fw_api_rx_h__ 66 #define __iwl_fw_api_rx_h__ 67 68 /* API for pre-9000 hardware */ 69 70 #define IWL_RX_INFO_PHY_CNT 8 71 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1 72 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 73 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 74 #define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 75 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0 76 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8 77 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16 78 79 enum iwl_mac_context_info { 80 MAC_CONTEXT_INFO_NONE, 81 MAC_CONTEXT_INFO_GSCAN, 82 }; 83 84 /** 85 * struct iwl_rx_phy_info - phy info 86 * (REPLY_RX_PHY_CMD = 0xc0) 87 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 88 * @cfg_phy_cnt: configurable DSP phy data byte count 89 * @stat_id: configurable DSP phy data set ID 90 * @reserved1: reserved 91 * @system_timestamp: GP2 at on air rise 92 * @timestamp: TSF at on air rise 93 * @beacon_time_stamp: beacon at on-air rise 94 * @phy_flags: general phy flags: band, modulation, ... 95 * @channel: channel number 96 * @non_cfg_phy: for various implementations of non_cfg_phy 97 * @rate_n_flags: RATE_MCS_* 98 * @byte_count: frame's byte-count 99 * @frame_time: frame's time on the air, based on byte count and frame rate 100 * calculation 101 * @mac_active_msk: what MACs were active when the frame was received 102 * @mac_context_info: additional info on the context in which the frame was 103 * received as defined in &enum iwl_mac_context_info 104 * 105 * Before each Rx, the device sends this data. It contains PHY information 106 * about the reception of the packet. 107 */ 108 struct iwl_rx_phy_info { 109 u8 non_cfg_phy_cnt; 110 u8 cfg_phy_cnt; 111 u8 stat_id; 112 u8 reserved1; 113 __le32 system_timestamp; 114 __le64 timestamp; 115 __le32 beacon_time_stamp; 116 __le16 phy_flags; 117 __le16 channel; 118 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; 119 __le32 rate_n_flags; 120 __le32 byte_count; 121 u8 mac_active_msk; 122 u8 mac_context_info; 123 __le16 frame_time; 124 } __packed; 125 126 /* 127 * TCP offload Rx assist info 128 * 129 * bits 0:3 - reserved 130 * bits 4:7 - MIC CRC length 131 * bits 8:12 - MAC header length 132 * bit 13 - Padding indication 133 * bit 14 - A-AMSDU indication 134 * bit 15 - Offload enabled 135 */ 136 enum iwl_csum_rx_assist_info { 137 CSUM_RXA_RESERVED_MASK = 0x000f, 138 CSUM_RXA_MICSIZE_MASK = 0x00f0, 139 CSUM_RXA_HEADERLEN_MASK = 0x1f00, 140 CSUM_RXA_PADD = BIT(13), 141 CSUM_RXA_AMSDU = BIT(14), 142 CSUM_RXA_ENA = BIT(15) 143 }; 144 145 /** 146 * struct iwl_rx_mpdu_res_start - phy info 147 * @byte_count: byte count of the frame 148 * @assist: see &enum iwl_csum_rx_assist_info 149 */ 150 struct iwl_rx_mpdu_res_start { 151 __le16 byte_count; 152 __le16 assist; 153 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */ 154 155 /** 156 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags 157 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 158 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK 159 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 160 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive 161 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 162 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position 163 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 164 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 165 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 166 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 167 */ 168 enum iwl_rx_phy_flags { 169 RX_RES_PHY_FLAGS_BAND_24 = BIT(0), 170 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), 171 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), 172 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), 173 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 174 RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 175 RX_RES_PHY_FLAGS_AGG = BIT(7), 176 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), 177 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), 178 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), 179 }; 180 181 /** 182 * enum iwl_mvm_rx_status - written by fw for each Rx packet 183 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 184 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 185 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found 186 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid 187 * @RX_MPDU_RES_STATUS_KEY_PARAM_OK: key parameters were usable 188 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 189 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 190 * in the driver. 191 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 192 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 193 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 194 * %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 195 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 196 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 197 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 198 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 199 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension 200 * algorithm 201 * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 202 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 203 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 204 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 205 * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: extended IV (set with TKIP) 206 * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: key ID comparison done 207 * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 208 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw 209 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors 210 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask 211 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift 212 */ 213 enum iwl_mvm_rx_status { 214 RX_MPDU_RES_STATUS_CRC_OK = BIT(0), 215 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), 216 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), 217 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), 218 RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4), 219 RX_MPDU_RES_STATUS_ICV_OK = BIT(5), 220 RX_MPDU_RES_STATUS_MIC_OK = BIT(6), 221 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 222 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), 223 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 224 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 225 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 226 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 227 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 228 RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 229 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 230 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 231 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), 232 RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13), 233 RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14), 234 RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15), 235 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), 236 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), 237 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24, 238 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT, 239 }; 240 241 /* 9000 series API */ 242 enum iwl_rx_mpdu_mac_flags1 { 243 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03, 244 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0, 245 /* shift should be 4, but the length is measured in 2-byte 246 * words, so shifting only by 3 gives a byte result 247 */ 248 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3, 249 }; 250 251 enum iwl_rx_mpdu_mac_flags2 { 252 /* in 2-byte words */ 253 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f, 254 IWL_RX_MPDU_MFLG2_PAD = 0x20, 255 IWL_RX_MPDU_MFLG2_AMSDU = 0x40, 256 }; 257 258 enum iwl_rx_mpdu_amsdu_info { 259 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f, 260 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80, 261 }; 262 263 enum iwl_rx_l3_proto_values { 264 IWL_RX_L3_TYPE_NONE, 265 IWL_RX_L3_TYPE_IPV4, 266 IWL_RX_L3_TYPE_IPV4_FRAG, 267 IWL_RX_L3_TYPE_IPV6_FRAG, 268 IWL_RX_L3_TYPE_IPV6, 269 IWL_RX_L3_TYPE_IPV6_IN_IPV4, 270 IWL_RX_L3_TYPE_ARP, 271 IWL_RX_L3_TYPE_EAPOL, 272 }; 273 274 #define IWL_RX_L3_PROTO_POS 4 275 276 enum iwl_rx_l3l4_flags { 277 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), 278 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), 279 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), 280 IWL_RX_L3L4_TCP_ACK = BIT(3), 281 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS, 282 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8, 283 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12, 284 }; 285 286 enum iwl_rx_mpdu_status { 287 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), 288 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), 289 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), 290 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), 291 IWL_RX_MPDU_STATUS_KEY_PARAM_OK = BIT(4), 292 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), 293 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), 294 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 295 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8, 296 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK, 297 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8, 298 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8, 299 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8, 300 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8, 301 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8, 302 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8, 303 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), 304 IWL_RX_MPDU_STATUS_WEP_MATCH = BIT(12), 305 IWL_RX_MPDU_STATUS_EXT_IV_MATCH = BIT(13), 306 IWL_RX_MPDU_STATUS_KEY_ID_MATCH = BIT(14), 307 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), 308 }; 309 310 enum iwl_rx_mpdu_hash_filter { 311 IWL_RX_MPDU_HF_A1_HASH_MASK = 0x3f, 312 IWL_RX_MPDU_HF_FILTER_STATUS_MASK = 0xc0, 313 }; 314 315 enum iwl_rx_mpdu_sta_id_flags { 316 IWL_RX_MPDU_SIF_STA_ID_MASK = 0x1f, 317 IWL_RX_MPDU_SIF_RRF_ABORT = 0x20, 318 IWL_RX_MPDU_SIF_FILTER_STATUS_MASK = 0xc0, 319 }; 320 321 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f 322 323 enum iwl_rx_mpdu_reorder_data { 324 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff, 325 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000, 326 IWL_RX_MPDU_REORDER_SN_SHIFT = 12, 327 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000, 328 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24, 329 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000, 330 }; 331 332 enum iwl_rx_mpdu_phy_info { 333 IWL_RX_MPDU_PHY_AMPDU = BIT(5), 334 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), 335 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), 336 /* short preamble is only for CCK, for non-CCK overridden by this */ 337 IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY = BIT(7), 338 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), 339 }; 340 341 enum iwl_rx_mpdu_mac_info { 342 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f, 343 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0, 344 }; 345 346 /* TSF overload low dword */ 347 enum iwl_rx_phy_data0 { 348 /* info type: HE any */ 349 IWL_RX_PHY_DATA0_HE_BEAM_CHNG = 0x00000001, 350 IWL_RX_PHY_DATA0_HE_UPLINK = 0x00000002, 351 IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK = 0x000000fc, 352 IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK = 0x00000f00, 353 /* 1 bit reserved */ 354 IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK = 0x000fe000, 355 IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM = 0x00100000, 356 IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK = 0x00600000, 357 IWL_RX_PHY_DATA0_HE_PE_DISAMBIG = 0x00800000, 358 IWL_RX_PHY_DATA0_HE_DOPPLER = 0x01000000, 359 /* 6 bits reserved */ 360 IWL_RX_PHY_DATA0_HE_DELIM_EOF = 0x80000000, 361 }; 362 363 enum iwl_rx_phy_info_type { 364 IWL_RX_PHY_INFO_TYPE_NONE = 0, 365 IWL_RX_PHY_INFO_TYPE_CCK = 1, 366 IWL_RX_PHY_INFO_TYPE_OFDM_LGCY = 2, 367 IWL_RX_PHY_INFO_TYPE_HT = 3, 368 IWL_RX_PHY_INFO_TYPE_VHT_SU = 4, 369 IWL_RX_PHY_INFO_TYPE_VHT_MU = 5, 370 IWL_RX_PHY_INFO_TYPE_HE_SU = 6, 371 IWL_RX_PHY_INFO_TYPE_HE_MU = 7, 372 IWL_RX_PHY_INFO_TYPE_HE_TB = 8, 373 IWL_RX_PHY_INFO_TYPE_HE_MU_EXT = 9, 374 IWL_RX_PHY_INFO_TYPE_HE_TB_EXT = 10, 375 }; 376 377 /* TSF overload high dword */ 378 enum iwl_rx_phy_data1 { 379 /* 380 * check this first - if TSF overload is set, 381 * see &enum iwl_rx_phy_info_type 382 */ 383 IWL_RX_PHY_DATA1_INFO_TYPE_MASK = 0xf0000000, 384 385 /* info type: HT/VHT/HE any */ 386 IWL_RX_PHY_DATA1_LSIG_LEN_MASK = 0x0fff0000, 387 388 /* info type: HE MU/MU-EXT */ 389 IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION = 0x00000001, 390 IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK = 0x0000001e, 391 392 /* info type: HE any */ 393 IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK = 0x000000e0, 394 IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80 = 0x00000100, 395 /* trigger encoded */ 396 IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK = 0x0000fe00, 397 398 /* info type: HE TB/TX-EXT */ 399 IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE = 0x00000001, 400 IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK = 0x0000000e, 401 }; 402 403 /* goes into Metadata DW 7 */ 404 enum iwl_rx_phy_data2 { 405 /* info type: HE MU-EXT */ 406 /* the a1/a2/... is what the PHY/firmware calls the values */ 407 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0 = 0x000000ff, /* a1 */ 408 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2 = 0x0000ff00, /* a2 */ 409 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0 = 0x00ff0000, /* b1 */ 410 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2 = 0xff000000, /* b2 */ 411 412 /* info type: HE TB-EXT */ 413 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1 = 0x0000000f, 414 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2 = 0x000000f0, 415 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3 = 0x00000f00, 416 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4 = 0x0000f000, 417 }; 418 419 /* goes into Metadata DW 8 */ 420 enum iwl_rx_phy_data3 { 421 /* info type: HE MU-EXT */ 422 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1 = 0x000000ff, /* c1 */ 423 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3 = 0x0000ff00, /* c2 */ 424 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1 = 0x00ff0000, /* d1 */ 425 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3 = 0xff000000, /* d2 */ 426 }; 427 428 /* goes into Metadata DW 4 high 16 bits */ 429 enum iwl_rx_phy_data4 { 430 /* info type: HE MU-EXT */ 431 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU = 0x0001, 432 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU = 0x0002, 433 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK = 0x0004, 434 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK = 0x0008, 435 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK = 0x00f0, 436 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM = 0x0100, 437 IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK = 0x0600, 438 }; 439 440 /** 441 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor 442 */ 443 struct iwl_rx_mpdu_desc_v1 { 444 /* DW7 - carries rss_hash only when rpa_en == 1 */ 445 union { 446 /** 447 * @rss_hash: RSS hash value 448 */ 449 __le32 rss_hash; 450 451 /** 452 * @phy_data2: depends on info type (see @phy_data1) 453 */ 454 __le32 phy_data2; 455 }; 456 457 /* DW8 - carries filter_match only when rpa_en == 1 */ 458 union { 459 /** 460 * @filter_match: filter match value 461 */ 462 __le32 filter_match; 463 464 /** 465 * @phy_data3: depends on info type (see @phy_data1) 466 */ 467 __le32 phy_data3; 468 }; 469 470 /* DW9 */ 471 /** 472 * @rate_n_flags: RX rate/flags encoding 473 */ 474 __le32 rate_n_flags; 475 /* DW10 */ 476 /** 477 * @energy_a: energy chain A 478 */ 479 u8 energy_a; 480 /** 481 * @energy_b: energy chain B 482 */ 483 u8 energy_b; 484 /** 485 * @channel: channel number 486 */ 487 u8 channel; 488 /** 489 * @mac_context: MAC context mask 490 */ 491 u8 mac_context; 492 /* DW11 */ 493 /** 494 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 495 */ 496 __le32 gp2_on_air_rise; 497 /* DW12 & DW13 */ 498 union { 499 /** 500 * @tsf_on_air_rise: 501 * TSF value on air rise (INA), only valid if 502 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 503 */ 504 __le64 tsf_on_air_rise; 505 506 struct { 507 /** 508 * @phy_data0: depends on info_type, see @phy_data1 509 */ 510 __le32 phy_data0; 511 /** 512 * @phy_data1: valid only if 513 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 514 * see &enum iwl_rx_phy_data1. 515 */ 516 __le32 phy_data1; 517 }; 518 }; 519 } __packed; 520 521 /** 522 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor 523 */ 524 struct iwl_rx_mpdu_desc_v3 { 525 /* DW7 - carries filter_match only when rpa_en == 1 */ 526 union { 527 /** 528 * @filter_match: filter match value 529 */ 530 __le32 filter_match; 531 532 /** 533 * @phy_data2: depends on info type (see @phy_data1) 534 */ 535 __le32 phy_data2; 536 }; 537 538 /* DW8 - carries rss_hash only when rpa_en == 1 */ 539 union { 540 /** 541 * @rss_hash: RSS hash value 542 */ 543 __le32 rss_hash; 544 545 /** 546 * @phy_data3: depends on info type (see @phy_data1) 547 */ 548 __le32 phy_data3; 549 }; 550 /* DW9 */ 551 /** 552 * @partial_hash: 31:0 ip/tcp header hash 553 * w/o some fields (such as IP SRC addr) 554 */ 555 __le32 partial_hash; 556 /* DW10 */ 557 /** 558 * @raw_xsum: raw xsum value 559 */ 560 __le32 raw_xsum; 561 /* DW11 */ 562 /** 563 * @rate_n_flags: RX rate/flags encoding 564 */ 565 __le32 rate_n_flags; 566 /* DW12 */ 567 /** 568 * @energy_a: energy chain A 569 */ 570 u8 energy_a; 571 /** 572 * @energy_b: energy chain B 573 */ 574 u8 energy_b; 575 /** 576 * @channel: channel number 577 */ 578 u8 channel; 579 /** 580 * @mac_context: MAC context mask 581 */ 582 u8 mac_context; 583 /* DW13 */ 584 /** 585 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 586 */ 587 __le32 gp2_on_air_rise; 588 /* DW14 & DW15 */ 589 union { 590 /** 591 * @tsf_on_air_rise: 592 * TSF value on air rise (INA), only valid if 593 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 594 */ 595 __le64 tsf_on_air_rise; 596 597 struct { 598 /** 599 * @phy_data0: depends on info_type, see @phy_data1 600 */ 601 __le32 phy_data0; 602 /** 603 * @phy_data1: valid only if 604 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 605 * see &enum iwl_rx_phy_data1. 606 */ 607 __le32 phy_data1; 608 }; 609 }; 610 /* DW16 & DW17 */ 611 /** 612 * @reserved: reserved 613 */ 614 __le32 reserved[2]; 615 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */ 616 617 /** 618 * struct iwl_rx_mpdu_desc - RX MPDU descriptor 619 */ 620 struct iwl_rx_mpdu_desc { 621 /* DW2 */ 622 /** 623 * @mpdu_len: MPDU length 624 */ 625 __le16 mpdu_len; 626 /** 627 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1 628 */ 629 u8 mac_flags1; 630 /** 631 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2 632 */ 633 u8 mac_flags2; 634 /* DW3 */ 635 /** 636 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info 637 */ 638 u8 amsdu_info; 639 /** 640 * @phy_info: &enum iwl_rx_mpdu_phy_info 641 */ 642 __le16 phy_info; 643 /** 644 * @mac_phy_idx: MAC/PHY index 645 */ 646 u8 mac_phy_idx; 647 /* DW4 - carries csum data only when rpa_en == 1 */ 648 /** 649 * @raw_csum: raw checksum (alledgedly unreliable) 650 */ 651 __le16 raw_csum; 652 653 union { 654 /** 655 * @l3l4_flags: &enum iwl_rx_l3l4_flags 656 */ 657 __le16 l3l4_flags; 658 659 /** 660 * @phy_data4: depends on info type, see phy_data1 661 */ 662 __le16 phy_data4; 663 }; 664 /* DW5 */ 665 /** 666 * @status: &enum iwl_rx_mpdu_status 667 */ 668 __le16 status; 669 /** 670 * @hash_filter: hash filter value 671 */ 672 u8 hash_filter; 673 /** 674 * @sta_id_flags: &enum iwl_rx_mpdu_sta_id_flags 675 */ 676 u8 sta_id_flags; 677 /* DW6 */ 678 /** 679 * @reorder_data: &enum iwl_rx_mpdu_reorder_data 680 */ 681 __le32 reorder_data; 682 683 union { 684 struct iwl_rx_mpdu_desc_v1 v1; 685 struct iwl_rx_mpdu_desc_v3 v3; 686 }; 687 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */ 688 689 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1) 690 691 #define RX_NO_DATA_CHAIN_A_POS 0 692 #define RX_NO_DATA_CHAIN_A_MSK (0xff << RX_NO_DATA_CHAIN_A_POS) 693 #define RX_NO_DATA_CHAIN_B_POS 8 694 #define RX_NO_DATA_CHAIN_B_MSK (0xff << RX_NO_DATA_CHAIN_B_POS) 695 #define RX_NO_DATA_CHANNEL_POS 16 696 #define RX_NO_DATA_CHANNEL_MSK (0xff << RX_NO_DATA_CHANNEL_POS) 697 698 #define RX_NO_DATA_INFO_TYPE_POS 0 699 #define RX_NO_DATA_INFO_TYPE_MSK (0xff << RX_NO_DATA_INFO_TYPE_POS) 700 #define RX_NO_DATA_INFO_TYPE_NONE 0 701 #define RX_NO_DATA_INFO_TYPE_RX_ERR 1 702 #define RX_NO_DATA_INFO_TYPE_NDP 2 703 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED 3 704 #define RX_NO_DATA_INFO_TYPE_HE_TB_UNMATCHED 4 705 706 #define RX_NO_DATA_INFO_ERR_POS 8 707 #define RX_NO_DATA_INFO_ERR_MSK (0xff << RX_NO_DATA_INFO_ERR_POS) 708 #define RX_NO_DATA_INFO_ERR_NONE 0 709 #define RX_NO_DATA_INFO_ERR_BAD_PLCP 1 710 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE 2 711 #define RX_NO_DATA_INFO_ERR_NO_DELIM 3 712 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR 4 713 714 #define RX_NO_DATA_FRAME_TIME_POS 0 715 #define RX_NO_DATA_FRAME_TIME_MSK (0xfffff << RX_NO_DATA_FRAME_TIME_POS) 716 717 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK 0x03800000 718 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK 0x38000000 719 720 /** 721 * struct iwl_rx_no_data - RX no data descriptor 722 * @info: 7:0 frame type, 15:8 RX error type 723 * @rssi: 7:0 energy chain-A, 724 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 725 * @on_air_rise_time: GP2 during on air rise 726 * @fr_time: frame time 727 * @rate: rate/mcs of frame 728 * @phy_info: &enum iwl_rx_phy_data0 and &enum iwl_rx_phy_info_type 729 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 730 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 731 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 732 */ 733 struct iwl_rx_no_data { 734 __le32 info; 735 __le32 rssi; 736 __le32 on_air_rise_time; 737 __le32 fr_time; 738 __le32 rate; 739 __le32 phy_info[2]; 740 __le32 rx_vec[2]; 741 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1 */ 742 743 struct iwl_frame_release { 744 u8 baid; 745 u8 reserved; 746 __le16 nssn; 747 }; 748 749 enum iwl_rss_hash_func_en { 750 IWL_RSS_HASH_TYPE_IPV4_TCP, 751 IWL_RSS_HASH_TYPE_IPV4_UDP, 752 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD, 753 IWL_RSS_HASH_TYPE_IPV6_TCP, 754 IWL_RSS_HASH_TYPE_IPV6_UDP, 755 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 756 }; 757 758 #define IWL_RSS_HASH_KEY_CNT 10 759 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128 760 #define IWL_RSS_ENABLE 1 761 762 /** 763 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration 764 * 765 * @flags: 1 - enable, 0 - disable 766 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en 767 * @reserved: reserved 768 * @secret_key: 320 bit input of random key configuration from driver 769 * @indirection_table: indirection table 770 */ 771 struct iwl_rss_config_cmd { 772 __le32 flags; 773 u8 hash_mask; 774 u8 reserved[3]; 775 __le32 secret_key[IWL_RSS_HASH_KEY_CNT]; 776 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE]; 777 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */ 778 779 #define IWL_MULTI_QUEUE_SYNC_MSG_MAX_SIZE 128 780 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0 781 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf 782 783 /** 784 * struct iwl_rxq_sync_cmd - RXQ notification trigger 785 * 786 * @flags: flags of the notification. bit 0:3 are the sender queue 787 * @rxq_mask: rx queues to send the notification on 788 * @count: number of bytes in payload, should be DWORD aligned 789 * @payload: data to send to rx queues 790 */ 791 struct iwl_rxq_sync_cmd { 792 __le32 flags; 793 __le32 rxq_mask; 794 __le32 count; 795 u8 payload[]; 796 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 797 798 /** 799 * struct iwl_rxq_sync_notification - Notification triggered by RXQ 800 * sync command 801 * 802 * @count: number of bytes in payload 803 * @payload: data to send to rx queues 804 */ 805 struct iwl_rxq_sync_notification { 806 __le32 count; 807 u8 payload[]; 808 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 809 810 /** 811 * enum iwl_mvm_rxq_notif_type - Internal message identifier 812 * 813 * @IWL_MVM_RXQ_EMPTY: empty sync notification 814 * @IWL_MVM_RXQ_NOTIF_DEL_BA: notify RSS queues of delBA 815 */ 816 enum iwl_mvm_rxq_notif_type { 817 IWL_MVM_RXQ_EMPTY, 818 IWL_MVM_RXQ_NOTIF_DEL_BA, 819 }; 820 821 /** 822 * struct iwl_mvm_internal_rxq_notif - Internal representation of the data sent 823 * in &iwl_rxq_sync_cmd. Should be DWORD aligned. 824 * FW is agnostic to the payload, so there are no endianity requirements. 825 * 826 * @type: value from &iwl_mvm_rxq_notif_type 827 * @sync: ctrl path is waiting for all notifications to be received 828 * @cookie: internal cookie to identify old notifications 829 * @data: payload 830 */ 831 struct iwl_mvm_internal_rxq_notif { 832 u16 type; 833 u16 sync; 834 u32 cookie; 835 u8 data[]; 836 } __packed; 837 838 /** 839 * enum iwl_mvm_pm_event - type of station PM event 840 * @IWL_MVM_PM_EVENT_AWAKE: station woke up 841 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep 842 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger 843 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll 844 */ 845 enum iwl_mvm_pm_event { 846 IWL_MVM_PM_EVENT_AWAKE, 847 IWL_MVM_PM_EVENT_ASLEEP, 848 IWL_MVM_PM_EVENT_UAPSD, 849 IWL_MVM_PM_EVENT_PS_POLL, 850 }; /* PEER_PM_NTFY_API_E_VER_1 */ 851 852 /** 853 * struct iwl_mvm_pm_state_notification - station PM state notification 854 * @sta_id: station ID of the station changing state 855 * @type: the new powersave state, see &enum iwl_mvm_pm_event 856 */ 857 struct iwl_mvm_pm_state_notification { 858 u8 sta_id; 859 u8 type; 860 /* private: */ 861 __le16 reserved; 862 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */ 863 864 #define BA_WINDOW_STREAMS_MAX 16 865 #define BA_WINDOW_STATUS_TID_MSK 0x000F 866 #define BA_WINDOW_STATUS_STA_ID_POS 4 867 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0 868 #define BA_WINDOW_STATUS_VALID_MSK BIT(9) 869 870 /** 871 * struct iwl_ba_window_status_notif - reordering window's status notification 872 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63] 873 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid 874 * @start_seq_num: the start sequence number of the bitmap 875 * @mpdu_rx_count: the number of received MPDUs since entering D0i3 876 */ 877 struct iwl_ba_window_status_notif { 878 __le64 bitmap[BA_WINDOW_STREAMS_MAX]; 879 __le16 ra_tid[BA_WINDOW_STREAMS_MAX]; 880 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX]; 881 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX]; 882 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */ 883 884 /** 885 * struct iwl_rfh_queue_config - RX queue configuration 886 * @q_num: Q num 887 * @enable: enable queue 888 * @reserved: alignment 889 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 890 * @fr_bd_cb: DMA address of freeRB table 891 * @ur_bd_cb: DMA address of used RB table 892 * @fr_bd_wid: Initial index of the free table 893 */ 894 struct iwl_rfh_queue_data { 895 u8 q_num; 896 u8 enable; 897 __le16 reserved; 898 __le64 urbd_stts_wrptr; 899 __le64 fr_bd_cb; 900 __le64 ur_bd_cb; 901 __le32 fr_bd_wid; 902 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */ 903 904 /** 905 * struct iwl_rfh_queue_config - RX queue configuration 906 * @num_queues: number of queues configured 907 * @reserved: alignment 908 * @data: DMA addresses per-queue 909 */ 910 struct iwl_rfh_queue_config { 911 u8 num_queues; 912 u8 reserved[3]; 913 struct iwl_rfh_queue_data data[]; 914 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */ 915 916 #endif /* __iwl_fw_api_rx_h__ */ 917