1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 65 #ifndef __iwl_fw_api_rx_h__ 66 #define __iwl_fw_api_rx_h__ 67 68 /* API for pre-9000 hardware */ 69 70 #define IWL_RX_INFO_PHY_CNT 8 71 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1 72 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 73 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 74 #define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 75 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0 76 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8 77 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16 78 79 enum iwl_mac_context_info { 80 MAC_CONTEXT_INFO_NONE, 81 MAC_CONTEXT_INFO_GSCAN, 82 }; 83 84 /** 85 * struct iwl_rx_phy_info - phy info 86 * (REPLY_RX_PHY_CMD = 0xc0) 87 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 88 * @cfg_phy_cnt: configurable DSP phy data byte count 89 * @stat_id: configurable DSP phy data set ID 90 * @reserved1: reserved 91 * @system_timestamp: GP2 at on air rise 92 * @timestamp: TSF at on air rise 93 * @beacon_time_stamp: beacon at on-air rise 94 * @phy_flags: general phy flags: band, modulation, ... 95 * @channel: channel number 96 * @non_cfg_phy: for various implementations of non_cfg_phy 97 * @rate_n_flags: RATE_MCS_* 98 * @byte_count: frame's byte-count 99 * @frame_time: frame's time on the air, based on byte count and frame rate 100 * calculation 101 * @mac_active_msk: what MACs were active when the frame was received 102 * @mac_context_info: additional info on the context in which the frame was 103 * received as defined in &enum iwl_mac_context_info 104 * 105 * Before each Rx, the device sends this data. It contains PHY information 106 * about the reception of the packet. 107 */ 108 struct iwl_rx_phy_info { 109 u8 non_cfg_phy_cnt; 110 u8 cfg_phy_cnt; 111 u8 stat_id; 112 u8 reserved1; 113 __le32 system_timestamp; 114 __le64 timestamp; 115 __le32 beacon_time_stamp; 116 __le16 phy_flags; 117 __le16 channel; 118 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; 119 __le32 rate_n_flags; 120 __le32 byte_count; 121 u8 mac_active_msk; 122 u8 mac_context_info; 123 __le16 frame_time; 124 } __packed; 125 126 /* 127 * TCP offload Rx assist info 128 * 129 * bits 0:3 - reserved 130 * bits 4:7 - MIC CRC length 131 * bits 8:12 - MAC header length 132 * bit 13 - Padding indication 133 * bit 14 - A-AMSDU indication 134 * bit 15 - Offload enabled 135 */ 136 enum iwl_csum_rx_assist_info { 137 CSUM_RXA_RESERVED_MASK = 0x000f, 138 CSUM_RXA_MICSIZE_MASK = 0x00f0, 139 CSUM_RXA_HEADERLEN_MASK = 0x1f00, 140 CSUM_RXA_PADD = BIT(13), 141 CSUM_RXA_AMSDU = BIT(14), 142 CSUM_RXA_ENA = BIT(15) 143 }; 144 145 /** 146 * struct iwl_rx_mpdu_res_start - phy info 147 * @byte_count: byte count of the frame 148 * @assist: see &enum iwl_csum_rx_assist_info 149 */ 150 struct iwl_rx_mpdu_res_start { 151 __le16 byte_count; 152 __le16 assist; 153 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */ 154 155 /** 156 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags 157 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 158 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK 159 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 160 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive 161 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 162 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position 163 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 164 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 165 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 166 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 167 */ 168 enum iwl_rx_phy_flags { 169 RX_RES_PHY_FLAGS_BAND_24 = BIT(0), 170 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), 171 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), 172 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), 173 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 174 RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 175 RX_RES_PHY_FLAGS_AGG = BIT(7), 176 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), 177 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), 178 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), 179 }; 180 181 /** 182 * enum iwl_mvm_rx_status - written by fw for each Rx packet 183 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 184 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 185 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found 186 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid 187 * @RX_MPDU_RES_STATUS_KEY_PARAM_OK: key parameters were usable 188 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 189 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 190 * in the driver. 191 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 192 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 193 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 194 * %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 195 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 196 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 197 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 198 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 199 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension 200 * algorithm 201 * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 202 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 203 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 204 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 205 * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: extended IV (set with TKIP) 206 * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: key ID comparison done 207 * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 208 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw 209 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors 210 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask 211 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift 212 * @RX_MPDU_RES_STATUS_FILTERING_MSK: filter status 213 * @RX_MPDU_RES_STATUS2_FILTERING_MSK: filter status 2 214 */ 215 enum iwl_mvm_rx_status { 216 RX_MPDU_RES_STATUS_CRC_OK = BIT(0), 217 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), 218 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), 219 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), 220 RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4), 221 RX_MPDU_RES_STATUS_ICV_OK = BIT(5), 222 RX_MPDU_RES_STATUS_MIC_OK = BIT(6), 223 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 224 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), 225 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 226 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 227 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 228 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 229 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 230 RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 231 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 232 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 233 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), 234 RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13), 235 RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14), 236 RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15), 237 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), 238 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), 239 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24, 240 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT, 241 RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 242 RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 243 }; 244 245 /* 9000 series API */ 246 enum iwl_rx_mpdu_mac_flags1 { 247 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03, 248 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0, 249 /* shift should be 4, but the length is measured in 2-byte 250 * words, so shifting only by 3 gives a byte result 251 */ 252 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3, 253 }; 254 255 enum iwl_rx_mpdu_mac_flags2 { 256 /* in 2-byte words */ 257 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f, 258 IWL_RX_MPDU_MFLG2_PAD = 0x20, 259 IWL_RX_MPDU_MFLG2_AMSDU = 0x40, 260 }; 261 262 enum iwl_rx_mpdu_amsdu_info { 263 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f, 264 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80, 265 }; 266 267 enum iwl_rx_l3_proto_values { 268 IWL_RX_L3_TYPE_NONE, 269 IWL_RX_L3_TYPE_IPV4, 270 IWL_RX_L3_TYPE_IPV4_FRAG, 271 IWL_RX_L3_TYPE_IPV6_FRAG, 272 IWL_RX_L3_TYPE_IPV6, 273 IWL_RX_L3_TYPE_IPV6_IN_IPV4, 274 IWL_RX_L3_TYPE_ARP, 275 IWL_RX_L3_TYPE_EAPOL, 276 }; 277 278 #define IWL_RX_L3_PROTO_POS 4 279 280 enum iwl_rx_l3l4_flags { 281 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), 282 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), 283 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), 284 IWL_RX_L3L4_TCP_ACK = BIT(3), 285 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS, 286 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8, 287 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12, 288 }; 289 290 enum iwl_rx_mpdu_status { 291 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), 292 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), 293 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), 294 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), 295 IWL_RX_MPDU_STATUS_KEY_PARAM_OK = BIT(4), 296 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), 297 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), 298 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 299 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8, 300 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK, 301 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8, 302 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8, 303 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8, 304 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8, 305 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8, 306 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8, 307 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), 308 IWL_RX_MPDU_STATUS_WEP_MATCH = BIT(12), 309 IWL_RX_MPDU_STATUS_EXT_IV_MATCH = BIT(13), 310 IWL_RX_MPDU_STATUS_KEY_ID_MATCH = BIT(14), 311 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), 312 }; 313 314 enum iwl_rx_mpdu_hash_filter { 315 IWL_RX_MPDU_HF_A1_HASH_MASK = 0x3f, 316 IWL_RX_MPDU_HF_FILTER_STATUS_MASK = 0xc0, 317 }; 318 319 enum iwl_rx_mpdu_sta_id_flags { 320 IWL_RX_MPDU_SIF_STA_ID_MASK = 0x1f, 321 IWL_RX_MPDU_SIF_RRF_ABORT = 0x20, 322 IWL_RX_MPDU_SIF_FILTER_STATUS_MASK = 0xc0, 323 }; 324 325 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f 326 327 enum iwl_rx_mpdu_reorder_data { 328 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff, 329 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000, 330 IWL_RX_MPDU_REORDER_SN_SHIFT = 12, 331 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000, 332 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24, 333 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000, 334 }; 335 336 enum iwl_rx_mpdu_phy_info { 337 IWL_RX_MPDU_PHY_AMPDU = BIT(5), 338 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), 339 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), 340 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), 341 }; 342 343 enum iwl_rx_mpdu_mac_info { 344 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f, 345 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0, 346 }; 347 348 /* TSF overload low dword */ 349 enum iwl_rx_phy_data0 { 350 /* info type: HE any */ 351 IWL_RX_PHY_DATA0_HE_BEAM_CHNG = 0x00000001, 352 IWL_RX_PHY_DATA0_HE_UPLINK = 0x00000002, 353 IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK = 0x000000fc, 354 IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK = 0x00000f00, 355 /* 1 bit reserved */ 356 IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK = 0x000fe000, 357 IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM = 0x00100000, 358 IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK = 0x00600000, 359 IWL_RX_PHY_DATA0_HE_PE_DISAMBIG = 0x00800000, 360 IWL_RX_PHY_DATA0_HE_DOPPLER = 0x01000000, 361 /* 6 bits reserved */ 362 IWL_RX_PHY_DATA0_HE_DELIM_EOF = 0x80000000, 363 }; 364 365 enum iwl_rx_phy_info_type { 366 IWL_RX_PHY_INFO_TYPE_NONE = 0, 367 IWL_RX_PHY_INFO_TYPE_CCK = 1, 368 IWL_RX_PHY_INFO_TYPE_OFDM_LGCY = 2, 369 IWL_RX_PHY_INFO_TYPE_HT = 3, 370 IWL_RX_PHY_INFO_TYPE_VHT_SU = 4, 371 IWL_RX_PHY_INFO_TYPE_VHT_MU = 5, 372 IWL_RX_PHY_INFO_TYPE_HE_SU = 6, 373 IWL_RX_PHY_INFO_TYPE_HE_MU = 7, 374 IWL_RX_PHY_INFO_TYPE_HE_TB = 8, 375 IWL_RX_PHY_INFO_TYPE_HE_MU_EXT = 9, 376 IWL_RX_PHY_INFO_TYPE_HE_TB_EXT = 10, 377 }; 378 379 /* TSF overload high dword */ 380 enum iwl_rx_phy_data1 { 381 /* 382 * check this first - if TSF overload is set, 383 * see &enum iwl_rx_phy_info_type 384 */ 385 IWL_RX_PHY_DATA1_INFO_TYPE_MASK = 0xf0000000, 386 387 /* info type: HT/VHT/HE any */ 388 IWL_RX_PHY_DATA1_LSIG_LEN_MASK = 0x0fff0000, 389 390 /* info type: HE MU/MU-EXT */ 391 IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION = 0x00000001, 392 IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK = 0x0000001e, 393 394 /* info type: HE any */ 395 IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK = 0x000000e0, 396 IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80 = 0x00000100, 397 /* trigger encoded */ 398 IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK = 0x0000fe00, 399 400 /* info type: HE TB/TX-EXT */ 401 IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE = 0x00000001, 402 IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK = 0x0000000e, 403 }; 404 405 /* goes into Metadata DW 7 */ 406 enum iwl_rx_phy_data2 { 407 /* info type: HE MU-EXT */ 408 /* the a1/a2/... is what the PHY/firmware calls the values */ 409 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0 = 0x000000ff, /* a1 */ 410 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2 = 0x0000ff00, /* a2 */ 411 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0 = 0x00ff0000, /* b1 */ 412 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2 = 0xff000000, /* b2 */ 413 414 /* info type: HE TB-EXT */ 415 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1 = 0x0000000f, 416 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2 = 0x000000f0, 417 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3 = 0x00000f00, 418 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4 = 0x0000f000, 419 }; 420 421 /* goes into Metadata DW 8 */ 422 enum iwl_rx_phy_data3 { 423 /* info type: HE MU-EXT */ 424 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1 = 0x000000ff, /* c1 */ 425 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3 = 0x0000ff00, /* c2 */ 426 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1 = 0x00ff0000, /* d1 */ 427 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3 = 0xff000000, /* d2 */ 428 }; 429 430 /* goes into Metadata DW 4 high 16 bits */ 431 enum iwl_rx_phy_data4 { 432 /* info type: HE MU-EXT */ 433 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU = 0x0001, 434 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU = 0x0002, 435 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK = 0x0004, 436 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK = 0x0008, 437 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK = 0x00f0, 438 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM = 0x0100, 439 IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK = 0x0600, 440 }; 441 442 /** 443 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor 444 */ 445 struct iwl_rx_mpdu_desc_v1 { 446 /* DW7 - carries rss_hash only when rpa_en == 1 */ 447 union { 448 /** 449 * @rss_hash: RSS hash value 450 */ 451 __le32 rss_hash; 452 453 /** 454 * @phy_data2: depends on info type (see @phy_data1) 455 */ 456 __le32 phy_data2; 457 }; 458 459 /* DW8 - carries filter_match only when rpa_en == 1 */ 460 union { 461 /** 462 * @filter_match: filter match value 463 */ 464 __le32 filter_match; 465 466 /** 467 * @phy_data3: depends on info type (see @phy_data1) 468 */ 469 __le32 phy_data3; 470 }; 471 472 /* DW9 */ 473 /** 474 * @rate_n_flags: RX rate/flags encoding 475 */ 476 __le32 rate_n_flags; 477 /* DW10 */ 478 /** 479 * @energy_a: energy chain A 480 */ 481 u8 energy_a; 482 /** 483 * @energy_b: energy chain B 484 */ 485 u8 energy_b; 486 /** 487 * @channel: channel number 488 */ 489 u8 channel; 490 /** 491 * @mac_context: MAC context mask 492 */ 493 u8 mac_context; 494 /* DW11 */ 495 /** 496 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 497 */ 498 __le32 gp2_on_air_rise; 499 /* DW12 & DW13 */ 500 union { 501 /** 502 * @tsf_on_air_rise: 503 * TSF value on air rise (INA), only valid if 504 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 505 */ 506 __le64 tsf_on_air_rise; 507 508 struct { 509 /** 510 * @phy_data0: depends on info_type, see @phy_data1 511 */ 512 __le32 phy_data0; 513 /** 514 * @phy_data1: valid only if 515 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 516 * see &enum iwl_rx_phy_data1. 517 */ 518 __le32 phy_data1; 519 }; 520 }; 521 } __packed; 522 523 /** 524 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor 525 */ 526 struct iwl_rx_mpdu_desc_v3 { 527 /* DW7 - carries filter_match only when rpa_en == 1 */ 528 union { 529 /** 530 * @filter_match: filter match value 531 */ 532 __le32 filter_match; 533 534 /** 535 * @phy_data2: depends on info type (see @phy_data1) 536 */ 537 __le32 phy_data2; 538 }; 539 540 /* DW8 - carries rss_hash only when rpa_en == 1 */ 541 union { 542 /** 543 * @rss_hash: RSS hash value 544 */ 545 __le32 rss_hash; 546 547 /** 548 * @phy_data3: depends on info type (see @phy_data1) 549 */ 550 __le32 phy_data3; 551 }; 552 /* DW9 */ 553 /** 554 * @partial_hash: 31:0 ip/tcp header hash 555 * w/o some fields (such as IP SRC addr) 556 */ 557 __le32 partial_hash; 558 /* DW10 */ 559 /** 560 * @raw_xsum: raw xsum value 561 */ 562 __le32 raw_xsum; 563 /* DW11 */ 564 /** 565 * @rate_n_flags: RX rate/flags encoding 566 */ 567 __le32 rate_n_flags; 568 /* DW12 */ 569 /** 570 * @energy_a: energy chain A 571 */ 572 u8 energy_a; 573 /** 574 * @energy_b: energy chain B 575 */ 576 u8 energy_b; 577 /** 578 * @channel: channel number 579 */ 580 u8 channel; 581 /** 582 * @mac_context: MAC context mask 583 */ 584 u8 mac_context; 585 /* DW13 */ 586 /** 587 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 588 */ 589 __le32 gp2_on_air_rise; 590 /* DW14 & DW15 */ 591 union { 592 /** 593 * @tsf_on_air_rise: 594 * TSF value on air rise (INA), only valid if 595 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 596 */ 597 __le64 tsf_on_air_rise; 598 599 struct { 600 /** 601 * @phy_data0: depends on info_type, see @phy_data1 602 */ 603 __le32 phy_data0; 604 /** 605 * @phy_data1: valid only if 606 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 607 * see &enum iwl_rx_phy_data1. 608 */ 609 __le32 phy_data1; 610 }; 611 }; 612 /* DW16 & DW17 */ 613 /** 614 * @reserved: reserved 615 */ 616 __le32 reserved[2]; 617 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */ 618 619 /** 620 * struct iwl_rx_mpdu_desc - RX MPDU descriptor 621 */ 622 struct iwl_rx_mpdu_desc { 623 /* DW2 */ 624 /** 625 * @mpdu_len: MPDU length 626 */ 627 __le16 mpdu_len; 628 /** 629 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1 630 */ 631 u8 mac_flags1; 632 /** 633 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2 634 */ 635 u8 mac_flags2; 636 /* DW3 */ 637 /** 638 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info 639 */ 640 u8 amsdu_info; 641 /** 642 * @phy_info: &enum iwl_rx_mpdu_phy_info 643 */ 644 __le16 phy_info; 645 /** 646 * @mac_phy_idx: MAC/PHY index 647 */ 648 u8 mac_phy_idx; 649 /* DW4 - carries csum data only when rpa_en == 1 */ 650 /** 651 * @raw_csum: raw checksum (alledgedly unreliable) 652 */ 653 __le16 raw_csum; 654 655 union { 656 /** 657 * @l3l4_flags: &enum iwl_rx_l3l4_flags 658 */ 659 __le16 l3l4_flags; 660 661 /** 662 * @phy_data4: depends on info type, see phy_data1 663 */ 664 __le16 phy_data4; 665 }; 666 /* DW5 */ 667 /** 668 * @status: &enum iwl_rx_mpdu_status 669 */ 670 __le16 status; 671 /** 672 * @hash_filter: hash filter value 673 */ 674 u8 hash_filter; 675 /** 676 * @sta_id_flags: &enum iwl_rx_mpdu_sta_id_flags 677 */ 678 u8 sta_id_flags; 679 /* DW6 */ 680 /** 681 * @reorder_data: &enum iwl_rx_mpdu_reorder_data 682 */ 683 __le32 reorder_data; 684 685 union { 686 struct iwl_rx_mpdu_desc_v1 v1; 687 struct iwl_rx_mpdu_desc_v3 v3; 688 }; 689 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */ 690 691 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1) 692 693 #define IWL_CD_STTS_OPTIMIZED_POS 0 694 #define IWL_CD_STTS_OPTIMIZED_MSK 0x01 695 #define IWL_CD_STTS_TRANSFER_STATUS_POS 1 696 #define IWL_CD_STTS_TRANSFER_STATUS_MSK 0x0E 697 #define IWL_CD_STTS_WIFI_STATUS_POS 4 698 #define IWL_CD_STTS_WIFI_STATUS_MSK 0xF0 699 700 #define RX_NO_DATA_CHAIN_A_POS 0 701 #define RX_NO_DATA_CHAIN_A_MSK (0xff << RX_NO_DATA_CHAIN_A_POS) 702 #define RX_NO_DATA_CHAIN_B_POS 8 703 #define RX_NO_DATA_CHAIN_B_MSK (0xff << RX_NO_DATA_CHAIN_B_POS) 704 #define RX_NO_DATA_CHANNEL_POS 16 705 #define RX_NO_DATA_CHANNEL_MSK (0xff << RX_NO_DATA_CHANNEL_POS) 706 707 #define RX_NO_DATA_INFO_TYPE_POS 0 708 #define RX_NO_DATA_INFO_TYPE_MSK (0xff << RX_NO_DATA_INFO_TYPE_POS) 709 #define RX_NO_DATA_INFO_TYPE_NONE 0 710 #define RX_NO_DATA_INFO_TYPE_RX_ERR 1 711 #define RX_NO_DATA_INFO_TYPE_NDP 2 712 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED 3 713 #define RX_NO_DATA_INFO_TYPE_HE_TB_UNMATCHED 4 714 715 #define RX_NO_DATA_INFO_ERR_POS 8 716 #define RX_NO_DATA_INFO_ERR_MSK (0xff << RX_NO_DATA_INFO_ERR_POS) 717 #define RX_NO_DATA_INFO_ERR_NONE 0 718 #define RX_NO_DATA_INFO_ERR_BAD_PLCP 1 719 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE 2 720 #define RX_NO_DATA_INFO_ERR_NO_DELIM 3 721 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR 4 722 723 #define RX_NO_DATA_FRAME_TIME_POS 0 724 #define RX_NO_DATA_FRAME_TIME_MSK (0xfffff << RX_NO_DATA_FRAME_TIME_POS) 725 726 /** 727 * struct iwl_rx_no_data - RX no data descriptor 728 * @info: 7:0 frame type, 15:8 RX error type 729 * @rssi: 7:0 energy chain-A, 730 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 731 * @on_air_rise_time: GP2 during on air rise 732 * @fr_time: frame time 733 * @rate: rate/mcs of frame 734 * @phy_info: &enum iwl_rx_phy_data0 and &enum iwl_rx_phy_info_type 735 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 736 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 737 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 738 */ 739 struct iwl_rx_no_data { 740 __le32 info; 741 __le32 rssi; 742 __le32 on_air_rise_time; 743 __le32 fr_time; 744 __le32 rate; 745 __le32 phy_info[2]; 746 __le32 rx_vec[3]; 747 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1 */ 748 749 /** 750 * enum iwl_completion_desc_transfer_status - transfer status (bits 1-3) 751 * @IWL_CD_STTS_UNUSED: unused 752 * @IWL_CD_STTS_UNUSED_2: unused 753 * @IWL_CD_STTS_END_TRANSFER: successful transfer complete. 754 * In sniffer mode, when split is used, set in last CD completion. (RX) 755 * @IWL_CD_STTS_OVERFLOW: In sniffer mode, when using split - used for 756 * all CD completion. (RX) 757 * @IWL_CD_STTS_ABORTED: CR abort / close flow. (RX) 758 * @IWL_CD_STTS_ERROR: general error (RX) 759 */ 760 enum iwl_completion_desc_transfer_status { 761 IWL_CD_STTS_UNUSED, 762 IWL_CD_STTS_UNUSED_2, 763 IWL_CD_STTS_END_TRANSFER, 764 IWL_CD_STTS_OVERFLOW, 765 IWL_CD_STTS_ABORTED, 766 IWL_CD_STTS_ERROR, 767 }; 768 769 /** 770 * enum iwl_completion_desc_wifi_status - wifi status (bits 4-7) 771 * @IWL_CD_STTS_VALID: the packet is valid (RX) 772 * @IWL_CD_STTS_FCS_ERR: frame check sequence error (RX) 773 * @IWL_CD_STTS_SEC_KEY_ERR: error handling the security key of rx (RX) 774 * @IWL_CD_STTS_DECRYPTION_ERR: error decrypting the frame (RX) 775 * @IWL_CD_STTS_DUP: duplicate packet (RX) 776 * @IWL_CD_STTS_ICV_MIC_ERR: MIC error (RX) 777 * @IWL_CD_STTS_INTERNAL_SNAP_ERR: problems removing the snap (RX) 778 * @IWL_CD_STTS_SEC_PORT_FAIL: security port fail (RX) 779 * @IWL_CD_STTS_BA_OLD_SN: block ack received old SN (RX) 780 * @IWL_CD_STTS_QOS_NULL: QoS null packet (RX) 781 * @IWL_CD_STTS_MAC_HDR_ERR: MAC header conversion error (RX) 782 * @IWL_CD_STTS_MAX_RETRANS: reached max number of retransmissions (TX) 783 * @IWL_CD_STTS_EX_LIFETIME: exceeded lifetime (TX) 784 * @IWL_CD_STTS_NOT_USED: completed but not used (RX) 785 * @IWL_CD_STTS_REPLAY_ERR: pn check failed, replay error (RX) 786 */ 787 enum iwl_completion_desc_wifi_status { 788 IWL_CD_STTS_VALID, 789 IWL_CD_STTS_FCS_ERR, 790 IWL_CD_STTS_SEC_KEY_ERR, 791 IWL_CD_STTS_DECRYPTION_ERR, 792 IWL_CD_STTS_DUP, 793 IWL_CD_STTS_ICV_MIC_ERR, 794 IWL_CD_STTS_INTERNAL_SNAP_ERR, 795 IWL_CD_STTS_SEC_PORT_FAIL, 796 IWL_CD_STTS_BA_OLD_SN, 797 IWL_CD_STTS_QOS_NULL, 798 IWL_CD_STTS_MAC_HDR_ERR, 799 IWL_CD_STTS_MAX_RETRANS, 800 IWL_CD_STTS_EX_LIFETIME, 801 IWL_CD_STTS_NOT_USED, 802 IWL_CD_STTS_REPLAY_ERR, 803 }; 804 805 struct iwl_frame_release { 806 u8 baid; 807 u8 reserved; 808 __le16 nssn; 809 }; 810 811 enum iwl_rss_hash_func_en { 812 IWL_RSS_HASH_TYPE_IPV4_TCP, 813 IWL_RSS_HASH_TYPE_IPV4_UDP, 814 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD, 815 IWL_RSS_HASH_TYPE_IPV6_TCP, 816 IWL_RSS_HASH_TYPE_IPV6_UDP, 817 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 818 }; 819 820 #define IWL_RSS_HASH_KEY_CNT 10 821 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128 822 #define IWL_RSS_ENABLE 1 823 824 /** 825 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration 826 * 827 * @flags: 1 - enable, 0 - disable 828 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en 829 * @reserved: reserved 830 * @secret_key: 320 bit input of random key configuration from driver 831 * @indirection_table: indirection table 832 */ 833 struct iwl_rss_config_cmd { 834 __le32 flags; 835 u8 hash_mask; 836 u8 reserved[3]; 837 __le32 secret_key[IWL_RSS_HASH_KEY_CNT]; 838 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE]; 839 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */ 840 841 #define IWL_MULTI_QUEUE_SYNC_MSG_MAX_SIZE 128 842 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0 843 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf 844 845 /** 846 * struct iwl_rxq_sync_cmd - RXQ notification trigger 847 * 848 * @flags: flags of the notification. bit 0:3 are the sender queue 849 * @rxq_mask: rx queues to send the notification on 850 * @count: number of bytes in payload, should be DWORD aligned 851 * @payload: data to send to rx queues 852 */ 853 struct iwl_rxq_sync_cmd { 854 __le32 flags; 855 __le32 rxq_mask; 856 __le32 count; 857 u8 payload[]; 858 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 859 860 /** 861 * struct iwl_rxq_sync_notification - Notification triggered by RXQ 862 * sync command 863 * 864 * @count: number of bytes in payload 865 * @payload: data to send to rx queues 866 */ 867 struct iwl_rxq_sync_notification { 868 __le32 count; 869 u8 payload[]; 870 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 871 872 /** 873 * enum iwl_mvm_rxq_notif_type - Internal message identifier 874 * 875 * @IWL_MVM_RXQ_EMPTY: empty sync notification 876 * @IWL_MVM_RXQ_NOTIF_DEL_BA: notify RSS queues of delBA 877 */ 878 enum iwl_mvm_rxq_notif_type { 879 IWL_MVM_RXQ_EMPTY, 880 IWL_MVM_RXQ_NOTIF_DEL_BA, 881 }; 882 883 /** 884 * struct iwl_mvm_internal_rxq_notif - Internal representation of the data sent 885 * in &iwl_rxq_sync_cmd. Should be DWORD aligned. 886 * FW is agnostic to the payload, so there are no endianity requirements. 887 * 888 * @type: value from &iwl_mvm_rxq_notif_type 889 * @sync: ctrl path is waiting for all notifications to be received 890 * @cookie: internal cookie to identify old notifications 891 * @data: payload 892 */ 893 struct iwl_mvm_internal_rxq_notif { 894 u16 type; 895 u16 sync; 896 u32 cookie; 897 u8 data[]; 898 } __packed; 899 900 /** 901 * enum iwl_mvm_pm_event - type of station PM event 902 * @IWL_MVM_PM_EVENT_AWAKE: station woke up 903 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep 904 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger 905 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll 906 */ 907 enum iwl_mvm_pm_event { 908 IWL_MVM_PM_EVENT_AWAKE, 909 IWL_MVM_PM_EVENT_ASLEEP, 910 IWL_MVM_PM_EVENT_UAPSD, 911 IWL_MVM_PM_EVENT_PS_POLL, 912 }; /* PEER_PM_NTFY_API_E_VER_1 */ 913 914 /** 915 * struct iwl_mvm_pm_state_notification - station PM state notification 916 * @sta_id: station ID of the station changing state 917 * @type: the new powersave state, see &enum iwl_mvm_pm_event 918 */ 919 struct iwl_mvm_pm_state_notification { 920 u8 sta_id; 921 u8 type; 922 /* private: */ 923 __le16 reserved; 924 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */ 925 926 #define BA_WINDOW_STREAMS_MAX 16 927 #define BA_WINDOW_STATUS_TID_MSK 0x000F 928 #define BA_WINDOW_STATUS_STA_ID_POS 4 929 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0 930 #define BA_WINDOW_STATUS_VALID_MSK BIT(9) 931 932 /** 933 * struct iwl_ba_window_status_notif - reordering window's status notification 934 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63] 935 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid 936 * @start_seq_num: the start sequence number of the bitmap 937 * @mpdu_rx_count: the number of received MPDUs since entering D0i3 938 */ 939 struct iwl_ba_window_status_notif { 940 __le64 bitmap[BA_WINDOW_STREAMS_MAX]; 941 __le16 ra_tid[BA_WINDOW_STREAMS_MAX]; 942 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX]; 943 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX]; 944 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */ 945 946 /** 947 * struct iwl_rfh_queue_config - RX queue configuration 948 * @q_num: Q num 949 * @enable: enable queue 950 * @reserved: alignment 951 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 952 * @fr_bd_cb: DMA address of freeRB table 953 * @ur_bd_cb: DMA address of used RB table 954 * @fr_bd_wid: Initial index of the free table 955 */ 956 struct iwl_rfh_queue_data { 957 u8 q_num; 958 u8 enable; 959 __le16 reserved; 960 __le64 urbd_stts_wrptr; 961 __le64 fr_bd_cb; 962 __le64 ur_bd_cb; 963 __le32 fr_bd_wid; 964 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */ 965 966 /** 967 * struct iwl_rfh_queue_config - RX queue configuration 968 * @num_queues: number of queues configured 969 * @reserved: alignment 970 * @data: DMA addresses per-queue 971 */ 972 struct iwl_rfh_queue_config { 973 u8 num_queues; 974 u8 reserved[3]; 975 struct iwl_rfh_queue_data data[]; 976 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */ 977 978 #endif /* __iwl_fw_api_rx_h__ */ 979