1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /*
3  * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
4  * Copyright (C) 2017 Intel Deutschland GmbH
5  */
6 #ifndef __iwl_fw_api_rs_h__
7 #define __iwl_fw_api_rs_h__
8 
9 #include "mac.h"
10 
11 /**
12  * enum iwl_tlc_mng_cfg_flags_enum - options for TLC config flags
13  * @IWL_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC. For HE this enables STBC for
14  *				    bandwidths <= 80MHz
15  * @IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC
16  * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
17  *					      bandwidth
18  * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK: enable HE Dual Carrier Modulation
19  *					    for BPSK (MCS 0) with 1 spatial
20  *					    stream
21  * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation
22  *					    for BPSK (MCS 0) with 2 spatial
23  *					    streams
24  */
25 enum iwl_tlc_mng_cfg_flags {
26 	IWL_TLC_MNG_CFG_FLAGS_STBC_MSK			= BIT(0),
27 	IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK			= BIT(1),
28 	IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK	= BIT(2),
29 	IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK		= BIT(3),
30 	IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK		= BIT(4),
31 };
32 
33 /**
34  * enum iwl_tlc_mng_cfg_cw - channel width options
35  * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
36  * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
37  * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
38  * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
39  * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
40  */
41 enum iwl_tlc_mng_cfg_cw {
42 	IWL_TLC_MNG_CH_WIDTH_20MHZ,
43 	IWL_TLC_MNG_CH_WIDTH_40MHZ,
44 	IWL_TLC_MNG_CH_WIDTH_80MHZ,
45 	IWL_TLC_MNG_CH_WIDTH_160MHZ,
46 	IWL_TLC_MNG_CH_WIDTH_320MHZ,
47 };
48 
49 /**
50  * enum iwl_tlc_mng_cfg_chains - possible chains
51  * @IWL_TLC_MNG_CHAIN_A_MSK: chain A
52  * @IWL_TLC_MNG_CHAIN_B_MSK: chain B
53  */
54 enum iwl_tlc_mng_cfg_chains {
55 	IWL_TLC_MNG_CHAIN_A_MSK = BIT(0),
56 	IWL_TLC_MNG_CHAIN_B_MSK = BIT(1),
57 };
58 
59 /**
60  * enum iwl_tlc_mng_cfg_mode - supported modes
61  * @IWL_TLC_MNG_MODE_CCK: enable CCK
62  * @IWL_TLC_MNG_MODE_OFDM_NON_HT: enable OFDM (non HT)
63  * @IWL_TLC_MNG_MODE_NON_HT: enable non HT
64  * @IWL_TLC_MNG_MODE_HT: enable HT
65  * @IWL_TLC_MNG_MODE_VHT: enable VHT
66  * @IWL_TLC_MNG_MODE_HE: enable HE
67  * @IWL_TLC_MNG_MODE_EHT: enable EHT
68  */
69 enum iwl_tlc_mng_cfg_mode {
70 	IWL_TLC_MNG_MODE_CCK = 0,
71 	IWL_TLC_MNG_MODE_OFDM_NON_HT = IWL_TLC_MNG_MODE_CCK,
72 	IWL_TLC_MNG_MODE_NON_HT = IWL_TLC_MNG_MODE_CCK,
73 	IWL_TLC_MNG_MODE_HT,
74 	IWL_TLC_MNG_MODE_VHT,
75 	IWL_TLC_MNG_MODE_HE,
76 	IWL_TLC_MNG_MODE_EHT,
77 };
78 
79 /**
80  * enum iwl_tlc_mng_ht_rates - HT/VHT/HE rates
81  * @IWL_TLC_MNG_HT_RATE_MCS0: index of MCS0
82  * @IWL_TLC_MNG_HT_RATE_MCS1: index of MCS1
83  * @IWL_TLC_MNG_HT_RATE_MCS2: index of MCS2
84  * @IWL_TLC_MNG_HT_RATE_MCS3: index of MCS3
85  * @IWL_TLC_MNG_HT_RATE_MCS4: index of MCS4
86  * @IWL_TLC_MNG_HT_RATE_MCS5: index of MCS5
87  * @IWL_TLC_MNG_HT_RATE_MCS6: index of MCS6
88  * @IWL_TLC_MNG_HT_RATE_MCS7: index of MCS7
89  * @IWL_TLC_MNG_HT_RATE_MCS8: index of MCS8
90  * @IWL_TLC_MNG_HT_RATE_MCS9: index of MCS9
91  * @IWL_TLC_MNG_HT_RATE_MCS10: index of MCS10
92  * @IWL_TLC_MNG_HT_RATE_MCS11: index of MCS11
93  * @IWL_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT
94  */
95 enum iwl_tlc_mng_ht_rates {
96 	IWL_TLC_MNG_HT_RATE_MCS0 = 0,
97 	IWL_TLC_MNG_HT_RATE_MCS1,
98 	IWL_TLC_MNG_HT_RATE_MCS2,
99 	IWL_TLC_MNG_HT_RATE_MCS3,
100 	IWL_TLC_MNG_HT_RATE_MCS4,
101 	IWL_TLC_MNG_HT_RATE_MCS5,
102 	IWL_TLC_MNG_HT_RATE_MCS6,
103 	IWL_TLC_MNG_HT_RATE_MCS7,
104 	IWL_TLC_MNG_HT_RATE_MCS8,
105 	IWL_TLC_MNG_HT_RATE_MCS9,
106 	IWL_TLC_MNG_HT_RATE_MCS10,
107 	IWL_TLC_MNG_HT_RATE_MCS11,
108 	IWL_TLC_MNG_HT_RATE_MAX = IWL_TLC_MNG_HT_RATE_MCS11,
109 };
110 
111 enum IWL_TLC_MNG_NSS {
112 	IWL_TLC_NSS_1,
113 	IWL_TLC_NSS_2,
114 	IWL_TLC_NSS_MAX
115 };
116 
117 /**
118  * enum IWL_TLC_MCS_PER_BW - mcs index per BW
119  * @IWL_TLC_MCS_PER_BW_80: mcs for bw - 20Hhz, 40Hhz, 80Hhz
120  * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
121  * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
122  * @IWL_TLC_MCS_PER_BW_NUM_V3: number of entries up to version 3
123  * @IWL_TLC_MCS_PER_BW_NUM_V4: number of entries from version 4
124  */
125 enum IWL_TLC_MCS_PER_BW {
126 	IWL_TLC_MCS_PER_BW_80,
127 	IWL_TLC_MCS_PER_BW_160,
128 	IWL_TLC_MCS_PER_BW_320,
129 	IWL_TLC_MCS_PER_BW_NUM_V3 = IWL_TLC_MCS_PER_BW_160 + 1,
130 	IWL_TLC_MCS_PER_BW_NUM_V4 = IWL_TLC_MCS_PER_BW_320 + 1,
131 };
132 
133 /**
134  * struct iwl_tlc_config_cmd_v3 - TLC configuration
135  * @sta_id: station id
136  * @reserved1: reserved
137  * @max_ch_width: max supported channel width from @enum iwl_tlc_mng_cfg_cw
138  * @mode: &enum iwl_tlc_mng_cfg_mode
139  * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains
140  * @amsdu: TX amsdu is supported
141  * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags
142  * @non_ht_rates: bitmap of supported legacy rates
143  * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per &enum IWL_TLC_MCS_PER_BW
144  *	      <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz).
145  * @max_mpdu_len: max MPDU length, in bytes
146  * @sgi_ch_width_supp: bitmap of SGI support per channel width
147  *		       use BIT(@enum iwl_tlc_mng_cfg_cw)
148  * @reserved2: reserved
149  * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI),
150  *	       set zero for no limit.
151  */
152 struct iwl_tlc_config_cmd_v3 {
153 	u8 sta_id;
154 	u8 reserved1[3];
155 	u8 max_ch_width;
156 	u8 mode;
157 	u8 chains;
158 	u8 amsdu;
159 	__le16 flags;
160 	__le16 non_ht_rates;
161 	__le16 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V3];
162 	__le16 max_mpdu_len;
163 	u8 sgi_ch_width_supp;
164 	u8 reserved2;
165 	__le32 max_tx_op;
166 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_3 */
167 
168 /**
169  * struct iwl_tlc_config_cmd_v4 - TLC configuration
170  * @sta_id: station id
171  * @reserved1: reserved
172  * @max_ch_width: max supported channel width from &enum iwl_tlc_mng_cfg_cw
173  * @mode: &enum iwl_tlc_mng_cfg_mode
174  * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains
175  * @sgi_ch_width_supp: bitmap of SGI support per channel width
176  *		       use BIT(&enum iwl_tlc_mng_cfg_cw)
177  * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags
178  * @non_ht_rates: bitmap of supported legacy rates
179  * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per <nss, channel-width>
180  *	      pair (0 - 80mhz width and below, 1 - 160mhz, 2 - 320mhz).
181  * @max_mpdu_len: max MPDU length, in bytes
182  * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI),
183  *	       set zero for no limit.
184  */
185 struct iwl_tlc_config_cmd_v4 {
186 	u8 sta_id;
187 	u8 reserved1[3];
188 	u8 max_ch_width;
189 	u8 mode;
190 	u8 chains;
191 	u8 sgi_ch_width_supp;
192 	__le16 flags;
193 	__le16 non_ht_rates;
194 	__le16 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V4];
195 	__le16 max_mpdu_len;
196 	__le16 max_tx_op;
197 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_4 */
198 
199 /**
200  * enum iwl_tlc_update_flags - updated fields
201  * @IWL_TLC_NOTIF_FLAG_RATE: last initial rate update
202  * @IWL_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update
203  */
204 enum iwl_tlc_update_flags {
205 	IWL_TLC_NOTIF_FLAG_RATE  = BIT(0),
206 	IWL_TLC_NOTIF_FLAG_AMSDU = BIT(1),
207 };
208 
209 /**
210  * struct iwl_tlc_update_notif - TLC notification from FW
211  * @sta_id: station id
212  * @reserved: reserved
213  * @flags: bitmap of notifications reported
214  * @rate: current initial rate
215  * @amsdu_size: Max AMSDU size, in bytes
216  * @amsdu_enabled: bitmap for per-TID AMSDU enablement
217  */
218 struct iwl_tlc_update_notif {
219 	u8 sta_id;
220 	u8 reserved[3];
221 	__le32 flags;
222 	__le32 rate;
223 	__le32 amsdu_size;
224 	__le32 amsdu_enabled;
225 } __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2 */
226 
227 
228 #define IWL_MAX_MCS_DISPLAY_SIZE        12
229 
230 struct iwl_rate_mcs_info {
231 	char    mbps[IWL_MAX_MCS_DISPLAY_SIZE];
232 	char    mcs[IWL_MAX_MCS_DISPLAY_SIZE];
233 };
234 
235 /*
236  * These serve as indexes into
237  * struct iwl_rate_info fw_rate_idx_to_plcp[IWL_RATE_COUNT];
238  * TODO: avoid overlap between legacy and HT rates
239  */
240 enum {
241 	IWL_RATE_1M_INDEX = 0,
242 	IWL_FIRST_CCK_RATE = IWL_RATE_1M_INDEX,
243 	IWL_RATE_2M_INDEX,
244 	IWL_RATE_5M_INDEX,
245 	IWL_RATE_11M_INDEX,
246 	IWL_LAST_CCK_RATE = IWL_RATE_11M_INDEX,
247 	IWL_RATE_6M_INDEX,
248 	IWL_FIRST_OFDM_RATE = IWL_RATE_6M_INDEX,
249 	IWL_RATE_MCS_0_INDEX = IWL_RATE_6M_INDEX,
250 	IWL_FIRST_HT_RATE = IWL_RATE_MCS_0_INDEX,
251 	IWL_FIRST_VHT_RATE = IWL_RATE_MCS_0_INDEX,
252 	IWL_RATE_9M_INDEX,
253 	IWL_RATE_12M_INDEX,
254 	IWL_RATE_MCS_1_INDEX = IWL_RATE_12M_INDEX,
255 	IWL_RATE_18M_INDEX,
256 	IWL_RATE_MCS_2_INDEX = IWL_RATE_18M_INDEX,
257 	IWL_RATE_24M_INDEX,
258 	IWL_RATE_MCS_3_INDEX = IWL_RATE_24M_INDEX,
259 	IWL_RATE_36M_INDEX,
260 	IWL_RATE_MCS_4_INDEX = IWL_RATE_36M_INDEX,
261 	IWL_RATE_48M_INDEX,
262 	IWL_RATE_MCS_5_INDEX = IWL_RATE_48M_INDEX,
263 	IWL_RATE_54M_INDEX,
264 	IWL_RATE_MCS_6_INDEX = IWL_RATE_54M_INDEX,
265 	IWL_LAST_NON_HT_RATE = IWL_RATE_54M_INDEX,
266 	IWL_RATE_60M_INDEX,
267 	IWL_RATE_MCS_7_INDEX = IWL_RATE_60M_INDEX,
268 	IWL_LAST_HT_RATE = IWL_RATE_MCS_7_INDEX,
269 	IWL_RATE_MCS_8_INDEX,
270 	IWL_RATE_MCS_9_INDEX,
271 	IWL_LAST_VHT_RATE = IWL_RATE_MCS_9_INDEX,
272 	IWL_RATE_MCS_10_INDEX,
273 	IWL_RATE_MCS_11_INDEX,
274 	IWL_LAST_HE_RATE = IWL_RATE_MCS_11_INDEX,
275 	IWL_RATE_COUNT_LEGACY = IWL_LAST_NON_HT_RATE + 1,
276 	IWL_RATE_COUNT = IWL_LAST_HE_RATE + 1,
277 	IWL_RATE_INVM_INDEX = IWL_RATE_COUNT,
278 	IWL_RATE_INVALID = IWL_RATE_COUNT,
279 };
280 
281 #define IWL_RATE_BIT_MSK(r) BIT(IWL_RATE_##r##M_INDEX)
282 
283 /* fw API values for legacy bit rates, both OFDM and CCK */
284 enum {
285 	IWL_RATE_6M_PLCP  = 13,
286 	IWL_RATE_9M_PLCP  = 15,
287 	IWL_RATE_12M_PLCP = 5,
288 	IWL_RATE_18M_PLCP = 7,
289 	IWL_RATE_24M_PLCP = 9,
290 	IWL_RATE_36M_PLCP = 11,
291 	IWL_RATE_48M_PLCP = 1,
292 	IWL_RATE_54M_PLCP = 3,
293 	IWL_RATE_1M_PLCP  = 10,
294 	IWL_RATE_2M_PLCP  = 20,
295 	IWL_RATE_5M_PLCP  = 55,
296 	IWL_RATE_11M_PLCP = 110,
297 	IWL_RATE_INVM_PLCP = -1,
298 };
299 
300 /*
301  * rate_n_flags bit fields version 1
302  *
303  * The 32-bit value has different layouts in the low 8 bites depending on the
304  * format. There are three formats, HT, VHT and legacy (11abg, with subformats
305  * for CCK and OFDM).
306  *
307  * High-throughput (HT) rate format
308  *	bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
309  * Very High-throughput (VHT) rate format
310  *	bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
311  * Legacy OFDM rate format for bits 7:0
312  *	bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
313  * Legacy CCK rate format for bits 7:0:
314  *	bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
315  */
316 
317 /* Bit 8: (1) HT format, (0) legacy or VHT format */
318 #define RATE_MCS_HT_POS 8
319 #define RATE_MCS_HT_MSK_V1 BIT(RATE_MCS_HT_POS)
320 
321 /* Bit 9: (1) CCK, (0) OFDM.  HT (bit 8) must be "0" for this bit to be valid */
322 #define RATE_MCS_CCK_POS_V1 9
323 #define RATE_MCS_CCK_MSK_V1 BIT(RATE_MCS_CCK_POS_V1)
324 
325 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
326 #define RATE_MCS_VHT_POS_V1 26
327 #define RATE_MCS_VHT_MSK_V1 BIT(RATE_MCS_VHT_POS_V1)
328 
329 
330 /*
331  * High-throughput (HT) rate format for bits 7:0
332  *
333  *  2-0:  MCS rate base
334  *        0)   6 Mbps
335  *        1)  12 Mbps
336  *        2)  18 Mbps
337  *        3)  24 Mbps
338  *        4)  36 Mbps
339  *        5)  48 Mbps
340  *        6)  54 Mbps
341  *        7)  60 Mbps
342  *  4-3:  0)  Single stream (SISO)
343  *        1)  Dual stream (MIMO)
344  *        2)  Triple stream (MIMO)
345  *    5:  Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
346  *  (bits 7-6 are zero)
347  *
348  * Together the low 5 bits work out to the MCS index because we don't
349  * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
350  * streams and 16-23 have three streams. We could also support MCS 32
351  * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
352  */
353 #define RATE_HT_MCS_RATE_CODE_MSK_V1	0x7
354 #define RATE_HT_MCS_NSS_POS_V1          3
355 #define RATE_HT_MCS_NSS_MSK_V1          (3 << RATE_HT_MCS_NSS_POS_V1)
356 #define RATE_HT_MCS_MIMO2_MSK		BIT(RATE_HT_MCS_NSS_POS_V1)
357 
358 /* Bit 10: (1) Use Green Field preamble */
359 #define RATE_HT_MCS_GF_POS		10
360 #define RATE_HT_MCS_GF_MSK		(1 << RATE_HT_MCS_GF_POS)
361 
362 #define RATE_HT_MCS_INDEX_MSK_V1	0x3f
363 
364 /*
365  * Very High-throughput (VHT) rate format for bits 7:0
366  *
367  *  3-0:  VHT MCS (0-9)
368  *  5-4:  number of streams - 1:
369  *        0)  Single stream (SISO)
370  *        1)  Dual stream (MIMO)
371  *        2)  Triple stream (MIMO)
372  */
373 
374 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
375 #define RATE_VHT_MCS_RATE_CODE_MSK	0xf
376 
377 /*
378  * Legacy OFDM rate format for bits 7:0
379  *
380  *  3-0:  0xD)   6 Mbps
381  *        0xF)   9 Mbps
382  *        0x5)  12 Mbps
383  *        0x7)  18 Mbps
384  *        0x9)  24 Mbps
385  *        0xB)  36 Mbps
386  *        0x1)  48 Mbps
387  *        0x3)  54 Mbps
388  * (bits 7-4 are 0)
389  *
390  * Legacy CCK rate format for bits 7:0:
391  * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
392  *
393  *  6-0:   10)  1 Mbps
394  *         20)  2 Mbps
395  *         55)  5.5 Mbps
396  *        110)  11 Mbps
397  * (bit 7 is 0)
398  */
399 #define RATE_LEGACY_RATE_MSK_V1 0xff
400 
401 /* Bit 10 - OFDM HE */
402 #define RATE_MCS_HE_POS_V1	10
403 #define RATE_MCS_HE_MSK_V1	BIT(RATE_MCS_HE_POS_V1)
404 
405 /*
406  * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
407  * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
408  */
409 #define RATE_MCS_CHAN_WIDTH_POS		11
410 #define RATE_MCS_CHAN_WIDTH_MSK_V1	(3 << RATE_MCS_CHAN_WIDTH_POS)
411 
412 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
413 #define RATE_MCS_SGI_POS_V1		13
414 #define RATE_MCS_SGI_MSK_V1		BIT(RATE_MCS_SGI_POS_V1)
415 
416 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
417 #define RATE_MCS_ANT_POS		14
418 #define RATE_MCS_ANT_A_MSK		(1 << RATE_MCS_ANT_POS)
419 #define RATE_MCS_ANT_B_MSK		(2 << RATE_MCS_ANT_POS)
420 #define RATE_MCS_ANT_AB_MSK		(RATE_MCS_ANT_A_MSK | \
421 					 RATE_MCS_ANT_B_MSK)
422 #define RATE_MCS_ANT_MSK		RATE_MCS_ANT_AB_MSK
423 
424 /* Bit 17: (0) SS, (1) SS*2 */
425 #define RATE_MCS_STBC_POS		17
426 #define RATE_MCS_STBC_MSK		BIT(RATE_MCS_STBC_POS)
427 
428 /* Bit 18: OFDM-HE dual carrier mode */
429 #define RATE_HE_DUAL_CARRIER_MODE	18
430 #define RATE_HE_DUAL_CARRIER_MODE_MSK	BIT(RATE_HE_DUAL_CARRIER_MODE)
431 
432 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
433 #define RATE_MCS_BF_POS			19
434 #define RATE_MCS_BF_MSK			(1 << RATE_MCS_BF_POS)
435 
436 /*
437  * Bit 20-21: HE LTF type and guard interval
438  * HE (ext) SU:
439  *	0			1xLTF+0.8us
440  *	1			2xLTF+0.8us
441  *	2			2xLTF+1.6us
442  *	3 & SGI (bit 13) clear	4xLTF+3.2us
443  *	3 & SGI (bit 13) set	4xLTF+0.8us
444  * HE MU:
445  *	0			4xLTF+0.8us
446  *	1			2xLTF+0.8us
447  *	2			2xLTF+1.6us
448  *	3			4xLTF+3.2us
449  * HE-EHT TRIG:
450  *	0			1xLTF+1.6us
451  *	1			2xLTF+1.6us
452  *	2			4xLTF+3.2us
453  *	3			(does not occur)
454  * EHT MU:
455  *	0			2xLTF+0.8us
456  *	1			2xLTF+1.6us
457  *	2			4xLTF+0.8us
458  *	3			4xLTF+3.2us
459  */
460 #define RATE_MCS_HE_GI_LTF_POS		20
461 #define RATE_MCS_HE_GI_LTF_MSK_V1		(3 << RATE_MCS_HE_GI_LTF_POS)
462 
463 /* Bit 22-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */
464 #define RATE_MCS_HE_TYPE_POS_V1		22
465 #define RATE_MCS_HE_TYPE_SU_V1		(0 << RATE_MCS_HE_TYPE_POS_V1)
466 #define RATE_MCS_HE_TYPE_EXT_SU_V1		BIT(RATE_MCS_HE_TYPE_POS_V1)
467 #define RATE_MCS_HE_TYPE_MU_V1		(2 << RATE_MCS_HE_TYPE_POS_V1)
468 #define RATE_MCS_HE_TYPE_TRIG_V1	(3 << RATE_MCS_HE_TYPE_POS_V1)
469 #define RATE_MCS_HE_TYPE_MSK_V1		(3 << RATE_MCS_HE_TYPE_POS_V1)
470 
471 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
472 #define RATE_MCS_DUP_POS_V1		24
473 #define RATE_MCS_DUP_MSK_V1		(3 << RATE_MCS_DUP_POS_V1)
474 
475 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
476 #define RATE_MCS_LDPC_POS_V1		27
477 #define RATE_MCS_LDPC_MSK_V1		BIT(RATE_MCS_LDPC_POS_V1)
478 
479 /* Bit 28: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */
480 #define RATE_MCS_HE_106T_POS_V1		28
481 #define RATE_MCS_HE_106T_MSK_V1		BIT(RATE_MCS_HE_106T_POS_V1)
482 
483 /* Bit 30-31: (1) RTS, (2) CTS */
484 #define RATE_MCS_RTS_REQUIRED_POS  (30)
485 #define RATE_MCS_RTS_REQUIRED_MSK  (0x1 << RATE_MCS_RTS_REQUIRED_POS)
486 
487 #define RATE_MCS_CTS_REQUIRED_POS  (31)
488 #define RATE_MCS_CTS_REQUIRED_MSK  (0x1 << RATE_MCS_CTS_REQUIRED_POS)
489 
490 /* rate_n_flags bit field version 2
491  *
492  * The 32-bit value has different layouts in the low 8 bits depending on the
493  * format. There are three formats, HT, VHT and legacy (11abg, with subformats
494  * for CCK and OFDM).
495  *
496  */
497 
498 /* Bits 10-8: rate format
499  * (0) Legacy CCK (1) Legacy OFDM (2) High-throughput (HT)
500  * (3) Very High-throughput (VHT) (4) High-efficiency (HE)
501  * (5) Extremely High-throughput (EHT)
502  */
503 #define RATE_MCS_MOD_TYPE_POS		8
504 #define RATE_MCS_MOD_TYPE_MSK		(0x7 << RATE_MCS_MOD_TYPE_POS)
505 #define RATE_MCS_CCK_MSK		(0 << RATE_MCS_MOD_TYPE_POS)
506 #define RATE_MCS_LEGACY_OFDM_MSK	(1 << RATE_MCS_MOD_TYPE_POS)
507 #define RATE_MCS_HT_MSK			(2 << RATE_MCS_MOD_TYPE_POS)
508 #define RATE_MCS_VHT_MSK		(3 << RATE_MCS_MOD_TYPE_POS)
509 #define RATE_MCS_HE_MSK			(4 << RATE_MCS_MOD_TYPE_POS)
510 #define RATE_MCS_EHT_MSK		(5 << RATE_MCS_MOD_TYPE_POS)
511 
512 /*
513  * Legacy CCK rate format for bits 0:3:
514  *
515  * (0) 0xa - 1 Mbps
516  * (1) 0x14 - 2 Mbps
517  * (2) 0x37 - 5.5 Mbps
518  * (3) 0x6e - 11 nbps
519  *
520  * Legacy OFDM rate format for bis 3:0:
521  *
522  * (0) 6 Mbps
523  * (1) 9 Mbps
524  * (2) 12 Mbps
525  * (3) 18 Mbps
526  * (4) 24 Mbps
527  * (5) 36 Mbps
528  * (6) 48 Mbps
529  * (7) 54 Mbps
530  *
531  */
532 #define RATE_LEGACY_RATE_MSK		0x7
533 
534 /*
535  * HT, VHT, HE, EHT rate format for bits 3:0
536  * 3-0: MCS
537  *
538  */
539 #define RATE_HT_MCS_CODE_MSK		0x7
540 #define RATE_MCS_NSS_POS		4
541 #define RATE_MCS_NSS_MSK		(1 << RATE_MCS_NSS_POS)
542 #define RATE_MCS_CODE_MSK		0xf
543 #define RATE_HT_MCS_INDEX(r)		((((r) & RATE_MCS_NSS_MSK) >> 1) | \
544 					 ((r) & RATE_HT_MCS_CODE_MSK))
545 
546 /* Bits 7-5: reserved */
547 
548 /*
549  * Bits 13-11: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz, (4) 320MHz
550  */
551 #define RATE_MCS_CHAN_WIDTH_MSK		(0x7 << RATE_MCS_CHAN_WIDTH_POS)
552 #define RATE_MCS_CHAN_WIDTH_20_VAL	0
553 #define RATE_MCS_CHAN_WIDTH_20		(RATE_MCS_CHAN_WIDTH_20_VAL << RATE_MCS_CHAN_WIDTH_POS)
554 #define RATE_MCS_CHAN_WIDTH_40_VAL	1
555 #define RATE_MCS_CHAN_WIDTH_40		(RATE_MCS_CHAN_WIDTH_40_VAL << RATE_MCS_CHAN_WIDTH_POS)
556 #define RATE_MCS_CHAN_WIDTH_80_VAL	2
557 #define RATE_MCS_CHAN_WIDTH_80		(RATE_MCS_CHAN_WIDTH_80_VAL << RATE_MCS_CHAN_WIDTH_POS)
558 #define RATE_MCS_CHAN_WIDTH_160_VAL	3
559 #define RATE_MCS_CHAN_WIDTH_160		(RATE_MCS_CHAN_WIDTH_160_VAL << RATE_MCS_CHAN_WIDTH_POS)
560 #define RATE_MCS_CHAN_WIDTH_320_VAL	4
561 #define RATE_MCS_CHAN_WIDTH_320		(RATE_MCS_CHAN_WIDTH_320_VAL << RATE_MCS_CHAN_WIDTH_POS)
562 
563 /* Bit 15-14: Antenna selection:
564  * Bit 14: Ant A active
565  * Bit 15: Ant B active
566  *
567  * All relevant definitions are same as in v1
568  */
569 
570 /* Bit 16 (1) LDPC enables, (0) LDPC disabled */
571 #define RATE_MCS_LDPC_POS	16
572 #define RATE_MCS_LDPC_MSK	(1 << RATE_MCS_LDPC_POS)
573 
574 /* Bit 17: (0) SS, (1) SS*2 (same as v1) */
575 
576 /* Bit 18: OFDM-HE dual carrier mode (same as v1) */
577 
578 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on (same as v1) */
579 
580 /*
581  * Bit 22-20: HE LTF type and guard interval
582  * CCK:
583  *	0			long preamble
584  *	1			short preamble
585  * HT/VHT:
586  *	0			0.8us
587  *	1			0.4us
588  * HE (ext) SU:
589  *	0			1xLTF+0.8us
590  *	1			2xLTF+0.8us
591  *	2			2xLTF+1.6us
592  *	3			4xLTF+3.2us
593  *	4			4xLTF+0.8us
594  * HE MU:
595  *	0			4xLTF+0.8us
596  *	1			2xLTF+0.8us
597  *	2			2xLTF+1.6us
598  *	3			4xLTF+3.2us
599  * HE TRIG:
600  *	0			1xLTF+1.6us
601  *	1			2xLTF+1.6us
602  *	2			4xLTF+3.2us
603  * */
604 #define RATE_MCS_HE_GI_LTF_MSK		(0x7 << RATE_MCS_HE_GI_LTF_POS)
605 #define RATE_MCS_SGI_POS		RATE_MCS_HE_GI_LTF_POS
606 #define RATE_MCS_SGI_MSK		(1 << RATE_MCS_SGI_POS)
607 #define RATE_MCS_HE_SU_4_LTF		3
608 #define RATE_MCS_HE_SU_4_LTF_08_GI	4
609 
610 /* Bit 24-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */
611 #define RATE_MCS_HE_TYPE_POS		23
612 #define RATE_MCS_HE_TYPE_SU		(0 << RATE_MCS_HE_TYPE_POS)
613 #define RATE_MCS_HE_TYPE_EXT_SU		(1 << RATE_MCS_HE_TYPE_POS)
614 #define RATE_MCS_HE_TYPE_MU		(2 << RATE_MCS_HE_TYPE_POS)
615 #define RATE_MCS_HE_TYPE_TRIG		(3 << RATE_MCS_HE_TYPE_POS)
616 #define RATE_MCS_HE_TYPE_MSK		(3 << RATE_MCS_HE_TYPE_POS)
617 
618 /* Bit 25: duplicate channel enabled
619  *
620  * if this bit is set, duplicate is according to BW (bits 11-13):
621  *
622  * CCK:  2x 20MHz
623  * OFDM Legacy: N x 20Mhz, (N = BW \ 2 , either 2, 4, 8, 16)
624  * EHT: 2 x BW/2, (80 - 2x40, 160 - 2x80, 320 - 2x160)
625  * */
626 #define RATE_MCS_DUP_POS		25
627 #define RATE_MCS_DUP_MSK		(1 << RATE_MCS_DUP_POS)
628 
629 /* Bit 26: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */
630 #define RATE_MCS_HE_106T_POS		26
631 #define RATE_MCS_HE_106T_MSK		(1 << RATE_MCS_HE_106T_POS)
632 
633 /* Bit 27: EHT extra LTF:
634  * instead of 1 LTF for SISO use 2 LTFs,
635  * instead of 2 LTFs for NSTS=2 use 4 LTFs*/
636 #define RATE_MCS_EHT_EXTRA_LTF_POS	27
637 #define RATE_MCS_EHT_EXTRA_LTF_MSK	(1 << RATE_MCS_EHT_EXTRA_LTF_POS)
638 
639 /* Bit 31-28: reserved */
640 
641 /* Link Quality definitions */
642 
643 /* # entries in rate scale table to support Tx retries */
644 #define  LQ_MAX_RETRY_NUM 16
645 
646 /* Link quality command flags bit fields */
647 
648 /* Bit 0: (0) Don't use RTS (1) Use RTS */
649 #define LQ_FLAG_USE_RTS_POS             0
650 #define LQ_FLAG_USE_RTS_MSK	        (1 << LQ_FLAG_USE_RTS_POS)
651 
652 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
653 #define LQ_FLAG_COLOR_POS               1
654 #define LQ_FLAG_COLOR_MSK               (7 << LQ_FLAG_COLOR_POS)
655 #define LQ_FLAG_COLOR_GET(_f)		(((_f) & LQ_FLAG_COLOR_MSK) >>\
656 					 LQ_FLAG_COLOR_POS)
657 #define LQ_FLAGS_COLOR_INC(_c)		((((_c) + 1) << LQ_FLAG_COLOR_POS) &\
658 					 LQ_FLAG_COLOR_MSK)
659 #define LQ_FLAG_COLOR_SET(_f, _c)	((_c) | ((_f) & ~LQ_FLAG_COLOR_MSK))
660 
661 /* Bit 4-5: Tx RTS BW Signalling
662  * (0) No RTS BW signalling
663  * (1) Static BW signalling
664  * (2) Dynamic BW signalling
665  */
666 #define LQ_FLAG_RTS_BW_SIG_POS          4
667 #define LQ_FLAG_RTS_BW_SIG_NONE         (0 << LQ_FLAG_RTS_BW_SIG_POS)
668 #define LQ_FLAG_RTS_BW_SIG_STATIC       (1 << LQ_FLAG_RTS_BW_SIG_POS)
669 #define LQ_FLAG_RTS_BW_SIG_DYNAMIC      (2 << LQ_FLAG_RTS_BW_SIG_POS)
670 
671 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
672  * Dyanmic BW selection allows Tx with narrower BW then requested in rates
673  */
674 #define LQ_FLAG_DYNAMIC_BW_POS          6
675 #define LQ_FLAG_DYNAMIC_BW_MSK          (1 << LQ_FLAG_DYNAMIC_BW_POS)
676 
677 /* Single Stream Tx Parameters (lq_cmd->ss_params)
678  * Flags to control a smart FW decision about whether BFER/STBC/SISO will be
679  * used for single stream Tx.
680  */
681 
682 /* Bit 0-1: Max STBC streams allowed. Can be 0-3.
683  * (0) - No STBC allowed
684  * (1) - 2x1 STBC allowed (HT/VHT)
685  * (2) - 4x2 STBC allowed (HT/VHT)
686  * (3) - 3x2 STBC allowed (HT only)
687  * All our chips are at most 2 antennas so only (1) is valid for now.
688  */
689 #define LQ_SS_STBC_ALLOWED_POS          0
690 #define LQ_SS_STBC_ALLOWED_MSK		(3 << LQ_SS_STBC_ALLOWED_MSK)
691 
692 /* 2x1 STBC is allowed */
693 #define LQ_SS_STBC_1SS_ALLOWED		(1 << LQ_SS_STBC_ALLOWED_POS)
694 
695 /* Bit 2: Beamformer (VHT only) is allowed */
696 #define LQ_SS_BFER_ALLOWED_POS		2
697 #define LQ_SS_BFER_ALLOWED		(1 << LQ_SS_BFER_ALLOWED_POS)
698 
699 /* Bit 3: Force BFER or STBC for testing
700  * If this is set:
701  * If BFER is allowed then force the ucode to choose BFER else
702  * If STBC is allowed then force the ucode to choose STBC over SISO
703  */
704 #define LQ_SS_FORCE_POS			3
705 #define LQ_SS_FORCE			(1 << LQ_SS_FORCE_POS)
706 
707 /* Bit 31: ss_params field is valid. Used for FW backward compatibility
708  * with other drivers which don't support the ss_params API yet
709  */
710 #define LQ_SS_PARAMS_VALID_POS		31
711 #define LQ_SS_PARAMS_VALID		(1 << LQ_SS_PARAMS_VALID_POS)
712 
713 /**
714  * struct iwl_lq_cmd - link quality command
715  * @sta_id: station to update
716  * @reduced_tpc: reduced transmit power control value
717  * @control: not used
718  * @flags: combination of LQ_FLAG_*
719  * @mimo_delim: the first SISO index in rs_table, which separates MIMO
720  *	and SISO rates
721  * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
722  *	Should be ANT_[ABC]
723  * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
724  * @initial_rate_index: first index from rs_table per AC category
725  * @agg_time_limit: aggregation max time threshold in usec/100, meaning
726  *	value of 100 is one usec. Range is 100 to 8000
727  * @agg_disable_start_th: try-count threshold for starting aggregation.
728  *	If a frame has higher try-count, it should not be selected for
729  *	starting an aggregation sequence.
730  * @agg_frame_cnt_limit: max frame count in an aggregation.
731  *	0: no limit
732  *	1: no aggregation (one frame per aggregation)
733  *	2 - 0x3f: maximal number of frames (up to 3f == 63)
734  * @reserved2: reserved
735  * @rs_table: array of rates for each TX try, each is rate_n_flags,
736  *	meaning it is a combination of RATE_MCS_* and IWL_RATE_*_PLCP
737  * @ss_params: single stream features. declare whether STBC or BFER are allowed.
738  */
739 struct iwl_lq_cmd {
740 	u8 sta_id;
741 	u8 reduced_tpc;
742 	__le16 control;
743 	/* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
744 	u8 flags;
745 	u8 mimo_delim;
746 	u8 single_stream_ant_msk;
747 	u8 dual_stream_ant_msk;
748 	u8 initial_rate_index[AC_NUM];
749 	/* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
750 	__le16 agg_time_limit;
751 	u8 agg_disable_start_th;
752 	u8 agg_frame_cnt_limit;
753 	__le32 reserved2;
754 	__le32 rs_table[LQ_MAX_RETRY_NUM];
755 	__le32 ss_params;
756 }; /* LINK_QUALITY_CMD_API_S_VER_1 */
757 
758 u8 iwl_fw_rate_idx_to_plcp(int idx);
759 u32 iwl_new_rate_from_v1(u32 rate_v1);
760 const struct iwl_rate_mcs_info *iwl_rate_mcs(int idx);
761 const char *iwl_rs_pretty_ant(u8 ant);
762 const char *iwl_rs_pretty_bw(int bw);
763 int rs_pretty_print_rate(char *buf, int bufsz, const u32 rate);
764 bool iwl_he_is_sgi(u32 rate_n_flags);
765 
766 #endif /* __iwl_fw_api_rs_h__ */
767