1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 9 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 10 * Copyright(c) 2007 - 2014, 2018 - 2020 Intel Corporation 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * The full GNU General Public License is included in this distribution 22 * in the file called COPYING. 23 * 24 * Contact Information: 25 * Intel Linux Wireless <linuxwifi@intel.com> 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27 * 28 * BSD LICENSE 29 * 30 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 31 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 32 * Copyright(c) 2005 - 2014, 2018 - 2020 Intel Corporation 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 39 * * Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * * Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in 43 * the documentation and/or other materials provided with the 44 * distribution. 45 * * Neither the name Intel Corporation nor the names of its 46 * contributors may be used to endorse or promote products derived 47 * from this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 50 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 51 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 52 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 53 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 55 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 59 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 *****************************************************************************/ 62 #ifndef __iwl_fw_api_debug_h__ 63 #define __iwl_fw_api_debug_h__ 64 65 /** 66 * enum iwl_debug_cmds - debug commands 67 */ 68 enum iwl_debug_cmds { 69 /** 70 * @LMAC_RD_WR: 71 * LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and 72 * &struct iwl_dbg_mem_access_rsp 73 */ 74 LMAC_RD_WR = 0x0, 75 /** 76 * @UMAC_RD_WR: 77 * UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and 78 * &struct iwl_dbg_mem_access_rsp 79 */ 80 UMAC_RD_WR = 0x1, 81 /** 82 * @DBGC_SUSPEND_RESUME: 83 * DBGC suspend/resume commad. Uses a single dword as data: 84 * 0 - resume DBGC recording 85 * 1 - suspend DBGC recording 86 */ 87 DBGC_SUSPEND_RESUME = 0x7, 88 /** 89 * @BUFFER_ALLOCATION: 90 * passes DRAM buffers to a DBGC 91 * &struct iwl_buf_alloc_cmd 92 */ 93 BUFFER_ALLOCATION = 0x8, 94 /** 95 * @MFU_ASSERT_DUMP_NTF: 96 * &struct iwl_mfu_assert_dump_notif 97 */ 98 MFU_ASSERT_DUMP_NTF = 0xFE, 99 }; 100 101 /* Error response/notification */ 102 enum { 103 FW_ERR_UNKNOWN_CMD = 0x0, 104 FW_ERR_INVALID_CMD_PARAM = 0x1, 105 FW_ERR_SERVICE = 0x2, 106 FW_ERR_ARC_MEMORY = 0x3, 107 FW_ERR_ARC_CODE = 0x4, 108 FW_ERR_WATCH_DOG = 0x5, 109 FW_ERR_WEP_GRP_KEY_INDX = 0x10, 110 FW_ERR_WEP_KEY_SIZE = 0x11, 111 FW_ERR_OBSOLETE_FUNC = 0x12, 112 FW_ERR_UNEXPECTED = 0xFE, 113 FW_ERR_FATAL = 0xFF 114 }; 115 116 /** enum iwl_dbg_suspend_resume_cmds - dbgc suspend resume operations 117 * dbgc suspend resume command operations 118 * @DBGC_RESUME_CMD: resume dbgc recording 119 * @DBGC_SUSPEND_CMD: stop dbgc recording 120 */ 121 enum iwl_dbg_suspend_resume_cmds { 122 DBGC_RESUME_CMD, 123 DBGC_SUSPEND_CMD, 124 }; 125 126 /** 127 * struct iwl_error_resp - FW error indication 128 * ( REPLY_ERROR = 0x2 ) 129 * @error_type: one of FW_ERR_* 130 * @cmd_id: the command ID for which the error occurred 131 * @reserved1: reserved 132 * @bad_cmd_seq_num: sequence number of the erroneous command 133 * @error_service: which service created the error, applicable only if 134 * error_type = 2, otherwise 0 135 * @timestamp: TSF in usecs. 136 */ 137 struct iwl_error_resp { 138 __le32 error_type; 139 u8 cmd_id; 140 u8 reserved1; 141 __le16 bad_cmd_seq_num; 142 __le32 error_service; 143 __le64 timestamp; 144 } __packed; 145 146 #define TX_FIFO_MAX_NUM_9000 8 147 #define TX_FIFO_MAX_NUM 15 148 #define RX_FIFO_MAX_NUM 2 149 #define TX_FIFO_INTERNAL_MAX_NUM 6 150 151 /** 152 * struct iwl_shared_mem_cfg_v2 - Shared memory configuration information 153 * 154 * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not 155 * accessible) 156 * @shared_mem_size: shared memory size 157 * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to 158 * 0x0 as accessible only via DBGM RDAT) 159 * @sample_buff_size: internal sample buff size 160 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre 161 * 8000 HW set to 0x0 as not accessible) 162 * @txfifo_size: size of TXF0 ... TXF7 163 * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0 164 * @page_buff_addr: used by UMAC and performance debug (page miss analysis), 165 * when paging is not supported this should be 0 166 * @page_buff_size: size of %page_buff_addr 167 * @rxfifo_addr: Start address of rxFifo 168 * @internal_txfifo_addr: start address of internalFifo 169 * @internal_txfifo_size: internal fifos' size 170 * 171 * NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 172 * set, the last 3 members don't exist. 173 */ 174 struct iwl_shared_mem_cfg_v2 { 175 __le32 shared_mem_addr; 176 __le32 shared_mem_size; 177 __le32 sample_buff_addr; 178 __le32 sample_buff_size; 179 __le32 txfifo_addr; 180 __le32 txfifo_size[TX_FIFO_MAX_NUM_9000]; 181 __le32 rxfifo_size[RX_FIFO_MAX_NUM]; 182 __le32 page_buff_addr; 183 __le32 page_buff_size; 184 __le32 rxfifo_addr; 185 __le32 internal_txfifo_addr; 186 __le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM]; 187 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */ 188 189 /** 190 * struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration 191 * 192 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB) 193 * @txfifo_size: size of TX FIFOs 194 * @rxfifo1_addr: RXF1 addr 195 * @rxfifo1_size: RXF1 size 196 */ 197 struct iwl_shared_mem_lmac_cfg { 198 __le32 txfifo_addr; 199 __le32 txfifo_size[TX_FIFO_MAX_NUM]; 200 __le32 rxfifo1_addr; 201 __le32 rxfifo1_size; 202 203 } __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */ 204 205 /** 206 * struct iwl_shared_mem_cfg - Shared memory configuration information 207 * 208 * @shared_mem_addr: shared memory address 209 * @shared_mem_size: shared memory size 210 * @sample_buff_addr: internal sample (mon/adc) buff addr 211 * @sample_buff_size: internal sample buff size 212 * @rxfifo2_addr: start addr of RXF2 213 * @rxfifo2_size: size of RXF2 214 * @page_buff_addr: used by UMAC and performance debug (page miss analysis), 215 * when paging is not supported this should be 0 216 * @page_buff_size: size of %page_buff_addr 217 * @lmac_num: number of LMACs (1 or 2) 218 * @lmac_smem: per - LMAC smem data 219 * @rxfifo2_control_addr: start addr of RXF2C 220 * @rxfifo2_control_size: size of RXF2C 221 */ 222 struct iwl_shared_mem_cfg { 223 __le32 shared_mem_addr; 224 __le32 shared_mem_size; 225 __le32 sample_buff_addr; 226 __le32 sample_buff_size; 227 __le32 rxfifo2_addr; 228 __le32 rxfifo2_size; 229 __le32 page_buff_addr; 230 __le32 page_buff_size; 231 __le32 lmac_num; 232 struct iwl_shared_mem_lmac_cfg lmac_smem[3]; 233 __le32 rxfifo2_control_addr; 234 __le32 rxfifo2_control_size; 235 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_4 */ 236 237 /** 238 * struct iwl_mfuart_load_notif - mfuart image version & status 239 * ( MFUART_LOAD_NOTIFICATION = 0xb1 ) 240 * @installed_ver: installed image version 241 * @external_ver: external image version 242 * @status: MFUART loading status 243 * @duration: MFUART loading time 244 * @image_size: MFUART image size in bytes 245 */ 246 struct iwl_mfuart_load_notif { 247 __le32 installed_ver; 248 __le32 external_ver; 249 __le32 status; 250 __le32 duration; 251 /* image size valid only in v2 of the command */ 252 __le32 image_size; 253 } __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */ 254 255 /** 256 * struct iwl_mfu_assert_dump_notif - mfuart dump logs 257 * ( MFU_ASSERT_DUMP_NTF = 0xfe ) 258 * @assert_id: mfuart assert id that cause the notif 259 * @curr_reset_num: number of asserts since uptime 260 * @index_num: current chunk id 261 * @parts_num: total number of chunks 262 * @data_size: number of data bytes sent 263 * @data: data buffer 264 */ 265 struct iwl_mfu_assert_dump_notif { 266 __le32 assert_id; 267 __le32 curr_reset_num; 268 __le16 index_num; 269 __le16 parts_num; 270 __le32 data_size; 271 __le32 data[0]; 272 } __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */ 273 274 /** 275 * enum iwl_mvm_marker_id - marker ids 276 * 277 * The ids for different type of markers to insert into the usniffer logs 278 * 279 * @MARKER_ID_TX_FRAME_LATENCY: TX latency marker 280 * @MARKER_ID_SYNC_CLOCK: sync FW time and systime 281 */ 282 enum iwl_mvm_marker_id { 283 MARKER_ID_TX_FRAME_LATENCY = 1, 284 MARKER_ID_SYNC_CLOCK = 2, 285 }; /* MARKER_ID_API_E_VER_2 */ 286 287 /** 288 * struct iwl_mvm_marker - mark info into the usniffer logs 289 * 290 * (MARKER_CMD = 0xcb) 291 * 292 * Mark the UTC time stamp into the usniffer logs together with additional 293 * metadata, so the usniffer output can be parsed. 294 * In the command response the ucode will return the GP2 time. 295 * 296 * @dw_len: The amount of dwords following this byte including this byte. 297 * @marker_id: A unique marker id (iwl_mvm_marker_id). 298 * @reserved: reserved. 299 * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC 300 * @metadata: additional meta data that will be written to the unsiffer log 301 */ 302 struct iwl_mvm_marker { 303 u8 dw_len; 304 u8 marker_id; 305 __le16 reserved; 306 __le64 timestamp; 307 __le32 metadata[0]; 308 } __packed; /* MARKER_API_S_VER_1 */ 309 310 /** 311 * struct iwl_mvm_marker_rsp - Response to marker cmd 312 * 313 * @gp2: The gp2 clock value in the FW 314 */ 315 struct iwl_mvm_marker_rsp { 316 __le32 gp2; 317 } __packed; 318 319 /* Operation types for the debug mem access */ 320 enum { 321 DEBUG_MEM_OP_READ = 0, 322 DEBUG_MEM_OP_WRITE = 1, 323 DEBUG_MEM_OP_WRITE_BYTES = 2, 324 }; 325 326 #define DEBUG_MEM_MAX_SIZE_DWORDS 32 327 328 /** 329 * struct iwl_dbg_mem_access_cmd - Request the device to read/write memory 330 * @op: DEBUG_MEM_OP_* 331 * @addr: address to read/write from/to 332 * @len: in dwords, to read/write 333 * @data: for write opeations, contains the source buffer 334 */ 335 struct iwl_dbg_mem_access_cmd { 336 __le32 op; 337 __le32 addr; 338 __le32 len; 339 __le32 data[]; 340 } __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */ 341 342 /* Status responses for the debug mem access */ 343 enum { 344 DEBUG_MEM_STATUS_SUCCESS = 0x0, 345 DEBUG_MEM_STATUS_FAILED = 0x1, 346 DEBUG_MEM_STATUS_LOCKED = 0x2, 347 DEBUG_MEM_STATUS_HIDDEN = 0x3, 348 DEBUG_MEM_STATUS_LENGTH = 0x4, 349 }; 350 351 /** 352 * struct iwl_dbg_mem_access_rsp - Response to debug mem commands 353 * @status: DEBUG_MEM_STATUS_* 354 * @len: read dwords (0 for write operations) 355 * @data: contains the read DWs 356 */ 357 struct iwl_dbg_mem_access_rsp { 358 __le32 status; 359 __le32 len; 360 __le32 data[]; 361 } __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */ 362 363 /** 364 * struct iwl_dbg_suspend_resume_cmd - dbgc suspend resume command 365 * @operation: suspend or resume operation, uses 366 * &enum iwl_dbg_suspend_resume_cmds 367 */ 368 struct iwl_dbg_suspend_resume_cmd { 369 __le32 operation; 370 } __packed; 371 372 #define BUF_ALLOC_MAX_NUM_FRAGS 16 373 374 /** 375 * struct iwl_buf_alloc_frag - a DBGC fragment 376 * @addr: base address of the fragment 377 * @size: size of the fragment 378 */ 379 struct iwl_buf_alloc_frag { 380 __le64 addr; 381 __le32 size; 382 } __packed; /* FRAGMENT_STRUCTURE_API_S_VER_1 */ 383 384 /** 385 * struct iwl_buf_alloc_cmd - buffer allocation command 386 * @alloc_id: &enum iwl_fw_ini_allocation_id 387 * @buf_location: &enum iwl_fw_ini_buffer_location 388 * @num_frags: number of fragments 389 * @frags: fragments array 390 */ 391 struct iwl_buf_alloc_cmd { 392 __le32 alloc_id; 393 __le32 buf_location; 394 __le32 num_frags; 395 struct iwl_buf_alloc_frag frags[BUF_ALLOC_MAX_NUM_FRAGS]; 396 } __packed; /* BUFFER_ALLOCATION_CMD_API_S_VER_2 */ 397 398 #endif /* __iwl_fw_api_debug_h__ */ 399