1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /*
3  * Copyright (C) 2005-2014, 2018-2022 Intel Corporation
4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5  * Copyright (C) 2016-2017 Intel Deutschland GmbH
6  */
7 #ifndef __iwl_fw_api_debug_h__
8 #define __iwl_fw_api_debug_h__
9 
10 /**
11  * enum iwl_debug_cmds - debug commands
12  */
13 enum iwl_debug_cmds {
14 	/**
15 	 * @LMAC_RD_WR:
16 	 * LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
17 	 * &struct iwl_dbg_mem_access_rsp
18 	 */
19 	LMAC_RD_WR = 0x0,
20 	/**
21 	 * @UMAC_RD_WR:
22 	 * UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
23 	 * &struct iwl_dbg_mem_access_rsp
24 	 */
25 	UMAC_RD_WR = 0x1,
26 	/**
27 	 * @HOST_EVENT_CFG:
28 	 * updates the enabled event severities
29 	 * &struct iwl_dbg_host_event_cfg_cmd
30 	 */
31 	HOST_EVENT_CFG = 0x3,
32 	/**
33 	 * @DBGC_SUSPEND_RESUME:
34 	 * DBGC suspend/resume commad. Uses a single dword as data:
35 	 * 0 - resume DBGC recording
36 	 * 1 - suspend DBGC recording
37 	 */
38 	DBGC_SUSPEND_RESUME = 0x7,
39 	/**
40 	 * @BUFFER_ALLOCATION:
41 	 * passes DRAM buffers to a DBGC
42 	 * &struct iwl_buf_alloc_cmd
43 	 */
44 	BUFFER_ALLOCATION = 0x8,
45 	/**
46 	 * @FW_DUMP_COMPLETE_CMD:
47 	 * sends command to fw once dump collection completed
48 	 * &struct iwl_dbg_dump_complete_cmd
49 	 */
50 	FW_DUMP_COMPLETE_CMD = 0xB,
51 	/**
52 	 * @MFU_ASSERT_DUMP_NTF:
53 	 * &struct iwl_mfu_assert_dump_notif
54 	 */
55 	MFU_ASSERT_DUMP_NTF = 0xFE,
56 };
57 
58 /* Error response/notification */
59 enum {
60 	FW_ERR_UNKNOWN_CMD = 0x0,
61 	FW_ERR_INVALID_CMD_PARAM = 0x1,
62 	FW_ERR_SERVICE = 0x2,
63 	FW_ERR_ARC_MEMORY = 0x3,
64 	FW_ERR_ARC_CODE = 0x4,
65 	FW_ERR_WATCH_DOG = 0x5,
66 	FW_ERR_WEP_GRP_KEY_INDX = 0x10,
67 	FW_ERR_WEP_KEY_SIZE = 0x11,
68 	FW_ERR_OBSOLETE_FUNC = 0x12,
69 	FW_ERR_UNEXPECTED = 0xFE,
70 	FW_ERR_FATAL = 0xFF
71 };
72 
73 /** enum iwl_dbg_suspend_resume_cmds - dbgc suspend resume operations
74  * dbgc suspend resume command operations
75  * @DBGC_RESUME_CMD: resume dbgc recording
76  * @DBGC_SUSPEND_CMD: stop dbgc recording
77  */
78 enum iwl_dbg_suspend_resume_cmds {
79 	DBGC_RESUME_CMD,
80 	DBGC_SUSPEND_CMD,
81 };
82 
83 /**
84  * struct iwl_error_resp - FW error indication
85  * ( REPLY_ERROR = 0x2 )
86  * @error_type: one of FW_ERR_*
87  * @cmd_id: the command ID for which the error occurred
88  * @reserved1: reserved
89  * @bad_cmd_seq_num: sequence number of the erroneous command
90  * @error_service: which service created the error, applicable only if
91  *     error_type = 2, otherwise 0
92  * @timestamp: TSF in usecs.
93  */
94 struct iwl_error_resp {
95 	__le32 error_type;
96 	u8 cmd_id;
97 	u8 reserved1;
98 	__le16 bad_cmd_seq_num;
99 	__le32 error_service;
100 	__le64 timestamp;
101 } __packed;
102 
103 #define TX_FIFO_MAX_NUM_9000		8
104 #define TX_FIFO_MAX_NUM			15
105 #define RX_FIFO_MAX_NUM			2
106 #define TX_FIFO_INTERNAL_MAX_NUM	6
107 
108 /**
109  * struct iwl_shared_mem_cfg_v2 - Shared memory configuration information
110  *
111  * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not
112  *	accessible)
113  * @shared_mem_size: shared memory size
114  * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to
115  *	0x0 as accessible only via DBGM RDAT)
116  * @sample_buff_size: internal sample buff size
117  * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre
118  *	8000 HW set to 0x0 as not accessible)
119  * @txfifo_size: size of TXF0 ... TXF7
120  * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0
121  * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
122  *	when paging is not supported this should be 0
123  * @page_buff_size: size of %page_buff_addr
124  * @rxfifo_addr: Start address of rxFifo
125  * @internal_txfifo_addr: start address of internalFifo
126  * @internal_txfifo_size: internal fifos' size
127  *
128  * NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG
129  *	 set, the last 3 members don't exist.
130  */
131 struct iwl_shared_mem_cfg_v2 {
132 	__le32 shared_mem_addr;
133 	__le32 shared_mem_size;
134 	__le32 sample_buff_addr;
135 	__le32 sample_buff_size;
136 	__le32 txfifo_addr;
137 	__le32 txfifo_size[TX_FIFO_MAX_NUM_9000];
138 	__le32 rxfifo_size[RX_FIFO_MAX_NUM];
139 	__le32 page_buff_addr;
140 	__le32 page_buff_size;
141 	__le32 rxfifo_addr;
142 	__le32 internal_txfifo_addr;
143 	__le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM];
144 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */
145 
146 /**
147  * struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration
148  *
149  * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB)
150  * @txfifo_size: size of TX FIFOs
151  * @rxfifo1_addr: RXF1 addr
152  * @rxfifo1_size: RXF1 size
153  */
154 struct iwl_shared_mem_lmac_cfg {
155 	__le32 txfifo_addr;
156 	__le32 txfifo_size[TX_FIFO_MAX_NUM];
157 	__le32 rxfifo1_addr;
158 	__le32 rxfifo1_size;
159 
160 } __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */
161 
162 /**
163  * struct iwl_shared_mem_cfg - Shared memory configuration information
164  *
165  * @shared_mem_addr: shared memory address
166  * @shared_mem_size: shared memory size
167  * @sample_buff_addr: internal sample (mon/adc) buff addr
168  * @sample_buff_size: internal sample buff size
169  * @rxfifo2_addr: start addr of RXF2
170  * @rxfifo2_size: size of RXF2
171  * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
172  *	when paging is not supported this should be 0
173  * @page_buff_size: size of %page_buff_addr
174  * @lmac_num: number of LMACs (1 or 2)
175  * @lmac_smem: per - LMAC smem data
176  * @rxfifo2_control_addr: start addr of RXF2C
177  * @rxfifo2_control_size: size of RXF2C
178  */
179 struct iwl_shared_mem_cfg {
180 	__le32 shared_mem_addr;
181 	__le32 shared_mem_size;
182 	__le32 sample_buff_addr;
183 	__le32 sample_buff_size;
184 	__le32 rxfifo2_addr;
185 	__le32 rxfifo2_size;
186 	__le32 page_buff_addr;
187 	__le32 page_buff_size;
188 	__le32 lmac_num;
189 	struct iwl_shared_mem_lmac_cfg lmac_smem[3];
190 	__le32 rxfifo2_control_addr;
191 	__le32 rxfifo2_control_size;
192 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_4 */
193 
194 /**
195  * struct iwl_mfuart_load_notif_v1 - mfuart image version & status
196  * ( MFUART_LOAD_NOTIFICATION = 0xb1 )
197  * @installed_ver: installed image version
198  * @external_ver: external image version
199  * @status: MFUART loading status
200  * @duration: MFUART loading time
201 */
202 struct iwl_mfuart_load_notif_v1 {
203 	__le32 installed_ver;
204 	__le32 external_ver;
205 	__le32 status;
206 	__le32 duration;
207 } __packed; /* MFU_LOADER_NTFY_API_S_VER_1 */
208 
209 /**
210  * struct iwl_mfuart_load_notif - mfuart image version & status
211  * ( MFUART_LOAD_NOTIFICATION = 0xb1 )
212  * @installed_ver: installed image version
213  * @external_ver: external image version
214  * @status: MFUART loading status
215  * @duration: MFUART loading time
216  * @image_size: MFUART image size in bytes
217 */
218 struct iwl_mfuart_load_notif {
219 	__le32 installed_ver;
220 	__le32 external_ver;
221 	__le32 status;
222 	__le32 duration;
223 	/* image size valid only in v2 of the command */
224 	__le32 image_size;
225 } __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */
226 
227 /**
228  * struct iwl_mfu_assert_dump_notif - mfuart dump logs
229  * ( MFU_ASSERT_DUMP_NTF = 0xfe )
230  * @assert_id: mfuart assert id that cause the notif
231  * @curr_reset_num: number of asserts since uptime
232  * @index_num: current chunk id
233  * @parts_num: total number of chunks
234  * @data_size: number of data bytes sent
235  * @data: data buffer
236  */
237 struct iwl_mfu_assert_dump_notif {
238 	__le32   assert_id;
239 	__le32   curr_reset_num;
240 	__le16   index_num;
241 	__le16   parts_num;
242 	__le32   data_size;
243 	__le32   data[0];
244 } __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */
245 
246 /**
247  * enum iwl_mvm_marker_id - marker ids
248  *
249  * The ids for different type of markers to insert into the usniffer logs
250  *
251  * @MARKER_ID_TX_FRAME_LATENCY: TX latency marker
252  * @MARKER_ID_SYNC_CLOCK: sync FW time and systime
253  */
254 enum iwl_mvm_marker_id {
255 	MARKER_ID_TX_FRAME_LATENCY = 1,
256 	MARKER_ID_SYNC_CLOCK = 2,
257 }; /* MARKER_ID_API_E_VER_2 */
258 
259 /**
260  * struct iwl_mvm_marker - mark info into the usniffer logs
261  *
262  * (MARKER_CMD = 0xcb)
263  *
264  * Mark the UTC time stamp into the usniffer logs together with additional
265  * metadata, so the usniffer output can be parsed.
266  * In the command response the ucode will return the GP2 time.
267  *
268  * @dw_len: The amount of dwords following this byte including this byte.
269  * @marker_id: A unique marker id (iwl_mvm_marker_id).
270  * @reserved: reserved.
271  * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC
272  * @metadata: additional meta data that will be written to the unsiffer log
273  */
274 struct iwl_mvm_marker {
275 	u8 dw_len;
276 	u8 marker_id;
277 	__le16 reserved;
278 	__le64 timestamp;
279 	__le32 metadata[0];
280 } __packed; /* MARKER_API_S_VER_1 */
281 
282 /**
283  * struct iwl_mvm_marker_rsp - Response to marker cmd
284  *
285  * @gp2: The gp2 clock value in the FW
286  */
287 struct iwl_mvm_marker_rsp {
288 	__le32 gp2;
289 } __packed;
290 
291 /* Operation types for the debug mem access */
292 enum {
293 	DEBUG_MEM_OP_READ = 0,
294 	DEBUG_MEM_OP_WRITE = 1,
295 	DEBUG_MEM_OP_WRITE_BYTES = 2,
296 };
297 
298 #define DEBUG_MEM_MAX_SIZE_DWORDS 32
299 
300 /**
301  * struct iwl_dbg_mem_access_cmd - Request the device to read/write memory
302  * @op: DEBUG_MEM_OP_*
303  * @addr: address to read/write from/to
304  * @len: in dwords, to read/write
305  * @data: for write opeations, contains the source buffer
306  */
307 struct iwl_dbg_mem_access_cmd {
308 	__le32 op;
309 	__le32 addr;
310 	__le32 len;
311 	__le32 data[];
312 } __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */
313 
314 /* Status responses for the debug mem access */
315 enum {
316 	DEBUG_MEM_STATUS_SUCCESS = 0x0,
317 	DEBUG_MEM_STATUS_FAILED = 0x1,
318 	DEBUG_MEM_STATUS_LOCKED = 0x2,
319 	DEBUG_MEM_STATUS_HIDDEN = 0x3,
320 	DEBUG_MEM_STATUS_LENGTH = 0x4,
321 };
322 
323 /**
324  * struct iwl_dbg_mem_access_rsp - Response to debug mem commands
325  * @status: DEBUG_MEM_STATUS_*
326  * @len: read dwords (0 for write operations)
327  * @data: contains the read DWs
328  */
329 struct iwl_dbg_mem_access_rsp {
330 	__le32 status;
331 	__le32 len;
332 	__le32 data[];
333 } __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */
334 
335 /**
336  * struct iwl_dbg_suspend_resume_cmd - dbgc suspend resume command
337  * @operation: suspend or resume operation, uses
338  *	&enum iwl_dbg_suspend_resume_cmds
339  */
340 struct iwl_dbg_suspend_resume_cmd {
341 	__le32 operation;
342 } __packed;
343 
344 #define BUF_ALLOC_MAX_NUM_FRAGS 16
345 
346 /**
347  * struct iwl_buf_alloc_frag - a DBGC fragment
348  * @addr: base address of the fragment
349  * @size: size of the fragment
350  */
351 struct iwl_buf_alloc_frag {
352 	__le64 addr;
353 	__le32 size;
354 } __packed; /* FRAGMENT_STRUCTURE_API_S_VER_1 */
355 
356 /**
357  * struct iwl_buf_alloc_cmd - buffer allocation command
358  * @alloc_id: &enum iwl_fw_ini_allocation_id
359  * @buf_location: &enum iwl_fw_ini_buffer_location
360  * @num_frags: number of fragments
361  * @frags: fragments array
362  */
363 struct iwl_buf_alloc_cmd {
364 	__le32 alloc_id;
365 	__le32 buf_location;
366 	__le32 num_frags;
367 	struct iwl_buf_alloc_frag frags[BUF_ALLOC_MAX_NUM_FRAGS];
368 } __packed; /* BUFFER_ALLOCATION_CMD_API_S_VER_2 */
369 
370 #define DRAM_INFO_FIRST_MAGIC_WORD 0x76543210
371 #define DRAM_INFO_SECOND_MAGIC_WORD 0x89ABCDEF
372 
373 /**
374  * struct iwL_dram_info - DRAM fragments allocation struct
375  *
376  * Driver will fill in the first 1K(+) of the pointed DRAM fragment
377  *
378  * @first_word: magic word value
379  * @second_word: magic word value
380  * @framfrags: DRAM fragmentaion detail
381 */
382 struct iwl_dram_info {
383 	__le32 first_word;
384 	__le32 second_word;
385 	struct iwl_buf_alloc_cmd dram_frags[IWL_FW_INI_ALLOCATION_NUM - 1];
386 } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */
387 
388 /**
389  * struct iwl_dbgc1_info - DBGC1 address and size
390  *
391  * Driver will fill the dbcg1 address and size at address based on config TLV.
392  *
393  * @first_word: all 0 set as identifier
394  * @dbgc1_add_lsb: LSB bits of DBGC1 physical address
395  * @dbgc1_add_msb: MSB bits of DBGC1 physical address
396  * @dbgc1_size: DBGC1 size
397 */
398 struct iwl_dbgc1_info {
399 	__le32 first_word;
400 	__le32 dbgc1_add_lsb;
401 	__le32 dbgc1_add_msb;
402 	__le32 dbgc1_size;
403 } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */
404 
405 /**
406  * struct iwl_dbg_host_event_cfg_cmd
407  * @enabled_severities: enabled severities
408  */
409 struct iwl_dbg_host_event_cfg_cmd {
410 	__le32 enabled_severities;
411 } __packed; /* DEBUG_HOST_EVENT_CFG_CMD_API_S_VER_1 */
412 
413 /**
414  * struct iwl_dbg_dump_complete_cmd - dump complete cmd
415  *
416  * @tp: timepoint whose dump has completed
417  * @tp_data: timepoint data
418  */
419 struct iwl_dbg_dump_complete_cmd {
420 	__le32 tp;
421 	__le32 tp_data;
422 } __packed; /* FW_DUMP_COMPLETE_CMD_API_S_VER_1 */
423 
424 #endif /* __iwl_fw_api_debug_h__ */
425