1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2005-2014, 2018-2022 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_fw_api_debug_h__ 8 #define __iwl_fw_api_debug_h__ 9 10 /** 11 * enum iwl_debug_cmds - debug commands 12 */ 13 enum iwl_debug_cmds { 14 /** 15 * @LMAC_RD_WR: 16 * LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and 17 * &struct iwl_dbg_mem_access_rsp 18 */ 19 LMAC_RD_WR = 0x0, 20 /** 21 * @UMAC_RD_WR: 22 * UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and 23 * &struct iwl_dbg_mem_access_rsp 24 */ 25 UMAC_RD_WR = 0x1, 26 /** 27 * @HOST_EVENT_CFG: 28 * updates the enabled event severities 29 * &struct iwl_dbg_host_event_cfg_cmd 30 */ 31 HOST_EVENT_CFG = 0x3, 32 /** 33 * @DBGC_SUSPEND_RESUME: 34 * DBGC suspend/resume commad. Uses a single dword as data: 35 * 0 - resume DBGC recording 36 * 1 - suspend DBGC recording 37 */ 38 DBGC_SUSPEND_RESUME = 0x7, 39 /** 40 * @BUFFER_ALLOCATION: 41 * passes DRAM buffers to a DBGC 42 * &struct iwl_buf_alloc_cmd 43 */ 44 BUFFER_ALLOCATION = 0x8, 45 /** 46 * @GET_TAS_STATUS: 47 * sends command to fw to get TAS status 48 * the response is &struct iwl_mvm_tas_status_resp 49 */ 50 GET_TAS_STATUS = 0xA, 51 /** 52 * @FW_DUMP_COMPLETE_CMD: 53 * sends command to fw once dump collection completed 54 * &struct iwl_dbg_dump_complete_cmd 55 */ 56 FW_DUMP_COMPLETE_CMD = 0xB, 57 /** 58 * @MFU_ASSERT_DUMP_NTF: 59 * &struct iwl_mfu_assert_dump_notif 60 */ 61 MFU_ASSERT_DUMP_NTF = 0xFE, 62 }; 63 64 /* Error response/notification */ 65 enum { 66 FW_ERR_UNKNOWN_CMD = 0x0, 67 FW_ERR_INVALID_CMD_PARAM = 0x1, 68 FW_ERR_SERVICE = 0x2, 69 FW_ERR_ARC_MEMORY = 0x3, 70 FW_ERR_ARC_CODE = 0x4, 71 FW_ERR_WATCH_DOG = 0x5, 72 FW_ERR_WEP_GRP_KEY_INDX = 0x10, 73 FW_ERR_WEP_KEY_SIZE = 0x11, 74 FW_ERR_OBSOLETE_FUNC = 0x12, 75 FW_ERR_UNEXPECTED = 0xFE, 76 FW_ERR_FATAL = 0xFF 77 }; 78 79 /** enum iwl_dbg_suspend_resume_cmds - dbgc suspend resume operations 80 * dbgc suspend resume command operations 81 * @DBGC_RESUME_CMD: resume dbgc recording 82 * @DBGC_SUSPEND_CMD: stop dbgc recording 83 */ 84 enum iwl_dbg_suspend_resume_cmds { 85 DBGC_RESUME_CMD, 86 DBGC_SUSPEND_CMD, 87 }; 88 89 /** 90 * struct iwl_error_resp - FW error indication 91 * ( REPLY_ERROR = 0x2 ) 92 * @error_type: one of FW_ERR_* 93 * @cmd_id: the command ID for which the error occurred 94 * @reserved1: reserved 95 * @bad_cmd_seq_num: sequence number of the erroneous command 96 * @error_service: which service created the error, applicable only if 97 * error_type = 2, otherwise 0 98 * @timestamp: TSF in usecs. 99 */ 100 struct iwl_error_resp { 101 __le32 error_type; 102 u8 cmd_id; 103 u8 reserved1; 104 __le16 bad_cmd_seq_num; 105 __le32 error_service; 106 __le64 timestamp; 107 } __packed; 108 109 #define TX_FIFO_MAX_NUM_9000 8 110 #define TX_FIFO_MAX_NUM 15 111 #define RX_FIFO_MAX_NUM 2 112 #define TX_FIFO_INTERNAL_MAX_NUM 6 113 114 /** 115 * struct iwl_shared_mem_cfg_v2 - Shared memory configuration information 116 * 117 * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not 118 * accessible) 119 * @shared_mem_size: shared memory size 120 * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to 121 * 0x0 as accessible only via DBGM RDAT) 122 * @sample_buff_size: internal sample buff size 123 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre 124 * 8000 HW set to 0x0 as not accessible) 125 * @txfifo_size: size of TXF0 ... TXF7 126 * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0 127 * @page_buff_addr: used by UMAC and performance debug (page miss analysis), 128 * when paging is not supported this should be 0 129 * @page_buff_size: size of %page_buff_addr 130 * @rxfifo_addr: Start address of rxFifo 131 * @internal_txfifo_addr: start address of internalFifo 132 * @internal_txfifo_size: internal fifos' size 133 * 134 * NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 135 * set, the last 3 members don't exist. 136 */ 137 struct iwl_shared_mem_cfg_v2 { 138 __le32 shared_mem_addr; 139 __le32 shared_mem_size; 140 __le32 sample_buff_addr; 141 __le32 sample_buff_size; 142 __le32 txfifo_addr; 143 __le32 txfifo_size[TX_FIFO_MAX_NUM_9000]; 144 __le32 rxfifo_size[RX_FIFO_MAX_NUM]; 145 __le32 page_buff_addr; 146 __le32 page_buff_size; 147 __le32 rxfifo_addr; 148 __le32 internal_txfifo_addr; 149 __le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM]; 150 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */ 151 152 /** 153 * struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration 154 * 155 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB) 156 * @txfifo_size: size of TX FIFOs 157 * @rxfifo1_addr: RXF1 addr 158 * @rxfifo1_size: RXF1 size 159 */ 160 struct iwl_shared_mem_lmac_cfg { 161 __le32 txfifo_addr; 162 __le32 txfifo_size[TX_FIFO_MAX_NUM]; 163 __le32 rxfifo1_addr; 164 __le32 rxfifo1_size; 165 166 } __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */ 167 168 /** 169 * struct iwl_shared_mem_cfg - Shared memory configuration information 170 * 171 * @shared_mem_addr: shared memory address 172 * @shared_mem_size: shared memory size 173 * @sample_buff_addr: internal sample (mon/adc) buff addr 174 * @sample_buff_size: internal sample buff size 175 * @rxfifo2_addr: start addr of RXF2 176 * @rxfifo2_size: size of RXF2 177 * @page_buff_addr: used by UMAC and performance debug (page miss analysis), 178 * when paging is not supported this should be 0 179 * @page_buff_size: size of %page_buff_addr 180 * @lmac_num: number of LMACs (1 or 2) 181 * @lmac_smem: per - LMAC smem data 182 * @rxfifo2_control_addr: start addr of RXF2C 183 * @rxfifo2_control_size: size of RXF2C 184 */ 185 struct iwl_shared_mem_cfg { 186 __le32 shared_mem_addr; 187 __le32 shared_mem_size; 188 __le32 sample_buff_addr; 189 __le32 sample_buff_size; 190 __le32 rxfifo2_addr; 191 __le32 rxfifo2_size; 192 __le32 page_buff_addr; 193 __le32 page_buff_size; 194 __le32 lmac_num; 195 struct iwl_shared_mem_lmac_cfg lmac_smem[3]; 196 __le32 rxfifo2_control_addr; 197 __le32 rxfifo2_control_size; 198 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_4 */ 199 200 /** 201 * struct iwl_mfuart_load_notif_v1 - mfuart image version & status 202 * ( MFUART_LOAD_NOTIFICATION = 0xb1 ) 203 * @installed_ver: installed image version 204 * @external_ver: external image version 205 * @status: MFUART loading status 206 * @duration: MFUART loading time 207 */ 208 struct iwl_mfuart_load_notif_v1 { 209 __le32 installed_ver; 210 __le32 external_ver; 211 __le32 status; 212 __le32 duration; 213 } __packed; /* MFU_LOADER_NTFY_API_S_VER_1 */ 214 215 /** 216 * struct iwl_mfuart_load_notif - mfuart image version & status 217 * ( MFUART_LOAD_NOTIFICATION = 0xb1 ) 218 * @installed_ver: installed image version 219 * @external_ver: external image version 220 * @status: MFUART loading status 221 * @duration: MFUART loading time 222 * @image_size: MFUART image size in bytes 223 */ 224 struct iwl_mfuart_load_notif { 225 __le32 installed_ver; 226 __le32 external_ver; 227 __le32 status; 228 __le32 duration; 229 /* image size valid only in v2 of the command */ 230 __le32 image_size; 231 } __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */ 232 233 /** 234 * struct iwl_mfu_assert_dump_notif - mfuart dump logs 235 * ( MFU_ASSERT_DUMP_NTF = 0xfe ) 236 * @assert_id: mfuart assert id that cause the notif 237 * @curr_reset_num: number of asserts since uptime 238 * @index_num: current chunk id 239 * @parts_num: total number of chunks 240 * @data_size: number of data bytes sent 241 * @data: data buffer 242 */ 243 struct iwl_mfu_assert_dump_notif { 244 __le32 assert_id; 245 __le32 curr_reset_num; 246 __le16 index_num; 247 __le16 parts_num; 248 __le32 data_size; 249 __le32 data[]; 250 } __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */ 251 252 /** 253 * enum iwl_mvm_marker_id - marker ids 254 * 255 * The ids for different type of markers to insert into the usniffer logs 256 * 257 * @MARKER_ID_TX_FRAME_LATENCY: TX latency marker 258 * @MARKER_ID_SYNC_CLOCK: sync FW time and systime 259 */ 260 enum iwl_mvm_marker_id { 261 MARKER_ID_TX_FRAME_LATENCY = 1, 262 MARKER_ID_SYNC_CLOCK = 2, 263 }; /* MARKER_ID_API_E_VER_2 */ 264 265 /** 266 * struct iwl_mvm_marker - mark info into the usniffer logs 267 * 268 * (MARKER_CMD = 0xcb) 269 * 270 * Mark the UTC time stamp into the usniffer logs together with additional 271 * metadata, so the usniffer output can be parsed. 272 * In the command response the ucode will return the GP2 time. 273 * 274 * @dw_len: The amount of dwords following this byte including this byte. 275 * @marker_id: A unique marker id (iwl_mvm_marker_id). 276 * @reserved: reserved. 277 * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC 278 * @metadata: additional meta data that will be written to the unsiffer log 279 */ 280 struct iwl_mvm_marker { 281 u8 dw_len; 282 u8 marker_id; 283 __le16 reserved; 284 __le64 timestamp; 285 __le32 metadata[]; 286 } __packed; /* MARKER_API_S_VER_1 */ 287 288 /** 289 * struct iwl_mvm_marker_rsp - Response to marker cmd 290 * 291 * @gp2: The gp2 clock value in the FW 292 */ 293 struct iwl_mvm_marker_rsp { 294 __le32 gp2; 295 } __packed; 296 297 /* Operation types for the debug mem access */ 298 enum { 299 DEBUG_MEM_OP_READ = 0, 300 DEBUG_MEM_OP_WRITE = 1, 301 DEBUG_MEM_OP_WRITE_BYTES = 2, 302 }; 303 304 #define DEBUG_MEM_MAX_SIZE_DWORDS 32 305 306 /** 307 * struct iwl_dbg_mem_access_cmd - Request the device to read/write memory 308 * @op: DEBUG_MEM_OP_* 309 * @addr: address to read/write from/to 310 * @len: in dwords, to read/write 311 * @data: for write opeations, contains the source buffer 312 */ 313 struct iwl_dbg_mem_access_cmd { 314 __le32 op; 315 __le32 addr; 316 __le32 len; 317 __le32 data[]; 318 } __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */ 319 320 /* Status responses for the debug mem access */ 321 enum { 322 DEBUG_MEM_STATUS_SUCCESS = 0x0, 323 DEBUG_MEM_STATUS_FAILED = 0x1, 324 DEBUG_MEM_STATUS_LOCKED = 0x2, 325 DEBUG_MEM_STATUS_HIDDEN = 0x3, 326 DEBUG_MEM_STATUS_LENGTH = 0x4, 327 }; 328 329 /** 330 * struct iwl_dbg_mem_access_rsp - Response to debug mem commands 331 * @status: DEBUG_MEM_STATUS_* 332 * @len: read dwords (0 for write operations) 333 * @data: contains the read DWs 334 */ 335 struct iwl_dbg_mem_access_rsp { 336 __le32 status; 337 __le32 len; 338 __le32 data[]; 339 } __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */ 340 341 /** 342 * struct iwl_dbg_suspend_resume_cmd - dbgc suspend resume command 343 * @operation: suspend or resume operation, uses 344 * &enum iwl_dbg_suspend_resume_cmds 345 */ 346 struct iwl_dbg_suspend_resume_cmd { 347 __le32 operation; 348 } __packed; 349 350 #define BUF_ALLOC_MAX_NUM_FRAGS 16 351 352 /** 353 * struct iwl_buf_alloc_frag - a DBGC fragment 354 * @addr: base address of the fragment 355 * @size: size of the fragment 356 */ 357 struct iwl_buf_alloc_frag { 358 __le64 addr; 359 __le32 size; 360 } __packed; /* FRAGMENT_STRUCTURE_API_S_VER_1 */ 361 362 /** 363 * struct iwl_buf_alloc_cmd - buffer allocation command 364 * @alloc_id: &enum iwl_fw_ini_allocation_id 365 * @buf_location: &enum iwl_fw_ini_buffer_location 366 * @num_frags: number of fragments 367 * @frags: fragments array 368 */ 369 struct iwl_buf_alloc_cmd { 370 __le32 alloc_id; 371 __le32 buf_location; 372 __le32 num_frags; 373 struct iwl_buf_alloc_frag frags[BUF_ALLOC_MAX_NUM_FRAGS]; 374 } __packed; /* BUFFER_ALLOCATION_CMD_API_S_VER_2 */ 375 376 #define DRAM_INFO_FIRST_MAGIC_WORD 0x76543210 377 #define DRAM_INFO_SECOND_MAGIC_WORD 0x89ABCDEF 378 379 /** 380 * struct iwL_dram_info - DRAM fragments allocation struct 381 * 382 * Driver will fill in the first 1K(+) of the pointed DRAM fragment 383 * 384 * @first_word: magic word value 385 * @second_word: magic word value 386 * @framfrags: DRAM fragmentaion detail 387 */ 388 struct iwl_dram_info { 389 __le32 first_word; 390 __le32 second_word; 391 struct iwl_buf_alloc_cmd dram_frags[IWL_FW_INI_ALLOCATION_NUM - 1]; 392 } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */ 393 394 /** 395 * struct iwl_dbgc1_info - DBGC1 address and size 396 * 397 * Driver will fill the dbcg1 address and size at address based on config TLV. 398 * 399 * @first_word: all 0 set as identifier 400 * @dbgc1_add_lsb: LSB bits of DBGC1 physical address 401 * @dbgc1_add_msb: MSB bits of DBGC1 physical address 402 * @dbgc1_size: DBGC1 size 403 */ 404 struct iwl_dbgc1_info { 405 __le32 first_word; 406 __le32 dbgc1_add_lsb; 407 __le32 dbgc1_add_msb; 408 __le32 dbgc1_size; 409 } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */ 410 411 /** 412 * struct iwl_dbg_host_event_cfg_cmd 413 * @enabled_severities: enabled severities 414 */ 415 struct iwl_dbg_host_event_cfg_cmd { 416 __le32 enabled_severities; 417 } __packed; /* DEBUG_HOST_EVENT_CFG_CMD_API_S_VER_1 */ 418 419 /** 420 * struct iwl_dbg_dump_complete_cmd - dump complete cmd 421 * 422 * @tp: timepoint whose dump has completed 423 * @tp_data: timepoint data 424 */ 425 struct iwl_dbg_dump_complete_cmd { 426 __le32 tp; 427 __le32 tp_data; 428 } __packed; /* FW_DUMP_COMPLETE_CMD_API_S_VER_1 */ 429 430 #define TAS_LMAC_BAND_HB 0 431 #define TAS_LMAC_BAND_LB 1 432 #define TAS_LMAC_BAND_UHB 2 433 #define TAS_LMAC_BAND_INVALID 3 434 435 /** 436 * struct iwl_mvm_tas_status_per_mac - tas status per lmac 437 * @static_status: tas statically enabled or disabled per lmac - TRUE/FALSE 438 * @static_dis_reason: TAS static disable reason, uses 439 * &enum iwl_mvm_tas_statically_disabled_reason 440 * @dynamic_status: Current TAS status. uses 441 * &enum iwl_mvm_tas_dyna_status 442 * @near_disconnection: is TAS currently near disconnection per lmac? - TRUE/FALSE 443 * @max_reg_pwr_limit: Regulatory power limits in dBm 444 * @sar_limit: SAR limits per lmac in dBm 445 * @band: Band per lmac 446 * @reserved: reserved 447 */ 448 struct iwl_mvm_tas_status_per_mac { 449 u8 static_status; 450 u8 static_dis_reason; 451 u8 dynamic_status; 452 u8 near_disconnection; 453 __le16 max_reg_pwr_limit; 454 __le16 sar_limit; 455 u8 band; 456 u8 reserved[3]; 457 } __packed; /*DEBUG_GET_TAS_STATUS_PER_MAC_S_VER_1*/ 458 459 /** 460 * struct iwl_mvm_tas_status_resp - Response to GET_TAS_STATUS 461 * @tas_fw_version: TAS FW version 462 * @is_uhb_for_usa_enable: is UHB enabled in USA? - TRUE/FALSE 463 * @curr_mcc: current mcc 464 * @block_list: country block list 465 * @tas_status_mac: TAS status per lmac, uses 466 * &struct iwl_mvm_tas_status_per_mac 467 * @in_dual_radio: is TAS in dual radio? - TRUE/FALSE 468 * @reserved: reserved 469 */ 470 struct iwl_mvm_tas_status_resp { 471 u8 tas_fw_version; 472 u8 is_uhb_for_usa_enable; 473 __le16 curr_mcc; 474 __le16 block_list[16]; 475 struct iwl_mvm_tas_status_per_mac tas_status_mac[2]; 476 u8 in_dual_radio; 477 u8 reserved[3]; 478 } __packed; /*DEBUG_GET_TAS_STATUS_RSP_API_S_VER_3*/ 479 480 /** 481 * enum iwl_mvm_tas_dyna_status - TAS current running status 482 * @TAS_DYNA_INACTIVE: TAS status is inactive 483 * @TAS_DYNA_INACTIVE_MVM_MODE: TAS is disabled due because FW is in MVM mode 484 * or is in softap mode. 485 * @TAS_DYNA_INACTIVE_TRIGGER_MODE: TAS is disabled because FW is in 486 * multi user trigger mode 487 * @TAS_DYNA_INACTIVE_BLOCK_LISTED: TAS is disabled because current mcc 488 * is blocklisted mcc 489 * @TAS_DYNA_INACTIVE_UHB_NON_US: TAS is disabled because current band is UHB 490 * and current mcc is USA 491 * @TAS_DYNA_ACTIVE: TAS is currently active 492 * @TAS_DYNA_STATUS_MAX: TAS status max value 493 */ 494 enum iwl_mvm_tas_dyna_status { 495 TAS_DYNA_INACTIVE, 496 TAS_DYNA_INACTIVE_MVM_MODE, 497 TAS_DYNA_INACTIVE_TRIGGER_MODE, 498 TAS_DYNA_INACTIVE_BLOCK_LISTED, 499 TAS_DYNA_INACTIVE_UHB_NON_US, 500 TAS_DYNA_ACTIVE, 501 502 TAS_DYNA_STATUS_MAX, 503 }; /*_TAS_DYNA_STATUS_E*/ 504 505 /** 506 * enum iwl_mvm_tas_statically_disabled_reason - TAS statically disabled reason 507 * @TAS_DISABLED_DUE_TO_BIOS: TAS is disabled because TAS is disabled in BIOS 508 * @TAS_DISABLED_DUE_TO_SAR_6DBM: TAS is disabled because SAR limit is less than 6 Dbm 509 * @TAS_DISABLED_REASON_INVALID: TAS disable reason is invalid 510 * @TAS_DISABLED_REASON_MAX: TAS disable reason max value 511 */ 512 enum iwl_mvm_tas_statically_disabled_reason { 513 TAS_DISABLED_DUE_TO_BIOS, 514 TAS_DISABLED_DUE_TO_SAR_6DBM, 515 TAS_DISABLED_REASON_INVALID, 516 517 TAS_DISABLED_REASON_MAX, 518 }; /*_TAS_STATICALLY_DISABLED_REASON_E*/ 519 520 #endif /* __iwl_fw_api_debug_h__ */ 521