1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2023 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_BZ_UCODE_API_MAX 82 14 15 /* Lowest firmware API version supported */ 16 #define IWL_BZ_UCODE_API_MIN 80 17 18 /* NVM versions */ 19 #define IWL_BZ_NVM_VERSION 0x0a1d 20 21 /* Memory offsets and lengths */ 22 #define IWL_BZ_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_BZ_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_BZ_DCCM2_OFFSET 0x880000 25 #define IWL_BZ_DCCM2_LEN 0x8000 26 #define IWL_BZ_SMEM_OFFSET 0x400000 27 #define IWL_BZ_SMEM_LEN 0xD0000 28 29 #define IWL_BZ_A_HR_A_FW_PRE "iwlwifi-bz-a0-hr-b0-" 30 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0-" 31 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0-" 32 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0-" 33 #define IWL_BZ_A_MR_A_FW_PRE "iwlwifi-bz-a0-mr-a0-" 34 #define IWL_BZ_A_FM_A_FW_PRE "iwlwifi-bz-a0-fm-a0-" 35 #define IWL_BZ_A_FM4_A_FW_PRE "iwlwifi-bz-a0-fm4-a0-" 36 #define IWL_BZ_A_FM_B_FW_PRE "iwlwifi-bz-a0-fm-b0-" 37 #define IWL_BZ_A_FM_C_FW_PRE "iwlwifi-bz-a0-fm-c0-" 38 #define IWL_BZ_A_FM4_B_FW_PRE "iwlwifi-bz-a0-fm4-b0-" 39 #define IWL_BZ_B_GF_A_FW_PRE "iwlwifi-bz-b0-gf-a0-" 40 #define IWL_BZ_B_GF4_A_FW_PRE "iwlwifi-bz-b0-gf4-a0-" 41 #define IWL_BZ_B_FM_B_FW_PRE "iwlwifi-bz-b0-fm-b0-" 42 #define IWL_BZ_B_FM4_B_FW_PRE "iwlwifi-bz-b0-fm4-b0-" 43 #define IWL_GL_A_FM_A_FW_PRE "iwlwifi-gl-a0-fm-a0-" 44 #define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0-" 45 #define IWL_GL_C_FM_C_FW_PRE "iwlwifi-gl-c0-fm-c0-" 46 #define IWL_BZ_Z_GF_A_FW_PRE "iwlwifi-bz-z0-gf-a0-" 47 48 #define IWL_BZ_A_HR_A_MODULE_FIRMWARE(api) \ 49 IWL_BZ_A_HR_A_FW_PRE __stringify(api) ".ucode" 50 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 51 IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 52 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \ 53 IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode" 54 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \ 55 IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 56 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \ 57 IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode" 58 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \ 59 IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode" 60 #define IWL_BZ_A_FM4_A_MODULE_FIRMWARE(api) \ 61 IWL_BZ_A_FM4_A_FW_PRE __stringify(api) ".ucode" 62 #define IWL_BZ_A_FM_B_MODULE_FIRMWARE(api) \ 63 IWL_BZ_A_FM_B_FW_PRE __stringify(api) ".ucode" 64 #define IWL_BZ_A_FM_C_MODULE_FIRMWARE(api) \ 65 IWL_BZ_A_FM_C_FW_PRE __stringify(api) ".ucode" 66 #define IWL_BZ_A_FM4_B_MODULE_FIRMWARE(api) \ 67 IWL_BZ_A_FM4_B_FW_PRE __stringify(api) ".ucode" 68 #define IWL_BZ_B_GF_A_MODULE_FIRMWARE(api) \ 69 IWL_BZ_B_GF_A_FW_PRE __stringify(api) ".ucode" 70 #define IWL_BZ_B_GF4_A_MODULE_FIRMWARE(api) \ 71 IWL_BZ_B_GF4_A_FW_PRE __stringify(api) ".ucode" 72 #define IWL_BZ_B_FM_B_MODULE_FIRMWARE(api) \ 73 IWL_BZ_B_FM_B_FW_PRE __stringify(api) ".ucode" 74 #define IWL_BZ_B_FM4_B_MODULE_FIRMWARE(api) \ 75 IWL_BZ_B_FM4_B_FW_PRE __stringify(api) ".ucode" 76 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \ 77 IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode" 78 #define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \ 79 IWL_GL_B_FM_B_FW_PRE __stringify(api) ".ucode" 80 #define IWL_GL_C_FM_C_MODULE_FIRMWARE(api) \ 81 IWL_GL_C_FM_C_FW_PRE __stringify(api) ".ucode" 82 83 static const struct iwl_base_params iwl_bz_base_params = { 84 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 85 .num_of_queues = 512, 86 .max_tfd_queue_size = 65536, 87 .shadow_ram_support = true, 88 .led_compensation = 57, 89 .wd_timeout = IWL_LONG_WD_TIMEOUT, 90 .max_event_log_size = 512, 91 .shadow_reg_enable = true, 92 .pcie_l1_allowed = true, 93 }; 94 95 static const struct iwl_ht_params iwl_gl_a_ht_params = { 96 .stbc = false, /* we explicitly disable STBC for GL step A */ 97 .ldpc = true, 98 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 99 BIT(NL80211_BAND_6GHZ), 100 }; 101 102 #define IWL_DEVICE_BZ_COMMON \ 103 .ucode_api_max = IWL_BZ_UCODE_API_MAX, \ 104 .ucode_api_min = IWL_BZ_UCODE_API_MIN, \ 105 .led_mode = IWL_LED_RF_STATE, \ 106 .nvm_hw_section_num = 10, \ 107 .non_shared_ant = ANT_B, \ 108 .dccm_offset = IWL_BZ_DCCM_OFFSET, \ 109 .dccm_len = IWL_BZ_DCCM_LEN, \ 110 .dccm2_offset = IWL_BZ_DCCM2_OFFSET, \ 111 .dccm2_len = IWL_BZ_DCCM2_LEN, \ 112 .smem_offset = IWL_BZ_SMEM_OFFSET, \ 113 .smem_len = IWL_BZ_SMEM_LEN, \ 114 .apmg_not_supported = true, \ 115 .trans.mq_rx_supported = true, \ 116 .vht_mu_mimo_supported = true, \ 117 .mac_addr_from_csr = 0x30, \ 118 .nvm_ver = IWL_BZ_NVM_VERSION, \ 119 .trans.rf_id = true, \ 120 .trans.gen2 = true, \ 121 .nvm_type = IWL_NVM_EXT, \ 122 .dbgc_supported = true, \ 123 .min_umac_error_event_table = 0xD0000, \ 124 .d3_debug_data_base_addr = 0x401000, \ 125 .d3_debug_data_length = 60 * 1024, \ 126 .mon_smem_regs = { \ 127 .write_ptr = { \ 128 .addr = LDBG_M2S_BUF_WPTR, \ 129 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 130 }, \ 131 .cycle_cnt = { \ 132 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 133 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 134 }, \ 135 }, \ 136 .trans.umac_prph_offset = 0x300000, \ 137 .trans.device_family = IWL_DEVICE_FAMILY_BZ, \ 138 .trans.base_params = &iwl_bz_base_params, \ 139 .min_txq_size = 128, \ 140 .gp2_reg_addr = 0xd02c68, \ 141 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \ 142 .mon_dram_regs = { \ 143 .write_ptr = { \ 144 .addr = DBGC_CUR_DBGBUF_STATUS, \ 145 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 146 }, \ 147 .cycle_cnt = { \ 148 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 149 .mask = 0xffffffff, \ 150 }, \ 151 .cur_frag = { \ 152 .addr = DBGC_CUR_DBGBUF_STATUS, \ 153 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 154 }, \ 155 }, \ 156 .mon_dbgi_regs = { \ 157 .write_ptr = { \ 158 .addr = DBGI_SRAM_FIFO_POINTERS, \ 159 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \ 160 }, \ 161 } 162 163 #define IWL_DEVICE_BZ \ 164 IWL_DEVICE_BZ_COMMON, \ 165 .ht_params = &iwl_22000_ht_params 166 167 #define IWL_DEVICE_GL_A \ 168 IWL_DEVICE_BZ_COMMON, \ 169 .ht_params = &iwl_gl_a_ht_params 170 171 /* 172 * If the device doesn't support HE, no need to have that many buffers. 173 * These sizes were picked according to 8 MSDUs inside 256 A-MSDUs in an 174 * A-MPDU, with additional overhead to account for processing time. 175 */ 176 #define IWL_NUM_RBDS_NON_HE 512 177 #define IWL_NUM_RBDS_BZ_HE 4096 178 179 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = { 180 .device_family = IWL_DEVICE_FAMILY_BZ, 181 .base_params = &iwl_bz_base_params, 182 .mq_rx_supported = true, 183 .rf_id = true, 184 .gen2 = true, 185 .integrated = true, 186 .umac_prph_offset = 0x300000, 187 .xtal_latency = 12000, 188 .low_latency_xtal = true, 189 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 190 }; 191 192 const char iwl_bz_name[] = "Intel(R) TBD Bz device"; 193 194 const struct iwl_cfg iwl_cfg_bz = { 195 .fw_name_mac = "bz", 196 .uhb_supported = true, 197 IWL_DEVICE_BZ, 198 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 199 .num_rbds = IWL_NUM_RBDS_BZ_HE, 200 }; 201 202 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = { 203 .fw_name_pre = IWL_GL_A_FM_A_FW_PRE, 204 .uhb_supported = true, 205 IWL_DEVICE_GL_A, 206 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 207 .num_rbds = IWL_NUM_RBDS_BZ_HE, 208 }; 209 210 const struct iwl_cfg iwl_cfg_gl = { 211 .fw_name_mac = "gl", 212 .uhb_supported = true, 213 IWL_DEVICE_BZ, 214 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 215 .num_rbds = IWL_NUM_RBDS_BZ_HE, 216 }; 217 218 219 MODULE_FIRMWARE(IWL_BZ_A_HR_A_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 220 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 221 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 222 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 223 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 224 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 225 MODULE_FIRMWARE(IWL_BZ_A_FM_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 226 MODULE_FIRMWARE(IWL_BZ_A_FM_C_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 227 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 228 MODULE_FIRMWARE(IWL_BZ_A_FM4_A_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 229 MODULE_FIRMWARE(IWL_BZ_A_FM4_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 230 MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 231 MODULE_FIRMWARE(IWL_GL_C_FM_C_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 232