1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2022 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_22000_UCODE_API_MAX 77 14 15 /* Lowest firmware API version supported */ 16 #define IWL_22000_UCODE_API_MIN 39 17 18 /* NVM versions */ 19 #define IWL_22000_NVM_VERSION 0x0a1d 20 21 /* Memory offsets and lengths */ 22 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_22000_DCCM2_OFFSET 0x880000 25 #define IWL_22000_DCCM2_LEN 0x8000 26 #define IWL_22000_SMEM_OFFSET 0x400000 27 #define IWL_22000_SMEM_LEN 0xD0000 28 29 #define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-" 30 #define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-" 31 #define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-" 32 #define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-" 33 #define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-" 34 #define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-" 35 #define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-" 36 #define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-" 37 #define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-" 38 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-" 39 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-" 40 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-" 41 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-" 42 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-" 43 #define IWL_SO_A_MR_A_FW_PRE "iwlwifi-so-a0-mr-a0-" 44 #define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-" 45 #define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-" 46 #define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-" 47 #define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-" 48 #define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0-" 49 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-" 50 #define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0-" 51 #define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-" 52 #define IWL_MA_A_FM_A_FW_PRE "iwlwifi-ma-a0-fm-a0-" 53 #define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-" 54 #define IWL_BZ_A_HR_A_FW_PRE "iwlwifi-bz-a0-hr-b0-" 55 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0-" 56 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0-" 57 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0-" 58 #define IWL_BZ_A_MR_A_FW_PRE "iwlwifi-bz-a0-mr-a0-" 59 #define IWL_BZ_A_FM_A_FW_PRE "iwlwifi-bz-a0-fm-a0-" 60 #define IWL_BZ_A_FM4_A_FW_PRE "iwlwifi-bz-a0-fm4-a0-" 61 #define IWL_BZ_A_FM_B_FW_PRE "iwlwifi-bz-a0-fm-b0-" 62 #define IWL_BZ_A_FM4_B_FW_PRE "iwlwifi-bz-a0-fm4-b0-" 63 #define IWL_GL_A_FM_A_FW_PRE "iwlwifi-gl-a0-fm-a0-" 64 #define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0-" 65 #define IWL_BZ_Z_GF_A_FW_PRE "iwlwifi-bz-z0-gf-a0-" 66 #define IWL_BNJ_A_FM_A_FW_PRE "iwlwifi-BzBnj-a0-fm-a0-" 67 #define IWL_BNJ_A_FM4_A_FW_PRE "iwlwifi-BzBnj-a0-fm4-a0-" 68 #define IWL_BNJ_B_FM4_B_FW_PRE "iwlwifi-BzBnj-b0-fm4-b0-" 69 #define IWL_BNJ_A_GF_A_FW_PRE "iwlwifi-BzBnj-a0-gf-a0-" 70 #define IWL_BNJ_B_GF_A_FW_PRE "iwlwifi-BzBnj-b0-gf-a0-" 71 #define IWL_BNJ_A_GF4_A_FW_PRE "iwlwifi-BzBnj-a0-gf4-a0-" 72 #define IWL_BNJ_B_GF4_A_FW_PRE "iwlwifi-BzBnj-b0-gf4-a0-" 73 #define IWL_BNJ_A_HR_A_FW_PRE "iwlwifi-BzBnj-a0-hr-b0-" 74 #define IWL_BNJ_A_HR_B_FW_PRE "iwlwifi-BzBnj-a0-hr-b0-" 75 #define IWL_BNJ_B_HR_A_FW_PRE "iwlwifi-BzBnj-b0-hr-b0-" 76 #define IWL_BNJ_B_HR_B_FW_PRE "iwlwifi-BzBnj-b0-hr-b0-" 77 #define IWL_BNJ_B_FM_B_FW_PRE "iwlwifi-BzBnj-b0-fm-b0-" 78 79 80 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \ 81 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode" 82 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \ 83 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode" 84 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \ 85 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 86 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \ 87 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode" 88 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \ 89 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode" 90 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \ 91 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode" 92 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \ 93 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode" 94 #define IWL_CC_A_MODULE_FIRMWARE(api) \ 95 IWL_CC_A_FW_PRE __stringify(api) ".ucode" 96 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \ 97 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode" 98 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 99 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode" 100 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \ 101 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode" 102 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \ 103 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode" 104 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 105 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 106 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \ 107 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 108 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \ 109 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 110 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \ 111 IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode" 112 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \ 113 IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode" 114 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \ 115 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode" 116 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \ 117 IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode" 118 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \ 119 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode" 120 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api) \ 121 IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode" 122 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \ 123 IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode" 124 #define IWL_BZ_A_HR_A_MODULE_FIRMWARE(api) \ 125 IWL_BZ_A_HR_A_FW_PRE __stringify(api) ".ucode" 126 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 127 IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 128 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \ 129 IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode" 130 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \ 131 IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 132 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \ 133 IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode" 134 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \ 135 IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode" 136 #define IWL_BZ_A_FM4_A_MODULE_FIRMWARE(api) \ 137 IWL_BZ_A_FM4_A_FW_PRE __stringify(api) ".ucode" 138 #define IWL_BZ_A_FM_B_MODULE_FIRMWARE(api) \ 139 IWL_BZ_A_FM_B_FW_PRE __stringify(api) ".ucode" 140 #define IWL_BZ_A_FM4_B_MODULE_FIRMWARE(api) \ 141 IWL_BZ_A_FM4_B_FW_PRE __stringify(api) ".ucode" 142 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \ 143 IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode" 144 #define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \ 145 IWL_GL_B_FM_B_FW_PRE __stringify(api) ".ucode" 146 #define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \ 147 IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode" 148 #define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \ 149 IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode" 150 #define IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(api) \ 151 IWL_BNJ_B_FM4_B_FW_PRE __stringify(api) ".ucode" 152 #define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \ 153 IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 154 #define IWL_BNJ_B_GF_A_MODULE_FIRMWARE(api) \ 155 IWL_BNJ_B_GF_A_FW_PRE __stringify(api) ".ucode" 156 #define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 157 IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 158 #define IWL_BNJ_B_GF4_A_MODULE_FIRMWARE(api) \ 159 IWL_BNJ_B_GF4_A_FW_PRE __stringify(api) ".ucode" 160 #define IWL_BNJ_A_HR_A_MODULE_FIRMWARE(api) \ 161 IWL_BNJ_A_HR_A_FW_PRE __stringify(api) ".ucode" 162 #define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \ 163 IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 164 #define IWL_BNJ_B_HR_A_MODULE_FIRMWARE(api) \ 165 IWL_BNJ_B_HR_A_FW_PRE __stringify(api) ".ucode" 166 #define IWL_BNJ_B_HR_B_MODULE_FIRMWARE(api) \ 167 IWL_BNJ_B_HR_B_FW_PRE __stringify(api) ".ucode" 168 #define IWL_BNJ_B_FM_B_MODULE_FIRMWARE(api) \ 169 IWL_BNJ_B_FM_B_FW_PRE __stringify(api) ".ucode" 170 171 static const struct iwl_base_params iwl_22000_base_params = { 172 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 173 .num_of_queues = 512, 174 .max_tfd_queue_size = 256, 175 .shadow_ram_support = true, 176 .led_compensation = 57, 177 .wd_timeout = IWL_LONG_WD_TIMEOUT, 178 .max_event_log_size = 512, 179 .shadow_reg_enable = true, 180 .pcie_l1_allowed = true, 181 }; 182 183 static const struct iwl_base_params iwl_ax210_base_params = { 184 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 185 .num_of_queues = 512, 186 .max_tfd_queue_size = 65536, 187 .shadow_ram_support = true, 188 .led_compensation = 57, 189 .wd_timeout = IWL_LONG_WD_TIMEOUT, 190 .max_event_log_size = 512, 191 .shadow_reg_enable = true, 192 .pcie_l1_allowed = true, 193 }; 194 195 static const struct iwl_ht_params iwl_22000_ht_params = { 196 .stbc = true, 197 .ldpc = true, 198 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 199 BIT(NL80211_BAND_6GHZ), 200 }; 201 202 static const struct iwl_ht_params iwl_gl_a_ht_params = { 203 .stbc = false, /* we explicitly disable STBC for GL step A */ 204 .ldpc = true, 205 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 206 BIT(NL80211_BAND_6GHZ), 207 }; 208 209 #define IWL_DEVICE_22000_COMMON \ 210 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 211 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 212 .led_mode = IWL_LED_RF_STATE, \ 213 .nvm_hw_section_num = 10, \ 214 .non_shared_ant = ANT_B, \ 215 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 216 .dccm_len = IWL_22000_DCCM_LEN, \ 217 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 218 .dccm2_len = IWL_22000_DCCM2_LEN, \ 219 .smem_offset = IWL_22000_SMEM_OFFSET, \ 220 .smem_len = IWL_22000_SMEM_LEN, \ 221 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 222 .apmg_not_supported = true, \ 223 .trans.mq_rx_supported = true, \ 224 .vht_mu_mimo_supported = true, \ 225 .mac_addr_from_csr = 0x380, \ 226 .ht_params = &iwl_22000_ht_params, \ 227 .nvm_ver = IWL_22000_NVM_VERSION, \ 228 .trans.use_tfh = true, \ 229 .trans.rf_id = true, \ 230 .trans.gen2 = true, \ 231 .nvm_type = IWL_NVM_EXT, \ 232 .dbgc_supported = true, \ 233 .min_umac_error_event_table = 0x400000, \ 234 .d3_debug_data_base_addr = 0x401000, \ 235 .d3_debug_data_length = 60 * 1024, \ 236 .mon_smem_regs = { \ 237 .write_ptr = { \ 238 .addr = LDBG_M2S_BUF_WPTR, \ 239 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 240 }, \ 241 .cycle_cnt = { \ 242 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 243 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 244 }, \ 245 } 246 247 #define IWL_DEVICE_22500 \ 248 IWL_DEVICE_22000_COMMON, \ 249 .trans.device_family = IWL_DEVICE_FAMILY_22000, \ 250 .trans.base_params = &iwl_22000_base_params, \ 251 .gp2_reg_addr = 0xa02c68, \ 252 .mon_dram_regs = { \ 253 .write_ptr = { \ 254 .addr = MON_BUFF_WRPTR_VER2, \ 255 .mask = 0xffffffff, \ 256 }, \ 257 .cycle_cnt = { \ 258 .addr = MON_BUFF_CYCLE_CNT_VER2, \ 259 .mask = 0xffffffff, \ 260 }, \ 261 } 262 263 #define IWL_DEVICE_AX210 \ 264 IWL_DEVICE_22000_COMMON, \ 265 .trans.umac_prph_offset = 0x300000, \ 266 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \ 267 .trans.base_params = &iwl_ax210_base_params, \ 268 .min_txq_size = 128, \ 269 .gp2_reg_addr = 0xd02c68, \ 270 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, \ 271 .mon_dram_regs = { \ 272 .write_ptr = { \ 273 .addr = DBGC_CUR_DBGBUF_STATUS, \ 274 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 275 }, \ 276 .cycle_cnt = { \ 277 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 278 .mask = 0xffffffff, \ 279 }, \ 280 .cur_frag = { \ 281 .addr = DBGC_CUR_DBGBUF_STATUS, \ 282 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 283 }, \ 284 } 285 286 #define IWL_DEVICE_BZ_COMMON \ 287 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 288 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 289 .led_mode = IWL_LED_RF_STATE, \ 290 .nvm_hw_section_num = 10, \ 291 .non_shared_ant = ANT_B, \ 292 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 293 .dccm_len = IWL_22000_DCCM_LEN, \ 294 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 295 .dccm2_len = IWL_22000_DCCM2_LEN, \ 296 .smem_offset = IWL_22000_SMEM_OFFSET, \ 297 .smem_len = IWL_22000_SMEM_LEN, \ 298 .apmg_not_supported = true, \ 299 .trans.mq_rx_supported = true, \ 300 .vht_mu_mimo_supported = true, \ 301 .mac_addr_from_csr = 0x30, \ 302 .nvm_ver = IWL_22000_NVM_VERSION, \ 303 .trans.use_tfh = true, \ 304 .trans.rf_id = true, \ 305 .trans.gen2 = true, \ 306 .nvm_type = IWL_NVM_EXT, \ 307 .dbgc_supported = true, \ 308 .min_umac_error_event_table = 0xD0000, \ 309 .d3_debug_data_base_addr = 0x401000, \ 310 .d3_debug_data_length = 60 * 1024, \ 311 .mon_smem_regs = { \ 312 .write_ptr = { \ 313 .addr = LDBG_M2S_BUF_WPTR, \ 314 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 315 }, \ 316 .cycle_cnt = { \ 317 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 318 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 319 }, \ 320 }, \ 321 .trans.umac_prph_offset = 0x300000, \ 322 .trans.device_family = IWL_DEVICE_FAMILY_BZ, \ 323 .trans.base_params = &iwl_ax210_base_params, \ 324 .min_txq_size = 128, \ 325 .gp2_reg_addr = 0xd02c68, \ 326 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \ 327 .mon_dram_regs = { \ 328 .write_ptr = { \ 329 .addr = DBGC_CUR_DBGBUF_STATUS, \ 330 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 331 }, \ 332 .cycle_cnt = { \ 333 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 334 .mask = 0xffffffff, \ 335 }, \ 336 .cur_frag = { \ 337 .addr = DBGC_CUR_DBGBUF_STATUS, \ 338 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 339 }, \ 340 }, \ 341 .mon_dbgi_regs = { \ 342 .write_ptr = { \ 343 .addr = DBGI_SRAM_FIFO_POINTERS, \ 344 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \ 345 }, \ 346 } 347 348 #define IWL_DEVICE_BZ \ 349 IWL_DEVICE_BZ_COMMON, \ 350 .ht_params = &iwl_22000_ht_params 351 352 #define IWL_DEVICE_GL_A \ 353 IWL_DEVICE_BZ_COMMON, \ 354 .ht_params = &iwl_gl_a_ht_params 355 356 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = { 357 .mq_rx_supported = true, 358 .use_tfh = true, 359 .rf_id = true, 360 .gen2 = true, 361 .device_family = IWL_DEVICE_FAMILY_22000, 362 .base_params = &iwl_22000_base_params, 363 }; 364 365 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = { 366 .mq_rx_supported = true, 367 .use_tfh = true, 368 .rf_id = true, 369 .gen2 = true, 370 .device_family = IWL_DEVICE_FAMILY_22000, 371 .base_params = &iwl_22000_base_params, 372 .integrated = true, 373 .xtal_latency = 500, 374 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 375 }; 376 377 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = { 378 .mq_rx_supported = true, 379 .use_tfh = true, 380 .rf_id = true, 381 .gen2 = true, 382 .device_family = IWL_DEVICE_FAMILY_22000, 383 .base_params = &iwl_22000_base_params, 384 .integrated = true, 385 .xtal_latency = 1820, 386 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US, 387 }; 388 389 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = { 390 .mq_rx_supported = true, 391 .use_tfh = true, 392 .rf_id = true, 393 .gen2 = true, 394 .device_family = IWL_DEVICE_FAMILY_22000, 395 .base_params = &iwl_22000_base_params, 396 .integrated = true, 397 .xtal_latency = 12000, 398 .low_latency_xtal = true, 399 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 400 }; 401 402 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = { 403 .mq_rx_supported = true, 404 .use_tfh = true, 405 .rf_id = true, 406 .gen2 = true, 407 .device_family = IWL_DEVICE_FAMILY_AX210, 408 .base_params = &iwl_ax210_base_params, 409 .umac_prph_offset = 0x300000, 410 }; 411 412 const struct iwl_cfg_trans_params iwl_so_trans_cfg = { 413 .mq_rx_supported = true, 414 .use_tfh = true, 415 .rf_id = true, 416 .gen2 = true, 417 .device_family = IWL_DEVICE_FAMILY_AX210, 418 .base_params = &iwl_ax210_base_params, 419 .umac_prph_offset = 0x300000, 420 .integrated = true, 421 /* TODO: the following values need to be checked */ 422 .xtal_latency = 500, 423 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 424 }; 425 426 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = { 427 .mq_rx_supported = true, 428 .use_tfh = true, 429 .rf_id = true, 430 .gen2 = true, 431 .device_family = IWL_DEVICE_FAMILY_AX210, 432 .base_params = &iwl_ax210_base_params, 433 .umac_prph_offset = 0x300000, 434 .integrated = true, 435 .low_latency_xtal = true, 436 .xtal_latency = 12000, 437 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 438 }; 439 440 const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = { 441 .mq_rx_supported = true, 442 .use_tfh = true, 443 .rf_id = true, 444 .gen2 = true, 445 .device_family = IWL_DEVICE_FAMILY_AX210, 446 .base_params = &iwl_ax210_base_params, 447 .umac_prph_offset = 0x300000, 448 .integrated = true, 449 .low_latency_xtal = true, 450 .xtal_latency = 12000, 451 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 452 .imr_enabled = true, 453 }; 454 455 /* 456 * If the device doesn't support HE, no need to have that many buffers. 457 * 22000 devices can split multiple frames into a single RB, so fewer are 458 * needed; AX210 cannot (but use smaller RBs by default) - these sizes 459 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with 460 * additional overhead to account for processing time. 461 */ 462 #define IWL_NUM_RBDS_NON_HE 512 463 #define IWL_NUM_RBDS_22000_HE 2048 464 #define IWL_NUM_RBDS_AX210_HE 4096 465 466 /* 467 * All JF radio modules are part of the 9000 series, but the MAC part 468 * looks more like 22000. That's why this device is here, but called 469 * 9560 nevertheless. 470 */ 471 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = { 472 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE, 473 IWL_DEVICE_22500, 474 .num_rbds = IWL_NUM_RBDS_NON_HE, 475 }; 476 477 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = { 478 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE, 479 IWL_DEVICE_22500, 480 .num_rbds = IWL_NUM_RBDS_NON_HE, 481 }; 482 483 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = { 484 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE, 485 IWL_DEVICE_22500, 486 /* 487 * This device doesn't support receiving BlockAck with a large bitmap 488 * so we need to restrict the size of transmitted aggregation to the 489 * HT size; mac80211 would otherwise pick the HE max (256) by default. 490 */ 491 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 492 .num_rbds = IWL_NUM_RBDS_NON_HE, 493 }; 494 495 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = { 496 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE, 497 IWL_DEVICE_22500, 498 /* 499 * This device doesn't support receiving BlockAck with a large bitmap 500 * so we need to restrict the size of transmitted aggregation to the 501 * HT size; mac80211 would otherwise pick the HE max (256) by default. 502 */ 503 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 504 .num_rbds = IWL_NUM_RBDS_NON_HE, 505 }; 506 507 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = { 508 .device_family = IWL_DEVICE_FAMILY_22000, 509 .base_params = &iwl_22000_base_params, 510 .mq_rx_supported = true, 511 .use_tfh = true, 512 .rf_id = true, 513 .gen2 = true, 514 .bisr_workaround = 1, 515 }; 516 517 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = { 518 .device_family = IWL_DEVICE_FAMILY_AX210, 519 .base_params = &iwl_ax210_base_params, 520 .mq_rx_supported = true, 521 .use_tfh = true, 522 .rf_id = true, 523 .gen2 = true, 524 .integrated = true, 525 .umac_prph_offset = 0x300000 526 }; 527 528 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = { 529 .device_family = IWL_DEVICE_FAMILY_BZ, 530 .base_params = &iwl_ax210_base_params, 531 .mq_rx_supported = true, 532 .use_tfh = true, 533 .rf_id = true, 534 .gen2 = true, 535 .integrated = true, 536 .umac_prph_offset = 0x300000, 537 .xtal_latency = 12000, 538 .low_latency_xtal = true, 539 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 540 }; 541 542 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101"; 543 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz"; 544 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz"; 545 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203"; 546 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz"; 547 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz"; 548 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz"; 549 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz"; 550 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz"; 551 const char iwl_bz_name[] = "Intel(R) TBD Bz device"; 552 553 const char iwl_ax200_killer_1650w_name[] = 554 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)"; 555 const char iwl_ax200_killer_1650x_name[] = 556 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)"; 557 const char iwl_ax201_killer_1650s_name[] = 558 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)"; 559 const char iwl_ax201_killer_1650i_name[] = 560 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)"; 561 const char iwl_ax210_killer_1675w_name[] = 562 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)"; 563 const char iwl_ax210_killer_1675x_name[] = 564 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)"; 565 const char iwl_ax211_killer_1675s_name[] = 566 "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)"; 567 const char iwl_ax211_killer_1675i_name[] = 568 "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)"; 569 const char iwl_ax411_killer_1690s_name[] = 570 "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)"; 571 const char iwl_ax411_killer_1690i_name[] = 572 "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)"; 573 574 const struct iwl_cfg iwl_qu_b0_hr1_b0 = { 575 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 576 IWL_DEVICE_22500, 577 /* 578 * This device doesn't support receiving BlockAck with a large bitmap 579 * so we need to restrict the size of transmitted aggregation to the 580 * HT size; mac80211 would otherwise pick the HE max (256) by default. 581 */ 582 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 583 .tx_with_siso_diversity = true, 584 .num_rbds = IWL_NUM_RBDS_22000_HE, 585 }; 586 587 const struct iwl_cfg iwl_qu_b0_hr_b0 = { 588 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 589 IWL_DEVICE_22500, 590 /* 591 * This device doesn't support receiving BlockAck with a large bitmap 592 * so we need to restrict the size of transmitted aggregation to the 593 * HT size; mac80211 would otherwise pick the HE max (256) by default. 594 */ 595 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 596 .num_rbds = IWL_NUM_RBDS_22000_HE, 597 }; 598 599 const struct iwl_cfg iwl_ax201_cfg_qu_hr = { 600 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 601 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 602 IWL_DEVICE_22500, 603 /* 604 * This device doesn't support receiving BlockAck with a large bitmap 605 * so we need to restrict the size of transmitted aggregation to the 606 * HT size; mac80211 would otherwise pick the HE max (256) by default. 607 */ 608 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 609 .num_rbds = IWL_NUM_RBDS_22000_HE, 610 }; 611 612 const struct iwl_cfg iwl_qu_c0_hr1_b0 = { 613 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 614 IWL_DEVICE_22500, 615 /* 616 * This device doesn't support receiving BlockAck with a large bitmap 617 * so we need to restrict the size of transmitted aggregation to the 618 * HT size; mac80211 would otherwise pick the HE max (256) by default. 619 */ 620 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 621 .tx_with_siso_diversity = true, 622 .num_rbds = IWL_NUM_RBDS_22000_HE, 623 }; 624 625 const struct iwl_cfg iwl_qu_c0_hr_b0 = { 626 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 627 IWL_DEVICE_22500, 628 /* 629 * This device doesn't support receiving BlockAck with a large bitmap 630 * so we need to restrict the size of transmitted aggregation to the 631 * HT size; mac80211 would otherwise pick the HE max (256) by default. 632 */ 633 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 634 .num_rbds = IWL_NUM_RBDS_22000_HE, 635 }; 636 637 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = { 638 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 639 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 640 IWL_DEVICE_22500, 641 /* 642 * This device doesn't support receiving BlockAck with a large bitmap 643 * so we need to restrict the size of transmitted aggregation to the 644 * HT size; mac80211 would otherwise pick the HE max (256) by default. 645 */ 646 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 647 .num_rbds = IWL_NUM_RBDS_22000_HE, 648 }; 649 650 const struct iwl_cfg iwl_quz_a0_hr1_b0 = { 651 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 652 IWL_DEVICE_22500, 653 /* 654 * This device doesn't support receiving BlockAck with a large bitmap 655 * so we need to restrict the size of transmitted aggregation to the 656 * HT size; mac80211 would otherwise pick the HE max (256) by default. 657 */ 658 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 659 .tx_with_siso_diversity = true, 660 .num_rbds = IWL_NUM_RBDS_22000_HE, 661 }; 662 663 const struct iwl_cfg iwl_ax201_cfg_quz_hr = { 664 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 665 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 666 IWL_DEVICE_22500, 667 /* 668 * This device doesn't support receiving BlockAck with a large bitmap 669 * so we need to restrict the size of transmitted aggregation to the 670 * HT size; mac80211 would otherwise pick the HE max (256) by default. 671 */ 672 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 673 .num_rbds = IWL_NUM_RBDS_22000_HE, 674 }; 675 676 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = { 677 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 678 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 679 IWL_DEVICE_22500, 680 /* 681 * This device doesn't support receiving BlockAck with a large bitmap 682 * so we need to restrict the size of transmitted aggregation to the 683 * HT size; mac80211 would otherwise pick the HE max (256) by default. 684 */ 685 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 686 .num_rbds = IWL_NUM_RBDS_22000_HE, 687 }; 688 689 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = { 690 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 691 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 692 IWL_DEVICE_22500, 693 /* 694 * This device doesn't support receiving BlockAck with a large bitmap 695 * so we need to restrict the size of transmitted aggregation to the 696 * HT size; mac80211 would otherwise pick the HE max (256) by default. 697 */ 698 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 699 .num_rbds = IWL_NUM_RBDS_22000_HE, 700 }; 701 702 const struct iwl_cfg iwl_ax200_cfg_cc = { 703 .fw_name_pre = IWL_CC_A_FW_PRE, 704 IWL_DEVICE_22500, 705 /* 706 * This device doesn't support receiving BlockAck with a large bitmap 707 * so we need to restrict the size of transmitted aggregation to the 708 * HT size; mac80211 would otherwise pick the HE max (256) by default. 709 */ 710 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 711 .num_rbds = IWL_NUM_RBDS_22000_HE, 712 }; 713 714 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = { 715 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 716 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 717 IWL_DEVICE_22500, 718 /* 719 * This device doesn't support receiving BlockAck with a large bitmap 720 * so we need to restrict the size of transmitted aggregation to the 721 * HT size; mac80211 would otherwise pick the HE max (256) by default. 722 */ 723 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 724 .num_rbds = IWL_NUM_RBDS_22000_HE, 725 }; 726 727 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = { 728 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 729 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 730 IWL_DEVICE_22500, 731 /* 732 * This device doesn't support receiving BlockAck with a large bitmap 733 * so we need to restrict the size of transmitted aggregation to the 734 * HT size; mac80211 would otherwise pick the HE max (256) by default. 735 */ 736 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 737 .num_rbds = IWL_NUM_RBDS_22000_HE, 738 }; 739 740 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = { 741 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 742 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 743 IWL_DEVICE_22500, 744 /* 745 * This device doesn't support receiving BlockAck with a large bitmap 746 * so we need to restrict the size of transmitted aggregation to the 747 * HT size; mac80211 would otherwise pick the HE max (256) by default. 748 */ 749 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 750 .num_rbds = IWL_NUM_RBDS_22000_HE, 751 }; 752 753 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = { 754 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 755 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 756 IWL_DEVICE_22500, 757 /* 758 * This device doesn't support receiving BlockAck with a large bitmap 759 * so we need to restrict the size of transmitted aggregation to the 760 * HT size; mac80211 would otherwise pick the HE max (256) by default. 761 */ 762 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 763 .num_rbds = IWL_NUM_RBDS_22000_HE, 764 }; 765 766 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = { 767 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE, 768 IWL_DEVICE_22500, 769 /* 770 * This device doesn't support receiving BlockAck with a large bitmap 771 * so we need to restrict the size of transmitted aggregation to the 772 * HT size; mac80211 would otherwise pick the HE max (256) by default. 773 */ 774 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 775 .num_rbds = IWL_NUM_RBDS_22000_HE, 776 }; 777 778 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = { 779 .name = "Intel(R) Wireless-AC 9560 160MHz", 780 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE, 781 IWL_DEVICE_AX210, 782 .num_rbds = IWL_NUM_RBDS_NON_HE, 783 }; 784 785 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = { 786 .name = iwl_ax211_name, 787 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 788 .uhb_supported = true, 789 IWL_DEVICE_AX210, 790 .num_rbds = IWL_NUM_RBDS_AX210_HE, 791 }; 792 793 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = { 794 .name = iwl_ax211_name, 795 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 796 .uhb_supported = true, 797 IWL_DEVICE_AX210, 798 .num_rbds = IWL_NUM_RBDS_AX210_HE, 799 .trans.xtal_latency = 12000, 800 .trans.low_latency_xtal = true, 801 }; 802 803 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = { 804 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 805 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE, 806 .uhb_supported = true, 807 IWL_DEVICE_AX210, 808 .num_rbds = IWL_NUM_RBDS_AX210_HE, 809 }; 810 811 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = { 812 .name = iwl_ax411_name, 813 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 814 .uhb_supported = true, 815 IWL_DEVICE_AX210, 816 .num_rbds = IWL_NUM_RBDS_AX210_HE, 817 }; 818 819 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = { 820 .name = iwl_ax411_name, 821 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 822 .uhb_supported = true, 823 IWL_DEVICE_AX210, 824 .num_rbds = IWL_NUM_RBDS_AX210_HE, 825 .trans.xtal_latency = 12000, 826 .trans.low_latency_xtal = true, 827 }; 828 829 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = { 830 .name = iwl_ax411_name, 831 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE, 832 .uhb_supported = true, 833 IWL_DEVICE_AX210, 834 .num_rbds = IWL_NUM_RBDS_AX210_HE, 835 }; 836 837 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = { 838 .name = iwl_ax211_name, 839 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE, 840 .uhb_supported = true, 841 IWL_DEVICE_AX210, 842 .num_rbds = IWL_NUM_RBDS_AX210_HE, 843 }; 844 845 const struct iwl_cfg iwl_cfg_snj_hr_b0 = { 846 .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE, 847 .uhb_supported = true, 848 IWL_DEVICE_AX210, 849 .num_rbds = IWL_NUM_RBDS_AX210_HE, 850 }; 851 852 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = { 853 .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE, 854 .uhb_supported = true, 855 IWL_DEVICE_AX210, 856 .num_rbds = IWL_NUM_RBDS_AX210_HE, 857 }; 858 859 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = { 860 .fw_name_pre = IWL_MA_A_HR_B_FW_PRE, 861 .uhb_supported = true, 862 IWL_DEVICE_AX210, 863 .num_rbds = IWL_NUM_RBDS_AX210_HE, 864 }; 865 866 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = { 867 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE, 868 .uhb_supported = true, 869 IWL_DEVICE_AX210, 870 .num_rbds = IWL_NUM_RBDS_AX210_HE, 871 }; 872 873 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = { 874 .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE, 875 .uhb_supported = true, 876 IWL_DEVICE_AX210, 877 .num_rbds = IWL_NUM_RBDS_AX210_HE, 878 }; 879 880 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = { 881 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 882 .uhb_supported = true, 883 IWL_DEVICE_AX210, 884 .num_rbds = IWL_NUM_RBDS_AX210_HE, 885 }; 886 887 const struct iwl_cfg iwl_cfg_ma_a0_ms_a0 = { 888 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 889 .uhb_supported = false, 890 IWL_DEVICE_AX210, 891 .num_rbds = IWL_NUM_RBDS_AX210_HE, 892 }; 893 894 const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = { 895 .fw_name_pre = IWL_SO_A_MR_A_FW_PRE, 896 .uhb_supported = false, 897 IWL_DEVICE_AX210, 898 .num_rbds = IWL_NUM_RBDS_AX210_HE, 899 }; 900 901 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = { 902 .fw_name_pre = IWL_MA_A_FM_A_FW_PRE, 903 .uhb_supported = true, 904 IWL_DEVICE_AX210, 905 .num_rbds = IWL_NUM_RBDS_AX210_HE, 906 }; 907 908 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = { 909 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 910 .uhb_supported = true, 911 IWL_DEVICE_AX210, 912 .num_rbds = IWL_NUM_RBDS_AX210_HE, 913 }; 914 915 const struct iwl_cfg iwl_cfg_snj_a0_ms_a0 = { 916 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 917 .uhb_supported = false, 918 IWL_DEVICE_AX210, 919 .num_rbds = IWL_NUM_RBDS_AX210_HE, 920 }; 921 922 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = { 923 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 924 IWL_DEVICE_AX210, 925 .num_rbds = IWL_NUM_RBDS_AX210_HE, 926 }; 927 928 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = { 929 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 930 IWL_DEVICE_22500, 931 /* 932 * This device doesn't support receiving BlockAck with a large bitmap 933 * so we need to restrict the size of transmitted aggregation to the 934 * HT size; mac80211 would otherwise pick the HE max (256) by default. 935 */ 936 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 937 .num_rbds = IWL_NUM_RBDS_22000_HE, 938 }; 939 940 const struct iwl_cfg iwl_cfg_bz_a0_hr_a0 = { 941 .fw_name_pre = IWL_BZ_A_HR_A_FW_PRE, 942 .uhb_supported = true, 943 IWL_DEVICE_BZ, 944 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 945 .num_rbds = IWL_NUM_RBDS_AX210_HE, 946 }; 947 948 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = { 949 .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE, 950 .uhb_supported = true, 951 IWL_DEVICE_BZ, 952 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 953 .num_rbds = IWL_NUM_RBDS_AX210_HE, 954 }; 955 956 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = { 957 .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE, 958 .uhb_supported = true, 959 IWL_DEVICE_BZ, 960 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 961 .num_rbds = IWL_NUM_RBDS_AX210_HE, 962 }; 963 964 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = { 965 .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE, 966 .uhb_supported = true, 967 IWL_DEVICE_BZ, 968 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 969 .num_rbds = IWL_NUM_RBDS_AX210_HE, 970 }; 971 972 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = { 973 .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE, 974 .uhb_supported = true, 975 IWL_DEVICE_BZ, 976 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 977 .num_rbds = IWL_NUM_RBDS_AX210_HE, 978 }; 979 980 const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = { 981 .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE, 982 .uhb_supported = true, 983 IWL_DEVICE_BZ, 984 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 985 .num_rbds = IWL_NUM_RBDS_AX210_HE, 986 }; 987 988 const struct iwl_cfg iwl_cfg_bz_a0_fm4_a0 = { 989 .fw_name_pre = IWL_BZ_A_FM4_A_FW_PRE, 990 .uhb_supported = true, 991 IWL_DEVICE_BZ, 992 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 993 .num_rbds = IWL_NUM_RBDS_AX210_HE, 994 }; 995 996 const struct iwl_cfg iwl_cfg_bz_a0_fm_b0 = { 997 .fw_name_pre = IWL_BZ_A_FM_B_FW_PRE, 998 .uhb_supported = true, 999 IWL_DEVICE_BZ, 1000 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 1001 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1002 }; 1003 1004 const struct iwl_cfg iwl_cfg_bz_a0_fm4_b0 = { 1005 .fw_name_pre = IWL_BZ_A_FM4_B_FW_PRE, 1006 .uhb_supported = true, 1007 IWL_DEVICE_BZ, 1008 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 1009 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1010 }; 1011 1012 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = { 1013 .fw_name_pre = IWL_GL_A_FM_A_FW_PRE, 1014 .uhb_supported = true, 1015 IWL_DEVICE_GL_A, 1016 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1017 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1018 }; 1019 1020 const struct iwl_cfg iwl_cfg_gl_b0_fm_b0 = { 1021 .fw_name_pre = IWL_GL_B_FM_B_FW_PRE, 1022 .uhb_supported = true, 1023 IWL_DEVICE_BZ, 1024 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 1025 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1026 }; 1027 1028 const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = { 1029 .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE, 1030 .uhb_supported = true, 1031 IWL_DEVICE_BZ, 1032 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 1033 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1034 }; 1035 1036 const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = { 1037 .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE, 1038 .uhb_supported = true, 1039 IWL_DEVICE_BZ, 1040 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1041 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1042 }; 1043 1044 const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = { 1045 .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE, 1046 .uhb_supported = true, 1047 IWL_DEVICE_BZ, 1048 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1049 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1050 }; 1051 1052 const struct iwl_cfg iwl_cfg_bnj_b0_fm4_b0 = { 1053 .fw_name_pre = IWL_BNJ_B_FM4_B_FW_PRE, 1054 .uhb_supported = true, 1055 IWL_DEVICE_BZ, 1056 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1057 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1058 }; 1059 1060 const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = { 1061 .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE, 1062 .uhb_supported = true, 1063 IWL_DEVICE_BZ, 1064 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1065 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1066 }; 1067 1068 const struct iwl_cfg iwl_cfg_bnj_b0_gf_a0 = { 1069 .fw_name_pre = IWL_BNJ_B_GF_A_FW_PRE, 1070 .uhb_supported = true, 1071 IWL_DEVICE_BZ, 1072 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1073 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1074 }; 1075 1076 const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = { 1077 .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE, 1078 .uhb_supported = true, 1079 IWL_DEVICE_BZ, 1080 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1081 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1082 }; 1083 1084 const struct iwl_cfg iwl_cfg_bnj_b0_gf4_a0 = { 1085 .fw_name_pre = IWL_BNJ_B_GF4_A_FW_PRE, 1086 .uhb_supported = true, 1087 IWL_DEVICE_BZ, 1088 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1089 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1090 }; 1091 1092 const struct iwl_cfg iwl_cfg_bnj_a0_hr_a0 = { 1093 .fw_name_pre = IWL_BNJ_A_HR_A_FW_PRE, 1094 .uhb_supported = true, 1095 IWL_DEVICE_BZ, 1096 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1097 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1098 }; 1099 1100 const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = { 1101 .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE, 1102 .uhb_supported = true, 1103 IWL_DEVICE_BZ, 1104 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1105 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1106 }; 1107 1108 const struct iwl_cfg iwl_cfg_bnj_b0_hr_a0 = { 1109 .fw_name_pre = IWL_BNJ_B_HR_A_FW_PRE, 1110 .uhb_supported = true, 1111 IWL_DEVICE_BZ, 1112 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1113 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1114 }; 1115 1116 const struct iwl_cfg iwl_cfg_bnj_b0_hr_b0 = { 1117 .fw_name_pre = IWL_BNJ_B_HR_B_FW_PRE, 1118 .uhb_supported = true, 1119 IWL_DEVICE_BZ, 1120 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1121 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1122 }; 1123 1124 const struct iwl_cfg iwl_cfg_bnj_b0_fm_b0 = { 1125 .fw_name_pre = IWL_BNJ_B_FM_B_FW_PRE, 1126 .uhb_supported = true, 1127 IWL_DEVICE_BZ, 1128 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 1129 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1130 }; 1131 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1132 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1133 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1134 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1135 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1136 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1137 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1138 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1139 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1140 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1141 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1142 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1143 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1144 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1145 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1146 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1147 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1148 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1149 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1150 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1151 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1152 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1153 MODULE_FIRMWARE(IWL_BZ_A_HR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1154 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1155 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1156 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1157 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1158 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1159 MODULE_FIRMWARE(IWL_BZ_A_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1160 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1161 MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1162 MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1163 MODULE_FIRMWARE(IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1164 MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1165 MODULE_FIRMWARE(IWL_BNJ_B_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1166 MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1167 MODULE_FIRMWARE(IWL_BNJ_B_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1168 MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1169 MODULE_FIRMWARE(IWL_BNJ_B_HR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1170 MODULE_FIRMWARE(IWL_BNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1171 MODULE_FIRMWARE(IWL_BZ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1172 MODULE_FIRMWARE(IWL_BZ_A_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1173 MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1174 MODULE_FIRMWARE(IWL_BNJ_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1175