1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2022 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_22000_UCODE_API_MAX 75 14 15 /* Lowest firmware API version supported */ 16 #define IWL_22000_UCODE_API_MIN 39 17 18 /* NVM versions */ 19 #define IWL_22000_NVM_VERSION 0x0a1d 20 21 /* Memory offsets and lengths */ 22 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_22000_DCCM2_OFFSET 0x880000 25 #define IWL_22000_DCCM2_LEN 0x8000 26 #define IWL_22000_SMEM_OFFSET 0x400000 27 #define IWL_22000_SMEM_LEN 0xD0000 28 29 #define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-" 30 #define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-" 31 #define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-" 32 #define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-" 33 #define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-" 34 #define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-" 35 #define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-" 36 #define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-" 37 #define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-" 38 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-" 39 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-" 40 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-" 41 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-" 42 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-" 43 #define IWL_SO_A_MR_A_FW_PRE "iwlwifi-so-a0-mr-a0-" 44 #define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-" 45 #define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-" 46 #define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-" 47 #define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-" 48 #define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0-" 49 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-" 50 #define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0-" 51 #define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-" 52 #define IWL_MA_A_FM_A_FW_PRE "iwlwifi-ma-a0-fm-a0-" 53 #define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-" 54 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0-" 55 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0-" 56 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0-" 57 #define IWL_BZ_A_MR_A_FW_PRE "iwlwifi-bz-a0-mr-a0-" 58 #define IWL_BZ_A_FM_A_FW_PRE "iwlwifi-bz-a0-fm-a0-" 59 #define IWL_BZ_A_FM4_A_FW_PRE "iwlwifi-bz-a0-fm4-a0-" 60 #define IWL_BZ_A_FM_B_FW_PRE "iwlwifi-bz-a0-fm-b0-" 61 #define IWL_BZ_A_FM4_B_FW_PRE "iwlwifi-bz-a0-fm4-b0-" 62 #define IWL_GL_A_FM_A_FW_PRE "iwlwifi-gl-a0-fm-a0-" 63 #define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0-" 64 #define IWL_BZ_Z_GF_A_FW_PRE "iwlwifi-bz-z0-gf-a0-" 65 #define IWL_BNJ_A_FM_A_FW_PRE "iwlwifi-BzBnj-a0-fm-a0-" 66 #define IWL_BNJ_A_FM4_A_FW_PRE "iwlwifi-BzBnj-a0-fm4-a0-" 67 #define IWL_BNJ_B_FM4_B_FW_PRE "iwlwifi-BzBnj-b0-fm4-b0-" 68 #define IWL_BNJ_A_GF_A_FW_PRE "iwlwifi-BzBnj-a0-gf-a0-" 69 #define IWL_BNJ_B_GF_A_FW_PRE "iwlwifi-BzBnj-b0-gf-a0-" 70 #define IWL_BNJ_A_GF4_A_FW_PRE "iwlwifi-BzBnj-a0-gf4-a0-" 71 #define IWL_BNJ_B_GF4_A_FW_PRE "iwlwifi-BzBnj-b0-gf4-a0-" 72 #define IWL_BNJ_A_HR_B_FW_PRE "iwlwifi-BzBnj-a0-hr-b0-" 73 #define IWL_BNJ_B_HR_B_FW_PRE "iwlwifi-BzBnj-b0-hr-b0-" 74 #define IWL_BNJ_B_FM_B_FW_PRE "iwlwifi-BzBnj-b0-fm-b0-" 75 76 77 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \ 78 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode" 79 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \ 80 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode" 81 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \ 82 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 83 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \ 84 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode" 85 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \ 86 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode" 87 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \ 88 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode" 89 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \ 90 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode" 91 #define IWL_CC_A_MODULE_FIRMWARE(api) \ 92 IWL_CC_A_FW_PRE __stringify(api) ".ucode" 93 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \ 94 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode" 95 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 96 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode" 97 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \ 98 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode" 99 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \ 100 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode" 101 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 102 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 103 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \ 104 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 105 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \ 106 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 107 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \ 108 IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode" 109 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \ 110 IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode" 111 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \ 112 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode" 113 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \ 114 IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode" 115 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \ 116 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode" 117 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api) \ 118 IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode" 119 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \ 120 IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode" 121 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 122 IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 123 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \ 124 IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode" 125 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \ 126 IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 127 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \ 128 IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode" 129 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \ 130 IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode" 131 #define IWL_BZ_A_FM4_A_MODULE_FIRMWARE(api) \ 132 IWL_BZ_A_FM4_A_FW_PRE __stringify(api) ".ucode" 133 #define IWL_BZ_A_FM_B_MODULE_FIRMWARE(api) \ 134 IWL_BZ_A_FM_B_FW_PRE __stringify(api) ".ucode" 135 #define IWL_BZ_A_FM4_B_MODULE_FIRMWARE(api) \ 136 IWL_BZ_A_FM4_B_FW_PRE __stringify(api) ".ucode" 137 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \ 138 IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode" 139 #define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \ 140 IWL_GL_B_FM_B_FW_PRE __stringify(api) ".ucode" 141 #define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \ 142 IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode" 143 #define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \ 144 IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode" 145 #define IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(api) \ 146 IWL_BNJ_B_FM4_B_FW_PRE __stringify(api) ".ucode" 147 #define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \ 148 IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 149 #define IWL_BNJ_B_GF_A_MODULE_FIRMWARE(api) \ 150 IWL_BNJ_B_GF_A_FW_PRE __stringify(api) ".ucode" 151 #define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 152 IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 153 #define IWL_BNJ_B_GF4_A_MODULE_FIRMWARE(api) \ 154 IWL_BNJ_B_GF4_A_FW_PRE __stringify(api) ".ucode" 155 #define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \ 156 IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 157 #define IWL_BNJ_B_HR_B_MODULE_FIRMWARE(api) \ 158 IWL_BNJ_B_HR_B_FW_PRE __stringify(api) ".ucode" 159 #define IWL_BNJ_B_FM_B_MODULE_FIRMWARE(api) \ 160 IWL_BNJ_B_FM_B_FW_PRE __stringify(api) ".ucode" 161 162 static const struct iwl_base_params iwl_22000_base_params = { 163 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 164 .num_of_queues = 512, 165 .max_tfd_queue_size = 256, 166 .shadow_ram_support = true, 167 .led_compensation = 57, 168 .wd_timeout = IWL_LONG_WD_TIMEOUT, 169 .max_event_log_size = 512, 170 .shadow_reg_enable = true, 171 .pcie_l1_allowed = true, 172 }; 173 174 static const struct iwl_base_params iwl_ax210_base_params = { 175 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 176 .num_of_queues = 512, 177 .max_tfd_queue_size = 65536, 178 .shadow_ram_support = true, 179 .led_compensation = 57, 180 .wd_timeout = IWL_LONG_WD_TIMEOUT, 181 .max_event_log_size = 512, 182 .shadow_reg_enable = true, 183 .pcie_l1_allowed = true, 184 }; 185 186 static const struct iwl_ht_params iwl_22000_ht_params = { 187 .stbc = true, 188 .ldpc = true, 189 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 190 BIT(NL80211_BAND_6GHZ), 191 }; 192 193 static const struct iwl_ht_params iwl_gl_a_ht_params = { 194 .stbc = false, /* we explicitly disable STBC for GL step A */ 195 .ldpc = true, 196 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 197 BIT(NL80211_BAND_6GHZ), 198 }; 199 200 #define IWL_DEVICE_22000_COMMON \ 201 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 202 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 203 .led_mode = IWL_LED_RF_STATE, \ 204 .nvm_hw_section_num = 10, \ 205 .non_shared_ant = ANT_B, \ 206 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 207 .dccm_len = IWL_22000_DCCM_LEN, \ 208 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 209 .dccm2_len = IWL_22000_DCCM2_LEN, \ 210 .smem_offset = IWL_22000_SMEM_OFFSET, \ 211 .smem_len = IWL_22000_SMEM_LEN, \ 212 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 213 .apmg_not_supported = true, \ 214 .trans.mq_rx_supported = true, \ 215 .vht_mu_mimo_supported = true, \ 216 .mac_addr_from_csr = 0x380, \ 217 .ht_params = &iwl_22000_ht_params, \ 218 .nvm_ver = IWL_22000_NVM_VERSION, \ 219 .trans.use_tfh = true, \ 220 .trans.rf_id = true, \ 221 .trans.gen2 = true, \ 222 .nvm_type = IWL_NVM_EXT, \ 223 .dbgc_supported = true, \ 224 .min_umac_error_event_table = 0x400000, \ 225 .d3_debug_data_base_addr = 0x401000, \ 226 .d3_debug_data_length = 60 * 1024, \ 227 .mon_smem_regs = { \ 228 .write_ptr = { \ 229 .addr = LDBG_M2S_BUF_WPTR, \ 230 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 231 }, \ 232 .cycle_cnt = { \ 233 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 234 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 235 }, \ 236 } 237 238 #define IWL_DEVICE_22500 \ 239 IWL_DEVICE_22000_COMMON, \ 240 .trans.device_family = IWL_DEVICE_FAMILY_22000, \ 241 .trans.base_params = &iwl_22000_base_params, \ 242 .gp2_reg_addr = 0xa02c68, \ 243 .mon_dram_regs = { \ 244 .write_ptr = { \ 245 .addr = MON_BUFF_WRPTR_VER2, \ 246 .mask = 0xffffffff, \ 247 }, \ 248 .cycle_cnt = { \ 249 .addr = MON_BUFF_CYCLE_CNT_VER2, \ 250 .mask = 0xffffffff, \ 251 }, \ 252 } 253 254 #define IWL_DEVICE_AX210 \ 255 IWL_DEVICE_22000_COMMON, \ 256 .trans.umac_prph_offset = 0x300000, \ 257 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \ 258 .trans.base_params = &iwl_ax210_base_params, \ 259 .min_txq_size = 128, \ 260 .gp2_reg_addr = 0xd02c68, \ 261 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, \ 262 .mon_dram_regs = { \ 263 .write_ptr = { \ 264 .addr = DBGC_CUR_DBGBUF_STATUS, \ 265 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 266 }, \ 267 .cycle_cnt = { \ 268 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 269 .mask = 0xffffffff, \ 270 }, \ 271 .cur_frag = { \ 272 .addr = DBGC_CUR_DBGBUF_STATUS, \ 273 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 274 }, \ 275 } 276 277 #define IWL_DEVICE_BZ_COMMON \ 278 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 279 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 280 .led_mode = IWL_LED_RF_STATE, \ 281 .nvm_hw_section_num = 10, \ 282 .non_shared_ant = ANT_B, \ 283 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 284 .dccm_len = IWL_22000_DCCM_LEN, \ 285 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 286 .dccm2_len = IWL_22000_DCCM2_LEN, \ 287 .smem_offset = IWL_22000_SMEM_OFFSET, \ 288 .smem_len = IWL_22000_SMEM_LEN, \ 289 .apmg_not_supported = true, \ 290 .trans.mq_rx_supported = true, \ 291 .vht_mu_mimo_supported = true, \ 292 .mac_addr_from_csr = 0x30, \ 293 .nvm_ver = IWL_22000_NVM_VERSION, \ 294 .trans.use_tfh = true, \ 295 .trans.rf_id = true, \ 296 .trans.gen2 = true, \ 297 .nvm_type = IWL_NVM_EXT, \ 298 .dbgc_supported = true, \ 299 .min_umac_error_event_table = 0xD0000, \ 300 .d3_debug_data_base_addr = 0x401000, \ 301 .d3_debug_data_length = 60 * 1024, \ 302 .mon_smem_regs = { \ 303 .write_ptr = { \ 304 .addr = LDBG_M2S_BUF_WPTR, \ 305 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 306 }, \ 307 .cycle_cnt = { \ 308 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 309 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 310 }, \ 311 }, \ 312 .trans.umac_prph_offset = 0x300000, \ 313 .trans.device_family = IWL_DEVICE_FAMILY_BZ, \ 314 .trans.base_params = &iwl_ax210_base_params, \ 315 .min_txq_size = 128, \ 316 .gp2_reg_addr = 0xd02c68, \ 317 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \ 318 .mon_dram_regs = { \ 319 .write_ptr = { \ 320 .addr = DBGC_CUR_DBGBUF_STATUS, \ 321 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 322 }, \ 323 .cycle_cnt = { \ 324 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 325 .mask = 0xffffffff, \ 326 }, \ 327 .cur_frag = { \ 328 .addr = DBGC_CUR_DBGBUF_STATUS, \ 329 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 330 }, \ 331 }, \ 332 .mon_dbgi_regs = { \ 333 .write_ptr = { \ 334 .addr = DBGI_SRAM_FIFO_POINTERS, \ 335 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \ 336 }, \ 337 } 338 339 #define IWL_DEVICE_BZ \ 340 IWL_DEVICE_BZ_COMMON, \ 341 .ht_params = &iwl_22000_ht_params 342 343 #define IWL_DEVICE_GL_A \ 344 IWL_DEVICE_BZ_COMMON, \ 345 .ht_params = &iwl_gl_a_ht_params 346 347 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = { 348 .mq_rx_supported = true, 349 .use_tfh = true, 350 .rf_id = true, 351 .gen2 = true, 352 .device_family = IWL_DEVICE_FAMILY_22000, 353 .base_params = &iwl_22000_base_params, 354 }; 355 356 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = { 357 .mq_rx_supported = true, 358 .use_tfh = true, 359 .rf_id = true, 360 .gen2 = true, 361 .device_family = IWL_DEVICE_FAMILY_22000, 362 .base_params = &iwl_22000_base_params, 363 .integrated = true, 364 .xtal_latency = 500, 365 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 366 }; 367 368 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = { 369 .mq_rx_supported = true, 370 .use_tfh = true, 371 .rf_id = true, 372 .gen2 = true, 373 .device_family = IWL_DEVICE_FAMILY_22000, 374 .base_params = &iwl_22000_base_params, 375 .integrated = true, 376 .xtal_latency = 1820, 377 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US, 378 }; 379 380 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = { 381 .mq_rx_supported = true, 382 .use_tfh = true, 383 .rf_id = true, 384 .gen2 = true, 385 .device_family = IWL_DEVICE_FAMILY_22000, 386 .base_params = &iwl_22000_base_params, 387 .integrated = true, 388 .xtal_latency = 12000, 389 .low_latency_xtal = true, 390 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 391 }; 392 393 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = { 394 .mq_rx_supported = true, 395 .use_tfh = true, 396 .rf_id = true, 397 .gen2 = true, 398 .device_family = IWL_DEVICE_FAMILY_AX210, 399 .base_params = &iwl_ax210_base_params, 400 .umac_prph_offset = 0x300000, 401 }; 402 403 const struct iwl_cfg_trans_params iwl_so_trans_cfg = { 404 .mq_rx_supported = true, 405 .use_tfh = true, 406 .rf_id = true, 407 .gen2 = true, 408 .device_family = IWL_DEVICE_FAMILY_AX210, 409 .base_params = &iwl_ax210_base_params, 410 .umac_prph_offset = 0x300000, 411 .integrated = true, 412 /* TODO: the following values need to be checked */ 413 .xtal_latency = 500, 414 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 415 }; 416 417 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = { 418 .mq_rx_supported = true, 419 .use_tfh = true, 420 .rf_id = true, 421 .gen2 = true, 422 .device_family = IWL_DEVICE_FAMILY_AX210, 423 .base_params = &iwl_ax210_base_params, 424 .umac_prph_offset = 0x300000, 425 .integrated = true, 426 .low_latency_xtal = true, 427 .xtal_latency = 12000, 428 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 429 }; 430 431 const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = { 432 .mq_rx_supported = true, 433 .use_tfh = true, 434 .rf_id = true, 435 .gen2 = true, 436 .device_family = IWL_DEVICE_FAMILY_AX210, 437 .base_params = &iwl_ax210_base_params, 438 .umac_prph_offset = 0x300000, 439 .integrated = true, 440 .low_latency_xtal = true, 441 .xtal_latency = 12000, 442 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 443 .imr_enabled = true, 444 }; 445 446 /* 447 * If the device doesn't support HE, no need to have that many buffers. 448 * 22000 devices can split multiple frames into a single RB, so fewer are 449 * needed; AX210 cannot (but use smaller RBs by default) - these sizes 450 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with 451 * additional overhead to account for processing time. 452 */ 453 #define IWL_NUM_RBDS_NON_HE 512 454 #define IWL_NUM_RBDS_22000_HE 2048 455 #define IWL_NUM_RBDS_AX210_HE 4096 456 457 /* 458 * All JF radio modules are part of the 9000 series, but the MAC part 459 * looks more like 22000. That's why this device is here, but called 460 * 9560 nevertheless. 461 */ 462 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = { 463 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE, 464 IWL_DEVICE_22500, 465 .num_rbds = IWL_NUM_RBDS_NON_HE, 466 }; 467 468 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = { 469 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE, 470 IWL_DEVICE_22500, 471 .num_rbds = IWL_NUM_RBDS_NON_HE, 472 }; 473 474 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = { 475 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE, 476 IWL_DEVICE_22500, 477 /* 478 * This device doesn't support receiving BlockAck with a large bitmap 479 * so we need to restrict the size of transmitted aggregation to the 480 * HT size; mac80211 would otherwise pick the HE max (256) by default. 481 */ 482 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 483 .num_rbds = IWL_NUM_RBDS_NON_HE, 484 }; 485 486 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = { 487 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE, 488 IWL_DEVICE_22500, 489 /* 490 * This device doesn't support receiving BlockAck with a large bitmap 491 * so we need to restrict the size of transmitted aggregation to the 492 * HT size; mac80211 would otherwise pick the HE max (256) by default. 493 */ 494 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 495 .num_rbds = IWL_NUM_RBDS_NON_HE, 496 }; 497 498 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = { 499 .device_family = IWL_DEVICE_FAMILY_22000, 500 .base_params = &iwl_22000_base_params, 501 .mq_rx_supported = true, 502 .use_tfh = true, 503 .rf_id = true, 504 .gen2 = true, 505 .bisr_workaround = 1, 506 }; 507 508 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = { 509 .device_family = IWL_DEVICE_FAMILY_AX210, 510 .base_params = &iwl_ax210_base_params, 511 .mq_rx_supported = true, 512 .use_tfh = true, 513 .rf_id = true, 514 .gen2 = true, 515 .integrated = true, 516 .umac_prph_offset = 0x300000 517 }; 518 519 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = { 520 .device_family = IWL_DEVICE_FAMILY_BZ, 521 .base_params = &iwl_ax210_base_params, 522 .mq_rx_supported = true, 523 .use_tfh = true, 524 .rf_id = true, 525 .gen2 = true, 526 .integrated = true, 527 .umac_prph_offset = 0x300000, 528 .xtal_latency = 12000, 529 .low_latency_xtal = true, 530 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 531 }; 532 533 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101"; 534 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz"; 535 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz"; 536 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203"; 537 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz"; 538 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz"; 539 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz"; 540 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz"; 541 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz"; 542 const char iwl_bz_name[] = "Intel(R) TBD Bz device"; 543 544 const char iwl_ax200_killer_1650w_name[] = 545 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)"; 546 const char iwl_ax200_killer_1650x_name[] = 547 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)"; 548 const char iwl_ax201_killer_1650s_name[] = 549 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)"; 550 const char iwl_ax201_killer_1650i_name[] = 551 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)"; 552 const char iwl_ax210_killer_1675w_name[] = 553 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)"; 554 const char iwl_ax210_killer_1675x_name[] = 555 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)"; 556 const char iwl_ax211_killer_1675s_name[] = 557 "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)"; 558 const char iwl_ax211_killer_1675i_name[] = 559 "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)"; 560 const char iwl_ax411_killer_1690s_name[] = 561 "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)"; 562 const char iwl_ax411_killer_1690i_name[] = 563 "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)"; 564 565 const struct iwl_cfg iwl_qu_b0_hr1_b0 = { 566 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 567 IWL_DEVICE_22500, 568 /* 569 * This device doesn't support receiving BlockAck with a large bitmap 570 * so we need to restrict the size of transmitted aggregation to the 571 * HT size; mac80211 would otherwise pick the HE max (256) by default. 572 */ 573 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 574 .tx_with_siso_diversity = true, 575 .num_rbds = IWL_NUM_RBDS_22000_HE, 576 }; 577 578 const struct iwl_cfg iwl_qu_b0_hr_b0 = { 579 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 580 IWL_DEVICE_22500, 581 /* 582 * This device doesn't support receiving BlockAck with a large bitmap 583 * so we need to restrict the size of transmitted aggregation to the 584 * HT size; mac80211 would otherwise pick the HE max (256) by default. 585 */ 586 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 587 .num_rbds = IWL_NUM_RBDS_22000_HE, 588 }; 589 590 const struct iwl_cfg iwl_ax201_cfg_qu_hr = { 591 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 592 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 593 IWL_DEVICE_22500, 594 /* 595 * This device doesn't support receiving BlockAck with a large bitmap 596 * so we need to restrict the size of transmitted aggregation to the 597 * HT size; mac80211 would otherwise pick the HE max (256) by default. 598 */ 599 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 600 .num_rbds = IWL_NUM_RBDS_22000_HE, 601 }; 602 603 const struct iwl_cfg iwl_qu_c0_hr1_b0 = { 604 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 605 IWL_DEVICE_22500, 606 /* 607 * This device doesn't support receiving BlockAck with a large bitmap 608 * so we need to restrict the size of transmitted aggregation to the 609 * HT size; mac80211 would otherwise pick the HE max (256) by default. 610 */ 611 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 612 .tx_with_siso_diversity = true, 613 .num_rbds = IWL_NUM_RBDS_22000_HE, 614 }; 615 616 const struct iwl_cfg iwl_qu_c0_hr_b0 = { 617 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 618 IWL_DEVICE_22500, 619 /* 620 * This device doesn't support receiving BlockAck with a large bitmap 621 * so we need to restrict the size of transmitted aggregation to the 622 * HT size; mac80211 would otherwise pick the HE max (256) by default. 623 */ 624 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 625 .num_rbds = IWL_NUM_RBDS_22000_HE, 626 }; 627 628 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = { 629 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 630 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 631 IWL_DEVICE_22500, 632 /* 633 * This device doesn't support receiving BlockAck with a large bitmap 634 * so we need to restrict the size of transmitted aggregation to the 635 * HT size; mac80211 would otherwise pick the HE max (256) by default. 636 */ 637 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 638 .num_rbds = IWL_NUM_RBDS_22000_HE, 639 }; 640 641 const struct iwl_cfg iwl_quz_a0_hr1_b0 = { 642 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 643 IWL_DEVICE_22500, 644 /* 645 * This device doesn't support receiving BlockAck with a large bitmap 646 * so we need to restrict the size of transmitted aggregation to the 647 * HT size; mac80211 would otherwise pick the HE max (256) by default. 648 */ 649 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 650 .tx_with_siso_diversity = true, 651 .num_rbds = IWL_NUM_RBDS_22000_HE, 652 }; 653 654 const struct iwl_cfg iwl_ax201_cfg_quz_hr = { 655 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 656 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 657 IWL_DEVICE_22500, 658 /* 659 * This device doesn't support receiving BlockAck with a large bitmap 660 * so we need to restrict the size of transmitted aggregation to the 661 * HT size; mac80211 would otherwise pick the HE max (256) by default. 662 */ 663 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 664 .num_rbds = IWL_NUM_RBDS_22000_HE, 665 }; 666 667 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = { 668 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 669 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 670 IWL_DEVICE_22500, 671 /* 672 * This device doesn't support receiving BlockAck with a large bitmap 673 * so we need to restrict the size of transmitted aggregation to the 674 * HT size; mac80211 would otherwise pick the HE max (256) by default. 675 */ 676 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 677 .num_rbds = IWL_NUM_RBDS_22000_HE, 678 }; 679 680 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = { 681 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 682 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 683 IWL_DEVICE_22500, 684 /* 685 * This device doesn't support receiving BlockAck with a large bitmap 686 * so we need to restrict the size of transmitted aggregation to the 687 * HT size; mac80211 would otherwise pick the HE max (256) by default. 688 */ 689 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 690 .num_rbds = IWL_NUM_RBDS_22000_HE, 691 }; 692 693 const struct iwl_cfg iwl_ax200_cfg_cc = { 694 .fw_name_pre = IWL_CC_A_FW_PRE, 695 IWL_DEVICE_22500, 696 /* 697 * This device doesn't support receiving BlockAck with a large bitmap 698 * so we need to restrict the size of transmitted aggregation to the 699 * HT size; mac80211 would otherwise pick the HE max (256) by default. 700 */ 701 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 702 .num_rbds = IWL_NUM_RBDS_22000_HE, 703 }; 704 705 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = { 706 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 707 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 708 IWL_DEVICE_22500, 709 /* 710 * This device doesn't support receiving BlockAck with a large bitmap 711 * so we need to restrict the size of transmitted aggregation to the 712 * HT size; mac80211 would otherwise pick the HE max (256) by default. 713 */ 714 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 715 .num_rbds = IWL_NUM_RBDS_22000_HE, 716 }; 717 718 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = { 719 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 720 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 721 IWL_DEVICE_22500, 722 /* 723 * This device doesn't support receiving BlockAck with a large bitmap 724 * so we need to restrict the size of transmitted aggregation to the 725 * HT size; mac80211 would otherwise pick the HE max (256) by default. 726 */ 727 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 728 .num_rbds = IWL_NUM_RBDS_22000_HE, 729 }; 730 731 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = { 732 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 733 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 734 IWL_DEVICE_22500, 735 /* 736 * This device doesn't support receiving BlockAck with a large bitmap 737 * so we need to restrict the size of transmitted aggregation to the 738 * HT size; mac80211 would otherwise pick the HE max (256) by default. 739 */ 740 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 741 .num_rbds = IWL_NUM_RBDS_22000_HE, 742 }; 743 744 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = { 745 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 746 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 747 IWL_DEVICE_22500, 748 /* 749 * This device doesn't support receiving BlockAck with a large bitmap 750 * so we need to restrict the size of transmitted aggregation to the 751 * HT size; mac80211 would otherwise pick the HE max (256) by default. 752 */ 753 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 754 .num_rbds = IWL_NUM_RBDS_22000_HE, 755 }; 756 757 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = { 758 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE, 759 IWL_DEVICE_22500, 760 /* 761 * This device doesn't support receiving BlockAck with a large bitmap 762 * so we need to restrict the size of transmitted aggregation to the 763 * HT size; mac80211 would otherwise pick the HE max (256) by default. 764 */ 765 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 766 .num_rbds = IWL_NUM_RBDS_22000_HE, 767 }; 768 769 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = { 770 .name = "Intel(R) Wireless-AC 9560 160MHz", 771 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE, 772 IWL_DEVICE_AX210, 773 .num_rbds = IWL_NUM_RBDS_NON_HE, 774 }; 775 776 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = { 777 .name = iwl_ax211_name, 778 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 779 .uhb_supported = true, 780 IWL_DEVICE_AX210, 781 .num_rbds = IWL_NUM_RBDS_AX210_HE, 782 }; 783 784 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = { 785 .name = iwl_ax211_name, 786 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 787 .uhb_supported = true, 788 IWL_DEVICE_AX210, 789 .num_rbds = IWL_NUM_RBDS_AX210_HE, 790 .trans.xtal_latency = 12000, 791 .trans.low_latency_xtal = true, 792 }; 793 794 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = { 795 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 796 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE, 797 .uhb_supported = true, 798 IWL_DEVICE_AX210, 799 .num_rbds = IWL_NUM_RBDS_AX210_HE, 800 }; 801 802 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = { 803 .name = iwl_ax411_name, 804 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 805 .uhb_supported = true, 806 IWL_DEVICE_AX210, 807 .num_rbds = IWL_NUM_RBDS_AX210_HE, 808 }; 809 810 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = { 811 .name = iwl_ax411_name, 812 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 813 .uhb_supported = true, 814 IWL_DEVICE_AX210, 815 .num_rbds = IWL_NUM_RBDS_AX210_HE, 816 .trans.xtal_latency = 12000, 817 .trans.low_latency_xtal = true, 818 }; 819 820 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = { 821 .name = iwl_ax411_name, 822 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE, 823 .uhb_supported = true, 824 IWL_DEVICE_AX210, 825 .num_rbds = IWL_NUM_RBDS_AX210_HE, 826 }; 827 828 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = { 829 .name = iwl_ax211_name, 830 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE, 831 .uhb_supported = true, 832 IWL_DEVICE_AX210, 833 .num_rbds = IWL_NUM_RBDS_AX210_HE, 834 }; 835 836 const struct iwl_cfg iwl_cfg_snj_hr_b0 = { 837 .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE, 838 .uhb_supported = true, 839 IWL_DEVICE_AX210, 840 .num_rbds = IWL_NUM_RBDS_AX210_HE, 841 }; 842 843 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = { 844 .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE, 845 .uhb_supported = true, 846 IWL_DEVICE_AX210, 847 .num_rbds = IWL_NUM_RBDS_AX210_HE, 848 }; 849 850 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = { 851 .fw_name_pre = IWL_MA_A_HR_B_FW_PRE, 852 .uhb_supported = true, 853 IWL_DEVICE_AX210, 854 .num_rbds = IWL_NUM_RBDS_AX210_HE, 855 }; 856 857 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = { 858 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE, 859 .uhb_supported = true, 860 IWL_DEVICE_AX210, 861 .num_rbds = IWL_NUM_RBDS_AX210_HE, 862 }; 863 864 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = { 865 .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE, 866 .uhb_supported = true, 867 IWL_DEVICE_AX210, 868 .num_rbds = IWL_NUM_RBDS_AX210_HE, 869 }; 870 871 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = { 872 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 873 .uhb_supported = true, 874 IWL_DEVICE_AX210, 875 .num_rbds = IWL_NUM_RBDS_AX210_HE, 876 }; 877 878 const struct iwl_cfg iwl_cfg_ma_a0_ms_a0 = { 879 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 880 .uhb_supported = false, 881 IWL_DEVICE_AX210, 882 .num_rbds = IWL_NUM_RBDS_AX210_HE, 883 }; 884 885 const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = { 886 .fw_name_pre = IWL_SO_A_MR_A_FW_PRE, 887 .uhb_supported = false, 888 IWL_DEVICE_AX210, 889 .num_rbds = IWL_NUM_RBDS_AX210_HE, 890 }; 891 892 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = { 893 .fw_name_pre = IWL_MA_A_FM_A_FW_PRE, 894 .uhb_supported = true, 895 IWL_DEVICE_AX210, 896 .num_rbds = IWL_NUM_RBDS_AX210_HE, 897 }; 898 899 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = { 900 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 901 .uhb_supported = true, 902 IWL_DEVICE_AX210, 903 .num_rbds = IWL_NUM_RBDS_AX210_HE, 904 }; 905 906 const struct iwl_cfg iwl_cfg_snj_a0_ms_a0 = { 907 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 908 .uhb_supported = false, 909 IWL_DEVICE_AX210, 910 .num_rbds = IWL_NUM_RBDS_AX210_HE, 911 }; 912 913 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = { 914 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 915 IWL_DEVICE_AX210, 916 .num_rbds = IWL_NUM_RBDS_AX210_HE, 917 }; 918 919 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = { 920 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 921 IWL_DEVICE_22500, 922 /* 923 * This device doesn't support receiving BlockAck with a large bitmap 924 * so we need to restrict the size of transmitted aggregation to the 925 * HT size; mac80211 would otherwise pick the HE max (256) by default. 926 */ 927 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 928 .num_rbds = IWL_NUM_RBDS_22000_HE, 929 }; 930 931 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = { 932 .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE, 933 .uhb_supported = true, 934 IWL_DEVICE_BZ, 935 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 936 .num_rbds = IWL_NUM_RBDS_AX210_HE, 937 }; 938 939 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = { 940 .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE, 941 .uhb_supported = true, 942 IWL_DEVICE_BZ, 943 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 944 .num_rbds = IWL_NUM_RBDS_AX210_HE, 945 }; 946 947 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = { 948 .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE, 949 .uhb_supported = true, 950 IWL_DEVICE_BZ, 951 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 952 .num_rbds = IWL_NUM_RBDS_AX210_HE, 953 }; 954 955 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = { 956 .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE, 957 .uhb_supported = true, 958 IWL_DEVICE_BZ, 959 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 960 .num_rbds = IWL_NUM_RBDS_AX210_HE, 961 }; 962 963 const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = { 964 .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE, 965 .uhb_supported = true, 966 IWL_DEVICE_BZ, 967 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 968 .num_rbds = IWL_NUM_RBDS_AX210_HE, 969 }; 970 971 const struct iwl_cfg iwl_cfg_bz_a0_fm4_a0 = { 972 .fw_name_pre = IWL_BZ_A_FM4_A_FW_PRE, 973 .uhb_supported = true, 974 IWL_DEVICE_BZ, 975 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 976 .num_rbds = IWL_NUM_RBDS_AX210_HE, 977 }; 978 979 const struct iwl_cfg iwl_cfg_bz_a0_fm_b0 = { 980 .fw_name_pre = IWL_BZ_A_FM_B_FW_PRE, 981 .uhb_supported = true, 982 IWL_DEVICE_BZ, 983 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 984 .num_rbds = IWL_NUM_RBDS_AX210_HE, 985 }; 986 987 const struct iwl_cfg iwl_cfg_bz_a0_fm4_b0 = { 988 .fw_name_pre = IWL_BZ_A_FM4_B_FW_PRE, 989 .uhb_supported = true, 990 IWL_DEVICE_BZ, 991 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 992 .num_rbds = IWL_NUM_RBDS_AX210_HE, 993 }; 994 995 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = { 996 .fw_name_pre = IWL_GL_A_FM_A_FW_PRE, 997 .uhb_supported = true, 998 IWL_DEVICE_GL_A, 999 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1000 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1001 }; 1002 1003 const struct iwl_cfg iwl_cfg_gl_b0_fm_b0 = { 1004 .fw_name_pre = IWL_GL_B_FM_B_FW_PRE, 1005 .uhb_supported = true, 1006 IWL_DEVICE_BZ, 1007 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 1008 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1009 }; 1010 1011 const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = { 1012 .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE, 1013 .uhb_supported = true, 1014 IWL_DEVICE_BZ, 1015 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 1016 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1017 }; 1018 1019 const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = { 1020 .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE, 1021 .uhb_supported = true, 1022 IWL_DEVICE_BZ, 1023 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1024 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1025 }; 1026 1027 const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = { 1028 .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE, 1029 .uhb_supported = true, 1030 IWL_DEVICE_BZ, 1031 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1032 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1033 }; 1034 1035 const struct iwl_cfg iwl_cfg_bnj_b0_fm4_b0 = { 1036 .fw_name_pre = IWL_BNJ_B_FM4_B_FW_PRE, 1037 .uhb_supported = true, 1038 IWL_DEVICE_BZ, 1039 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1040 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1041 }; 1042 1043 const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = { 1044 .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE, 1045 .uhb_supported = true, 1046 IWL_DEVICE_BZ, 1047 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1048 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1049 }; 1050 1051 const struct iwl_cfg iwl_cfg_bnj_b0_gf_a0 = { 1052 .fw_name_pre = IWL_BNJ_B_GF_A_FW_PRE, 1053 .uhb_supported = true, 1054 IWL_DEVICE_BZ, 1055 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1056 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1057 }; 1058 1059 const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = { 1060 .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE, 1061 .uhb_supported = true, 1062 IWL_DEVICE_BZ, 1063 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1064 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1065 }; 1066 1067 const struct iwl_cfg iwl_cfg_bnj_b0_gf4_a0 = { 1068 .fw_name_pre = IWL_BNJ_B_GF4_A_FW_PRE, 1069 .uhb_supported = true, 1070 IWL_DEVICE_BZ, 1071 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1072 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1073 }; 1074 1075 const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = { 1076 .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE, 1077 .uhb_supported = true, 1078 IWL_DEVICE_BZ, 1079 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1080 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1081 }; 1082 1083 const struct iwl_cfg iwl_cfg_bnj_b0_hr_b0 = { 1084 .fw_name_pre = IWL_BNJ_B_HR_B_FW_PRE, 1085 .uhb_supported = true, 1086 IWL_DEVICE_BZ, 1087 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1088 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1089 }; 1090 1091 const struct iwl_cfg iwl_cfg_bnj_b0_fm_b0 = { 1092 .fw_name_pre = IWL_BNJ_B_FM_B_FW_PRE, 1093 .uhb_supported = true, 1094 IWL_DEVICE_BZ, 1095 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 1096 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1097 }; 1098 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1099 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1100 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1101 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1102 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1103 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1104 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1105 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1106 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1107 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1108 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1109 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1110 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1111 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1112 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1113 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1114 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1115 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1116 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1117 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1118 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1119 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1120 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1121 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1122 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1123 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1124 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1125 MODULE_FIRMWARE(IWL_BZ_A_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1126 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1127 MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1128 MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1129 MODULE_FIRMWARE(IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1130 MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1131 MODULE_FIRMWARE(IWL_BNJ_B_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1132 MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1133 MODULE_FIRMWARE(IWL_BNJ_B_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1134 MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1135 MODULE_FIRMWARE(IWL_BNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1136 MODULE_FIRMWARE(IWL_BZ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1137 MODULE_FIRMWARE(IWL_BZ_A_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1138 MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1139 MODULE_FIRMWARE(IWL_BNJ_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1140