1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2020 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 11 /* Highest firmware API version supported */ 12 #define IWL_22000_UCODE_API_MAX 60 13 14 /* Lowest firmware API version supported */ 15 #define IWL_22000_UCODE_API_MIN 39 16 17 /* NVM versions */ 18 #define IWL_22000_NVM_VERSION 0x0a1d 19 20 /* Memory offsets and lengths */ 21 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */ 22 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */ 23 #define IWL_22000_DCCM2_OFFSET 0x880000 24 #define IWL_22000_DCCM2_LEN 0x8000 25 #define IWL_22000_SMEM_OFFSET 0x400000 26 #define IWL_22000_SMEM_LEN 0xD0000 27 28 #define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-" 29 #define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-" 30 #define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-" 31 #define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-" 32 #define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-" 33 #define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-" 34 #define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-" 35 #define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-" 36 #define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-" 37 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-" 38 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-" 39 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-" 40 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-" 41 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-" 42 #define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-" 43 #define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-" 44 #define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-" 45 #define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-" 46 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-" 47 #define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-" 48 #define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-" 49 50 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \ 51 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode" 52 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \ 53 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode" 54 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \ 55 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 56 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \ 57 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode" 58 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \ 59 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode" 60 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \ 61 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode" 62 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \ 63 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode" 64 #define IWL_CC_A_MODULE_FIRMWARE(api) \ 65 IWL_CC_A_FW_PRE __stringify(api) ".ucode" 66 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \ 67 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode" 68 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 69 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode" 70 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \ 71 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode" 72 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \ 73 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode" 74 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 75 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 76 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \ 77 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 78 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \ 79 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 80 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \ 81 IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode" 82 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \ 83 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode" 84 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \ 85 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode" 86 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \ 87 IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode" 88 89 static const struct iwl_base_params iwl_22000_base_params = { 90 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 91 .num_of_queues = 512, 92 .max_tfd_queue_size = 256, 93 .shadow_ram_support = true, 94 .led_compensation = 57, 95 .wd_timeout = IWL_LONG_WD_TIMEOUT, 96 .max_event_log_size = 512, 97 .shadow_reg_enable = true, 98 .pcie_l1_allowed = true, 99 }; 100 101 static const struct iwl_base_params iwl_ax210_base_params = { 102 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 103 .num_of_queues = 512, 104 .max_tfd_queue_size = 65536, 105 .shadow_ram_support = true, 106 .led_compensation = 57, 107 .wd_timeout = IWL_LONG_WD_TIMEOUT, 108 .max_event_log_size = 512, 109 .shadow_reg_enable = true, 110 .pcie_l1_allowed = true, 111 }; 112 113 static const struct iwl_ht_params iwl_22000_ht_params = { 114 .stbc = true, 115 .ldpc = true, 116 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 117 BIT(NL80211_BAND_6GHZ), 118 }; 119 120 #define IWL_DEVICE_22000_COMMON \ 121 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 122 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 123 .led_mode = IWL_LED_RF_STATE, \ 124 .nvm_hw_section_num = 10, \ 125 .non_shared_ant = ANT_B, \ 126 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 127 .dccm_len = IWL_22000_DCCM_LEN, \ 128 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 129 .dccm2_len = IWL_22000_DCCM2_LEN, \ 130 .smem_offset = IWL_22000_SMEM_OFFSET, \ 131 .smem_len = IWL_22000_SMEM_LEN, \ 132 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 133 .apmg_not_supported = true, \ 134 .trans.mq_rx_supported = true, \ 135 .vht_mu_mimo_supported = true, \ 136 .mac_addr_from_csr = true, \ 137 .ht_params = &iwl_22000_ht_params, \ 138 .nvm_ver = IWL_22000_NVM_VERSION, \ 139 .max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \ 140 .trans.use_tfh = true, \ 141 .trans.rf_id = true, \ 142 .trans.gen2 = true, \ 143 .nvm_type = IWL_NVM_EXT, \ 144 .dbgc_supported = true, \ 145 .min_umac_error_event_table = 0x400000, \ 146 .d3_debug_data_base_addr = 0x401000, \ 147 .d3_debug_data_length = 60 * 1024, \ 148 .mon_smem_regs = { \ 149 .write_ptr = { \ 150 .addr = LDBG_M2S_BUF_WPTR, \ 151 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 152 }, \ 153 .cycle_cnt = { \ 154 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 155 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 156 }, \ 157 } 158 159 #define IWL_DEVICE_22500 \ 160 IWL_DEVICE_22000_COMMON, \ 161 .trans.device_family = IWL_DEVICE_FAMILY_22000, \ 162 .trans.base_params = &iwl_22000_base_params, \ 163 .gp2_reg_addr = 0xa02c68, \ 164 .mon_dram_regs = { \ 165 .write_ptr = { \ 166 .addr = MON_BUFF_WRPTR_VER2, \ 167 .mask = 0xffffffff, \ 168 }, \ 169 .cycle_cnt = { \ 170 .addr = MON_BUFF_CYCLE_CNT_VER2, \ 171 .mask = 0xffffffff, \ 172 }, \ 173 } 174 175 #define IWL_DEVICE_AX210 \ 176 IWL_DEVICE_22000_COMMON, \ 177 .trans.umac_prph_offset = 0x300000, \ 178 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \ 179 .trans.base_params = &iwl_ax210_base_params, \ 180 .min_txq_size = 128, \ 181 .gp2_reg_addr = 0xd02c68, \ 182 .min_256_ba_txq_size = 1024, \ 183 .mon_dram_regs = { \ 184 .write_ptr = { \ 185 .addr = DBGC_CUR_DBGBUF_STATUS, \ 186 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 187 }, \ 188 .cycle_cnt = { \ 189 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 190 .mask = 0xffffffff, \ 191 }, \ 192 .cur_frag = { \ 193 .addr = DBGC_CUR_DBGBUF_STATUS, \ 194 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 195 }, \ 196 } 197 198 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = { 199 .mq_rx_supported = true, 200 .use_tfh = true, 201 .rf_id = true, 202 .gen2 = true, 203 .device_family = IWL_DEVICE_FAMILY_22000, 204 .base_params = &iwl_22000_base_params, 205 }; 206 207 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = { 208 .mq_rx_supported = true, 209 .use_tfh = true, 210 .rf_id = true, 211 .gen2 = true, 212 .device_family = IWL_DEVICE_FAMILY_22000, 213 .base_params = &iwl_22000_base_params, 214 .integrated = true, 215 .xtal_latency = 500, 216 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 217 }; 218 219 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = { 220 .mq_rx_supported = true, 221 .use_tfh = true, 222 .rf_id = true, 223 .gen2 = true, 224 .device_family = IWL_DEVICE_FAMILY_22000, 225 .base_params = &iwl_22000_base_params, 226 .integrated = true, 227 .xtal_latency = 1820, 228 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US, 229 }; 230 231 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = { 232 .mq_rx_supported = true, 233 .use_tfh = true, 234 .rf_id = true, 235 .gen2 = true, 236 .device_family = IWL_DEVICE_FAMILY_22000, 237 .base_params = &iwl_22000_base_params, 238 .integrated = true, 239 .xtal_latency = 12000, 240 .low_latency_xtal = true, 241 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 242 }; 243 244 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = { 245 .mq_rx_supported = true, 246 .use_tfh = true, 247 .rf_id = true, 248 .gen2 = true, 249 .device_family = IWL_DEVICE_FAMILY_AX210, 250 .base_params = &iwl_ax210_base_params, 251 .umac_prph_offset = 0x300000, 252 }; 253 254 const struct iwl_cfg_trans_params iwl_so_trans_cfg = { 255 .mq_rx_supported = true, 256 .use_tfh = true, 257 .rf_id = true, 258 .gen2 = true, 259 .device_family = IWL_DEVICE_FAMILY_AX210, 260 .base_params = &iwl_ax210_base_params, 261 .umac_prph_offset = 0x300000, 262 .integrated = true, 263 /* TODO: the following values need to be checked */ 264 .xtal_latency = 500, 265 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 266 }; 267 268 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = { 269 .mq_rx_supported = true, 270 .use_tfh = true, 271 .rf_id = true, 272 .gen2 = true, 273 .device_family = IWL_DEVICE_FAMILY_AX210, 274 .base_params = &iwl_ax210_base_params, 275 .umac_prph_offset = 0x300000, 276 .integrated = true, 277 /* TODO: the following values need to be checked */ 278 .xtal_latency = 12000, 279 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 280 }; 281 282 /* 283 * If the device doesn't support HE, no need to have that many buffers. 284 * 22000 devices can split multiple frames into a single RB, so fewer are 285 * needed; AX210 cannot (but use smaller RBs by default) - these sizes 286 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with 287 * additional overhead to account for processing time. 288 */ 289 #define IWL_NUM_RBDS_NON_HE 512 290 #define IWL_NUM_RBDS_22000_HE 2048 291 #define IWL_NUM_RBDS_AX210_HE 4096 292 293 /* 294 * All JF radio modules are part of the 9000 series, but the MAC part 295 * looks more like 22000. That's why this device is here, but called 296 * 9560 nevertheless. 297 */ 298 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = { 299 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE, 300 IWL_DEVICE_22500, 301 .num_rbds = IWL_NUM_RBDS_NON_HE, 302 }; 303 304 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = { 305 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE, 306 IWL_DEVICE_22500, 307 .num_rbds = IWL_NUM_RBDS_NON_HE, 308 }; 309 310 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = { 311 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE, 312 IWL_DEVICE_22500, 313 /* 314 * This device doesn't support receiving BlockAck with a large bitmap 315 * so we need to restrict the size of transmitted aggregation to the 316 * HT size; mac80211 would otherwise pick the HE max (256) by default. 317 */ 318 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 319 .num_rbds = IWL_NUM_RBDS_NON_HE, 320 }; 321 322 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = { 323 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE, 324 IWL_DEVICE_22500, 325 /* 326 * This device doesn't support receiving BlockAck with a large bitmap 327 * so we need to restrict the size of transmitted aggregation to the 328 * HT size; mac80211 would otherwise pick the HE max (256) by default. 329 */ 330 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 331 .num_rbds = IWL_NUM_RBDS_NON_HE, 332 }; 333 334 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = { 335 .device_family = IWL_DEVICE_FAMILY_22000, 336 .base_params = &iwl_22000_base_params, 337 .mq_rx_supported = true, 338 .use_tfh = true, 339 .rf_id = true, 340 .gen2 = true, 341 .bisr_workaround = 1, 342 }; 343 344 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = { 345 .device_family = IWL_DEVICE_FAMILY_AX210, 346 .base_params = &iwl_ax210_base_params, 347 .mq_rx_supported = true, 348 .use_tfh = true, 349 .rf_id = true, 350 .gen2 = true, 351 .integrated = true, 352 .umac_prph_offset = 0x300000 353 }; 354 355 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101"; 356 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz"; 357 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz"; 358 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6 AX211 160MHz"; 359 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6 AX411 160MHz"; 360 const char iwl_ma_name[] = "Intel(R) Wi-Fi 6"; 361 362 const char iwl_ax200_killer_1650w_name[] = 363 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)"; 364 const char iwl_ax200_killer_1650x_name[] = 365 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)"; 366 const char iwl_ax201_killer_1650s_name[] = 367 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)"; 368 const char iwl_ax201_killer_1650i_name[] = 369 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)"; 370 371 const struct iwl_cfg iwl_qu_b0_hr1_b0 = { 372 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 373 IWL_DEVICE_22500, 374 /* 375 * This device doesn't support receiving BlockAck with a large bitmap 376 * so we need to restrict the size of transmitted aggregation to the 377 * HT size; mac80211 would otherwise pick the HE max (256) by default. 378 */ 379 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 380 .tx_with_siso_diversity = true, 381 .num_rbds = IWL_NUM_RBDS_22000_HE, 382 }; 383 384 const struct iwl_cfg iwl_ax201_cfg_qu_hr = { 385 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 386 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 387 IWL_DEVICE_22500, 388 /* 389 * This device doesn't support receiving BlockAck with a large bitmap 390 * so we need to restrict the size of transmitted aggregation to the 391 * HT size; mac80211 would otherwise pick the HE max (256) by default. 392 */ 393 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 394 .num_rbds = IWL_NUM_RBDS_22000_HE, 395 }; 396 397 const struct iwl_cfg iwl_qu_c0_hr1_b0 = { 398 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 399 IWL_DEVICE_22500, 400 /* 401 * This device doesn't support receiving BlockAck with a large bitmap 402 * so we need to restrict the size of transmitted aggregation to the 403 * HT size; mac80211 would otherwise pick the HE max (256) by default. 404 */ 405 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 406 .tx_with_siso_diversity = true, 407 .num_rbds = IWL_NUM_RBDS_22000_HE, 408 }; 409 410 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = { 411 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 412 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 413 IWL_DEVICE_22500, 414 /* 415 * This device doesn't support receiving BlockAck with a large bitmap 416 * so we need to restrict the size of transmitted aggregation to the 417 * HT size; mac80211 would otherwise pick the HE max (256) by default. 418 */ 419 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 420 .num_rbds = IWL_NUM_RBDS_22000_HE, 421 }; 422 423 const struct iwl_cfg iwl_quz_a0_hr1_b0 = { 424 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 425 IWL_DEVICE_22500, 426 /* 427 * This device doesn't support receiving BlockAck with a large bitmap 428 * so we need to restrict the size of transmitted aggregation to the 429 * HT size; mac80211 would otherwise pick the HE max (256) by default. 430 */ 431 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 432 .tx_with_siso_diversity = true, 433 .num_rbds = IWL_NUM_RBDS_22000_HE, 434 }; 435 436 const struct iwl_cfg iwl_ax201_cfg_quz_hr = { 437 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 438 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 439 IWL_DEVICE_22500, 440 /* 441 * This device doesn't support receiving BlockAck with a large bitmap 442 * so we need to restrict the size of transmitted aggregation to the 443 * HT size; mac80211 would otherwise pick the HE max (256) by default. 444 */ 445 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 446 .num_rbds = IWL_NUM_RBDS_22000_HE, 447 }; 448 449 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = { 450 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 451 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 452 IWL_DEVICE_22500, 453 /* 454 * This device doesn't support receiving BlockAck with a large bitmap 455 * so we need to restrict the size of transmitted aggregation to the 456 * HT size; mac80211 would otherwise pick the HE max (256) by default. 457 */ 458 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 459 .num_rbds = IWL_NUM_RBDS_22000_HE, 460 }; 461 462 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = { 463 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 464 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 465 IWL_DEVICE_22500, 466 /* 467 * This device doesn't support receiving BlockAck with a large bitmap 468 * so we need to restrict the size of transmitted aggregation to the 469 * HT size; mac80211 would otherwise pick the HE max (256) by default. 470 */ 471 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 472 .num_rbds = IWL_NUM_RBDS_22000_HE, 473 }; 474 475 const struct iwl_cfg iwl_ax200_cfg_cc = { 476 .fw_name_pre = IWL_CC_A_FW_PRE, 477 IWL_DEVICE_22500, 478 /* 479 * This device doesn't support receiving BlockAck with a large bitmap 480 * so we need to restrict the size of transmitted aggregation to the 481 * HT size; mac80211 would otherwise pick the HE max (256) by default. 482 */ 483 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 484 .num_rbds = IWL_NUM_RBDS_22000_HE, 485 }; 486 487 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = { 488 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 489 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 490 IWL_DEVICE_22500, 491 /* 492 * This device doesn't support receiving BlockAck with a large bitmap 493 * so we need to restrict the size of transmitted aggregation to the 494 * HT size; mac80211 would otherwise pick the HE max (256) by default. 495 */ 496 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 497 .num_rbds = IWL_NUM_RBDS_22000_HE, 498 }; 499 500 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = { 501 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 502 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 503 IWL_DEVICE_22500, 504 /* 505 * This device doesn't support receiving BlockAck with a large bitmap 506 * so we need to restrict the size of transmitted aggregation to the 507 * HT size; mac80211 would otherwise pick the HE max (256) by default. 508 */ 509 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 510 .num_rbds = IWL_NUM_RBDS_22000_HE, 511 }; 512 513 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = { 514 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 515 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 516 IWL_DEVICE_22500, 517 /* 518 * This device doesn't support receiving BlockAck with a large bitmap 519 * so we need to restrict the size of transmitted aggregation to the 520 * HT size; mac80211 would otherwise pick the HE max (256) by default. 521 */ 522 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 523 .num_rbds = IWL_NUM_RBDS_22000_HE, 524 }; 525 526 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = { 527 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 528 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 529 IWL_DEVICE_22500, 530 /* 531 * This device doesn't support receiving BlockAck with a large bitmap 532 * so we need to restrict the size of transmitted aggregation to the 533 * HT size; mac80211 would otherwise pick the HE max (256) by default. 534 */ 535 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 536 .num_rbds = IWL_NUM_RBDS_22000_HE, 537 }; 538 539 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = { 540 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE, 541 IWL_DEVICE_22500, 542 /* 543 * This device doesn't support receiving BlockAck with a large bitmap 544 * so we need to restrict the size of transmitted aggregation to the 545 * HT size; mac80211 would otherwise pick the HE max (256) by default. 546 */ 547 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 548 .num_rbds = IWL_NUM_RBDS_22000_HE, 549 }; 550 551 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_a0 = { 552 .name = "Intel(R) Wireless-AC 9560 160MHz", 553 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE, 554 IWL_DEVICE_AX210, 555 .num_rbds = IWL_NUM_RBDS_NON_HE, 556 }; 557 558 const struct iwl_cfg iwlax210_2ax_cfg_so_hr_a0 = { 559 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 560 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 561 IWL_DEVICE_AX210, 562 .num_rbds = IWL_NUM_RBDS_AX210_HE, 563 }; 564 565 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = { 566 .name = iwl_ax211_name, 567 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 568 .uhb_supported = true, 569 IWL_DEVICE_AX210, 570 .num_rbds = IWL_NUM_RBDS_AX210_HE, 571 }; 572 573 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = { 574 .name = iwl_ax211_name, 575 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 576 .uhb_supported = true, 577 IWL_DEVICE_AX210, 578 .num_rbds = IWL_NUM_RBDS_AX210_HE, 579 .trans.xtal_latency = 12000, 580 .trans.low_latency_xtal = true, 581 }; 582 583 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = { 584 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 585 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE, 586 .uhb_supported = true, 587 IWL_DEVICE_AX210, 588 .num_rbds = IWL_NUM_RBDS_AX210_HE, 589 }; 590 591 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = { 592 .name = iwl_ax411_name, 593 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 594 .uhb_supported = true, 595 IWL_DEVICE_AX210, 596 .num_rbds = IWL_NUM_RBDS_AX210_HE, 597 }; 598 599 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = { 600 .name = iwl_ax411_name, 601 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 602 .uhb_supported = true, 603 IWL_DEVICE_AX210, 604 .num_rbds = IWL_NUM_RBDS_AX210_HE, 605 .trans.xtal_latency = 12000, 606 .trans.low_latency_xtal = true, 607 }; 608 609 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = { 610 .name = iwl_ax411_name, 611 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE, 612 .uhb_supported = true, 613 IWL_DEVICE_AX210, 614 .num_rbds = IWL_NUM_RBDS_AX210_HE, 615 }; 616 617 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = { 618 .name = iwl_ax211_name, 619 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE, 620 .uhb_supported = true, 621 IWL_DEVICE_AX210, 622 .num_rbds = IWL_NUM_RBDS_AX210_HE, 623 }; 624 625 const struct iwl_cfg iwl_cfg_snj_hr_b0 = { 626 .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE, 627 .uhb_supported = true, 628 IWL_DEVICE_AX210, 629 .num_rbds = IWL_NUM_RBDS_AX210_HE, 630 }; 631 632 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = { 633 .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE, 634 .uhb_supported = true, 635 IWL_DEVICE_AX210, 636 .num_rbds = IWL_NUM_RBDS_AX210_HE, 637 }; 638 639 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = { 640 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE, 641 .uhb_supported = true, 642 IWL_DEVICE_AX210, 643 .num_rbds = IWL_NUM_RBDS_AX210_HE, 644 }; 645 646 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = { 647 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 648 .uhb_supported = true, 649 IWL_DEVICE_AX210, 650 .num_rbds = IWL_NUM_RBDS_AX210_HE, 651 }; 652 653 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = { 654 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 655 .uhb_supported = true, 656 IWL_DEVICE_AX210, 657 .num_rbds = IWL_NUM_RBDS_AX210_HE, 658 }; 659 660 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 661 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 662 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 663 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 664 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 665 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 666 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 667 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 668 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 669 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 670 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 671 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 672 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 673 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 674 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 675 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 676 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 677 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 678 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 679