1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2020 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 11 /* Highest firmware API version supported */ 12 #define IWL_22000_UCODE_API_MAX 59 13 14 /* Lowest firmware API version supported */ 15 #define IWL_22000_UCODE_API_MIN 39 16 17 /* NVM versions */ 18 #define IWL_22000_NVM_VERSION 0x0a1d 19 20 /* Memory offsets and lengths */ 21 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */ 22 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */ 23 #define IWL_22000_DCCM2_OFFSET 0x880000 24 #define IWL_22000_DCCM2_LEN 0x8000 25 #define IWL_22000_SMEM_OFFSET 0x400000 26 #define IWL_22000_SMEM_LEN 0xD0000 27 28 #define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-" 29 #define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-" 30 #define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-" 31 #define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-" 32 #define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-" 33 #define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-" 34 #define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-" 35 #define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-" 36 #define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-" 37 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-" 38 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-" 39 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-" 40 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-" 41 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-" 42 #define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-" 43 #define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-" 44 #define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-" 45 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-" 46 #define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-" 47 48 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \ 49 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode" 50 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \ 51 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode" 52 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \ 53 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 54 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \ 55 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode" 56 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \ 57 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode" 58 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \ 59 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode" 60 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \ 61 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode" 62 #define IWL_CC_A_MODULE_FIRMWARE(api) \ 63 IWL_CC_A_FW_PRE __stringify(api) ".ucode" 64 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \ 65 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode" 66 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 67 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode" 68 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \ 69 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode" 70 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \ 71 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode" 72 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 73 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 74 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \ 75 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 76 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \ 77 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 78 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \ 79 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode" 80 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \ 81 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode" 82 83 static const struct iwl_base_params iwl_22000_base_params = { 84 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 85 .num_of_queues = 512, 86 .max_tfd_queue_size = 256, 87 .shadow_ram_support = true, 88 .led_compensation = 57, 89 .wd_timeout = IWL_LONG_WD_TIMEOUT, 90 .max_event_log_size = 512, 91 .shadow_reg_enable = true, 92 .pcie_l1_allowed = true, 93 }; 94 95 static const struct iwl_base_params iwl_ax210_base_params = { 96 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 97 .num_of_queues = 512, 98 .max_tfd_queue_size = 65536, 99 .shadow_ram_support = true, 100 .led_compensation = 57, 101 .wd_timeout = IWL_LONG_WD_TIMEOUT, 102 .max_event_log_size = 512, 103 .shadow_reg_enable = true, 104 .pcie_l1_allowed = true, 105 }; 106 107 static const struct iwl_ht_params iwl_22000_ht_params = { 108 .stbc = true, 109 .ldpc = true, 110 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 111 BIT(NL80211_BAND_6GHZ), 112 }; 113 114 #define IWL_DEVICE_22000_COMMON \ 115 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 116 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 117 .led_mode = IWL_LED_RF_STATE, \ 118 .nvm_hw_section_num = 10, \ 119 .non_shared_ant = ANT_B, \ 120 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 121 .dccm_len = IWL_22000_DCCM_LEN, \ 122 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 123 .dccm2_len = IWL_22000_DCCM2_LEN, \ 124 .smem_offset = IWL_22000_SMEM_OFFSET, \ 125 .smem_len = IWL_22000_SMEM_LEN, \ 126 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 127 .apmg_not_supported = true, \ 128 .trans.mq_rx_supported = true, \ 129 .vht_mu_mimo_supported = true, \ 130 .mac_addr_from_csr = true, \ 131 .ht_params = &iwl_22000_ht_params, \ 132 .nvm_ver = IWL_22000_NVM_VERSION, \ 133 .max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \ 134 .trans.use_tfh = true, \ 135 .trans.rf_id = true, \ 136 .trans.gen2 = true, \ 137 .nvm_type = IWL_NVM_EXT, \ 138 .dbgc_supported = true, \ 139 .min_umac_error_event_table = 0x400000, \ 140 .d3_debug_data_base_addr = 0x401000, \ 141 .d3_debug_data_length = 60 * 1024, \ 142 .mon_smem_regs = { \ 143 .write_ptr = { \ 144 .addr = LDBG_M2S_BUF_WPTR, \ 145 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 146 }, \ 147 .cycle_cnt = { \ 148 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 149 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 150 }, \ 151 } 152 153 #define IWL_DEVICE_22500 \ 154 IWL_DEVICE_22000_COMMON, \ 155 .trans.device_family = IWL_DEVICE_FAMILY_22000, \ 156 .trans.base_params = &iwl_22000_base_params, \ 157 .gp2_reg_addr = 0xa02c68, \ 158 .mon_dram_regs = { \ 159 .write_ptr = { \ 160 .addr = MON_BUFF_WRPTR_VER2, \ 161 .mask = 0xffffffff, \ 162 }, \ 163 .cycle_cnt = { \ 164 .addr = MON_BUFF_CYCLE_CNT_VER2, \ 165 .mask = 0xffffffff, \ 166 }, \ 167 } 168 169 #define IWL_DEVICE_AX210 \ 170 IWL_DEVICE_22000_COMMON, \ 171 .trans.umac_prph_offset = 0x300000, \ 172 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \ 173 .trans.base_params = &iwl_ax210_base_params, \ 174 .min_txq_size = 128, \ 175 .gp2_reg_addr = 0xd02c68, \ 176 .min_256_ba_txq_size = 1024, \ 177 .mon_dram_regs = { \ 178 .write_ptr = { \ 179 .addr = DBGC_CUR_DBGBUF_STATUS, \ 180 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 181 }, \ 182 .cycle_cnt = { \ 183 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 184 .mask = 0xffffffff, \ 185 }, \ 186 .cur_frag = { \ 187 .addr = DBGC_CUR_DBGBUF_STATUS, \ 188 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 189 }, \ 190 } 191 192 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = { 193 .mq_rx_supported = true, 194 .use_tfh = true, 195 .rf_id = true, 196 .gen2 = true, 197 .device_family = IWL_DEVICE_FAMILY_22000, 198 .base_params = &iwl_22000_base_params, 199 }; 200 201 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = { 202 .mq_rx_supported = true, 203 .use_tfh = true, 204 .rf_id = true, 205 .gen2 = true, 206 .device_family = IWL_DEVICE_FAMILY_22000, 207 .base_params = &iwl_22000_base_params, 208 .integrated = true, 209 .xtal_latency = 500, 210 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 211 }; 212 213 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = { 214 .mq_rx_supported = true, 215 .use_tfh = true, 216 .rf_id = true, 217 .gen2 = true, 218 .device_family = IWL_DEVICE_FAMILY_22000, 219 .base_params = &iwl_22000_base_params, 220 .integrated = true, 221 .xtal_latency = 1820, 222 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US, 223 }; 224 225 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = { 226 .mq_rx_supported = true, 227 .use_tfh = true, 228 .rf_id = true, 229 .gen2 = true, 230 .device_family = IWL_DEVICE_FAMILY_22000, 231 .base_params = &iwl_22000_base_params, 232 .integrated = true, 233 .xtal_latency = 12000, 234 .low_latency_xtal = true, 235 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 236 }; 237 238 /* 239 * If the device doesn't support HE, no need to have that many buffers. 240 * 22000 devices can split multiple frames into a single RB, so fewer are 241 * needed; AX210 cannot (but use smaller RBs by default) - these sizes 242 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with 243 * additional overhead to account for processing time. 244 */ 245 #define IWL_NUM_RBDS_NON_HE 512 246 #define IWL_NUM_RBDS_22000_HE 2048 247 #define IWL_NUM_RBDS_AX210_HE 4096 248 249 /* 250 * All JF radio modules are part of the 9000 series, but the MAC part 251 * looks more like 22000. That's why this device is here, but called 252 * 9560 nevertheless. 253 */ 254 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = { 255 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE, 256 IWL_DEVICE_22500, 257 .num_rbds = IWL_NUM_RBDS_NON_HE, 258 }; 259 260 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = { 261 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE, 262 IWL_DEVICE_22500, 263 .num_rbds = IWL_NUM_RBDS_NON_HE, 264 }; 265 266 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = { 267 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE, 268 IWL_DEVICE_22500, 269 /* 270 * This device doesn't support receiving BlockAck with a large bitmap 271 * so we need to restrict the size of transmitted aggregation to the 272 * HT size; mac80211 would otherwise pick the HE max (256) by default. 273 */ 274 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 275 .num_rbds = IWL_NUM_RBDS_NON_HE, 276 }; 277 278 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = { 279 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE, 280 IWL_DEVICE_22500, 281 /* 282 * This device doesn't support receiving BlockAck with a large bitmap 283 * so we need to restrict the size of transmitted aggregation to the 284 * HT size; mac80211 would otherwise pick the HE max (256) by default. 285 */ 286 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 287 .num_rbds = IWL_NUM_RBDS_NON_HE, 288 }; 289 290 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = { 291 .device_family = IWL_DEVICE_FAMILY_22000, 292 .base_params = &iwl_22000_base_params, 293 .mq_rx_supported = true, 294 .use_tfh = true, 295 .rf_id = true, 296 .gen2 = true, 297 .bisr_workaround = 1, 298 }; 299 300 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = { 301 .device_family = IWL_DEVICE_FAMILY_AX210, 302 .base_params = &iwl_ax210_base_params, 303 .mq_rx_supported = true, 304 .use_tfh = true, 305 .rf_id = true, 306 .gen2 = true, 307 .integrated = true, 308 .umac_prph_offset = 0x300000 309 }; 310 311 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101"; 312 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz"; 313 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz"; 314 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6 AX211 160MHz"; 315 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6 AX411 160MHz"; 316 const char iwl_ma_name[] = "Intel(R) Wi-Fi 6"; 317 318 const char iwl_ax200_killer_1650w_name[] = 319 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)"; 320 const char iwl_ax200_killer_1650x_name[] = 321 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)"; 322 const char iwl_ax201_killer_1650s_name[] = 323 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)"; 324 const char iwl_ax201_killer_1650i_name[] = 325 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)"; 326 327 const struct iwl_cfg iwl_qu_b0_hr1_b0 = { 328 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 329 IWL_DEVICE_22500, 330 /* 331 * This device doesn't support receiving BlockAck with a large bitmap 332 * so we need to restrict the size of transmitted aggregation to the 333 * HT size; mac80211 would otherwise pick the HE max (256) by default. 334 */ 335 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 336 .tx_with_siso_diversity = true, 337 .num_rbds = IWL_NUM_RBDS_22000_HE, 338 }; 339 340 const struct iwl_cfg iwl_ax201_cfg_qu_hr = { 341 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 342 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 343 IWL_DEVICE_22500, 344 /* 345 * This device doesn't support receiving BlockAck with a large bitmap 346 * so we need to restrict the size of transmitted aggregation to the 347 * HT size; mac80211 would otherwise pick the HE max (256) by default. 348 */ 349 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 350 .num_rbds = IWL_NUM_RBDS_22000_HE, 351 }; 352 353 const struct iwl_cfg iwl_qu_c0_hr1_b0 = { 354 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 355 IWL_DEVICE_22500, 356 /* 357 * This device doesn't support receiving BlockAck with a large bitmap 358 * so we need to restrict the size of transmitted aggregation to the 359 * HT size; mac80211 would otherwise pick the HE max (256) by default. 360 */ 361 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 362 .tx_with_siso_diversity = true, 363 .num_rbds = IWL_NUM_RBDS_22000_HE, 364 }; 365 366 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = { 367 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 368 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 369 IWL_DEVICE_22500, 370 /* 371 * This device doesn't support receiving BlockAck with a large bitmap 372 * so we need to restrict the size of transmitted aggregation to the 373 * HT size; mac80211 would otherwise pick the HE max (256) by default. 374 */ 375 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 376 .num_rbds = IWL_NUM_RBDS_22000_HE, 377 }; 378 379 const struct iwl_cfg iwl_quz_a0_hr1_b0 = { 380 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 381 IWL_DEVICE_22500, 382 /* 383 * This device doesn't support receiving BlockAck with a large bitmap 384 * so we need to restrict the size of transmitted aggregation to the 385 * HT size; mac80211 would otherwise pick the HE max (256) by default. 386 */ 387 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 388 .tx_with_siso_diversity = true, 389 .num_rbds = IWL_NUM_RBDS_22000_HE, 390 }; 391 392 const struct iwl_cfg iwl_ax201_cfg_quz_hr = { 393 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 394 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 395 IWL_DEVICE_22500, 396 /* 397 * This device doesn't support receiving BlockAck with a large bitmap 398 * so we need to restrict the size of transmitted aggregation to the 399 * HT size; mac80211 would otherwise pick the HE max (256) by default. 400 */ 401 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 402 .num_rbds = IWL_NUM_RBDS_22000_HE, 403 }; 404 405 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = { 406 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 407 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 408 IWL_DEVICE_22500, 409 /* 410 * This device doesn't support receiving BlockAck with a large bitmap 411 * so we need to restrict the size of transmitted aggregation to the 412 * HT size; mac80211 would otherwise pick the HE max (256) by default. 413 */ 414 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 415 .num_rbds = IWL_NUM_RBDS_22000_HE, 416 }; 417 418 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = { 419 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 420 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 421 IWL_DEVICE_22500, 422 /* 423 * This device doesn't support receiving BlockAck with a large bitmap 424 * so we need to restrict the size of transmitted aggregation to the 425 * HT size; mac80211 would otherwise pick the HE max (256) by default. 426 */ 427 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 428 .num_rbds = IWL_NUM_RBDS_22000_HE, 429 }; 430 431 const struct iwl_cfg iwl_ax200_cfg_cc = { 432 .fw_name_pre = IWL_CC_A_FW_PRE, 433 IWL_DEVICE_22500, 434 /* 435 * This device doesn't support receiving BlockAck with a large bitmap 436 * so we need to restrict the size of transmitted aggregation to the 437 * HT size; mac80211 would otherwise pick the HE max (256) by default. 438 */ 439 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 440 .num_rbds = IWL_NUM_RBDS_22000_HE, 441 }; 442 443 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = { 444 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 445 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 446 IWL_DEVICE_22500, 447 /* 448 * This device doesn't support receiving BlockAck with a large bitmap 449 * so we need to restrict the size of transmitted aggregation to the 450 * HT size; mac80211 would otherwise pick the HE max (256) by default. 451 */ 452 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 453 .num_rbds = IWL_NUM_RBDS_22000_HE, 454 }; 455 456 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = { 457 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 458 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 459 IWL_DEVICE_22500, 460 /* 461 * This device doesn't support receiving BlockAck with a large bitmap 462 * so we need to restrict the size of transmitted aggregation to the 463 * HT size; mac80211 would otherwise pick the HE max (256) by default. 464 */ 465 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 466 .num_rbds = IWL_NUM_RBDS_22000_HE, 467 }; 468 469 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = { 470 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 471 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 472 IWL_DEVICE_22500, 473 /* 474 * This device doesn't support receiving BlockAck with a large bitmap 475 * so we need to restrict the size of transmitted aggregation to the 476 * HT size; mac80211 would otherwise pick the HE max (256) by default. 477 */ 478 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 479 .num_rbds = IWL_NUM_RBDS_22000_HE, 480 }; 481 482 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = { 483 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 484 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 485 IWL_DEVICE_22500, 486 /* 487 * This device doesn't support receiving BlockAck with a large bitmap 488 * so we need to restrict the size of transmitted aggregation to the 489 * HT size; mac80211 would otherwise pick the HE max (256) by default. 490 */ 491 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 492 .num_rbds = IWL_NUM_RBDS_22000_HE, 493 }; 494 495 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = { 496 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE, 497 IWL_DEVICE_22500, 498 /* 499 * This device doesn't support receiving BlockAck with a large bitmap 500 * so we need to restrict the size of transmitted aggregation to the 501 * HT size; mac80211 would otherwise pick the HE max (256) by default. 502 */ 503 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 504 .num_rbds = IWL_NUM_RBDS_22000_HE, 505 }; 506 507 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_a0 = { 508 .name = "Intel(R) Wireless-AC 9560 160MHz", 509 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE, 510 IWL_DEVICE_AX210, 511 .num_rbds = IWL_NUM_RBDS_NON_HE, 512 }; 513 514 const struct iwl_cfg iwlax210_2ax_cfg_so_hr_a0 = { 515 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 516 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 517 IWL_DEVICE_AX210, 518 .num_rbds = IWL_NUM_RBDS_AX210_HE, 519 }; 520 521 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = { 522 .name = iwl_ax211_name, 523 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 524 .uhb_supported = true, 525 IWL_DEVICE_AX210, 526 .num_rbds = IWL_NUM_RBDS_AX210_HE, 527 }; 528 529 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = { 530 .name = iwl_ax211_name, 531 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 532 .uhb_supported = true, 533 IWL_DEVICE_AX210, 534 .num_rbds = IWL_NUM_RBDS_AX210_HE, 535 .trans.xtal_latency = 12000, 536 .trans.low_latency_xtal = true, 537 }; 538 539 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = { 540 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 541 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE, 542 .uhb_supported = true, 543 IWL_DEVICE_AX210, 544 .num_rbds = IWL_NUM_RBDS_AX210_HE, 545 }; 546 547 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = { 548 .name = iwl_ax411_name, 549 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 550 .uhb_supported = true, 551 IWL_DEVICE_AX210, 552 .num_rbds = IWL_NUM_RBDS_AX210_HE, 553 }; 554 555 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = { 556 .name = iwl_ax411_name, 557 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 558 .uhb_supported = true, 559 IWL_DEVICE_AX210, 560 .num_rbds = IWL_NUM_RBDS_AX210_HE, 561 .trans.xtal_latency = 12000, 562 .trans.low_latency_xtal = true, 563 }; 564 565 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = { 566 .name = iwl_ax411_name, 567 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE, 568 .uhb_supported = true, 569 IWL_DEVICE_AX210, 570 .num_rbds = IWL_NUM_RBDS_AX210_HE, 571 }; 572 573 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = { 574 .name = iwl_ax211_name, 575 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE, 576 .uhb_supported = true, 577 IWL_DEVICE_AX210, 578 .num_rbds = IWL_NUM_RBDS_AX210_HE, 579 }; 580 581 const struct iwl_cfg iwlax201_cfg_snj_hr_b0 = { 582 .name = iwl_ax201_name, 583 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 584 .uhb_supported = true, 585 IWL_DEVICE_AX210, 586 .num_rbds = IWL_NUM_RBDS_AX210_HE, 587 }; 588 589 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = { 590 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE, 591 .uhb_supported = true, 592 IWL_DEVICE_AX210, 593 .num_rbds = IWL_NUM_RBDS_AX210_HE, 594 }; 595 596 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = { 597 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 598 .uhb_supported = true, 599 IWL_DEVICE_AX210, 600 .num_rbds = IWL_NUM_RBDS_AX210_HE, 601 }; 602 603 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 604 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 605 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 606 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 607 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 608 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 609 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 610 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 611 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 612 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 613 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 614 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 615 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 616 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 617 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 618 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 619 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 620