1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2022 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_22000_UCODE_API_MAX 74 14 15 /* Lowest firmware API version supported */ 16 #define IWL_22000_UCODE_API_MIN 39 17 18 /* NVM versions */ 19 #define IWL_22000_NVM_VERSION 0x0a1d 20 21 /* Memory offsets and lengths */ 22 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_22000_DCCM2_OFFSET 0x880000 25 #define IWL_22000_DCCM2_LEN 0x8000 26 #define IWL_22000_SMEM_OFFSET 0x400000 27 #define IWL_22000_SMEM_LEN 0xD0000 28 29 #define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-" 30 #define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-" 31 #define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-" 32 #define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-" 33 #define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-" 34 #define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-" 35 #define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-" 36 #define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-" 37 #define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-" 38 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-" 39 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-" 40 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-" 41 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-" 42 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-" 43 #define IWL_SO_A_MR_A_FW_PRE "iwlwifi-so-a0-mr-a0-" 44 #define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-" 45 #define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-" 46 #define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-" 47 #define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-" 48 #define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0-" 49 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-" 50 #define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0-" 51 #define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-" 52 #define IWL_MA_A_FM_A_FW_PRE "iwlwifi-ma-a0-fm-a0-" 53 #define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-" 54 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0-" 55 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0-" 56 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0-" 57 #define IWL_BZ_A_MR_A_FW_PRE "iwlwifi-bz-a0-mr-a0-" 58 #define IWL_BZ_A_FM_A_FW_PRE "iwlwifi-bz-a0-fm-a0-" 59 #define IWL_BZ_A_FM4_A_FW_PRE "iwlwifi-bz-a0-fm4-a0-" 60 #define IWL_GL_A_FM_A_FW_PRE "iwlwifi-gl-a0-fm-a0-" 61 #define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0-" 62 #define IWL_BZ_Z_GF_A_FW_PRE "iwlwifi-bz-z0-gf-a0-" 63 #define IWL_BNJ_A_FM_A_FW_PRE "iwlwifi-BzBnj-a0-fm-a0-" 64 #define IWL_BNJ_A_FM4_A_FW_PRE "iwlwifi-BzBnj-a0-fm4-a0-" 65 #define IWL_BNJ_B_FM4_B_FW_PRE "iwlwifi-BzBnj-b0-fm4-b0-" 66 #define IWL_BNJ_A_GF_A_FW_PRE "iwlwifi-BzBnj-a0-gf-a0-" 67 #define IWL_BNJ_A_GF4_A_FW_PRE "iwlwifi-BzBnj-a0-gf4-a0-" 68 #define IWL_BNJ_A_HR_B_FW_PRE "iwlwifi-BzBnj-a0-hr-b0-" 69 #define IWL_BNJ_B_FM_B_FW_PRE "iwlwifi-BzBnj-b0-fm-b0-" 70 71 72 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \ 73 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode" 74 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \ 75 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode" 76 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \ 77 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 78 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \ 79 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode" 80 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \ 81 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode" 82 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \ 83 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode" 84 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \ 85 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode" 86 #define IWL_CC_A_MODULE_FIRMWARE(api) \ 87 IWL_CC_A_FW_PRE __stringify(api) ".ucode" 88 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \ 89 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode" 90 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 91 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode" 92 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \ 93 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode" 94 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \ 95 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode" 96 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 97 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 98 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \ 99 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 100 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \ 101 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 102 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \ 103 IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode" 104 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \ 105 IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode" 106 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \ 107 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode" 108 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \ 109 IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode" 110 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \ 111 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode" 112 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api) \ 113 IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode" 114 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \ 115 IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode" 116 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 117 IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 118 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \ 119 IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode" 120 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \ 121 IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 122 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \ 123 IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode" 124 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \ 125 IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode" 126 #define IWL_BZ_A_FM4_A_MODULE_FIRMWARE(api) \ 127 IWL_BZ_A_FM4_A_FW_PRE __stringify(api) ".ucode" 128 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \ 129 IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode" 130 #define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \ 131 IWL_GL_B_FM_B_FW_PRE __stringify(api) ".ucode" 132 #define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \ 133 IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode" 134 #define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \ 135 IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode" 136 #define IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(api) \ 137 IWL_BNJ_B_FM4_B_FW_PRE __stringify(api) ".ucode" 138 #define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \ 139 IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 140 #define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 141 IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 142 #define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \ 143 IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 144 #define IWL_BNJ_B_FM_B_MODULE_FIRMWARE(api) \ 145 IWL_BNJ_B_FM_B_FW_PRE __stringify(api) ".ucode" 146 147 static const struct iwl_base_params iwl_22000_base_params = { 148 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 149 .num_of_queues = 512, 150 .max_tfd_queue_size = 256, 151 .shadow_ram_support = true, 152 .led_compensation = 57, 153 .wd_timeout = IWL_LONG_WD_TIMEOUT, 154 .max_event_log_size = 512, 155 .shadow_reg_enable = true, 156 .pcie_l1_allowed = true, 157 }; 158 159 static const struct iwl_base_params iwl_ax210_base_params = { 160 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 161 .num_of_queues = 512, 162 .max_tfd_queue_size = 65536, 163 .shadow_ram_support = true, 164 .led_compensation = 57, 165 .wd_timeout = IWL_LONG_WD_TIMEOUT, 166 .max_event_log_size = 512, 167 .shadow_reg_enable = true, 168 .pcie_l1_allowed = true, 169 }; 170 171 static const struct iwl_ht_params iwl_22000_ht_params = { 172 .stbc = true, 173 .ldpc = true, 174 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 175 BIT(NL80211_BAND_6GHZ), 176 }; 177 178 static const struct iwl_ht_params iwl_gl_a_ht_params = { 179 .stbc = false, /* we explicitly disable STBC for GL step A */ 180 .ldpc = true, 181 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 182 BIT(NL80211_BAND_6GHZ), 183 }; 184 185 #define IWL_DEVICE_22000_COMMON \ 186 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 187 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 188 .led_mode = IWL_LED_RF_STATE, \ 189 .nvm_hw_section_num = 10, \ 190 .non_shared_ant = ANT_B, \ 191 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 192 .dccm_len = IWL_22000_DCCM_LEN, \ 193 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 194 .dccm2_len = IWL_22000_DCCM2_LEN, \ 195 .smem_offset = IWL_22000_SMEM_OFFSET, \ 196 .smem_len = IWL_22000_SMEM_LEN, \ 197 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 198 .apmg_not_supported = true, \ 199 .trans.mq_rx_supported = true, \ 200 .vht_mu_mimo_supported = true, \ 201 .mac_addr_from_csr = 0x380, \ 202 .ht_params = &iwl_22000_ht_params, \ 203 .nvm_ver = IWL_22000_NVM_VERSION, \ 204 .trans.use_tfh = true, \ 205 .trans.rf_id = true, \ 206 .trans.gen2 = true, \ 207 .nvm_type = IWL_NVM_EXT, \ 208 .dbgc_supported = true, \ 209 .min_umac_error_event_table = 0x400000, \ 210 .d3_debug_data_base_addr = 0x401000, \ 211 .d3_debug_data_length = 60 * 1024, \ 212 .mon_smem_regs = { \ 213 .write_ptr = { \ 214 .addr = LDBG_M2S_BUF_WPTR, \ 215 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 216 }, \ 217 .cycle_cnt = { \ 218 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 219 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 220 }, \ 221 } 222 223 #define IWL_DEVICE_22500 \ 224 IWL_DEVICE_22000_COMMON, \ 225 .trans.device_family = IWL_DEVICE_FAMILY_22000, \ 226 .trans.base_params = &iwl_22000_base_params, \ 227 .gp2_reg_addr = 0xa02c68, \ 228 .mon_dram_regs = { \ 229 .write_ptr = { \ 230 .addr = MON_BUFF_WRPTR_VER2, \ 231 .mask = 0xffffffff, \ 232 }, \ 233 .cycle_cnt = { \ 234 .addr = MON_BUFF_CYCLE_CNT_VER2, \ 235 .mask = 0xffffffff, \ 236 }, \ 237 } 238 239 #define IWL_DEVICE_AX210 \ 240 IWL_DEVICE_22000_COMMON, \ 241 .trans.umac_prph_offset = 0x300000, \ 242 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \ 243 .trans.base_params = &iwl_ax210_base_params, \ 244 .min_txq_size = 128, \ 245 .gp2_reg_addr = 0xd02c68, \ 246 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, \ 247 .mon_dram_regs = { \ 248 .write_ptr = { \ 249 .addr = DBGC_CUR_DBGBUF_STATUS, \ 250 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 251 }, \ 252 .cycle_cnt = { \ 253 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 254 .mask = 0xffffffff, \ 255 }, \ 256 .cur_frag = { \ 257 .addr = DBGC_CUR_DBGBUF_STATUS, \ 258 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 259 }, \ 260 } 261 262 #define IWL_DEVICE_BZ_COMMON \ 263 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 264 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 265 .led_mode = IWL_LED_RF_STATE, \ 266 .nvm_hw_section_num = 10, \ 267 .non_shared_ant = ANT_B, \ 268 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 269 .dccm_len = IWL_22000_DCCM_LEN, \ 270 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 271 .dccm2_len = IWL_22000_DCCM2_LEN, \ 272 .smem_offset = IWL_22000_SMEM_OFFSET, \ 273 .smem_len = IWL_22000_SMEM_LEN, \ 274 .apmg_not_supported = true, \ 275 .trans.mq_rx_supported = true, \ 276 .vht_mu_mimo_supported = true, \ 277 .mac_addr_from_csr = 0x30, \ 278 .nvm_ver = IWL_22000_NVM_VERSION, \ 279 .trans.use_tfh = true, \ 280 .trans.rf_id = true, \ 281 .trans.gen2 = true, \ 282 .nvm_type = IWL_NVM_EXT, \ 283 .dbgc_supported = true, \ 284 .min_umac_error_event_table = 0xD0000, \ 285 .d3_debug_data_base_addr = 0x401000, \ 286 .d3_debug_data_length = 60 * 1024, \ 287 .mon_smem_regs = { \ 288 .write_ptr = { \ 289 .addr = LDBG_M2S_BUF_WPTR, \ 290 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 291 }, \ 292 .cycle_cnt = { \ 293 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 294 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 295 }, \ 296 }, \ 297 .trans.umac_prph_offset = 0x300000, \ 298 .trans.device_family = IWL_DEVICE_FAMILY_BZ, \ 299 .trans.base_params = &iwl_ax210_base_params, \ 300 .min_txq_size = 128, \ 301 .gp2_reg_addr = 0xd02c68, \ 302 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \ 303 .mon_dram_regs = { \ 304 .write_ptr = { \ 305 .addr = DBGC_CUR_DBGBUF_STATUS, \ 306 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 307 }, \ 308 .cycle_cnt = { \ 309 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 310 .mask = 0xffffffff, \ 311 }, \ 312 .cur_frag = { \ 313 .addr = DBGC_CUR_DBGBUF_STATUS, \ 314 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 315 }, \ 316 }, \ 317 .mon_dbgi_regs = { \ 318 .write_ptr = { \ 319 .addr = DBGI_SRAM_FIFO_POINTERS, \ 320 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \ 321 }, \ 322 } 323 324 #define IWL_DEVICE_BZ \ 325 IWL_DEVICE_BZ_COMMON, \ 326 .ht_params = &iwl_22000_ht_params 327 328 #define IWL_DEVICE_GL_A \ 329 IWL_DEVICE_BZ_COMMON, \ 330 .ht_params = &iwl_gl_a_ht_params 331 332 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = { 333 .mq_rx_supported = true, 334 .use_tfh = true, 335 .rf_id = true, 336 .gen2 = true, 337 .device_family = IWL_DEVICE_FAMILY_22000, 338 .base_params = &iwl_22000_base_params, 339 }; 340 341 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = { 342 .mq_rx_supported = true, 343 .use_tfh = true, 344 .rf_id = true, 345 .gen2 = true, 346 .device_family = IWL_DEVICE_FAMILY_22000, 347 .base_params = &iwl_22000_base_params, 348 .integrated = true, 349 .xtal_latency = 500, 350 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 351 }; 352 353 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = { 354 .mq_rx_supported = true, 355 .use_tfh = true, 356 .rf_id = true, 357 .gen2 = true, 358 .device_family = IWL_DEVICE_FAMILY_22000, 359 .base_params = &iwl_22000_base_params, 360 .integrated = true, 361 .xtal_latency = 1820, 362 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US, 363 }; 364 365 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = { 366 .mq_rx_supported = true, 367 .use_tfh = true, 368 .rf_id = true, 369 .gen2 = true, 370 .device_family = IWL_DEVICE_FAMILY_22000, 371 .base_params = &iwl_22000_base_params, 372 .integrated = true, 373 .xtal_latency = 12000, 374 .low_latency_xtal = true, 375 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 376 }; 377 378 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = { 379 .mq_rx_supported = true, 380 .use_tfh = true, 381 .rf_id = true, 382 .gen2 = true, 383 .device_family = IWL_DEVICE_FAMILY_AX210, 384 .base_params = &iwl_ax210_base_params, 385 .umac_prph_offset = 0x300000, 386 }; 387 388 const struct iwl_cfg_trans_params iwl_so_trans_cfg = { 389 .mq_rx_supported = true, 390 .use_tfh = true, 391 .rf_id = true, 392 .gen2 = true, 393 .device_family = IWL_DEVICE_FAMILY_AX210, 394 .base_params = &iwl_ax210_base_params, 395 .umac_prph_offset = 0x300000, 396 .integrated = true, 397 /* TODO: the following values need to be checked */ 398 .xtal_latency = 500, 399 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 400 }; 401 402 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = { 403 .mq_rx_supported = true, 404 .use_tfh = true, 405 .rf_id = true, 406 .gen2 = true, 407 .device_family = IWL_DEVICE_FAMILY_AX210, 408 .base_params = &iwl_ax210_base_params, 409 .umac_prph_offset = 0x300000, 410 .integrated = true, 411 .low_latency_xtal = true, 412 .xtal_latency = 12000, 413 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 414 }; 415 416 const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = { 417 .mq_rx_supported = true, 418 .use_tfh = true, 419 .rf_id = true, 420 .gen2 = true, 421 .device_family = IWL_DEVICE_FAMILY_AX210, 422 .base_params = &iwl_ax210_base_params, 423 .umac_prph_offset = 0x300000, 424 .integrated = true, 425 .low_latency_xtal = true, 426 .xtal_latency = 12000, 427 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 428 .imr_enabled = true, 429 }; 430 431 /* 432 * If the device doesn't support HE, no need to have that many buffers. 433 * 22000 devices can split multiple frames into a single RB, so fewer are 434 * needed; AX210 cannot (but use smaller RBs by default) - these sizes 435 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with 436 * additional overhead to account for processing time. 437 */ 438 #define IWL_NUM_RBDS_NON_HE 512 439 #define IWL_NUM_RBDS_22000_HE 2048 440 #define IWL_NUM_RBDS_AX210_HE 4096 441 442 /* 443 * All JF radio modules are part of the 9000 series, but the MAC part 444 * looks more like 22000. That's why this device is here, but called 445 * 9560 nevertheless. 446 */ 447 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = { 448 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE, 449 IWL_DEVICE_22500, 450 .num_rbds = IWL_NUM_RBDS_NON_HE, 451 }; 452 453 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = { 454 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE, 455 IWL_DEVICE_22500, 456 .num_rbds = IWL_NUM_RBDS_NON_HE, 457 }; 458 459 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = { 460 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE, 461 IWL_DEVICE_22500, 462 /* 463 * This device doesn't support receiving BlockAck with a large bitmap 464 * so we need to restrict the size of transmitted aggregation to the 465 * HT size; mac80211 would otherwise pick the HE max (256) by default. 466 */ 467 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 468 .num_rbds = IWL_NUM_RBDS_NON_HE, 469 }; 470 471 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = { 472 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE, 473 IWL_DEVICE_22500, 474 /* 475 * This device doesn't support receiving BlockAck with a large bitmap 476 * so we need to restrict the size of transmitted aggregation to the 477 * HT size; mac80211 would otherwise pick the HE max (256) by default. 478 */ 479 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 480 .num_rbds = IWL_NUM_RBDS_NON_HE, 481 }; 482 483 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = { 484 .device_family = IWL_DEVICE_FAMILY_22000, 485 .base_params = &iwl_22000_base_params, 486 .mq_rx_supported = true, 487 .use_tfh = true, 488 .rf_id = true, 489 .gen2 = true, 490 .bisr_workaround = 1, 491 }; 492 493 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = { 494 .device_family = IWL_DEVICE_FAMILY_AX210, 495 .base_params = &iwl_ax210_base_params, 496 .mq_rx_supported = true, 497 .use_tfh = true, 498 .rf_id = true, 499 .gen2 = true, 500 .integrated = true, 501 .umac_prph_offset = 0x300000 502 }; 503 504 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = { 505 .device_family = IWL_DEVICE_FAMILY_BZ, 506 .base_params = &iwl_ax210_base_params, 507 .mq_rx_supported = true, 508 .use_tfh = true, 509 .rf_id = true, 510 .gen2 = true, 511 .integrated = true, 512 .umac_prph_offset = 0x300000, 513 .xtal_latency = 12000, 514 .low_latency_xtal = true, 515 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 516 }; 517 518 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101"; 519 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz"; 520 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz"; 521 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203"; 522 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz"; 523 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz"; 524 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz"; 525 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz"; 526 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz"; 527 const char iwl_bz_name[] = "Intel(R) TBD Bz device"; 528 529 const char iwl_ax200_killer_1650w_name[] = 530 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)"; 531 const char iwl_ax200_killer_1650x_name[] = 532 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)"; 533 const char iwl_ax201_killer_1650s_name[] = 534 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)"; 535 const char iwl_ax201_killer_1650i_name[] = 536 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)"; 537 const char iwl_ax210_killer_1675w_name[] = 538 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)"; 539 const char iwl_ax210_killer_1675x_name[] = 540 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)"; 541 const char iwl_ax211_killer_1675s_name[] = 542 "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)"; 543 const char iwl_ax211_killer_1675i_name[] = 544 "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)"; 545 const char iwl_ax411_killer_1690s_name[] = 546 "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)"; 547 const char iwl_ax411_killer_1690i_name[] = 548 "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)"; 549 550 const struct iwl_cfg iwl_qu_b0_hr1_b0 = { 551 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 552 IWL_DEVICE_22500, 553 /* 554 * This device doesn't support receiving BlockAck with a large bitmap 555 * so we need to restrict the size of transmitted aggregation to the 556 * HT size; mac80211 would otherwise pick the HE max (256) by default. 557 */ 558 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 559 .tx_with_siso_diversity = true, 560 .num_rbds = IWL_NUM_RBDS_22000_HE, 561 }; 562 563 const struct iwl_cfg iwl_qu_b0_hr_b0 = { 564 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 565 IWL_DEVICE_22500, 566 /* 567 * This device doesn't support receiving BlockAck with a large bitmap 568 * so we need to restrict the size of transmitted aggregation to the 569 * HT size; mac80211 would otherwise pick the HE max (256) by default. 570 */ 571 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 572 .num_rbds = IWL_NUM_RBDS_22000_HE, 573 }; 574 575 const struct iwl_cfg iwl_ax201_cfg_qu_hr = { 576 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 577 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 578 IWL_DEVICE_22500, 579 /* 580 * This device doesn't support receiving BlockAck with a large bitmap 581 * so we need to restrict the size of transmitted aggregation to the 582 * HT size; mac80211 would otherwise pick the HE max (256) by default. 583 */ 584 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 585 .num_rbds = IWL_NUM_RBDS_22000_HE, 586 }; 587 588 const struct iwl_cfg iwl_qu_c0_hr1_b0 = { 589 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 590 IWL_DEVICE_22500, 591 /* 592 * This device doesn't support receiving BlockAck with a large bitmap 593 * so we need to restrict the size of transmitted aggregation to the 594 * HT size; mac80211 would otherwise pick the HE max (256) by default. 595 */ 596 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 597 .tx_with_siso_diversity = true, 598 .num_rbds = IWL_NUM_RBDS_22000_HE, 599 }; 600 601 const struct iwl_cfg iwl_qu_c0_hr_b0 = { 602 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 603 IWL_DEVICE_22500, 604 /* 605 * This device doesn't support receiving BlockAck with a large bitmap 606 * so we need to restrict the size of transmitted aggregation to the 607 * HT size; mac80211 would otherwise pick the HE max (256) by default. 608 */ 609 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 610 .num_rbds = IWL_NUM_RBDS_22000_HE, 611 }; 612 613 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = { 614 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 615 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 616 IWL_DEVICE_22500, 617 /* 618 * This device doesn't support receiving BlockAck with a large bitmap 619 * so we need to restrict the size of transmitted aggregation to the 620 * HT size; mac80211 would otherwise pick the HE max (256) by default. 621 */ 622 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 623 .num_rbds = IWL_NUM_RBDS_22000_HE, 624 }; 625 626 const struct iwl_cfg iwl_quz_a0_hr1_b0 = { 627 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 628 IWL_DEVICE_22500, 629 /* 630 * This device doesn't support receiving BlockAck with a large bitmap 631 * so we need to restrict the size of transmitted aggregation to the 632 * HT size; mac80211 would otherwise pick the HE max (256) by default. 633 */ 634 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 635 .tx_with_siso_diversity = true, 636 .num_rbds = IWL_NUM_RBDS_22000_HE, 637 }; 638 639 const struct iwl_cfg iwl_ax201_cfg_quz_hr = { 640 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 641 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 642 IWL_DEVICE_22500, 643 /* 644 * This device doesn't support receiving BlockAck with a large bitmap 645 * so we need to restrict the size of transmitted aggregation to the 646 * HT size; mac80211 would otherwise pick the HE max (256) by default. 647 */ 648 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 649 .num_rbds = IWL_NUM_RBDS_22000_HE, 650 }; 651 652 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = { 653 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 654 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 655 IWL_DEVICE_22500, 656 /* 657 * This device doesn't support receiving BlockAck with a large bitmap 658 * so we need to restrict the size of transmitted aggregation to the 659 * HT size; mac80211 would otherwise pick the HE max (256) by default. 660 */ 661 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 662 .num_rbds = IWL_NUM_RBDS_22000_HE, 663 }; 664 665 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = { 666 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 667 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 668 IWL_DEVICE_22500, 669 /* 670 * This device doesn't support receiving BlockAck with a large bitmap 671 * so we need to restrict the size of transmitted aggregation to the 672 * HT size; mac80211 would otherwise pick the HE max (256) by default. 673 */ 674 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 675 .num_rbds = IWL_NUM_RBDS_22000_HE, 676 }; 677 678 const struct iwl_cfg iwl_ax200_cfg_cc = { 679 .fw_name_pre = IWL_CC_A_FW_PRE, 680 IWL_DEVICE_22500, 681 /* 682 * This device doesn't support receiving BlockAck with a large bitmap 683 * so we need to restrict the size of transmitted aggregation to the 684 * HT size; mac80211 would otherwise pick the HE max (256) by default. 685 */ 686 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 687 .num_rbds = IWL_NUM_RBDS_22000_HE, 688 }; 689 690 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = { 691 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 692 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 693 IWL_DEVICE_22500, 694 /* 695 * This device doesn't support receiving BlockAck with a large bitmap 696 * so we need to restrict the size of transmitted aggregation to the 697 * HT size; mac80211 would otherwise pick the HE max (256) by default. 698 */ 699 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 700 .num_rbds = IWL_NUM_RBDS_22000_HE, 701 }; 702 703 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = { 704 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 705 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 706 IWL_DEVICE_22500, 707 /* 708 * This device doesn't support receiving BlockAck with a large bitmap 709 * so we need to restrict the size of transmitted aggregation to the 710 * HT size; mac80211 would otherwise pick the HE max (256) by default. 711 */ 712 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 713 .num_rbds = IWL_NUM_RBDS_22000_HE, 714 }; 715 716 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = { 717 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 718 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 719 IWL_DEVICE_22500, 720 /* 721 * This device doesn't support receiving BlockAck with a large bitmap 722 * so we need to restrict the size of transmitted aggregation to the 723 * HT size; mac80211 would otherwise pick the HE max (256) by default. 724 */ 725 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 726 .num_rbds = IWL_NUM_RBDS_22000_HE, 727 }; 728 729 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = { 730 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 731 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 732 IWL_DEVICE_22500, 733 /* 734 * This device doesn't support receiving BlockAck with a large bitmap 735 * so we need to restrict the size of transmitted aggregation to the 736 * HT size; mac80211 would otherwise pick the HE max (256) by default. 737 */ 738 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 739 .num_rbds = IWL_NUM_RBDS_22000_HE, 740 }; 741 742 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = { 743 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE, 744 IWL_DEVICE_22500, 745 /* 746 * This device doesn't support receiving BlockAck with a large bitmap 747 * so we need to restrict the size of transmitted aggregation to the 748 * HT size; mac80211 would otherwise pick the HE max (256) by default. 749 */ 750 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 751 .num_rbds = IWL_NUM_RBDS_22000_HE, 752 }; 753 754 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = { 755 .name = "Intel(R) Wireless-AC 9560 160MHz", 756 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE, 757 IWL_DEVICE_AX210, 758 .num_rbds = IWL_NUM_RBDS_NON_HE, 759 }; 760 761 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = { 762 .name = iwl_ax211_name, 763 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 764 .uhb_supported = true, 765 IWL_DEVICE_AX210, 766 .num_rbds = IWL_NUM_RBDS_AX210_HE, 767 }; 768 769 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = { 770 .name = iwl_ax211_name, 771 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 772 .uhb_supported = true, 773 IWL_DEVICE_AX210, 774 .num_rbds = IWL_NUM_RBDS_AX210_HE, 775 .trans.xtal_latency = 12000, 776 .trans.low_latency_xtal = true, 777 }; 778 779 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = { 780 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 781 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE, 782 .uhb_supported = true, 783 IWL_DEVICE_AX210, 784 .num_rbds = IWL_NUM_RBDS_AX210_HE, 785 }; 786 787 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = { 788 .name = iwl_ax411_name, 789 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 790 .uhb_supported = true, 791 IWL_DEVICE_AX210, 792 .num_rbds = IWL_NUM_RBDS_AX210_HE, 793 }; 794 795 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = { 796 .name = iwl_ax411_name, 797 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 798 .uhb_supported = true, 799 IWL_DEVICE_AX210, 800 .num_rbds = IWL_NUM_RBDS_AX210_HE, 801 .trans.xtal_latency = 12000, 802 .trans.low_latency_xtal = true, 803 }; 804 805 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = { 806 .name = iwl_ax411_name, 807 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE, 808 .uhb_supported = true, 809 IWL_DEVICE_AX210, 810 .num_rbds = IWL_NUM_RBDS_AX210_HE, 811 }; 812 813 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = { 814 .name = iwl_ax211_name, 815 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE, 816 .uhb_supported = true, 817 IWL_DEVICE_AX210, 818 .num_rbds = IWL_NUM_RBDS_AX210_HE, 819 }; 820 821 const struct iwl_cfg iwl_cfg_snj_hr_b0 = { 822 .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE, 823 .uhb_supported = true, 824 IWL_DEVICE_AX210, 825 .num_rbds = IWL_NUM_RBDS_AX210_HE, 826 }; 827 828 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = { 829 .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE, 830 .uhb_supported = true, 831 IWL_DEVICE_AX210, 832 .num_rbds = IWL_NUM_RBDS_AX210_HE, 833 }; 834 835 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = { 836 .fw_name_pre = IWL_MA_A_HR_B_FW_PRE, 837 .uhb_supported = true, 838 IWL_DEVICE_AX210, 839 .num_rbds = IWL_NUM_RBDS_AX210_HE, 840 }; 841 842 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = { 843 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE, 844 .uhb_supported = true, 845 IWL_DEVICE_AX210, 846 .num_rbds = IWL_NUM_RBDS_AX210_HE, 847 }; 848 849 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = { 850 .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE, 851 .uhb_supported = true, 852 IWL_DEVICE_AX210, 853 .num_rbds = IWL_NUM_RBDS_AX210_HE, 854 }; 855 856 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = { 857 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 858 .uhb_supported = true, 859 IWL_DEVICE_AX210, 860 .num_rbds = IWL_NUM_RBDS_AX210_HE, 861 }; 862 863 const struct iwl_cfg iwl_cfg_ma_a0_ms_a0 = { 864 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 865 .uhb_supported = false, 866 IWL_DEVICE_AX210, 867 .num_rbds = IWL_NUM_RBDS_AX210_HE, 868 }; 869 870 const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = { 871 .fw_name_pre = IWL_SO_A_MR_A_FW_PRE, 872 .uhb_supported = false, 873 IWL_DEVICE_AX210, 874 .num_rbds = IWL_NUM_RBDS_AX210_HE, 875 }; 876 877 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = { 878 .fw_name_pre = IWL_MA_A_FM_A_FW_PRE, 879 .uhb_supported = true, 880 IWL_DEVICE_AX210, 881 .num_rbds = IWL_NUM_RBDS_AX210_HE, 882 }; 883 884 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = { 885 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 886 .uhb_supported = true, 887 IWL_DEVICE_AX210, 888 .num_rbds = IWL_NUM_RBDS_AX210_HE, 889 }; 890 891 const struct iwl_cfg iwl_cfg_snj_a0_ms_a0 = { 892 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 893 .uhb_supported = false, 894 IWL_DEVICE_AX210, 895 .num_rbds = IWL_NUM_RBDS_AX210_HE, 896 }; 897 898 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = { 899 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 900 IWL_DEVICE_AX210, 901 .num_rbds = IWL_NUM_RBDS_AX210_HE, 902 }; 903 904 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = { 905 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 906 IWL_DEVICE_22500, 907 /* 908 * This device doesn't support receiving BlockAck with a large bitmap 909 * so we need to restrict the size of transmitted aggregation to the 910 * HT size; mac80211 would otherwise pick the HE max (256) by default. 911 */ 912 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 913 .num_rbds = IWL_NUM_RBDS_22000_HE, 914 }; 915 916 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = { 917 .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE, 918 .uhb_supported = true, 919 IWL_DEVICE_BZ, 920 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 921 .num_rbds = IWL_NUM_RBDS_AX210_HE, 922 }; 923 924 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = { 925 .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE, 926 .uhb_supported = true, 927 IWL_DEVICE_BZ, 928 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 929 .num_rbds = IWL_NUM_RBDS_AX210_HE, 930 }; 931 932 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = { 933 .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE, 934 .uhb_supported = true, 935 IWL_DEVICE_BZ, 936 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 937 .num_rbds = IWL_NUM_RBDS_AX210_HE, 938 }; 939 940 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = { 941 .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE, 942 .uhb_supported = true, 943 IWL_DEVICE_BZ, 944 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 945 .num_rbds = IWL_NUM_RBDS_AX210_HE, 946 }; 947 948 const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = { 949 .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE, 950 .uhb_supported = true, 951 IWL_DEVICE_BZ, 952 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 953 .num_rbds = IWL_NUM_RBDS_AX210_HE, 954 }; 955 956 const struct iwl_cfg iwl_cfg_bz_a0_fm4_a0 = { 957 .fw_name_pre = IWL_BZ_A_FM4_A_FW_PRE, 958 .uhb_supported = true, 959 IWL_DEVICE_BZ, 960 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 961 .num_rbds = IWL_NUM_RBDS_AX210_HE, 962 }; 963 964 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = { 965 .fw_name_pre = IWL_GL_A_FM_A_FW_PRE, 966 .uhb_supported = true, 967 IWL_DEVICE_GL_A, 968 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 969 .num_rbds = IWL_NUM_RBDS_AX210_HE, 970 }; 971 972 const struct iwl_cfg iwl_cfg_gl_b0_fm_b0 = { 973 .fw_name_pre = IWL_GL_B_FM_B_FW_PRE, 974 .uhb_supported = true, 975 IWL_DEVICE_BZ, 976 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 977 .num_rbds = IWL_NUM_RBDS_AX210_HE, 978 }; 979 980 const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = { 981 .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE, 982 .uhb_supported = true, 983 IWL_DEVICE_BZ, 984 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 985 .num_rbds = IWL_NUM_RBDS_AX210_HE, 986 }; 987 988 const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = { 989 .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE, 990 .uhb_supported = true, 991 IWL_DEVICE_BZ, 992 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 993 .num_rbds = IWL_NUM_RBDS_AX210_HE, 994 }; 995 996 const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = { 997 .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE, 998 .uhb_supported = true, 999 IWL_DEVICE_BZ, 1000 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1001 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1002 }; 1003 1004 const struct iwl_cfg iwl_cfg_bnj_b0_fm4_b0 = { 1005 .fw_name_pre = IWL_BNJ_B_FM4_B_FW_PRE, 1006 .uhb_supported = true, 1007 IWL_DEVICE_BZ, 1008 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1009 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1010 }; 1011 1012 const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = { 1013 .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE, 1014 .uhb_supported = true, 1015 IWL_DEVICE_BZ, 1016 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1017 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1018 }; 1019 1020 const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = { 1021 .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE, 1022 .uhb_supported = true, 1023 IWL_DEVICE_BZ, 1024 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1025 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1026 }; 1027 1028 const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = { 1029 .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE, 1030 .uhb_supported = true, 1031 IWL_DEVICE_BZ, 1032 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1033 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1034 }; 1035 1036 const struct iwl_cfg iwl_cfg_bnj_b0_fm_b0 = { 1037 .fw_name_pre = IWL_BNJ_B_FM_B_FW_PRE, 1038 .uhb_supported = true, 1039 IWL_DEVICE_BZ, 1040 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 1041 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1042 }; 1043 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1044 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1045 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1046 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1047 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1048 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1049 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1050 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1051 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1052 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1053 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1054 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1055 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1056 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1057 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1058 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1059 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1060 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1061 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1062 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1063 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1064 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1065 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1066 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1067 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1068 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1069 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1070 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1071 MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1072 MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1073 MODULE_FIRMWARE(IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1074 MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1075 MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1076 MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1077 MODULE_FIRMWARE(IWL_BZ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1078 MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1079 MODULE_FIRMWARE(IWL_BNJ_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1080