1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2021 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 11 /* Highest firmware API version supported */ 12 #define IWL_22000_UCODE_API_MAX 69 13 14 /* Lowest firmware API version supported */ 15 #define IWL_22000_UCODE_API_MIN 39 16 17 /* NVM versions */ 18 #define IWL_22000_NVM_VERSION 0x0a1d 19 20 /* Memory offsets and lengths */ 21 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */ 22 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */ 23 #define IWL_22000_DCCM2_OFFSET 0x880000 24 #define IWL_22000_DCCM2_LEN 0x8000 25 #define IWL_22000_SMEM_OFFSET 0x400000 26 #define IWL_22000_SMEM_LEN 0xD0000 27 28 #define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-" 29 #define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-" 30 #define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-" 31 #define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-" 32 #define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-" 33 #define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-" 34 #define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-" 35 #define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-" 36 #define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-" 37 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-" 38 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-" 39 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-" 40 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-" 41 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-" 42 #define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-" 43 #define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-" 44 #define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-" 45 #define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-" 46 #define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0-" 47 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-" 48 #define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0-" 49 #define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-" 50 #define IWL_MA_A_FM_A_FW_PRE "iwlwifi-ma-a0-fm-a0-" 51 #define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-" 52 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0-" 53 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0-" 54 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0-" 55 #define IWL_BZ_A_MR_A_FW_PRE "iwlwifi-bz-a0-mr-a0-" 56 #define IWL_BZ_A_FM_A_FW_PRE "iwlwifi-bz-a0-fm-a0-" 57 #define IWL_GL_A_FM_A_FW_PRE "iwlwifi-gl-a0-fm-a0-" 58 #define IWL_BZ_Z_GF_A_FW_PRE "iwlwifi-bz-z0-gf-a0-" 59 #define IWL_BNJ_A_FM_A_FW_PRE "iwlwifi-BzBnj-a0-fm-a0-" 60 #define IWL_BNJ_A_FM4_A_FW_PRE "iwlwifi-BzBnj-a0-fm4-a0-" 61 #define IWL_BNJ_A_GF_A_FW_PRE "iwlwifi-BzBnj-a0-gf-a0-" 62 #define IWL_BNJ_A_GF4_A_FW_PRE "iwlwifi-BzBnj-a0-gf4-a0-" 63 #define IWL_BNJ_A_HR_B_FW_PRE "iwlwifi-BzBnj-a0-hr-b0-" 64 65 66 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \ 67 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode" 68 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \ 69 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode" 70 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \ 71 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 72 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \ 73 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode" 74 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \ 75 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode" 76 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \ 77 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode" 78 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \ 79 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode" 80 #define IWL_CC_A_MODULE_FIRMWARE(api) \ 81 IWL_CC_A_FW_PRE __stringify(api) ".ucode" 82 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \ 83 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode" 84 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 85 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode" 86 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \ 87 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode" 88 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \ 89 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode" 90 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 91 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 92 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \ 93 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 94 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \ 95 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 96 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \ 97 IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode" 98 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \ 99 IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode" 100 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \ 101 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode" 102 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \ 103 IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode" 104 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \ 105 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode" 106 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api) \ 107 IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode" 108 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \ 109 IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode" 110 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 111 IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 112 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \ 113 IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode" 114 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \ 115 IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 116 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \ 117 IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode" 118 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \ 119 IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode" 120 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \ 121 IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode" 122 #define IWL_BZ_Z_GF_A_MODULE_FIRMWARE(api) \ 123 IWL_BZ_Z_GF_A_FW_PRE __stringify(api) ".ucode" 124 #define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \ 125 IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode" 126 #define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \ 127 IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode" 128 #define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \ 129 IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 130 #define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 131 IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 132 #define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \ 133 IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 134 135 static const struct iwl_base_params iwl_22000_base_params = { 136 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 137 .num_of_queues = 512, 138 .max_tfd_queue_size = 256, 139 .shadow_ram_support = true, 140 .led_compensation = 57, 141 .wd_timeout = IWL_LONG_WD_TIMEOUT, 142 .max_event_log_size = 512, 143 .shadow_reg_enable = true, 144 .pcie_l1_allowed = true, 145 }; 146 147 static const struct iwl_base_params iwl_ax210_base_params = { 148 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 149 .num_of_queues = 512, 150 .max_tfd_queue_size = 65536, 151 .shadow_ram_support = true, 152 .led_compensation = 57, 153 .wd_timeout = IWL_LONG_WD_TIMEOUT, 154 .max_event_log_size = 512, 155 .shadow_reg_enable = true, 156 .pcie_l1_allowed = true, 157 }; 158 159 static const struct iwl_ht_params iwl_22000_ht_params = { 160 .stbc = true, 161 .ldpc = true, 162 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 163 BIT(NL80211_BAND_6GHZ), 164 }; 165 166 #define IWL_DEVICE_22000_COMMON \ 167 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 168 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 169 .led_mode = IWL_LED_RF_STATE, \ 170 .nvm_hw_section_num = 10, \ 171 .non_shared_ant = ANT_B, \ 172 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 173 .dccm_len = IWL_22000_DCCM_LEN, \ 174 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 175 .dccm2_len = IWL_22000_DCCM2_LEN, \ 176 .smem_offset = IWL_22000_SMEM_OFFSET, \ 177 .smem_len = IWL_22000_SMEM_LEN, \ 178 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 179 .apmg_not_supported = true, \ 180 .trans.mq_rx_supported = true, \ 181 .vht_mu_mimo_supported = true, \ 182 .mac_addr_from_csr = 0x380, \ 183 .ht_params = &iwl_22000_ht_params, \ 184 .nvm_ver = IWL_22000_NVM_VERSION, \ 185 .trans.use_tfh = true, \ 186 .trans.rf_id = true, \ 187 .trans.gen2 = true, \ 188 .nvm_type = IWL_NVM_EXT, \ 189 .dbgc_supported = true, \ 190 .min_umac_error_event_table = 0x400000, \ 191 .d3_debug_data_base_addr = 0x401000, \ 192 .d3_debug_data_length = 60 * 1024, \ 193 .mon_smem_regs = { \ 194 .write_ptr = { \ 195 .addr = LDBG_M2S_BUF_WPTR, \ 196 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 197 }, \ 198 .cycle_cnt = { \ 199 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 200 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 201 }, \ 202 } 203 204 #define IWL_DEVICE_22500 \ 205 IWL_DEVICE_22000_COMMON, \ 206 .trans.device_family = IWL_DEVICE_FAMILY_22000, \ 207 .trans.base_params = &iwl_22000_base_params, \ 208 .gp2_reg_addr = 0xa02c68, \ 209 .mon_dram_regs = { \ 210 .write_ptr = { \ 211 .addr = MON_BUFF_WRPTR_VER2, \ 212 .mask = 0xffffffff, \ 213 }, \ 214 .cycle_cnt = { \ 215 .addr = MON_BUFF_CYCLE_CNT_VER2, \ 216 .mask = 0xffffffff, \ 217 }, \ 218 } 219 220 #define IWL_DEVICE_AX210 \ 221 IWL_DEVICE_22000_COMMON, \ 222 .trans.umac_prph_offset = 0x300000, \ 223 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \ 224 .trans.base_params = &iwl_ax210_base_params, \ 225 .min_txq_size = 128, \ 226 .gp2_reg_addr = 0xd02c68, \ 227 .min_256_ba_txq_size = 1024, \ 228 .mon_dram_regs = { \ 229 .write_ptr = { \ 230 .addr = DBGC_CUR_DBGBUF_STATUS, \ 231 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 232 }, \ 233 .cycle_cnt = { \ 234 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 235 .mask = 0xffffffff, \ 236 }, \ 237 .cur_frag = { \ 238 .addr = DBGC_CUR_DBGBUF_STATUS, \ 239 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 240 }, \ 241 } 242 243 #define IWL_DEVICE_BZ_COMMON \ 244 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 245 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 246 .led_mode = IWL_LED_RF_STATE, \ 247 .nvm_hw_section_num = 10, \ 248 .non_shared_ant = ANT_B, \ 249 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 250 .dccm_len = IWL_22000_DCCM_LEN, \ 251 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 252 .dccm2_len = IWL_22000_DCCM2_LEN, \ 253 .smem_offset = IWL_22000_SMEM_OFFSET, \ 254 .smem_len = IWL_22000_SMEM_LEN, \ 255 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, \ 256 .apmg_not_supported = true, \ 257 .trans.mq_rx_supported = true, \ 258 .vht_mu_mimo_supported = true, \ 259 .mac_addr_from_csr = 0x30, \ 260 .ht_params = &iwl_22000_ht_params, \ 261 .nvm_ver = IWL_22000_NVM_VERSION, \ 262 .trans.use_tfh = true, \ 263 .trans.rf_id = true, \ 264 .trans.gen2 = true, \ 265 .nvm_type = IWL_NVM_EXT, \ 266 .dbgc_supported = true, \ 267 .min_umac_error_event_table = 0x400000, \ 268 .d3_debug_data_base_addr = 0x401000, \ 269 .d3_debug_data_length = 60 * 1024, \ 270 .mon_smem_regs = { \ 271 .write_ptr = { \ 272 .addr = LDBG_M2S_BUF_WPTR, \ 273 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 274 }, \ 275 .cycle_cnt = { \ 276 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 277 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 278 }, \ 279 } 280 281 #define IWL_DEVICE_BZ \ 282 IWL_DEVICE_BZ_COMMON, \ 283 .trans.umac_prph_offset = 0x300000, \ 284 .trans.device_family = IWL_DEVICE_FAMILY_BZ, \ 285 .trans.base_params = &iwl_ax210_base_params, \ 286 .min_txq_size = 128, \ 287 .gp2_reg_addr = 0xd02c68, \ 288 .min_256_ba_txq_size = 1024, \ 289 .mon_dram_regs = { \ 290 .write_ptr = { \ 291 .addr = DBGC_CUR_DBGBUF_STATUS, \ 292 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 293 }, \ 294 .cycle_cnt = { \ 295 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 296 .mask = 0xffffffff, \ 297 }, \ 298 .cur_frag = { \ 299 .addr = DBGC_CUR_DBGBUF_STATUS, \ 300 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 301 }, \ 302 } 303 304 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = { 305 .mq_rx_supported = true, 306 .use_tfh = true, 307 .rf_id = true, 308 .gen2 = true, 309 .device_family = IWL_DEVICE_FAMILY_22000, 310 .base_params = &iwl_22000_base_params, 311 }; 312 313 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = { 314 .mq_rx_supported = true, 315 .use_tfh = true, 316 .rf_id = true, 317 .gen2 = true, 318 .device_family = IWL_DEVICE_FAMILY_22000, 319 .base_params = &iwl_22000_base_params, 320 .integrated = true, 321 .xtal_latency = 500, 322 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 323 }; 324 325 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = { 326 .mq_rx_supported = true, 327 .use_tfh = true, 328 .rf_id = true, 329 .gen2 = true, 330 .device_family = IWL_DEVICE_FAMILY_22000, 331 .base_params = &iwl_22000_base_params, 332 .integrated = true, 333 .xtal_latency = 1820, 334 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US, 335 }; 336 337 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = { 338 .mq_rx_supported = true, 339 .use_tfh = true, 340 .rf_id = true, 341 .gen2 = true, 342 .device_family = IWL_DEVICE_FAMILY_22000, 343 .base_params = &iwl_22000_base_params, 344 .integrated = true, 345 .xtal_latency = 12000, 346 .low_latency_xtal = true, 347 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 348 }; 349 350 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = { 351 .mq_rx_supported = true, 352 .use_tfh = true, 353 .rf_id = true, 354 .gen2 = true, 355 .device_family = IWL_DEVICE_FAMILY_AX210, 356 .base_params = &iwl_ax210_base_params, 357 .umac_prph_offset = 0x300000, 358 }; 359 360 const struct iwl_cfg_trans_params iwl_so_trans_cfg = { 361 .mq_rx_supported = true, 362 .use_tfh = true, 363 .rf_id = true, 364 .gen2 = true, 365 .device_family = IWL_DEVICE_FAMILY_AX210, 366 .base_params = &iwl_ax210_base_params, 367 .umac_prph_offset = 0x300000, 368 .integrated = true, 369 /* TODO: the following values need to be checked */ 370 .xtal_latency = 500, 371 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 372 }; 373 374 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = { 375 .mq_rx_supported = true, 376 .use_tfh = true, 377 .rf_id = true, 378 .gen2 = true, 379 .device_family = IWL_DEVICE_FAMILY_AX210, 380 .base_params = &iwl_ax210_base_params, 381 .umac_prph_offset = 0x300000, 382 .integrated = true, 383 .low_latency_xtal = true, 384 .xtal_latency = 12000, 385 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 386 }; 387 388 /* 389 * If the device doesn't support HE, no need to have that many buffers. 390 * 22000 devices can split multiple frames into a single RB, so fewer are 391 * needed; AX210 cannot (but use smaller RBs by default) - these sizes 392 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with 393 * additional overhead to account for processing time. 394 */ 395 #define IWL_NUM_RBDS_NON_HE 512 396 #define IWL_NUM_RBDS_22000_HE 2048 397 #define IWL_NUM_RBDS_AX210_HE 4096 398 399 /* 400 * All JF radio modules are part of the 9000 series, but the MAC part 401 * looks more like 22000. That's why this device is here, but called 402 * 9560 nevertheless. 403 */ 404 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = { 405 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE, 406 IWL_DEVICE_22500, 407 .num_rbds = IWL_NUM_RBDS_NON_HE, 408 }; 409 410 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = { 411 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE, 412 IWL_DEVICE_22500, 413 .num_rbds = IWL_NUM_RBDS_NON_HE, 414 }; 415 416 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = { 417 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE, 418 IWL_DEVICE_22500, 419 /* 420 * This device doesn't support receiving BlockAck with a large bitmap 421 * so we need to restrict the size of transmitted aggregation to the 422 * HT size; mac80211 would otherwise pick the HE max (256) by default. 423 */ 424 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 425 .num_rbds = IWL_NUM_RBDS_NON_HE, 426 }; 427 428 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = { 429 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE, 430 IWL_DEVICE_22500, 431 /* 432 * This device doesn't support receiving BlockAck with a large bitmap 433 * so we need to restrict the size of transmitted aggregation to the 434 * HT size; mac80211 would otherwise pick the HE max (256) by default. 435 */ 436 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 437 .num_rbds = IWL_NUM_RBDS_NON_HE, 438 }; 439 440 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = { 441 .device_family = IWL_DEVICE_FAMILY_22000, 442 .base_params = &iwl_22000_base_params, 443 .mq_rx_supported = true, 444 .use_tfh = true, 445 .rf_id = true, 446 .gen2 = true, 447 .bisr_workaround = 1, 448 }; 449 450 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = { 451 .device_family = IWL_DEVICE_FAMILY_AX210, 452 .base_params = &iwl_ax210_base_params, 453 .mq_rx_supported = true, 454 .use_tfh = true, 455 .rf_id = true, 456 .gen2 = true, 457 .integrated = true, 458 .umac_prph_offset = 0x300000 459 }; 460 461 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = { 462 .device_family = IWL_DEVICE_FAMILY_BZ, 463 .base_params = &iwl_ax210_base_params, 464 .mq_rx_supported = true, 465 .use_tfh = true, 466 .rf_id = true, 467 .gen2 = true, 468 .integrated = true, 469 .umac_prph_offset = 0x300000, 470 .xtal_latency = 12000, 471 .low_latency_xtal = true, 472 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 473 }; 474 475 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101"; 476 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz"; 477 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz"; 478 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203"; 479 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz"; 480 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz"; 481 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz"; 482 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz"; 483 const char iwl_bz_name[] = "Intel(R) TBD Bz device"; 484 485 const char iwl_ax200_killer_1650w_name[] = 486 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)"; 487 const char iwl_ax200_killer_1650x_name[] = 488 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)"; 489 const char iwl_ax201_killer_1650s_name[] = 490 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)"; 491 const char iwl_ax201_killer_1650i_name[] = 492 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)"; 493 const char iwl_ax210_killer_1675w_name[] = 494 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)"; 495 const char iwl_ax210_killer_1675x_name[] = 496 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)"; 497 const char iwl_ax211_killer_1675s_name[] = 498 "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)"; 499 const char iwl_ax211_killer_1675i_name[] = 500 "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)"; 501 const char iwl_ax411_killer_1690s_name[] = 502 "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)"; 503 const char iwl_ax411_killer_1690i_name[] = 504 "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)"; 505 506 const struct iwl_cfg iwl_qu_b0_hr1_b0 = { 507 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 508 IWL_DEVICE_22500, 509 /* 510 * This device doesn't support receiving BlockAck with a large bitmap 511 * so we need to restrict the size of transmitted aggregation to the 512 * HT size; mac80211 would otherwise pick the HE max (256) by default. 513 */ 514 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 515 .tx_with_siso_diversity = true, 516 .num_rbds = IWL_NUM_RBDS_22000_HE, 517 }; 518 519 const struct iwl_cfg iwl_qu_b0_hr_b0 = { 520 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 521 IWL_DEVICE_22500, 522 /* 523 * This device doesn't support receiving BlockAck with a large bitmap 524 * so we need to restrict the size of transmitted aggregation to the 525 * HT size; mac80211 would otherwise pick the HE max (256) by default. 526 */ 527 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 528 .num_rbds = IWL_NUM_RBDS_22000_HE, 529 }; 530 531 const struct iwl_cfg iwl_ax201_cfg_qu_hr = { 532 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 533 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 534 IWL_DEVICE_22500, 535 /* 536 * This device doesn't support receiving BlockAck with a large bitmap 537 * so we need to restrict the size of transmitted aggregation to the 538 * HT size; mac80211 would otherwise pick the HE max (256) by default. 539 */ 540 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 541 .num_rbds = IWL_NUM_RBDS_22000_HE, 542 }; 543 544 const struct iwl_cfg iwl_qu_c0_hr1_b0 = { 545 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 546 IWL_DEVICE_22500, 547 /* 548 * This device doesn't support receiving BlockAck with a large bitmap 549 * so we need to restrict the size of transmitted aggregation to the 550 * HT size; mac80211 would otherwise pick the HE max (256) by default. 551 */ 552 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 553 .tx_with_siso_diversity = true, 554 .num_rbds = IWL_NUM_RBDS_22000_HE, 555 }; 556 557 const struct iwl_cfg iwl_qu_c0_hr_b0 = { 558 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 559 IWL_DEVICE_22500, 560 /* 561 * This device doesn't support receiving BlockAck with a large bitmap 562 * so we need to restrict the size of transmitted aggregation to the 563 * HT size; mac80211 would otherwise pick the HE max (256) by default. 564 */ 565 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 566 .num_rbds = IWL_NUM_RBDS_22000_HE, 567 }; 568 569 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = { 570 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 571 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 572 IWL_DEVICE_22500, 573 /* 574 * This device doesn't support receiving BlockAck with a large bitmap 575 * so we need to restrict the size of transmitted aggregation to the 576 * HT size; mac80211 would otherwise pick the HE max (256) by default. 577 */ 578 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 579 .num_rbds = IWL_NUM_RBDS_22000_HE, 580 }; 581 582 const struct iwl_cfg iwl_quz_a0_hr1_b0 = { 583 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 584 IWL_DEVICE_22500, 585 /* 586 * This device doesn't support receiving BlockAck with a large bitmap 587 * so we need to restrict the size of transmitted aggregation to the 588 * HT size; mac80211 would otherwise pick the HE max (256) by default. 589 */ 590 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 591 .tx_with_siso_diversity = true, 592 .num_rbds = IWL_NUM_RBDS_22000_HE, 593 }; 594 595 const struct iwl_cfg iwl_ax201_cfg_quz_hr = { 596 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 597 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 598 IWL_DEVICE_22500, 599 /* 600 * This device doesn't support receiving BlockAck with a large bitmap 601 * so we need to restrict the size of transmitted aggregation to the 602 * HT size; mac80211 would otherwise pick the HE max (256) by default. 603 */ 604 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 605 .num_rbds = IWL_NUM_RBDS_22000_HE, 606 }; 607 608 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = { 609 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 610 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 611 IWL_DEVICE_22500, 612 /* 613 * This device doesn't support receiving BlockAck with a large bitmap 614 * so we need to restrict the size of transmitted aggregation to the 615 * HT size; mac80211 would otherwise pick the HE max (256) by default. 616 */ 617 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 618 .num_rbds = IWL_NUM_RBDS_22000_HE, 619 }; 620 621 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = { 622 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 623 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 624 IWL_DEVICE_22500, 625 /* 626 * This device doesn't support receiving BlockAck with a large bitmap 627 * so we need to restrict the size of transmitted aggregation to the 628 * HT size; mac80211 would otherwise pick the HE max (256) by default. 629 */ 630 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 631 .num_rbds = IWL_NUM_RBDS_22000_HE, 632 }; 633 634 const struct iwl_cfg iwl_ax200_cfg_cc = { 635 .fw_name_pre = IWL_CC_A_FW_PRE, 636 IWL_DEVICE_22500, 637 /* 638 * This device doesn't support receiving BlockAck with a large bitmap 639 * so we need to restrict the size of transmitted aggregation to the 640 * HT size; mac80211 would otherwise pick the HE max (256) by default. 641 */ 642 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 643 .num_rbds = IWL_NUM_RBDS_22000_HE, 644 }; 645 646 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = { 647 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 648 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 649 IWL_DEVICE_22500, 650 /* 651 * This device doesn't support receiving BlockAck with a large bitmap 652 * so we need to restrict the size of transmitted aggregation to the 653 * HT size; mac80211 would otherwise pick the HE max (256) by default. 654 */ 655 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 656 .num_rbds = IWL_NUM_RBDS_22000_HE, 657 }; 658 659 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = { 660 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 661 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 662 IWL_DEVICE_22500, 663 /* 664 * This device doesn't support receiving BlockAck with a large bitmap 665 * so we need to restrict the size of transmitted aggregation to the 666 * HT size; mac80211 would otherwise pick the HE max (256) by default. 667 */ 668 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 669 .num_rbds = IWL_NUM_RBDS_22000_HE, 670 }; 671 672 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = { 673 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 674 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 675 IWL_DEVICE_22500, 676 /* 677 * This device doesn't support receiving BlockAck with a large bitmap 678 * so we need to restrict the size of transmitted aggregation to the 679 * HT size; mac80211 would otherwise pick the HE max (256) by default. 680 */ 681 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 682 .num_rbds = IWL_NUM_RBDS_22000_HE, 683 }; 684 685 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = { 686 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 687 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 688 IWL_DEVICE_22500, 689 /* 690 * This device doesn't support receiving BlockAck with a large bitmap 691 * so we need to restrict the size of transmitted aggregation to the 692 * HT size; mac80211 would otherwise pick the HE max (256) by default. 693 */ 694 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 695 .num_rbds = IWL_NUM_RBDS_22000_HE, 696 }; 697 698 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = { 699 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE, 700 IWL_DEVICE_22500, 701 /* 702 * This device doesn't support receiving BlockAck with a large bitmap 703 * so we need to restrict the size of transmitted aggregation to the 704 * HT size; mac80211 would otherwise pick the HE max (256) by default. 705 */ 706 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 707 .num_rbds = IWL_NUM_RBDS_22000_HE, 708 }; 709 710 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = { 711 .name = "Intel(R) Wireless-AC 9560 160MHz", 712 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE, 713 IWL_DEVICE_AX210, 714 .num_rbds = IWL_NUM_RBDS_NON_HE, 715 }; 716 717 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = { 718 .name = iwl_ax211_name, 719 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 720 .uhb_supported = true, 721 IWL_DEVICE_AX210, 722 .num_rbds = IWL_NUM_RBDS_AX210_HE, 723 }; 724 725 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = { 726 .name = iwl_ax211_name, 727 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 728 .uhb_supported = true, 729 IWL_DEVICE_AX210, 730 .num_rbds = IWL_NUM_RBDS_AX210_HE, 731 .trans.xtal_latency = 12000, 732 .trans.low_latency_xtal = true, 733 }; 734 735 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = { 736 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 737 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE, 738 .uhb_supported = true, 739 IWL_DEVICE_AX210, 740 .num_rbds = IWL_NUM_RBDS_AX210_HE, 741 }; 742 743 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = { 744 .name = iwl_ax411_name, 745 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 746 .uhb_supported = true, 747 IWL_DEVICE_AX210, 748 .num_rbds = IWL_NUM_RBDS_AX210_HE, 749 }; 750 751 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = { 752 .name = iwl_ax411_name, 753 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 754 .uhb_supported = true, 755 IWL_DEVICE_AX210, 756 .num_rbds = IWL_NUM_RBDS_AX210_HE, 757 .trans.xtal_latency = 12000, 758 .trans.low_latency_xtal = true, 759 }; 760 761 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = { 762 .name = iwl_ax411_name, 763 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE, 764 .uhb_supported = true, 765 IWL_DEVICE_AX210, 766 .num_rbds = IWL_NUM_RBDS_AX210_HE, 767 }; 768 769 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = { 770 .name = iwl_ax211_name, 771 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE, 772 .uhb_supported = true, 773 IWL_DEVICE_AX210, 774 .num_rbds = IWL_NUM_RBDS_AX210_HE, 775 }; 776 777 const struct iwl_cfg iwl_cfg_snj_hr_b0 = { 778 .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE, 779 .uhb_supported = true, 780 IWL_DEVICE_AX210, 781 .num_rbds = IWL_NUM_RBDS_AX210_HE, 782 }; 783 784 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = { 785 .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE, 786 .uhb_supported = true, 787 IWL_DEVICE_AX210, 788 .num_rbds = IWL_NUM_RBDS_AX210_HE, 789 }; 790 791 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = { 792 .fw_name_pre = IWL_MA_A_HR_B_FW_PRE, 793 .uhb_supported = true, 794 IWL_DEVICE_AX210, 795 .num_rbds = IWL_NUM_RBDS_AX210_HE, 796 }; 797 798 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = { 799 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE, 800 .uhb_supported = true, 801 IWL_DEVICE_AX210, 802 .num_rbds = IWL_NUM_RBDS_AX210_HE, 803 }; 804 805 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = { 806 .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE, 807 .uhb_supported = true, 808 IWL_DEVICE_AX210, 809 .num_rbds = IWL_NUM_RBDS_AX210_HE, 810 }; 811 812 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = { 813 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 814 .uhb_supported = true, 815 IWL_DEVICE_AX210, 816 .num_rbds = IWL_NUM_RBDS_AX210_HE, 817 }; 818 819 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = { 820 .fw_name_pre = IWL_MA_A_FM_A_FW_PRE, 821 .uhb_supported = true, 822 IWL_DEVICE_AX210, 823 .num_rbds = IWL_NUM_RBDS_AX210_HE, 824 }; 825 826 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = { 827 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 828 .uhb_supported = true, 829 IWL_DEVICE_AX210, 830 .num_rbds = IWL_NUM_RBDS_AX210_HE, 831 }; 832 833 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = { 834 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 835 IWL_DEVICE_AX210, 836 .num_rbds = IWL_NUM_RBDS_AX210_HE, 837 }; 838 839 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = { 840 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 841 IWL_DEVICE_22500, 842 /* 843 * This device doesn't support receiving BlockAck with a large bitmap 844 * so we need to restrict the size of transmitted aggregation to the 845 * HT size; mac80211 would otherwise pick the HE max (256) by default. 846 */ 847 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 848 .num_rbds = IWL_NUM_RBDS_22000_HE, 849 }; 850 851 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = { 852 .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE, 853 .uhb_supported = true, 854 IWL_DEVICE_BZ, 855 .num_rbds = IWL_NUM_RBDS_AX210_HE, 856 }; 857 858 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = { 859 .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE, 860 .uhb_supported = true, 861 IWL_DEVICE_BZ, 862 .num_rbds = IWL_NUM_RBDS_AX210_HE, 863 }; 864 865 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = { 866 .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE, 867 .uhb_supported = true, 868 IWL_DEVICE_BZ, 869 .num_rbds = IWL_NUM_RBDS_AX210_HE, 870 }; 871 872 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = { 873 .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE, 874 .uhb_supported = true, 875 IWL_DEVICE_BZ, 876 .num_rbds = IWL_NUM_RBDS_AX210_HE, 877 }; 878 879 const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = { 880 .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE, 881 .uhb_supported = true, 882 IWL_DEVICE_BZ, 883 .num_rbds = IWL_NUM_RBDS_AX210_HE, 884 }; 885 886 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = { 887 .fw_name_pre = IWL_GL_A_FM_A_FW_PRE, 888 .uhb_supported = true, 889 IWL_DEVICE_BZ, 890 .num_rbds = IWL_NUM_RBDS_AX210_HE, 891 }; 892 893 const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = { 894 .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE, 895 .uhb_supported = true, 896 IWL_DEVICE_BZ, 897 .num_rbds = IWL_NUM_RBDS_AX210_HE, 898 }; 899 900 const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = { 901 .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE, 902 .uhb_supported = true, 903 IWL_DEVICE_BZ, 904 .num_rbds = IWL_NUM_RBDS_AX210_HE, 905 }; 906 907 const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = { 908 .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE, 909 .uhb_supported = true, 910 IWL_DEVICE_BZ, 911 .num_rbds = IWL_NUM_RBDS_AX210_HE, 912 }; 913 914 const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = { 915 .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE, 916 .uhb_supported = true, 917 IWL_DEVICE_BZ, 918 .num_rbds = IWL_NUM_RBDS_AX210_HE, 919 }; 920 921 const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = { 922 .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE, 923 .uhb_supported = true, 924 IWL_DEVICE_BZ, 925 .num_rbds = IWL_NUM_RBDS_AX210_HE, 926 }; 927 928 const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = { 929 .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE, 930 .uhb_supported = true, 931 IWL_DEVICE_BZ, 932 .num_rbds = IWL_NUM_RBDS_AX210_HE, 933 }; 934 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 935 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 936 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 937 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 938 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 939 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 940 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 941 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 942 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 943 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 944 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 945 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 946 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 947 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 948 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 949 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 950 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 951 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 952 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 953 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 954 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 955 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 956 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 957 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 958 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 959 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 960 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 961 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 962 MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 963 MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 964 MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 965 MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 966 MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 967