1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2021 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 11 /* Highest firmware API version supported */ 12 #define IWL_22000_UCODE_API_MAX 67 13 14 /* Lowest firmware API version supported */ 15 #define IWL_22000_UCODE_API_MIN 39 16 17 /* NVM versions */ 18 #define IWL_22000_NVM_VERSION 0x0a1d 19 20 /* Memory offsets and lengths */ 21 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */ 22 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */ 23 #define IWL_22000_DCCM2_OFFSET 0x880000 24 #define IWL_22000_DCCM2_LEN 0x8000 25 #define IWL_22000_SMEM_OFFSET 0x400000 26 #define IWL_22000_SMEM_LEN 0xD0000 27 28 #define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-" 29 #define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-" 30 #define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-" 31 #define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-" 32 #define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-" 33 #define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-" 34 #define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-" 35 #define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-" 36 #define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-" 37 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-" 38 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-" 39 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-" 40 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-" 41 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-" 42 #define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-" 43 #define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-" 44 #define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-" 45 #define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-" 46 #define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0-" 47 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-" 48 #define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0-" 49 #define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-" 50 #define IWL_MA_A_FM_A_FW_PRE "iwlwifi-ma-a0-fm-a0-" 51 #define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-" 52 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0-" 53 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0-" 54 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0-" 55 #define IWL_BZ_A_MR_A_FW_PRE "iwlwifi-bz-a0-mr-a0-" 56 #define IWL_BZ_A_FM_A_FW_PRE "iwlwifi-bz-a0-fm-a0-" 57 #define IWL_GL_A_FM_A_FW_PRE "iwlwifi-gl-a0-fm7-a0-" 58 59 60 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \ 61 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode" 62 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \ 63 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode" 64 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \ 65 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 66 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \ 67 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode" 68 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \ 69 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode" 70 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \ 71 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode" 72 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \ 73 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode" 74 #define IWL_CC_A_MODULE_FIRMWARE(api) \ 75 IWL_CC_A_FW_PRE __stringify(api) ".ucode" 76 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \ 77 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode" 78 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 79 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode" 80 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \ 81 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode" 82 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \ 83 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode" 84 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 85 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 86 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \ 87 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 88 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \ 89 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 90 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \ 91 IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode" 92 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \ 93 IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode" 94 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \ 95 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode" 96 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \ 97 IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode" 98 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \ 99 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode" 100 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api) \ 101 IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode" 102 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \ 103 IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode" 104 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 105 IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 106 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \ 107 IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode" 108 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \ 109 IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 110 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \ 111 IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode" 112 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \ 113 IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode" 114 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \ 115 IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode" 116 117 static const struct iwl_base_params iwl_22000_base_params = { 118 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 119 .num_of_queues = 512, 120 .max_tfd_queue_size = 256, 121 .shadow_ram_support = true, 122 .led_compensation = 57, 123 .wd_timeout = IWL_LONG_WD_TIMEOUT, 124 .max_event_log_size = 512, 125 .shadow_reg_enable = true, 126 .pcie_l1_allowed = true, 127 }; 128 129 static const struct iwl_base_params iwl_ax210_base_params = { 130 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 131 .num_of_queues = 512, 132 .max_tfd_queue_size = 65536, 133 .shadow_ram_support = true, 134 .led_compensation = 57, 135 .wd_timeout = IWL_LONG_WD_TIMEOUT, 136 .max_event_log_size = 512, 137 .shadow_reg_enable = true, 138 .pcie_l1_allowed = true, 139 }; 140 141 static const struct iwl_ht_params iwl_22000_ht_params = { 142 .stbc = true, 143 .ldpc = true, 144 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 145 BIT(NL80211_BAND_6GHZ), 146 }; 147 148 #define IWL_DEVICE_22000_COMMON \ 149 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 150 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 151 .led_mode = IWL_LED_RF_STATE, \ 152 .nvm_hw_section_num = 10, \ 153 .non_shared_ant = ANT_B, \ 154 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 155 .dccm_len = IWL_22000_DCCM_LEN, \ 156 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 157 .dccm2_len = IWL_22000_DCCM2_LEN, \ 158 .smem_offset = IWL_22000_SMEM_OFFSET, \ 159 .smem_len = IWL_22000_SMEM_LEN, \ 160 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 161 .apmg_not_supported = true, \ 162 .trans.mq_rx_supported = true, \ 163 .vht_mu_mimo_supported = true, \ 164 .mac_addr_from_csr = 0x380, \ 165 .ht_params = &iwl_22000_ht_params, \ 166 .nvm_ver = IWL_22000_NVM_VERSION, \ 167 .trans.use_tfh = true, \ 168 .trans.rf_id = true, \ 169 .trans.gen2 = true, \ 170 .nvm_type = IWL_NVM_EXT, \ 171 .dbgc_supported = true, \ 172 .min_umac_error_event_table = 0x400000, \ 173 .d3_debug_data_base_addr = 0x401000, \ 174 .d3_debug_data_length = 60 * 1024, \ 175 .mon_smem_regs = { \ 176 .write_ptr = { \ 177 .addr = LDBG_M2S_BUF_WPTR, \ 178 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 179 }, \ 180 .cycle_cnt = { \ 181 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 182 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 183 }, \ 184 } 185 186 #define IWL_DEVICE_22500 \ 187 IWL_DEVICE_22000_COMMON, \ 188 .trans.device_family = IWL_DEVICE_FAMILY_22000, \ 189 .trans.base_params = &iwl_22000_base_params, \ 190 .gp2_reg_addr = 0xa02c68, \ 191 .mon_dram_regs = { \ 192 .write_ptr = { \ 193 .addr = MON_BUFF_WRPTR_VER2, \ 194 .mask = 0xffffffff, \ 195 }, \ 196 .cycle_cnt = { \ 197 .addr = MON_BUFF_CYCLE_CNT_VER2, \ 198 .mask = 0xffffffff, \ 199 }, \ 200 } 201 202 #define IWL_DEVICE_AX210 \ 203 IWL_DEVICE_22000_COMMON, \ 204 .trans.umac_prph_offset = 0x300000, \ 205 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \ 206 .trans.base_params = &iwl_ax210_base_params, \ 207 .min_txq_size = 128, \ 208 .gp2_reg_addr = 0xd02c68, \ 209 .min_256_ba_txq_size = 1024, \ 210 .mon_dram_regs = { \ 211 .write_ptr = { \ 212 .addr = DBGC_CUR_DBGBUF_STATUS, \ 213 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 214 }, \ 215 .cycle_cnt = { \ 216 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 217 .mask = 0xffffffff, \ 218 }, \ 219 .cur_frag = { \ 220 .addr = DBGC_CUR_DBGBUF_STATUS, \ 221 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 222 }, \ 223 } 224 225 #define IWL_DEVICE_BZ_COMMON \ 226 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 227 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 228 .led_mode = IWL_LED_RF_STATE, \ 229 .nvm_hw_section_num = 10, \ 230 .non_shared_ant = ANT_B, \ 231 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 232 .dccm_len = IWL_22000_DCCM_LEN, \ 233 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 234 .dccm2_len = IWL_22000_DCCM2_LEN, \ 235 .smem_offset = IWL_22000_SMEM_OFFSET, \ 236 .smem_len = IWL_22000_SMEM_LEN, \ 237 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 238 .apmg_not_supported = true, \ 239 .trans.mq_rx_supported = true, \ 240 .vht_mu_mimo_supported = true, \ 241 .mac_addr_from_csr = 0x30, \ 242 .ht_params = &iwl_22000_ht_params, \ 243 .nvm_ver = IWL_22000_NVM_VERSION, \ 244 .trans.use_tfh = true, \ 245 .trans.rf_id = true, \ 246 .trans.gen2 = true, \ 247 .nvm_type = IWL_NVM_EXT, \ 248 .dbgc_supported = true, \ 249 .min_umac_error_event_table = 0x400000, \ 250 .d3_debug_data_base_addr = 0x401000, \ 251 .d3_debug_data_length = 60 * 1024, \ 252 .mon_smem_regs = { \ 253 .write_ptr = { \ 254 .addr = LDBG_M2S_BUF_WPTR, \ 255 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 256 }, \ 257 .cycle_cnt = { \ 258 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 259 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 260 }, \ 261 } 262 263 #define IWL_DEVICE_BZ \ 264 IWL_DEVICE_BZ_COMMON, \ 265 .trans.umac_prph_offset = 0x300000, \ 266 .trans.device_family = IWL_DEVICE_FAMILY_BZ, \ 267 .trans.base_params = &iwl_ax210_base_params, \ 268 .min_txq_size = 128, \ 269 .gp2_reg_addr = 0xd02c68, \ 270 .min_256_ba_txq_size = 1024, \ 271 .mon_dram_regs = { \ 272 .write_ptr = { \ 273 .addr = DBGC_CUR_DBGBUF_STATUS, \ 274 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 275 }, \ 276 .cycle_cnt = { \ 277 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 278 .mask = 0xffffffff, \ 279 }, \ 280 .cur_frag = { \ 281 .addr = DBGC_CUR_DBGBUF_STATUS, \ 282 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 283 }, \ 284 } 285 286 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = { 287 .mq_rx_supported = true, 288 .use_tfh = true, 289 .rf_id = true, 290 .gen2 = true, 291 .device_family = IWL_DEVICE_FAMILY_22000, 292 .base_params = &iwl_22000_base_params, 293 }; 294 295 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = { 296 .mq_rx_supported = true, 297 .use_tfh = true, 298 .rf_id = true, 299 .gen2 = true, 300 .device_family = IWL_DEVICE_FAMILY_22000, 301 .base_params = &iwl_22000_base_params, 302 .integrated = true, 303 .xtal_latency = 500, 304 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 305 }; 306 307 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = { 308 .mq_rx_supported = true, 309 .use_tfh = true, 310 .rf_id = true, 311 .gen2 = true, 312 .device_family = IWL_DEVICE_FAMILY_22000, 313 .base_params = &iwl_22000_base_params, 314 .integrated = true, 315 .xtal_latency = 1820, 316 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US, 317 }; 318 319 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = { 320 .mq_rx_supported = true, 321 .use_tfh = true, 322 .rf_id = true, 323 .gen2 = true, 324 .device_family = IWL_DEVICE_FAMILY_22000, 325 .base_params = &iwl_22000_base_params, 326 .integrated = true, 327 .xtal_latency = 12000, 328 .low_latency_xtal = true, 329 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 330 }; 331 332 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = { 333 .mq_rx_supported = true, 334 .use_tfh = true, 335 .rf_id = true, 336 .gen2 = true, 337 .device_family = IWL_DEVICE_FAMILY_AX210, 338 .base_params = &iwl_ax210_base_params, 339 .umac_prph_offset = 0x300000, 340 }; 341 342 const struct iwl_cfg_trans_params iwl_so_trans_cfg = { 343 .mq_rx_supported = true, 344 .use_tfh = true, 345 .rf_id = true, 346 .gen2 = true, 347 .device_family = IWL_DEVICE_FAMILY_AX210, 348 .base_params = &iwl_ax210_base_params, 349 .umac_prph_offset = 0x300000, 350 .integrated = true, 351 /* TODO: the following values need to be checked */ 352 .xtal_latency = 500, 353 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 354 }; 355 356 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = { 357 .mq_rx_supported = true, 358 .use_tfh = true, 359 .rf_id = true, 360 .gen2 = true, 361 .device_family = IWL_DEVICE_FAMILY_AX210, 362 .base_params = &iwl_ax210_base_params, 363 .umac_prph_offset = 0x300000, 364 .integrated = true, 365 .low_latency_xtal = true, 366 .xtal_latency = 12000, 367 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 368 }; 369 370 /* 371 * If the device doesn't support HE, no need to have that many buffers. 372 * 22000 devices can split multiple frames into a single RB, so fewer are 373 * needed; AX210 cannot (but use smaller RBs by default) - these sizes 374 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with 375 * additional overhead to account for processing time. 376 */ 377 #define IWL_NUM_RBDS_NON_HE 512 378 #define IWL_NUM_RBDS_22000_HE 2048 379 #define IWL_NUM_RBDS_AX210_HE 4096 380 381 /* 382 * All JF radio modules are part of the 9000 series, but the MAC part 383 * looks more like 22000. That's why this device is here, but called 384 * 9560 nevertheless. 385 */ 386 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = { 387 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE, 388 IWL_DEVICE_22500, 389 .num_rbds = IWL_NUM_RBDS_NON_HE, 390 }; 391 392 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = { 393 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE, 394 IWL_DEVICE_22500, 395 .num_rbds = IWL_NUM_RBDS_NON_HE, 396 }; 397 398 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = { 399 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE, 400 IWL_DEVICE_22500, 401 /* 402 * This device doesn't support receiving BlockAck with a large bitmap 403 * so we need to restrict the size of transmitted aggregation to the 404 * HT size; mac80211 would otherwise pick the HE max (256) by default. 405 */ 406 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 407 .num_rbds = IWL_NUM_RBDS_NON_HE, 408 }; 409 410 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = { 411 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE, 412 IWL_DEVICE_22500, 413 /* 414 * This device doesn't support receiving BlockAck with a large bitmap 415 * so we need to restrict the size of transmitted aggregation to the 416 * HT size; mac80211 would otherwise pick the HE max (256) by default. 417 */ 418 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 419 .num_rbds = IWL_NUM_RBDS_NON_HE, 420 }; 421 422 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = { 423 .device_family = IWL_DEVICE_FAMILY_22000, 424 .base_params = &iwl_22000_base_params, 425 .mq_rx_supported = true, 426 .use_tfh = true, 427 .rf_id = true, 428 .gen2 = true, 429 .bisr_workaround = 1, 430 }; 431 432 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = { 433 .device_family = IWL_DEVICE_FAMILY_AX210, 434 .base_params = &iwl_ax210_base_params, 435 .mq_rx_supported = true, 436 .use_tfh = true, 437 .rf_id = true, 438 .gen2 = true, 439 .integrated = true, 440 .umac_prph_offset = 0x300000 441 }; 442 443 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = { 444 .device_family = IWL_DEVICE_FAMILY_BZ, 445 .base_params = &iwl_ax210_base_params, 446 .mq_rx_supported = true, 447 .use_tfh = true, 448 .rf_id = true, 449 .gen2 = true, 450 .integrated = true, 451 .umac_prph_offset = 0x300000, 452 .xtal_latency = 12000, 453 .low_latency_xtal = true, 454 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 455 }; 456 457 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101"; 458 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz"; 459 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz"; 460 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203"; 461 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz"; 462 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz"; 463 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz"; 464 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz"; 465 const char iwl_bz_name[] = "Intel(R) TBD Bz device"; 466 467 const char iwl_ax200_killer_1650w_name[] = 468 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)"; 469 const char iwl_ax200_killer_1650x_name[] = 470 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)"; 471 const char iwl_ax201_killer_1650s_name[] = 472 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)"; 473 const char iwl_ax201_killer_1650i_name[] = 474 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)"; 475 const char iwl_ax210_killer_1675w_name[] = 476 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)"; 477 const char iwl_ax210_killer_1675x_name[] = 478 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)"; 479 const char iwl_ax211_killer_1675s_name[] = 480 "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)"; 481 const char iwl_ax211_killer_1675i_name[] = 482 "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)"; 483 const char iwl_ax411_killer_1690s_name[] = 484 "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)"; 485 const char iwl_ax411_killer_1690i_name[] = 486 "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)"; 487 488 const struct iwl_cfg iwl_qu_b0_hr1_b0 = { 489 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 490 IWL_DEVICE_22500, 491 /* 492 * This device doesn't support receiving BlockAck with a large bitmap 493 * so we need to restrict the size of transmitted aggregation to the 494 * HT size; mac80211 would otherwise pick the HE max (256) by default. 495 */ 496 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 497 .tx_with_siso_diversity = true, 498 .num_rbds = IWL_NUM_RBDS_22000_HE, 499 }; 500 501 const struct iwl_cfg iwl_qu_b0_hr_b0 = { 502 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 503 IWL_DEVICE_22500, 504 /* 505 * This device doesn't support receiving BlockAck with a large bitmap 506 * so we need to restrict the size of transmitted aggregation to the 507 * HT size; mac80211 would otherwise pick the HE max (256) by default. 508 */ 509 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 510 .num_rbds = IWL_NUM_RBDS_22000_HE, 511 }; 512 513 const struct iwl_cfg iwl_ax201_cfg_qu_hr = { 514 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 515 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 516 IWL_DEVICE_22500, 517 /* 518 * This device doesn't support receiving BlockAck with a large bitmap 519 * so we need to restrict the size of transmitted aggregation to the 520 * HT size; mac80211 would otherwise pick the HE max (256) by default. 521 */ 522 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 523 .num_rbds = IWL_NUM_RBDS_22000_HE, 524 }; 525 526 const struct iwl_cfg iwl_qu_c0_hr1_b0 = { 527 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 528 IWL_DEVICE_22500, 529 /* 530 * This device doesn't support receiving BlockAck with a large bitmap 531 * so we need to restrict the size of transmitted aggregation to the 532 * HT size; mac80211 would otherwise pick the HE max (256) by default. 533 */ 534 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 535 .tx_with_siso_diversity = true, 536 .num_rbds = IWL_NUM_RBDS_22000_HE, 537 }; 538 539 const struct iwl_cfg iwl_qu_c0_hr_b0 = { 540 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 541 IWL_DEVICE_22500, 542 /* 543 * This device doesn't support receiving BlockAck with a large bitmap 544 * so we need to restrict the size of transmitted aggregation to the 545 * HT size; mac80211 would otherwise pick the HE max (256) by default. 546 */ 547 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 548 .num_rbds = IWL_NUM_RBDS_22000_HE, 549 }; 550 551 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = { 552 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 553 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 554 IWL_DEVICE_22500, 555 /* 556 * This device doesn't support receiving BlockAck with a large bitmap 557 * so we need to restrict the size of transmitted aggregation to the 558 * HT size; mac80211 would otherwise pick the HE max (256) by default. 559 */ 560 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 561 .num_rbds = IWL_NUM_RBDS_22000_HE, 562 }; 563 564 const struct iwl_cfg iwl_quz_a0_hr1_b0 = { 565 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 566 IWL_DEVICE_22500, 567 /* 568 * This device doesn't support receiving BlockAck with a large bitmap 569 * so we need to restrict the size of transmitted aggregation to the 570 * HT size; mac80211 would otherwise pick the HE max (256) by default. 571 */ 572 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 573 .tx_with_siso_diversity = true, 574 .num_rbds = IWL_NUM_RBDS_22000_HE, 575 }; 576 577 const struct iwl_cfg iwl_ax201_cfg_quz_hr = { 578 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 579 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 580 IWL_DEVICE_22500, 581 /* 582 * This device doesn't support receiving BlockAck with a large bitmap 583 * so we need to restrict the size of transmitted aggregation to the 584 * HT size; mac80211 would otherwise pick the HE max (256) by default. 585 */ 586 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 587 .num_rbds = IWL_NUM_RBDS_22000_HE, 588 }; 589 590 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = { 591 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 592 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 593 IWL_DEVICE_22500, 594 /* 595 * This device doesn't support receiving BlockAck with a large bitmap 596 * so we need to restrict the size of transmitted aggregation to the 597 * HT size; mac80211 would otherwise pick the HE max (256) by default. 598 */ 599 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 600 .num_rbds = IWL_NUM_RBDS_22000_HE, 601 }; 602 603 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = { 604 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 605 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 606 IWL_DEVICE_22500, 607 /* 608 * This device doesn't support receiving BlockAck with a large bitmap 609 * so we need to restrict the size of transmitted aggregation to the 610 * HT size; mac80211 would otherwise pick the HE max (256) by default. 611 */ 612 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 613 .num_rbds = IWL_NUM_RBDS_22000_HE, 614 }; 615 616 const struct iwl_cfg iwl_ax200_cfg_cc = { 617 .fw_name_pre = IWL_CC_A_FW_PRE, 618 IWL_DEVICE_22500, 619 /* 620 * This device doesn't support receiving BlockAck with a large bitmap 621 * so we need to restrict the size of transmitted aggregation to the 622 * HT size; mac80211 would otherwise pick the HE max (256) by default. 623 */ 624 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 625 .num_rbds = IWL_NUM_RBDS_22000_HE, 626 }; 627 628 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = { 629 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 630 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 631 IWL_DEVICE_22500, 632 /* 633 * This device doesn't support receiving BlockAck with a large bitmap 634 * so we need to restrict the size of transmitted aggregation to the 635 * HT size; mac80211 would otherwise pick the HE max (256) by default. 636 */ 637 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 638 .num_rbds = IWL_NUM_RBDS_22000_HE, 639 }; 640 641 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = { 642 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 643 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 644 IWL_DEVICE_22500, 645 /* 646 * This device doesn't support receiving BlockAck with a large bitmap 647 * so we need to restrict the size of transmitted aggregation to the 648 * HT size; mac80211 would otherwise pick the HE max (256) by default. 649 */ 650 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 651 .num_rbds = IWL_NUM_RBDS_22000_HE, 652 }; 653 654 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = { 655 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 656 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 657 IWL_DEVICE_22500, 658 /* 659 * This device doesn't support receiving BlockAck with a large bitmap 660 * so we need to restrict the size of transmitted aggregation to the 661 * HT size; mac80211 would otherwise pick the HE max (256) by default. 662 */ 663 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 664 .num_rbds = IWL_NUM_RBDS_22000_HE, 665 }; 666 667 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = { 668 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 669 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 670 IWL_DEVICE_22500, 671 /* 672 * This device doesn't support receiving BlockAck with a large bitmap 673 * so we need to restrict the size of transmitted aggregation to the 674 * HT size; mac80211 would otherwise pick the HE max (256) by default. 675 */ 676 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 677 .num_rbds = IWL_NUM_RBDS_22000_HE, 678 }; 679 680 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = { 681 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE, 682 IWL_DEVICE_22500, 683 /* 684 * This device doesn't support receiving BlockAck with a large bitmap 685 * so we need to restrict the size of transmitted aggregation to the 686 * HT size; mac80211 would otherwise pick the HE max (256) by default. 687 */ 688 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 689 .num_rbds = IWL_NUM_RBDS_22000_HE, 690 }; 691 692 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = { 693 .name = "Intel(R) Wireless-AC 9560 160MHz", 694 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE, 695 IWL_DEVICE_AX210, 696 .num_rbds = IWL_NUM_RBDS_NON_HE, 697 }; 698 699 const struct iwl_cfg iwlax210_2ax_cfg_so_hr_a0 = { 700 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 701 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 702 IWL_DEVICE_AX210, 703 .num_rbds = IWL_NUM_RBDS_AX210_HE, 704 }; 705 706 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = { 707 .name = iwl_ax211_name, 708 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 709 .uhb_supported = true, 710 IWL_DEVICE_AX210, 711 .num_rbds = IWL_NUM_RBDS_AX210_HE, 712 }; 713 714 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = { 715 .name = iwl_ax211_name, 716 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 717 .uhb_supported = true, 718 IWL_DEVICE_AX210, 719 .num_rbds = IWL_NUM_RBDS_AX210_HE, 720 .trans.xtal_latency = 12000, 721 .trans.low_latency_xtal = true, 722 }; 723 724 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = { 725 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 726 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE, 727 .uhb_supported = true, 728 IWL_DEVICE_AX210, 729 .num_rbds = IWL_NUM_RBDS_AX210_HE, 730 }; 731 732 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = { 733 .name = iwl_ax411_name, 734 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 735 .uhb_supported = true, 736 IWL_DEVICE_AX210, 737 .num_rbds = IWL_NUM_RBDS_AX210_HE, 738 }; 739 740 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = { 741 .name = iwl_ax411_name, 742 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 743 .uhb_supported = true, 744 IWL_DEVICE_AX210, 745 .num_rbds = IWL_NUM_RBDS_AX210_HE, 746 .trans.xtal_latency = 12000, 747 .trans.low_latency_xtal = true, 748 }; 749 750 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = { 751 .name = iwl_ax411_name, 752 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE, 753 .uhb_supported = true, 754 IWL_DEVICE_AX210, 755 .num_rbds = IWL_NUM_RBDS_AX210_HE, 756 }; 757 758 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = { 759 .name = iwl_ax211_name, 760 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE, 761 .uhb_supported = true, 762 IWL_DEVICE_AX210, 763 .num_rbds = IWL_NUM_RBDS_AX210_HE, 764 }; 765 766 const struct iwl_cfg iwl_cfg_snj_hr_b0 = { 767 .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE, 768 .uhb_supported = true, 769 IWL_DEVICE_AX210, 770 .num_rbds = IWL_NUM_RBDS_AX210_HE, 771 }; 772 773 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = { 774 .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE, 775 .uhb_supported = true, 776 IWL_DEVICE_AX210, 777 .num_rbds = IWL_NUM_RBDS_AX210_HE, 778 }; 779 780 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = { 781 .fw_name_pre = IWL_MA_A_HR_B_FW_PRE, 782 .uhb_supported = true, 783 IWL_DEVICE_AX210, 784 .num_rbds = IWL_NUM_RBDS_AX210_HE, 785 }; 786 787 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = { 788 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE, 789 .uhb_supported = true, 790 IWL_DEVICE_AX210, 791 .num_rbds = IWL_NUM_RBDS_AX210_HE, 792 }; 793 794 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = { 795 .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE, 796 .uhb_supported = true, 797 IWL_DEVICE_AX210, 798 .num_rbds = IWL_NUM_RBDS_AX210_HE, 799 }; 800 801 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = { 802 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 803 .uhb_supported = true, 804 IWL_DEVICE_AX210, 805 .num_rbds = IWL_NUM_RBDS_AX210_HE, 806 }; 807 808 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = { 809 .fw_name_pre = IWL_MA_A_FM_A_FW_PRE, 810 .uhb_supported = true, 811 IWL_DEVICE_AX210, 812 .num_rbds = IWL_NUM_RBDS_AX210_HE, 813 }; 814 815 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = { 816 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 817 .uhb_supported = true, 818 IWL_DEVICE_AX210, 819 .num_rbds = IWL_NUM_RBDS_AX210_HE, 820 }; 821 822 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = { 823 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 824 IWL_DEVICE_AX210, 825 .num_rbds = IWL_NUM_RBDS_AX210_HE, 826 }; 827 828 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = { 829 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 830 IWL_DEVICE_22500, 831 /* 832 * This device doesn't support receiving BlockAck with a large bitmap 833 * so we need to restrict the size of transmitted aggregation to the 834 * HT size; mac80211 would otherwise pick the HE max (256) by default. 835 */ 836 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 837 .num_rbds = IWL_NUM_RBDS_22000_HE, 838 }; 839 840 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = { 841 .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE, 842 .uhb_supported = true, 843 IWL_DEVICE_BZ, 844 .num_rbds = IWL_NUM_RBDS_AX210_HE, 845 }; 846 847 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = { 848 .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE, 849 .uhb_supported = true, 850 IWL_DEVICE_BZ, 851 .num_rbds = IWL_NUM_RBDS_AX210_HE, 852 }; 853 854 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = { 855 .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE, 856 .uhb_supported = true, 857 IWL_DEVICE_BZ, 858 .num_rbds = IWL_NUM_RBDS_AX210_HE, 859 }; 860 861 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = { 862 .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE, 863 .uhb_supported = true, 864 IWL_DEVICE_BZ, 865 .num_rbds = IWL_NUM_RBDS_AX210_HE, 866 }; 867 868 const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = { 869 .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE, 870 .uhb_supported = true, 871 IWL_DEVICE_BZ, 872 .num_rbds = IWL_NUM_RBDS_AX210_HE, 873 }; 874 875 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = { 876 .fw_name_pre = IWL_GL_A_FM_A_FW_PRE, 877 .uhb_supported = true, 878 IWL_DEVICE_BZ, 879 .num_rbds = IWL_NUM_RBDS_AX210_HE, 880 }; 881 882 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 883 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 884 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 885 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 886 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 887 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 888 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 889 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 890 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 891 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 892 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 893 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 894 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 895 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 896 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 897 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 898 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 899 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 900 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 901 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 902 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 903 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 904 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 905 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 906 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 907 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 908 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 909 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 910