1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /******************************************************************************
3  *
4  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5  *
6  * Contact Information:
7  *  Intel Linux Wireless <ilw@linux.intel.com>
8  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
9  *
10  *****************************************************************************/
11 #ifndef __il_core_h__
12 #define __il_core_h__
13 
14 #include <linux/interrupt.h>
15 #include <linux/pci.h>		/* for struct pci_device_id */
16 #include <linux/kernel.h>
17 #include <linux/leds.h>
18 #include <linux/wait.h>
19 #include <linux/io.h>
20 #include <net/mac80211.h>
21 #include <net/ieee80211_radiotap.h>
22 
23 #include "commands.h"
24 #include "csr.h"
25 #include "prph.h"
26 
27 struct il_host_cmd;
28 struct il_cmd;
29 struct il_tx_queue;
30 
31 #define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
32 #define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
33 #define IL_WARN_ONCE(f, a...) dev_warn_once(&il->pci_dev->dev, f, ## a)
34 #define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
35 
36 #define RX_QUEUE_SIZE                         256
37 #define RX_QUEUE_MASK                         255
38 #define RX_QUEUE_SIZE_LOG                     8
39 
40 /*
41  * RX related structures and functions
42  */
43 #define RX_FREE_BUFFERS 64
44 #define RX_LOW_WATERMARK 8
45 
46 #define U32_PAD(n)		((4-(n))&0x3)
47 
48 /* CT-KILL constants */
49 #define CT_KILL_THRESHOLD_LEGACY   110	/* in Celsius */
50 
51 /* Default noise level to report when noise measurement is not available.
52  *   This may be because we're:
53  *   1)  Not associated (4965, no beacon stats being sent to driver)
54  *   2)  Scanning (noise measurement does not apply to associated channel)
55  *   3)  Receiving CCK (3945 delivers noise info only for OFDM frames)
56  * Use default noise value of -127 ... this is below the range of measurable
57  *   Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
58  *   Also, -127 works better than 0 when averaging frames with/without
59  *   noise info (e.g. averaging might be done in app); measured dBm values are
60  *   always negative ... using a negative value as the default keeps all
61  *   averages within an s8's (used in some apps) range of negative values. */
62 #define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
63 
64 /*
65  * RTS threshold here is total size [2347] minus 4 FCS bytes
66  * Per spec:
67  *   a value of 0 means RTS on all data/management packets
68  *   a value > max MSDU size means no RTS
69  * else RTS for data/management frames where MPDU is larger
70  *   than RTS value.
71  */
72 #define DEFAULT_RTS_THRESHOLD     2347U
73 #define MIN_RTS_THRESHOLD         0U
74 #define MAX_RTS_THRESHOLD         2347U
75 #define MAX_MSDU_SIZE		  2304U
76 #define MAX_MPDU_SIZE		  2346U
77 #define DEFAULT_BEACON_INTERVAL   100U
78 #define	DEFAULT_SHORT_RETRY_LIMIT 7U
79 #define	DEFAULT_LONG_RETRY_LIMIT  4U
80 
81 struct il_rx_buf {
82 	dma_addr_t page_dma;
83 	struct page *page;
84 	struct list_head list;
85 };
86 
87 #define rxb_addr(r) page_address(r->page)
88 
89 /* defined below */
90 struct il_device_cmd;
91 
92 struct il_cmd_meta {
93 	/* only for SYNC commands, iff the reply skb is wanted */
94 	struct il_host_cmd *source;
95 	/*
96 	 * only for ASYNC commands
97 	 * (which is somewhat stupid -- look at common.c for instance
98 	 * which duplicates a bunch of code because the callback isn't
99 	 * invoked for SYNC commands, if it were and its result passed
100 	 * through it would be simpler...)
101 	 */
102 	void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
103 			  struct il_rx_pkt *pkt);
104 
105 	/* The CMD_SIZE_HUGE flag bit indicates that the command
106 	 * structure is stored at the end of the shared queue memory. */
107 	u32 flags;
108 
109 	 DEFINE_DMA_UNMAP_ADDR(mapping);
110 	 DEFINE_DMA_UNMAP_LEN(len);
111 };
112 
113 /*
114  * Generic queue structure
115  *
116  * Contains common data for Rx and Tx queues
117  */
118 struct il_queue {
119 	int n_bd;		/* number of BDs in this queue */
120 	int write_ptr;		/* 1-st empty entry (idx) host_w */
121 	int read_ptr;		/* last used entry (idx) host_r */
122 	/* use for monitoring and recovering the stuck queue */
123 	dma_addr_t dma_addr;	/* physical addr for BD's */
124 	int n_win;		/* safe queue win */
125 	u32 id;
126 	int low_mark;		/* low watermark, resume queue if free
127 				 * space more than this */
128 	int high_mark;		/* high watermark, stop queue if free
129 				 * space less than this */
130 };
131 
132 /**
133  * struct il_tx_queue - Tx Queue for DMA
134  * @q: generic Rx/Tx queue descriptor
135  * @bd: base of circular buffer of TFDs
136  * @cmd: array of command/TX buffer pointers
137  * @meta: array of meta data for each command/tx buffer
138  * @dma_addr_cmd: physical address of cmd/tx buffer array
139  * @skbs: array of per-TFD socket buffer pointers
140  * @time_stamp: time (in jiffies) of last read_ptr change
141  * @need_update: indicates need to update read/write idx
142  * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
143  *
144  * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
145  * descriptors) and required locking structures.
146  */
147 #define TFD_TX_CMD_SLOTS 256
148 #define TFD_CMD_SLOTS 32
149 
150 struct il_tx_queue {
151 	struct il_queue q;
152 	void *tfds;
153 	struct il_device_cmd **cmd;
154 	struct il_cmd_meta *meta;
155 	struct sk_buff **skbs;
156 	unsigned long time_stamp;
157 	u8 need_update;
158 	u8 sched_retry;
159 	u8 active;
160 	u8 swq_id;
161 };
162 
163 /*
164  * EEPROM access time values:
165  *
166  * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
167  * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
168  * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
169  * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
170  */
171 #define IL_EEPROM_ACCESS_TIMEOUT	5000	/* uSec */
172 
173 #define IL_EEPROM_SEM_TIMEOUT		10	/* microseconds */
174 #define IL_EEPROM_SEM_RETRY_LIMIT	1000	/* number of attempts (not time) */
175 
176 /*
177  * Regulatory channel usage flags in EEPROM struct il4965_eeprom_channel.flags.
178  *
179  * IBSS and/or AP operation is allowed *only* on those channels with
180  * (VALID && IBSS && ACTIVE && !RADAR).  This restriction is in place because
181  * RADAR detection is not supported by the 4965 driver, but is a
182  * requirement for establishing a new network for legal operation on channels
183  * requiring RADAR detection or restricting ACTIVE scanning.
184  *
185  * NOTE:  "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
186  *        It only indicates that 20 MHz channel use is supported; HT40 channel
187  *        usage is indicated by a separate set of regulatory flags for each
188  *        HT40 channel pair.
189  *
190  * NOTE:  Using a channel inappropriately will result in a uCode error!
191  */
192 #define IL_NUM_TX_CALIB_GROUPS 5
193 enum {
194 	EEPROM_CHANNEL_VALID = (1 << 0),	/* usable for this SKU/geo */
195 	EEPROM_CHANNEL_IBSS = (1 << 1),	/* usable as an IBSS channel */
196 	/* Bit 2 Reserved */
197 	EEPROM_CHANNEL_ACTIVE = (1 << 3),	/* active scanning allowed */
198 	EEPROM_CHANNEL_RADAR = (1 << 4),	/* radar detection required */
199 	EEPROM_CHANNEL_WIDE = (1 << 5),	/* 20 MHz channel okay */
200 	/* Bit 6 Reserved (was Narrow Channel) */
201 	EEPROM_CHANNEL_DFS = (1 << 7),	/* dynamic freq selection candidate */
202 };
203 
204 /* SKU Capabilities */
205 /* 3945 only */
206 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE                (1 << 0)
207 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE                (1 << 1)
208 
209 /* *regulatory* channel data format in eeprom, one for each channel.
210  * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
211 struct il_eeprom_channel {
212 	u8 flags;		/* EEPROM_CHANNEL_* flags copied from EEPROM */
213 	s8 max_power_avg;	/* max power (dBm) on this chnl, limit 31 */
214 } __packed;
215 
216 /* 3945 Specific */
217 #define EEPROM_3945_EEPROM_VERSION	(0x2f)
218 
219 /* 4965 has two radio transmitters (and 3 radio receivers) */
220 #define EEPROM_TX_POWER_TX_CHAINS      (2)
221 
222 /* 4965 has room for up to 8 sets of txpower calibration data */
223 #define EEPROM_TX_POWER_BANDS          (8)
224 
225 /* 4965 factory calibration measures txpower gain settings for
226  * each of 3 target output levels */
227 #define EEPROM_TX_POWER_MEASUREMENTS   (3)
228 
229 /* 4965 Specific */
230 /* 4965 driver does not work with txpower calibration version < 5 */
231 #define EEPROM_4965_TX_POWER_VERSION    (5)
232 #define EEPROM_4965_EEPROM_VERSION	(0x2f)
233 #define EEPROM_4965_CALIB_VERSION_OFFSET       (2*0xB6)	/* 2 bytes */
234 #define EEPROM_4965_CALIB_TXPOWER_OFFSET       (2*0xE8)	/* 48  bytes */
235 #define EEPROM_4965_BOARD_REVISION             (2*0x4F)	/* 2 bytes */
236 #define EEPROM_4965_BOARD_PBA                  (2*0x56+1)	/* 9 bytes */
237 
238 /* 2.4 GHz */
239 extern const u8 il_eeprom_band_1[14];
240 
241 /*
242  * factory calibration data for one txpower level, on one channel,
243  * measured on one of the 2 tx chains (radio transmitter and associated
244  * antenna).  EEPROM contains:
245  *
246  * 1)  Temperature (degrees Celsius) of device when measurement was made.
247  *
248  * 2)  Gain table idx used to achieve the target measurement power.
249  *     This refers to the "well-known" gain tables (see 4965.h).
250  *
251  * 3)  Actual measured output power, in half-dBm ("34" = 17 dBm).
252  *
253  * 4)  RF power amplifier detector level measurement (not used).
254  */
255 struct il_eeprom_calib_measure {
256 	u8 temperature;		/* Device temperature (Celsius) */
257 	u8 gain_idx;		/* Index into gain table */
258 	u8 actual_pow;		/* Measured RF output power, half-dBm */
259 	s8 pa_det;		/* Power amp detector level (not used) */
260 } __packed;
261 
262 /*
263  * measurement set for one channel.  EEPROM contains:
264  *
265  * 1)  Channel number measured
266  *
267  * 2)  Measurements for each of 3 power levels for each of 2 radio transmitters
268  *     (a.k.a. "tx chains") (6 measurements altogether)
269  */
270 struct il_eeprom_calib_ch_info {
271 	u8 ch_num;
272 	struct il_eeprom_calib_measure
273 	    measurements[EEPROM_TX_POWER_TX_CHAINS]
274 	    [EEPROM_TX_POWER_MEASUREMENTS];
275 } __packed;
276 
277 /*
278  * txpower subband info.
279  *
280  * For each frequency subband, EEPROM contains the following:
281  *
282  * 1)  First and last channels within range of the subband.  "0" values
283  *     indicate that this sample set is not being used.
284  *
285  * 2)  Sample measurement sets for 2 channels close to the range endpoints.
286  */
287 struct il_eeprom_calib_subband_info {
288 	u8 ch_from;		/* channel number of lowest channel in subband */
289 	u8 ch_to;		/* channel number of highest channel in subband */
290 	struct il_eeprom_calib_ch_info ch1;
291 	struct il_eeprom_calib_ch_info ch2;
292 } __packed;
293 
294 /*
295  * txpower calibration info.  EEPROM contains:
296  *
297  * 1)  Factory-measured saturation power levels (maximum levels at which
298  *     tx power amplifier can output a signal without too much distortion).
299  *     There is one level for 2.4 GHz band and one for 5 GHz band.  These
300  *     values apply to all channels within each of the bands.
301  *
302  * 2)  Factory-measured power supply voltage level.  This is assumed to be
303  *     constant (i.e. same value applies to all channels/bands) while the
304  *     factory measurements are being made.
305  *
306  * 3)  Up to 8 sets of factory-measured txpower calibration values.
307  *     These are for different frequency ranges, since txpower gain
308  *     characteristics of the analog radio circuitry vary with frequency.
309  *
310  *     Not all sets need to be filled with data;
311  *     struct il_eeprom_calib_subband_info contains range of channels
312  *     (0 if unused) for each set of data.
313  */
314 struct il_eeprom_calib_info {
315 	u8 saturation_power24;	/* half-dBm (e.g. "34" = 17 dBm) */
316 	u8 saturation_power52;	/* half-dBm */
317 	__le16 voltage;		/* signed */
318 	struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
319 } __packed;
320 
321 /* General */
322 #define EEPROM_DEVICE_ID                    (2*0x08)	/* 2 bytes */
323 #define EEPROM_MAC_ADDRESS                  (2*0x15)	/* 6  bytes */
324 #define EEPROM_BOARD_REVISION               (2*0x35)	/* 2  bytes */
325 #define EEPROM_BOARD_PBA_NUMBER             (2*0x3B+1)	/* 9  bytes */
326 #define EEPROM_VERSION                      (2*0x44)	/* 2  bytes */
327 #define EEPROM_SKU_CAP                      (2*0x45)	/* 2  bytes */
328 #define EEPROM_OEM_MODE                     (2*0x46)	/* 2  bytes */
329 #define EEPROM_WOWLAN_MODE                  (2*0x47)	/* 2  bytes */
330 #define EEPROM_RADIO_CONFIG                 (2*0x48)	/* 2  bytes */
331 #define EEPROM_NUM_MAC_ADDRESS              (2*0x4C)	/* 2  bytes */
332 
333 /* The following masks are to be applied on EEPROM_RADIO_CONFIG */
334 #define EEPROM_RF_CFG_TYPE_MSK(x)   (x & 0x3)	/* bits 0-1   */
335 #define EEPROM_RF_CFG_STEP_MSK(x)   ((x >> 2)  & 0x3)	/* bits 2-3   */
336 #define EEPROM_RF_CFG_DASH_MSK(x)   ((x >> 4)  & 0x3)	/* bits 4-5   */
337 #define EEPROM_RF_CFG_PNUM_MSK(x)   ((x >> 6)  & 0x3)	/* bits 6-7   */
338 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8)  & 0xF)	/* bits 8-11  */
339 #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF)	/* bits 12-15 */
340 
341 #define EEPROM_3945_RF_CFG_TYPE_MAX  0x0
342 #define EEPROM_4965_RF_CFG_TYPE_MAX  0x1
343 
344 /*
345  * Per-channel regulatory data.
346  *
347  * Each channel that *might* be supported by iwl has a fixed location
348  * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
349  * txpower (MSB).
350  *
351  * Entries immediately below are for 20 MHz channel width.  HT40 (40 MHz)
352  * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
353  *
354  * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
355  */
356 #define EEPROM_REGULATORY_SKU_ID            (2*0x60)	/* 4  bytes */
357 #define EEPROM_REGULATORY_BAND_1            (2*0x62)	/* 2  bytes */
358 #define EEPROM_REGULATORY_BAND_1_CHANNELS   (2*0x63)	/* 28 bytes */
359 
360 /*
361  * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
362  * 5.0 GHz channels 7, 8, 11, 12, 16
363  * (4915-5080MHz) (none of these is ever supported)
364  */
365 #define EEPROM_REGULATORY_BAND_2            (2*0x71)	/* 2  bytes */
366 #define EEPROM_REGULATORY_BAND_2_CHANNELS   (2*0x72)	/* 26 bytes */
367 
368 /*
369  * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
370  * (5170-5320MHz)
371  */
372 #define EEPROM_REGULATORY_BAND_3            (2*0x7F)	/* 2  bytes */
373 #define EEPROM_REGULATORY_BAND_3_CHANNELS   (2*0x80)	/* 24 bytes */
374 
375 /*
376  * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
377  * (5500-5700MHz)
378  */
379 #define EEPROM_REGULATORY_BAND_4            (2*0x8C)	/* 2  bytes */
380 #define EEPROM_REGULATORY_BAND_4_CHANNELS   (2*0x8D)	/* 22 bytes */
381 
382 /*
383  * 5.7 GHz channels 145, 149, 153, 157, 161, 165
384  * (5725-5825MHz)
385  */
386 #define EEPROM_REGULATORY_BAND_5            (2*0x98)	/* 2  bytes */
387 #define EEPROM_REGULATORY_BAND_5_CHANNELS   (2*0x99)	/* 12 bytes */
388 
389 /*
390  * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
391  *
392  * The channel listed is the center of the lower 20 MHz half of the channel.
393  * The overall center frequency is actually 2 channels (10 MHz) above that,
394  * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away
395  * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5,
396  * and the overall HT40 channel width centers on channel 3.
397  *
398  * NOTE:  The RXON command uses 20 MHz channel numbers to specify the
399  *        control channel to which to tune.  RXON also specifies whether the
400  *        control channel is the upper or lower half of a HT40 channel.
401  *
402  * NOTE:  4965 does not support HT40 channels on 2.4 GHz.
403  */
404 #define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0)	/* 14 bytes */
405 
406 /*
407  * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64),
408  * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
409  */
410 #define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8)	/* 22 bytes */
411 
412 #define EEPROM_REGULATORY_BAND_NO_HT40			(0)
413 
414 int il_eeprom_init(struct il_priv *il);
415 void il_eeprom_free(struct il_priv *il);
416 const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
417 u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
418 int il_init_channel_map(struct il_priv *il);
419 void il_free_channel_map(struct il_priv *il);
420 const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
421 						  enum nl80211_band band,
422 						  u16 channel);
423 
424 #define IL_NUM_SCAN_RATES         (2)
425 
426 struct il4965_channel_tgd_info {
427 	u8 type;
428 	s8 max_power;
429 };
430 
431 struct il4965_channel_tgh_info {
432 	s64 last_radar_time;
433 };
434 
435 #define IL4965_MAX_RATE (33)
436 
437 struct il3945_clip_group {
438 	/* maximum power level to prevent clipping for each rate, derived by
439 	 *   us from this band's saturation power in EEPROM */
440 	const s8 clip_powers[IL_MAX_RATES];
441 };
442 
443 /* current Tx power values to use, one for each rate for each channel.
444  * requested power is limited by:
445  * -- regulatory EEPROM limits for this channel
446  * -- hardware capabilities (clip-powers)
447  * -- spectrum management
448  * -- user preference (e.g. iwconfig)
449  * when requested power is set, base power idx must also be set. */
450 struct il3945_channel_power_info {
451 	struct il3945_tx_power tpc;	/* actual radio and DSP gain settings */
452 	s8 power_table_idx;	/* actual (compenst'd) idx into gain table */
453 	s8 base_power_idx;	/* gain idx for power at factory temp. */
454 	s8 requested_power;	/* power (dBm) requested for this chnl/rate */
455 };
456 
457 /* current scan Tx power values to use, one for each scan rate for each
458  * channel. */
459 struct il3945_scan_power_info {
460 	struct il3945_tx_power tpc;	/* actual radio and DSP gain settings */
461 	s8 power_table_idx;	/* actual (compenst'd) idx into gain table */
462 	s8 requested_power;	/* scan pwr (dBm) requested for chnl/rate */
463 };
464 
465 /*
466  * One for each channel, holds all channel setup data
467  * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
468  *     with one another!
469  */
470 struct il_channel_info {
471 	struct il4965_channel_tgd_info tgd;
472 	struct il4965_channel_tgh_info tgh;
473 	struct il_eeprom_channel eeprom;	/* EEPROM regulatory limit */
474 	struct il_eeprom_channel ht40_eeprom;	/* EEPROM regulatory limit for
475 						 * HT40 channel */
476 
477 	u8 channel;		/* channel number */
478 	u8 flags;		/* flags copied from EEPROM */
479 	s8 max_power_avg;	/* (dBm) regul. eeprom, normal Tx, any rate */
480 	s8 curr_txpow;		/* (dBm) regulatory/spectrum/user (not h/w) limit */
481 	s8 min_power;		/* always 0 */
482 	s8 scan_power;		/* (dBm) regul. eeprom, direct scans, any rate */
483 
484 	u8 group_idx;		/* 0-4, maps channel to group1/2/3/4/5 */
485 	u8 band_idx;		/* 0-4, maps channel to band1/2/3/4/5 */
486 	enum nl80211_band band;
487 
488 	/* HT40 channel info */
489 	s8 ht40_max_power_avg;	/* (dBm) regul. eeprom, normal Tx, any rate */
490 	u8 ht40_flags;		/* flags copied from EEPROM */
491 	u8 ht40_extension_channel;	/* HT_IE_EXT_CHANNEL_* */
492 
493 	/* Radio/DSP gain settings for each "normal" data Tx rate.
494 	 * These include, in addition to RF and DSP gain, a few fields for
495 	 *   remembering/modifying gain settings (idxes). */
496 	struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
497 
498 	/* Radio/DSP gain settings for each scan rate, for directed scans. */
499 	struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
500 };
501 
502 #define IL_TX_FIFO_BK		0	/* shared */
503 #define IL_TX_FIFO_BE		1
504 #define IL_TX_FIFO_VI		2	/* shared */
505 #define IL_TX_FIFO_VO		3
506 #define IL_TX_FIFO_UNUSED	-1
507 
508 /* Minimum number of queues. MAX_NUM is defined in hw specific files.
509  * Set the minimum to accommodate the 4 standard TX queues, 1 command
510  * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
511 #define IL_MIN_NUM_QUEUES	10
512 
513 #define IL_DEFAULT_CMD_QUEUE_NUM	4
514 
515 #define IEEE80211_DATA_LEN              2304
516 #define IEEE80211_4ADDR_LEN             30
517 #define IEEE80211_HLEN                  (IEEE80211_4ADDR_LEN)
518 #define IEEE80211_FRAME_LEN             (IEEE80211_DATA_LEN + IEEE80211_HLEN)
519 
520 struct il_frame {
521 	union {
522 		struct ieee80211_hdr frame;
523 		struct il_tx_beacon_cmd beacon;
524 		u8 raw[IEEE80211_FRAME_LEN];
525 		u8 cmd[360];
526 	} u;
527 	struct list_head list;
528 };
529 
530 enum {
531 	CMD_SYNC = 0,
532 	CMD_SIZE_NORMAL = 0,
533 	CMD_NO_SKB = 0,
534 	CMD_SIZE_HUGE = (1 << 0),
535 	CMD_ASYNC = (1 << 1),
536 	CMD_WANT_SKB = (1 << 2),
537 	CMD_MAPPED = (1 << 3),
538 };
539 
540 #define DEF_CMD_PAYLOAD_SIZE 320
541 
542 /**
543  * struct il_device_cmd
544  *
545  * For allocation of the command and tx queues, this establishes the overall
546  * size of the largest command we send to uCode, except for a scan command
547  * (which is relatively huge; space is allocated separately).
548  */
549 struct il_device_cmd {
550 	struct il_cmd_header hdr;	/* uCode API */
551 	union {
552 		u32 flags;
553 		u8 val8;
554 		u16 val16;
555 		u32 val32;
556 		struct il_tx_cmd tx;
557 		u8 payload[DEF_CMD_PAYLOAD_SIZE];
558 	} __packed cmd;
559 } __packed;
560 
561 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
562 
563 struct il_host_cmd {
564 	const void *data;
565 	unsigned long reply_page;
566 	void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
567 			  struct il_rx_pkt *pkt);
568 	u32 flags;
569 	u16 len;
570 	u8 id;
571 };
572 
573 #define SUP_RATE_11A_MAX_NUM_CHANNELS  8
574 #define SUP_RATE_11B_MAX_NUM_CHANNELS  4
575 #define SUP_RATE_11G_MAX_NUM_CHANNELS  12
576 
577 /**
578  * struct il_rx_queue - Rx queue
579  * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
580  * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
581  * @read: Shared idx to newest available Rx buffer
582  * @write: Shared idx to oldest written Rx packet
583  * @free_count: Number of pre-allocated buffers in rx_free
584  * @rx_free: list of free SKBs for use
585  * @rx_used: List of Rx buffers with no SKB
586  * @need_update: flag to indicate we need to update read/write idx
587  * @rb_stts: driver's pointer to receive buffer status
588  * @rb_stts_dma: bus address of receive buffer status
589  *
590  * NOTE:  rx_free and rx_used are used as a FIFO for il_rx_bufs
591  */
592 struct il_rx_queue {
593 	__le32 *bd;
594 	dma_addr_t bd_dma;
595 	struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
596 	struct il_rx_buf *queue[RX_QUEUE_SIZE];
597 	u32 read;
598 	u32 write;
599 	u32 free_count;
600 	u32 write_actual;
601 	struct list_head rx_free;
602 	struct list_head rx_used;
603 	int need_update;
604 	struct il_rb_status *rb_stts;
605 	dma_addr_t rb_stts_dma;
606 	spinlock_t lock;
607 };
608 
609 #define IL_SUPPORTED_RATES_IE_LEN         8
610 
611 #define MAX_TID_COUNT        9
612 
613 #define IL_INVALID_RATE     0xFF
614 #define IL_INVALID_VALUE    -1
615 
616 /**
617  * struct il_ht_agg -- aggregation status while waiting for block-ack
618  * @txq_id: Tx queue used for Tx attempt
619  * @frame_count: # frames attempted by Tx command
620  * @wait_for_ba: Expect block-ack before next Tx reply
621  * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win
622  * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win
623  * @bitmap1: High order, one bit for each frame pending ACK in Tx win
624  * @rate_n_flags: Rate at which Tx was attempted
625  *
626  * If C_TX indicates that aggregation was attempted, driver must wait
627  * for block ack (N_COMPRESSED_BA).  This struct stores tx reply info
628  * until block ack arrives.
629  */
630 struct il_ht_agg {
631 	u16 txq_id;
632 	u16 frame_count;
633 	u16 wait_for_ba;
634 	u16 start_idx;
635 	u64 bitmap;
636 	u32 rate_n_flags;
637 #define IL_AGG_OFF 0
638 #define IL_AGG_ON 1
639 #define IL_EMPTYING_HW_QUEUE_ADDBA 2
640 #define IL_EMPTYING_HW_QUEUE_DELBA 3
641 	u8 state;
642 };
643 
644 struct il_tid_data {
645 	u16 seq_number;		/* 4965 only */
646 	u16 tfds_in_queue;
647 	struct il_ht_agg agg;
648 };
649 
650 struct il_hw_key {
651 	u32 cipher;
652 	int keylen;
653 	u8 keyidx;
654 	u8 key[32];
655 };
656 
657 union il_ht_rate_supp {
658 	u16 rates;
659 	struct {
660 		u8 siso_rate;
661 		u8 mimo_rate;
662 	};
663 };
664 
665 #define CFG_HT_RX_AMPDU_FACTOR_8K   (0x0)
666 #define CFG_HT_RX_AMPDU_FACTOR_16K  (0x1)
667 #define CFG_HT_RX_AMPDU_FACTOR_32K  (0x2)
668 #define CFG_HT_RX_AMPDU_FACTOR_64K  (0x3)
669 #define CFG_HT_RX_AMPDU_FACTOR_DEF  CFG_HT_RX_AMPDU_FACTOR_64K
670 #define CFG_HT_RX_AMPDU_FACTOR_MAX  CFG_HT_RX_AMPDU_FACTOR_64K
671 #define CFG_HT_RX_AMPDU_FACTOR_MIN  CFG_HT_RX_AMPDU_FACTOR_8K
672 
673 /*
674  * Maximal MPDU density for TX aggregation
675  * 4 - 2us density
676  * 5 - 4us density
677  * 6 - 8us density
678  * 7 - 16us density
679  */
680 #define CFG_HT_MPDU_DENSITY_2USEC   (0x4)
681 #define CFG_HT_MPDU_DENSITY_4USEC   (0x5)
682 #define CFG_HT_MPDU_DENSITY_8USEC   (0x6)
683 #define CFG_HT_MPDU_DENSITY_16USEC  (0x7)
684 #define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
685 #define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
686 #define CFG_HT_MPDU_DENSITY_MIN     (0x1)
687 
688 struct il_ht_config {
689 	bool single_chain_sufficient;
690 	enum ieee80211_smps_mode smps;	/* current smps mode */
691 };
692 
693 /* QoS structures */
694 struct il_qos_info {
695 	int qos_active;
696 	struct il_qosparam_cmd def_qos_parm;
697 };
698 
699 /*
700  * Structure should be accessed with sta_lock held. When station addition
701  * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only
702  * the commands (il_addsta_cmd and il_link_quality_cmd) without
703  * sta_lock held.
704  */
705 struct il_station_entry {
706 	struct il_addsta_cmd sta;
707 	struct il_tid_data tid[MAX_TID_COUNT];
708 	u8 used;
709 	struct il_hw_key keyinfo;
710 	struct il_link_quality_cmd *lq;
711 };
712 
713 struct il_station_priv_common {
714 	u8 sta_id;
715 };
716 
717 /**
718  * struct il_vif_priv - driver's ilate per-interface information
719  *
720  * When mac80211 allocates a virtual interface, it can allocate
721  * space for us to put data into.
722  */
723 struct il_vif_priv {
724 	u8 ibss_bssid_sta_id;
725 };
726 
727 /* one for each uCode image (inst/data, boot/init/runtime) */
728 struct fw_desc {
729 	void *v_addr;		/* access by driver */
730 	dma_addr_t p_addr;	/* access by card's busmaster DMA */
731 	u32 len;		/* bytes */
732 };
733 
734 /* uCode file layout */
735 struct il_ucode_header {
736 	__le32 ver;		/* major/minor/API/serial */
737 	struct {
738 		__le32 inst_size;	/* bytes of runtime code */
739 		__le32 data_size;	/* bytes of runtime data */
740 		__le32 init_size;	/* bytes of init code */
741 		__le32 init_data_size;	/* bytes of init data */
742 		__le32 boot_size;	/* bytes of bootstrap code */
743 		u8 data[0];	/* in same order as sizes */
744 	} v1;
745 };
746 
747 struct il4965_ibss_seq {
748 	u8 mac[ETH_ALEN];
749 	u16 seq_num;
750 	u16 frag_num;
751 	unsigned long packet_time;
752 	struct list_head list;
753 };
754 
755 struct il_sensitivity_ranges {
756 	u16 min_nrg_cck;
757 	u16 max_nrg_cck;
758 
759 	u16 nrg_th_cck;
760 	u16 nrg_th_ofdm;
761 
762 	u16 auto_corr_min_ofdm;
763 	u16 auto_corr_min_ofdm_mrc;
764 	u16 auto_corr_min_ofdm_x1;
765 	u16 auto_corr_min_ofdm_mrc_x1;
766 
767 	u16 auto_corr_max_ofdm;
768 	u16 auto_corr_max_ofdm_mrc;
769 	u16 auto_corr_max_ofdm_x1;
770 	u16 auto_corr_max_ofdm_mrc_x1;
771 
772 	u16 auto_corr_max_cck;
773 	u16 auto_corr_max_cck_mrc;
774 	u16 auto_corr_min_cck;
775 	u16 auto_corr_min_cck_mrc;
776 
777 	u16 barker_corr_th_min;
778 	u16 barker_corr_th_min_mrc;
779 	u16 nrg_th_cca;
780 };
781 
782 /**
783  * struct il_hw_params
784  * @bcast_id: f/w broadcast station ID
785  * @max_txq_num: Max # Tx queues supported
786  * @dma_chnl_num: Number of Tx DMA/FIFO channels
787  * @scd_bc_tbls_size: size of scheduler byte count tables
788  * @tfd_size: TFD size
789  * @tx/rx_chains_num: Number of TX/RX chains
790  * @valid_tx/rx_ant: usable antennas
791  * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
792  * @max_rxq_log: Log-base-2 of max_rxq_size
793  * @rx_page_order: Rx buffer page order
794  * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
795  * @max_stations:
796  * @ht40_channel: is 40MHz width possible in band 2.4
797  * BIT(NL80211_BAND_5GHZ) BIT(NL80211_BAND_5GHZ)
798  * @sw_crypto: 0 for hw, 1 for sw
799  * @max_xxx_size: for ucode uses
800  * @ct_kill_threshold: temperature threshold
801  * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
802  * @struct il_sensitivity_ranges: range of sensitivity values
803  */
804 struct il_hw_params {
805 	u8 bcast_id;
806 	u8 max_txq_num;
807 	u8 dma_chnl_num;
808 	u16 scd_bc_tbls_size;
809 	u32 tfd_size;
810 	u8 tx_chains_num;
811 	u8 rx_chains_num;
812 	u8 valid_tx_ant;
813 	u8 valid_rx_ant;
814 	u16 max_rxq_size;
815 	u16 max_rxq_log;
816 	u32 rx_page_order;
817 	u32 rx_wrt_ptr_reg;
818 	u8 max_stations;
819 	u8 ht40_channel;
820 	u8 max_beacon_itrvl;	/* in 1024 ms */
821 	u32 max_inst_size;
822 	u32 max_data_size;
823 	u32 max_bsm_size;
824 	u32 ct_kill_threshold;	/* value in hw-dependent units */
825 	u16 beacon_time_tsf_bits;
826 	const struct il_sensitivity_ranges *sens;
827 };
828 
829 /******************************************************************************
830  *
831  * Functions implemented in core module which are forward declared here
832  * for use by iwl-[4-5].c
833  *
834  * NOTE:  The implementation of these functions are not hardware specific
835  * which is why they are in the core module files.
836  *
837  * Naming convention --
838  * il_         <-- Is part of iwlwifi
839  * iwlXXXX_     <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
840  * il4965_bg_      <-- Called from work queue context
841  * il4965_mac_     <-- mac80211 callback
842  *
843  ****************************************************************************/
844 void il4965_update_chain_flags(struct il_priv *il);
845 extern const u8 il_bcast_addr[ETH_ALEN];
846 int il_queue_space(const struct il_queue *q);
847 static inline int
848 il_queue_used(const struct il_queue *q, int i)
849 {
850 	return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
851 					      i < q->write_ptr) : !(i <
852 								    q->read_ptr
853 								    && i >=
854 								    q->
855 								    write_ptr);
856 }
857 
858 static inline u8
859 il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
860 {
861 	/*
862 	 * This is for init calibration result and scan command which
863 	 * required buffer > TFD_MAX_PAYLOAD_SIZE,
864 	 * the big buffer at end of command array
865 	 */
866 	if (is_huge)
867 		return q->n_win;	/* must be power of 2 */
868 
869 	/* Otherwise, use normal size buffers */
870 	return idx & (q->n_win - 1);
871 }
872 
873 struct il_dma_ptr {
874 	dma_addr_t dma;
875 	void *addr;
876 	size_t size;
877 };
878 
879 #define IL_OPERATION_MODE_AUTO     0
880 #define IL_OPERATION_MODE_HT_ONLY  1
881 #define IL_OPERATION_MODE_MIXED    2
882 #define IL_OPERATION_MODE_20MHZ    3
883 
884 #define IL_TX_CRC_SIZE 4
885 #define IL_TX_DELIMITER_SIZE 4
886 
887 #define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
888 
889 /* Sensitivity and chain noise calibration */
890 #define INITIALIZATION_VALUE		0xFFFF
891 #define IL4965_CAL_NUM_BEACONS		20
892 #define IL_CAL_NUM_BEACONS		16
893 #define MAXIMUM_ALLOWED_PATHLOSS	15
894 
895 #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
896 
897 #define MAX_FA_OFDM  50
898 #define MIN_FA_OFDM  5
899 #define MAX_FA_CCK   50
900 #define MIN_FA_CCK   5
901 
902 #define AUTO_CORR_STEP_OFDM       1
903 
904 #define AUTO_CORR_STEP_CCK     3
905 #define AUTO_CORR_MAX_TH_CCK   160
906 
907 #define NRG_DIFF               2
908 #define NRG_STEP_CCK           2
909 #define NRG_MARGIN             8
910 #define MAX_NUMBER_CCK_NO_FA 100
911 
912 #define AUTO_CORR_CCK_MIN_VAL_DEF    (125)
913 
914 #define CHAIN_A             0
915 #define CHAIN_B             1
916 #define CHAIN_C             2
917 #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
918 #define ALL_BAND_FILTER			0xFF00
919 #define IN_BAND_FILTER			0xFF
920 #define MIN_AVERAGE_NOISE_MAX_VALUE	0xFFFFFFFF
921 
922 #define NRG_NUM_PREV_STAT_L     20
923 #define NUM_RX_CHAINS           3
924 
925 enum il4965_false_alarm_state {
926 	IL_FA_TOO_MANY = 0,
927 	IL_FA_TOO_FEW = 1,
928 	IL_FA_GOOD_RANGE = 2,
929 };
930 
931 enum il4965_chain_noise_state {
932 	IL_CHAIN_NOISE_ALIVE = 0,	/* must be 0 */
933 	IL_CHAIN_NOISE_ACCUMULATE,
934 	IL_CHAIN_NOISE_CALIBRATED,
935 	IL_CHAIN_NOISE_DONE,
936 };
937 
938 enum ucode_type {
939 	UCODE_NONE = 0,
940 	UCODE_INIT,
941 	UCODE_RT
942 };
943 
944 /* Sensitivity calib data */
945 struct il_sensitivity_data {
946 	u32 auto_corr_ofdm;
947 	u32 auto_corr_ofdm_mrc;
948 	u32 auto_corr_ofdm_x1;
949 	u32 auto_corr_ofdm_mrc_x1;
950 	u32 auto_corr_cck;
951 	u32 auto_corr_cck_mrc;
952 
953 	u32 last_bad_plcp_cnt_ofdm;
954 	u32 last_fa_cnt_ofdm;
955 	u32 last_bad_plcp_cnt_cck;
956 	u32 last_fa_cnt_cck;
957 
958 	u32 nrg_curr_state;
959 	u32 nrg_prev_state;
960 	u32 nrg_value[10];
961 	u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
962 	u32 nrg_silence_ref;
963 	u32 nrg_energy_idx;
964 	u32 nrg_silence_idx;
965 	u32 nrg_th_cck;
966 	s32 nrg_auto_corr_silence_diff;
967 	u32 num_in_cck_no_fa;
968 	u32 nrg_th_ofdm;
969 
970 	u16 barker_corr_th_min;
971 	u16 barker_corr_th_min_mrc;
972 	u16 nrg_th_cca;
973 };
974 
975 /* Chain noise (differential Rx gain) calib data */
976 struct il_chain_noise_data {
977 	u32 active_chains;
978 	u32 chain_noise_a;
979 	u32 chain_noise_b;
980 	u32 chain_noise_c;
981 	u32 chain_signal_a;
982 	u32 chain_signal_b;
983 	u32 chain_signal_c;
984 	u16 beacon_count;
985 	u8 disconn_array[NUM_RX_CHAINS];
986 	u8 delta_gain_code[NUM_RX_CHAINS];
987 	u8 radio_write;
988 	u8 state;
989 };
990 
991 #define	EEPROM_SEM_TIMEOUT 10	/* milliseconds */
992 #define EEPROM_SEM_RETRY_LIMIT 1000	/* number of attempts (not time) */
993 
994 #define IL_TRAFFIC_ENTRIES	(256)
995 #define IL_TRAFFIC_ENTRY_SIZE  (64)
996 
997 enum {
998 	MEASUREMENT_READY = (1 << 0),
999 	MEASUREMENT_ACTIVE = (1 << 1),
1000 };
1001 
1002 /* interrupt stats */
1003 struct isr_stats {
1004 	u32 hw;
1005 	u32 sw;
1006 	u32 err_code;
1007 	u32 sch;
1008 	u32 alive;
1009 	u32 rfkill;
1010 	u32 ctkill;
1011 	u32 wakeup;
1012 	u32 rx;
1013 	u32 handlers[IL_CN_MAX];
1014 	u32 tx;
1015 	u32 unhandled;
1016 };
1017 
1018 /* management stats */
1019 enum il_mgmt_stats {
1020 	MANAGEMENT_ASSOC_REQ = 0,
1021 	MANAGEMENT_ASSOC_RESP,
1022 	MANAGEMENT_REASSOC_REQ,
1023 	MANAGEMENT_REASSOC_RESP,
1024 	MANAGEMENT_PROBE_REQ,
1025 	MANAGEMENT_PROBE_RESP,
1026 	MANAGEMENT_BEACON,
1027 	MANAGEMENT_ATIM,
1028 	MANAGEMENT_DISASSOC,
1029 	MANAGEMENT_AUTH,
1030 	MANAGEMENT_DEAUTH,
1031 	MANAGEMENT_ACTION,
1032 	MANAGEMENT_MAX,
1033 };
1034 /* control stats */
1035 enum il_ctrl_stats {
1036 	CONTROL_BACK_REQ = 0,
1037 	CONTROL_BACK,
1038 	CONTROL_PSPOLL,
1039 	CONTROL_RTS,
1040 	CONTROL_CTS,
1041 	CONTROL_ACK,
1042 	CONTROL_CFEND,
1043 	CONTROL_CFENDACK,
1044 	CONTROL_MAX,
1045 };
1046 
1047 struct traffic_stats {
1048 #ifdef CONFIG_IWLEGACY_DEBUGFS
1049 	u32 mgmt[MANAGEMENT_MAX];
1050 	u32 ctrl[CONTROL_MAX];
1051 	u32 data_cnt;
1052 	u64 data_bytes;
1053 #endif
1054 };
1055 
1056 /*
1057  * host interrupt timeout value
1058  * used with setting interrupt coalescing timer
1059  * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1060  *
1061  * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1062  * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1063  */
1064 #define IL_HOST_INT_TIMEOUT_MAX	(0xFF)
1065 #define IL_HOST_INT_TIMEOUT_DEF	(0x40)
1066 #define IL_HOST_INT_TIMEOUT_MIN	(0x0)
1067 #define IL_HOST_INT_CALIB_TIMEOUT_MAX	(0xFF)
1068 #define IL_HOST_INT_CALIB_TIMEOUT_DEF	(0x10)
1069 #define IL_HOST_INT_CALIB_TIMEOUT_MIN	(0x0)
1070 
1071 #define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1072 
1073 /* TX queue watchdog timeouts in mSecs */
1074 #define IL_DEF_WD_TIMEOUT	(2000)
1075 #define IL_LONG_WD_TIMEOUT	(10000)
1076 #define IL_MAX_WD_TIMEOUT	(120000)
1077 
1078 struct il_force_reset {
1079 	int reset_request_count;
1080 	int reset_success_count;
1081 	int reset_reject_count;
1082 	unsigned long reset_duration;
1083 	unsigned long last_force_reset_jiffies;
1084 };
1085 
1086 /* extend beacon time format bit shifting  */
1087 /*
1088  * for _3945 devices
1089  * bits 31:24 - extended
1090  * bits 23:0  - interval
1091  */
1092 #define IL3945_EXT_BEACON_TIME_POS	24
1093 /*
1094  * for _4965 devices
1095  * bits 31:22 - extended
1096  * bits 21:0  - interval
1097  */
1098 #define IL4965_EXT_BEACON_TIME_POS	22
1099 
1100 struct il_rxon_context {
1101 	struct ieee80211_vif *vif;
1102 };
1103 
1104 struct il_power_mgr {
1105 	struct il_powertable_cmd sleep_cmd;
1106 	struct il_powertable_cmd sleep_cmd_next;
1107 	int debug_sleep_level_override;
1108 	bool pci_pm;
1109 	bool ps_disabled;
1110 };
1111 
1112 struct il_priv {
1113 	struct ieee80211_hw *hw;
1114 	struct ieee80211_channel *ieee_channels;
1115 	struct ieee80211_rate *ieee_rates;
1116 
1117 	struct il_cfg *cfg;
1118 	const struct il_ops *ops;
1119 #ifdef CONFIG_IWLEGACY_DEBUGFS
1120 	const struct il_debugfs_ops *debugfs_ops;
1121 #endif
1122 
1123 	/* temporary frame storage list */
1124 	struct list_head free_frames;
1125 	int frames_count;
1126 
1127 	enum nl80211_band band;
1128 	int alloc_rxb_page;
1129 
1130 	void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1131 				     struct il_rx_buf *rxb);
1132 
1133 	struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1134 
1135 	/* spectrum measurement report caching */
1136 	struct il_spectrum_notification measure_report;
1137 	u8 measurement_status;
1138 
1139 	/* ucode beacon time */
1140 	u32 ucode_beacon_time;
1141 	int missed_beacon_threshold;
1142 
1143 	/* track IBSS manager (last beacon) status */
1144 	u32 ibss_manager;
1145 
1146 	/* force reset */
1147 	struct il_force_reset force_reset;
1148 
1149 	/* we allocate array of il_channel_info for NIC's valid channels.
1150 	 *    Access via channel # using indirect idx array */
1151 	struct il_channel_info *channel_info;	/* channel info array */
1152 	u8 channel_count;	/* # of channels */
1153 
1154 	/* thermal calibration */
1155 	s32 temperature;	/* degrees Kelvin */
1156 	s32 last_temperature;
1157 
1158 	/* Scan related variables */
1159 	unsigned long scan_start;
1160 	unsigned long scan_start_tsf;
1161 	void *scan_cmd;
1162 	enum nl80211_band scan_band;
1163 	struct cfg80211_scan_request *scan_request;
1164 	struct ieee80211_vif *scan_vif;
1165 	u8 scan_tx_ant[NUM_NL80211_BANDS];
1166 	u8 mgmt_tx_ant;
1167 
1168 	/* spinlock */
1169 	spinlock_t lock;	/* protect general shared data */
1170 	spinlock_t hcmd_lock;	/* protect hcmd */
1171 	spinlock_t reg_lock;	/* protect hw register access */
1172 	struct mutex mutex;
1173 
1174 	/* basic pci-network driver stuff */
1175 	struct pci_dev *pci_dev;
1176 
1177 	/* pci hardware address support */
1178 	void __iomem *hw_base;
1179 	u32 hw_rev;
1180 	u32 hw_wa_rev;
1181 	u8 rev_id;
1182 
1183 	/* command queue number */
1184 	u8 cmd_queue;
1185 
1186 	/* max number of station keys */
1187 	u8 sta_key_max_num;
1188 
1189 	/* EEPROM MAC addresses */
1190 	struct mac_address addresses[1];
1191 
1192 	/* uCode images, save to reload in case of failure */
1193 	int fw_idx;		/* firmware we're trying to load */
1194 	u32 ucode_ver;		/* version of ucode, copy of
1195 				   il_ucode.ver */
1196 	struct fw_desc ucode_code;	/* runtime inst */
1197 	struct fw_desc ucode_data;	/* runtime data original */
1198 	struct fw_desc ucode_data_backup;	/* runtime data save/restore */
1199 	struct fw_desc ucode_init;	/* initialization inst */
1200 	struct fw_desc ucode_init_data;	/* initialization data */
1201 	struct fw_desc ucode_boot;	/* bootstrap inst */
1202 	enum ucode_type ucode_type;
1203 	u8 ucode_write_complete;	/* the image write is complete */
1204 	char firmware_name[25];
1205 
1206 	struct ieee80211_vif *vif;
1207 
1208 	struct il_qos_info qos_data;
1209 
1210 	struct {
1211 		bool enabled;
1212 		bool is_40mhz;
1213 		bool non_gf_sta_present;
1214 		u8 protection;
1215 		u8 extension_chan_offset;
1216 	} ht;
1217 
1218 	/*
1219 	 * We declare this const so it can only be
1220 	 * changed via explicit cast within the
1221 	 * routines that actually update the physical
1222 	 * hardware.
1223 	 */
1224 	const struct il_rxon_cmd active;
1225 	struct il_rxon_cmd staging;
1226 
1227 	struct il_rxon_time_cmd timing;
1228 
1229 	__le16 switch_channel;
1230 
1231 	/* 1st responses from initialize and runtime uCode images.
1232 	 * _4965's initialize alive response contains some calibration data. */
1233 	struct il_init_alive_resp card_alive_init;
1234 	struct il_alive_resp card_alive;
1235 
1236 	u16 active_rate;
1237 
1238 	u8 start_calib;
1239 	struct il_sensitivity_data sensitivity_data;
1240 	struct il_chain_noise_data chain_noise_data;
1241 	__le16 sensitivity_tbl[HD_TBL_SIZE];
1242 
1243 	struct il_ht_config current_ht_config;
1244 
1245 	/* Rate scaling data */
1246 	u8 retry_rate;
1247 
1248 	wait_queue_head_t wait_command_queue;
1249 
1250 	int activity_timer_active;
1251 
1252 	/* Rx and Tx DMA processing queues */
1253 	struct il_rx_queue rxq;
1254 	struct il_tx_queue *txq;
1255 	unsigned long txq_ctx_active_msk;
1256 	struct il_dma_ptr kw;	/* keep warm address */
1257 	struct il_dma_ptr scd_bc_tbls;
1258 
1259 	u32 scd_base_addr;	/* scheduler sram base address */
1260 
1261 	unsigned long status;
1262 
1263 	/* counts mgmt, ctl, and data packets */
1264 	struct traffic_stats tx_stats;
1265 	struct traffic_stats rx_stats;
1266 
1267 	/* counts interrupts */
1268 	struct isr_stats isr_stats;
1269 
1270 	struct il_power_mgr power_data;
1271 
1272 	/* context information */
1273 	u8 bssid[ETH_ALEN];	/* used only on 3945 but filled by core */
1274 
1275 	/* station table variables */
1276 
1277 	/* Note: if lock and sta_lock are needed, lock must be acquired first */
1278 	spinlock_t sta_lock;
1279 	int num_stations;
1280 	struct il_station_entry stations[IL_STATION_COUNT];
1281 	unsigned long ucode_key_table;
1282 
1283 	/* queue refcounts */
1284 #define IL_MAX_HW_QUEUES	32
1285 	unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1286 #define IL_STOP_REASON_PASSIVE	0
1287 	unsigned long stop_reason;
1288 	/* for each AC */
1289 	atomic_t queue_stop_count[4];
1290 
1291 	/* Indication if ieee80211_ops->open has been called */
1292 	u8 is_open;
1293 
1294 	u8 mac80211_registered;
1295 
1296 	/* eeprom -- this is in the card's little endian byte order */
1297 	u8 *eeprom;
1298 	struct il_eeprom_calib_info *calib_info;
1299 
1300 	enum nl80211_iftype iw_mode;
1301 
1302 	/* Last Rx'd beacon timestamp */
1303 	u64 timestamp;
1304 
1305 	union {
1306 #if IS_ENABLED(CONFIG_IWL3945)
1307 		struct {
1308 			void *shared_virt;
1309 			dma_addr_t shared_phys;
1310 
1311 			struct delayed_work thermal_periodic;
1312 			struct delayed_work rfkill_poll;
1313 
1314 			struct il3945_notif_stats stats;
1315 #ifdef CONFIG_IWLEGACY_DEBUGFS
1316 			struct il3945_notif_stats accum_stats;
1317 			struct il3945_notif_stats delta_stats;
1318 			struct il3945_notif_stats max_delta;
1319 #endif
1320 
1321 			u32 sta_supp_rates;
1322 			int last_rx_rssi;	/* From Rx packet stats */
1323 
1324 			/* Rx'd packet timing information */
1325 			u32 last_beacon_time;
1326 			u64 last_tsf;
1327 
1328 			/*
1329 			 * each calibration channel group in the
1330 			 * EEPROM has a derived clip setting for
1331 			 * each rate.
1332 			 */
1333 			const struct il3945_clip_group clip_groups[5];
1334 
1335 		} _3945;
1336 #endif
1337 #if IS_ENABLED(CONFIG_IWL4965)
1338 		struct {
1339 			struct il_rx_phy_res last_phy_res;
1340 			bool last_phy_res_valid;
1341 			u32 ampdu_ref;
1342 
1343 			struct completion firmware_loading_complete;
1344 
1345 			/*
1346 			 * chain noise reset and gain commands are the
1347 			 * two extra calibration commands follows the standard
1348 			 * phy calibration commands
1349 			 */
1350 			u8 phy_calib_chain_noise_reset_cmd;
1351 			u8 phy_calib_chain_noise_gain_cmd;
1352 
1353 			u8 key_mapping_keys;
1354 			struct il_wep_key wep_keys[WEP_KEYS_MAX];
1355 
1356 			struct il_notif_stats stats;
1357 #ifdef CONFIG_IWLEGACY_DEBUGFS
1358 			struct il_notif_stats accum_stats;
1359 			struct il_notif_stats delta_stats;
1360 			struct il_notif_stats max_delta;
1361 #endif
1362 
1363 		} _4965;
1364 #endif
1365 	};
1366 
1367 	struct il_hw_params hw_params;
1368 
1369 	u32 inta_mask;
1370 
1371 	struct workqueue_struct *workqueue;
1372 
1373 	struct work_struct restart;
1374 	struct work_struct scan_completed;
1375 	struct work_struct rx_replenish;
1376 	struct work_struct abort_scan;
1377 
1378 	bool beacon_enabled;
1379 	struct sk_buff *beacon_skb;
1380 
1381 	struct work_struct tx_flush;
1382 
1383 	struct tasklet_struct irq_tasklet;
1384 
1385 	struct delayed_work init_alive_start;
1386 	struct delayed_work alive_start;
1387 	struct delayed_work scan_check;
1388 
1389 	/* TX Power */
1390 	s8 tx_power_user_lmt;
1391 	s8 tx_power_device_lmt;
1392 	s8 tx_power_next;
1393 
1394 #ifdef CONFIG_IWLEGACY_DEBUG
1395 	/* debugging info */
1396 	u32 debug_level;	/* per device debugging will override global
1397 				   il_debug_level if set */
1398 #endif				/* CONFIG_IWLEGACY_DEBUG */
1399 #ifdef CONFIG_IWLEGACY_DEBUGFS
1400 	/* debugfs */
1401 	u16 tx_traffic_idx;
1402 	u16 rx_traffic_idx;
1403 	u8 *tx_traffic;
1404 	u8 *rx_traffic;
1405 	struct dentry *debugfs_dir;
1406 	u32 dbgfs_sram_offset, dbgfs_sram_len;
1407 	bool disable_ht40;
1408 #endif				/* CONFIG_IWLEGACY_DEBUGFS */
1409 
1410 	struct work_struct txpower_work;
1411 	bool disable_sens_cal;
1412 	bool disable_chain_noise_cal;
1413 	bool disable_tx_power_cal;
1414 	struct work_struct run_time_calib_work;
1415 	struct timer_list stats_periodic;
1416 	struct timer_list watchdog;
1417 	bool hw_ready;
1418 
1419 	struct led_classdev led;
1420 	unsigned long blink_on, blink_off;
1421 	bool led_registered;
1422 };				/*il_priv */
1423 
1424 static inline void
1425 il_txq_ctx_activate(struct il_priv *il, int txq_id)
1426 {
1427 	set_bit(txq_id, &il->txq_ctx_active_msk);
1428 }
1429 
1430 static inline void
1431 il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
1432 {
1433 	clear_bit(txq_id, &il->txq_ctx_active_msk);
1434 }
1435 
1436 static inline int
1437 il_is_associated(struct il_priv *il)
1438 {
1439 	return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1440 }
1441 
1442 static inline int
1443 il_is_any_associated(struct il_priv *il)
1444 {
1445 	return il_is_associated(il);
1446 }
1447 
1448 static inline int
1449 il_is_channel_valid(const struct il_channel_info *ch_info)
1450 {
1451 	if (ch_info == NULL)
1452 		return 0;
1453 	return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1454 }
1455 
1456 static inline int
1457 il_is_channel_radar(const struct il_channel_info *ch_info)
1458 {
1459 	return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1460 }
1461 
1462 static inline u8
1463 il_is_channel_a_band(const struct il_channel_info *ch_info)
1464 {
1465 	return ch_info->band == NL80211_BAND_5GHZ;
1466 }
1467 
1468 static inline int
1469 il_is_channel_passive(const struct il_channel_info *ch)
1470 {
1471 	return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1472 }
1473 
1474 static inline int
1475 il_is_channel_ibss(const struct il_channel_info *ch)
1476 {
1477 	return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1478 }
1479 
1480 static inline void
1481 __il_free_pages(struct il_priv *il, struct page *page)
1482 {
1483 	__free_pages(page, il->hw_params.rx_page_order);
1484 	il->alloc_rxb_page--;
1485 }
1486 
1487 static inline void
1488 il_free_pages(struct il_priv *il, unsigned long page)
1489 {
1490 	free_pages(page, il->hw_params.rx_page_order);
1491 	il->alloc_rxb_page--;
1492 }
1493 
1494 #define IWLWIFI_VERSION "in-tree:"
1495 #define DRV_COPYRIGHT	"Copyright(c) 2003-2011 Intel Corporation"
1496 #define DRV_AUTHOR     "<ilw@linux.intel.com>"
1497 
1498 #define IL_PCI_DEVICE(dev, subdev, cfg) \
1499 	.vendor = PCI_VENDOR_ID_INTEL,  .device = (dev), \
1500 	.subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1501 	.driver_data = (kernel_ulong_t)&(cfg)
1502 
1503 #define TIME_UNIT		1024
1504 
1505 #define IL_SKU_G       0x1
1506 #define IL_SKU_A       0x2
1507 #define IL_SKU_N       0x8
1508 
1509 #define IL_CMD(x) case x: return #x
1510 
1511 /* Size of one Rx buffer in host DRAM */
1512 #define IL_RX_BUF_SIZE_3K (3 * 1000)	/* 3945 only */
1513 #define IL_RX_BUF_SIZE_4K (4 * 1024)
1514 #define IL_RX_BUF_SIZE_8K (8 * 1024)
1515 
1516 #ifdef CONFIG_IWLEGACY_DEBUGFS
1517 struct il_debugfs_ops {
1518 	ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1519 				 size_t count, loff_t *ppos);
1520 	ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1521 				 size_t count, loff_t *ppos);
1522 	ssize_t(*general_stats_read) (struct file *file,
1523 				      char __user *user_buf, size_t count,
1524 				      loff_t *ppos);
1525 };
1526 #endif
1527 
1528 struct il_ops {
1529 	/* Handling TX */
1530 	void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1531 					 struct il_tx_queue *txq,
1532 					 u16 byte_cnt);
1533 	int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1534 				      struct il_tx_queue *txq, dma_addr_t addr,
1535 				      u16 len, u8 reset, u8 pad);
1536 	void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1537 	int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
1538 	/* alive notification after init uCode load */
1539 	void (*init_alive_start) (struct il_priv *il);
1540 	/* check validity of rtc data address */
1541 	int (*is_valid_rtc_data_addr) (u32 addr);
1542 	/* 1st ucode load */
1543 	int (*load_ucode) (struct il_priv *il);
1544 
1545 	void (*dump_nic_error_log) (struct il_priv *il);
1546 	int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1547 	int (*set_channel_switch) (struct il_priv *il,
1548 				   struct ieee80211_channel_switch *ch_switch);
1549 	/* power management */
1550 	int (*apm_init) (struct il_priv *il);
1551 
1552 	/* tx power */
1553 	int (*send_tx_power) (struct il_priv *il);
1554 	void (*update_chain_flags) (struct il_priv *il);
1555 
1556 	/* eeprom operations */
1557 	int (*eeprom_acquire_semaphore) (struct il_priv *il);
1558 	void (*eeprom_release_semaphore) (struct il_priv *il);
1559 
1560 	int (*rxon_assoc) (struct il_priv *il);
1561 	int (*commit_rxon) (struct il_priv *il);
1562 	void (*set_rxon_chain) (struct il_priv *il);
1563 
1564 	u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1565 	u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1566 
1567 	int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1568 	void (*post_scan) (struct il_priv *il);
1569 	void (*post_associate) (struct il_priv *il);
1570 	void (*config_ap) (struct il_priv *il);
1571 	/* station management */
1572 	int (*update_bcast_stations) (struct il_priv *il);
1573 	int (*manage_ibss_station) (struct il_priv *il,
1574 				    struct ieee80211_vif *vif, bool add);
1575 
1576 	int (*send_led_cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
1577 };
1578 
1579 struct il_mod_params {
1580 	int sw_crypto;		/* def: 0 = using hardware encryption */
1581 	int disable_hw_scan;	/* def: 0 = use h/w scan */
1582 	int num_of_queues;	/* def: HW dependent */
1583 	int disable_11n;	/* def: 0 = 11n capabilities enabled */
1584 	int amsdu_size_8K;	/* def: 0 = disable 8K amsdu size */
1585 	int antenna;		/* def: 0 = both antennas (use diversity) */
1586 	int restart_fw;		/* def: 1 = restart firmware */
1587 };
1588 
1589 #define IL_LED_SOLID 11
1590 #define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1591 
1592 #define IL_LED_ACTIVITY       (0<<1)
1593 #define IL_LED_LINK           (1<<1)
1594 
1595 /*
1596  * LED mode
1597  *    IL_LED_DEFAULT:  use device default
1598  *    IL_LED_RF_STATE: turn LED on/off based on RF state
1599  *			LED ON  = RF ON
1600  *			LED OFF = RF OFF
1601  *    IL_LED_BLINK:    adjust led blink rate based on blink table
1602  */
1603 enum il_led_mode {
1604 	IL_LED_DEFAULT,
1605 	IL_LED_RF_STATE,
1606 	IL_LED_BLINK,
1607 };
1608 
1609 void il_leds_init(struct il_priv *il);
1610 void il_leds_exit(struct il_priv *il);
1611 
1612 /**
1613  * struct il_cfg
1614  * @fw_name_pre: Firmware filename prefix. The api version and extension
1615  *	(.ucode) will be added to filename before loading from disk. The
1616  *	filename is constructed as fw_name_pre<api>.ucode.
1617  * @ucode_api_max: Highest version of uCode API supported by driver.
1618  * @ucode_api_min: Lowest version of uCode API supported by driver.
1619  * @scan_antennas: available antenna for scan operation
1620  * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
1621  *
1622  * We enable the driver to be backward compatible wrt API version. The
1623  * driver specifies which APIs it supports (with @ucode_api_max being the
1624  * highest and @ucode_api_min the lowest). Firmware will only be loaded if
1625  * it has a supported API version. The firmware's API version will be
1626  * stored in @il_priv, enabling the driver to make runtime changes based
1627  * on firmware version used.
1628  *
1629  * For example,
1630  * if (IL_UCODE_API(il->ucode_ver) >= 2) {
1631  *	Driver interacts with Firmware API version >= 2.
1632  * } else {
1633  *	Driver interacts with Firmware API version 1.
1634  * }
1635  *
1636  * The ideal usage of this infrastructure is to treat a new ucode API
1637  * release as a new hardware revision. That is, through utilizing the
1638  * il_hcmd_utils_ops etc. we accommodate different command structures
1639  * and flows between hardware versions as well as their API
1640  * versions.
1641  *
1642  */
1643 struct il_cfg {
1644 	/* params specific to an individual device within a device family */
1645 	const char *name;
1646 	const char *fw_name_pre;
1647 	const unsigned int ucode_api_max;
1648 	const unsigned int ucode_api_min;
1649 	u8 valid_tx_ant;
1650 	u8 valid_rx_ant;
1651 	unsigned int sku;
1652 	u16 eeprom_ver;
1653 	u16 eeprom_calib_ver;
1654 	/* module based parameters which can be set from modprobe cmd */
1655 	const struct il_mod_params *mod_params;
1656 	/* params not likely to change within a device family */
1657 	struct il_base_params *base_params;
1658 	/* params likely to change within a device family */
1659 	u8 scan_rx_antennas[NUM_NL80211_BANDS];
1660 	enum il_led_mode led_mode;
1661 
1662 	int eeprom_size;
1663 	int num_of_queues;		/* def: HW dependent */
1664 	int num_of_ampdu_queues;	/* def: HW dependent */
1665 	/* for il_apm_init() */
1666 	u32 pll_cfg_val;
1667 	bool set_l0s;
1668 	bool use_bsm;
1669 
1670 	u16 led_compensation;
1671 	int chain_noise_num_beacons;
1672 	unsigned int wd_timeout;
1673 	bool temperature_kelvin;
1674 	const bool ucode_tracing;
1675 	const bool sensitivity_calib_by_driver;
1676 	const bool chain_noise_calib_by_driver;
1677 
1678 	const u32 regulatory_bands[7];
1679 };
1680 
1681 /***************************
1682  *   L i b                 *
1683  ***************************/
1684 
1685 int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1686 		   u16 queue, const struct ieee80211_tx_queue_params *params);
1687 int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
1688 
1689 void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt);
1690 int il_check_rxon_cmd(struct il_priv *il);
1691 int il_full_rxon_required(struct il_priv *il);
1692 int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch);
1693 void il_set_flags_for_band(struct il_priv *il, enum nl80211_band band,
1694 			   struct ieee80211_vif *vif);
1695 u8 il_get_single_channel_number(struct il_priv *il, enum nl80211_band band);
1696 void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
1697 bool il_is_ht40_tx_allowed(struct il_priv *il,
1698 			   struct ieee80211_sta_ht_cap *ht_cap);
1699 void il_connection_init_rx_config(struct il_priv *il);
1700 void il_set_rate(struct il_priv *il);
1701 int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1702 			  u32 decrypt_res, struct ieee80211_rx_status *stats);
1703 void il_irq_handle_error(struct il_priv *il);
1704 int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1705 void il_mac_remove_interface(struct ieee80211_hw *hw,
1706 			     struct ieee80211_vif *vif);
1707 int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1708 			    enum nl80211_iftype newtype, bool newp2p);
1709 void il_mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1710 		  u32 queues, bool drop);
1711 int il_alloc_txq_mem(struct il_priv *il);
1712 void il_free_txq_mem(struct il_priv *il);
1713 
1714 #ifdef CONFIG_IWLEGACY_DEBUGFS
1715 void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
1716 #else
1717 static inline void
1718 il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
1719 {
1720 }
1721 #endif
1722 
1723 /*****************************************************
1724  * Handlers
1725  ***************************************************/
1726 void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1727 void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1728 void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
1729 void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
1730 
1731 /*****************************************************
1732 * RX
1733 ******************************************************/
1734 void il_cmd_queue_unmap(struct il_priv *il);
1735 void il_cmd_queue_free(struct il_priv *il);
1736 int il_rx_queue_alloc(struct il_priv *il);
1737 void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
1738 int il_rx_queue_space(const struct il_rx_queue *q);
1739 void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
1740 
1741 void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1742 void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
1743 void il_chswitch_done(struct il_priv *il, bool is_success);
1744 
1745 /*****************************************************
1746 * TX
1747 ******************************************************/
1748 void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1749 int il_tx_queue_init(struct il_priv *il, u32 txq_id);
1750 void il_tx_queue_reset(struct il_priv *il, u32 txq_id);
1751 void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1752 void il_tx_queue_free(struct il_priv *il, int txq_id);
1753 void il_setup_watchdog(struct il_priv *il);
1754 /*****************************************************
1755  * TX power
1756  ****************************************************/
1757 int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
1758 
1759 /*******************************************************************************
1760  * Rate
1761  ******************************************************************************/
1762 
1763 u8 il_get_lowest_plcp(struct il_priv *il);
1764 
1765 /*******************************************************************************
1766  * Scanning
1767  ******************************************************************************/
1768 void il_init_scan_params(struct il_priv *il);
1769 int il_scan_cancel(struct il_priv *il);
1770 int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1771 void il_force_scan_end(struct il_priv *il);
1772 int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1773 		   struct ieee80211_scan_request *hw_req);
1774 void il_internal_short_hw_scan(struct il_priv *il);
1775 int il_force_reset(struct il_priv *il, bool external);
1776 u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1777 		      const u8 *ta, const u8 *ie, int ie_len, int left);
1778 void il_setup_rx_scan_handlers(struct il_priv *il);
1779 u16 il_get_active_dwell_time(struct il_priv *il, enum nl80211_band band,
1780 			     u8 n_probes);
1781 u16 il_get_passive_dwell_time(struct il_priv *il, enum nl80211_band band,
1782 			      struct ieee80211_vif *vif);
1783 void il_setup_scan_deferred_work(struct il_priv *il);
1784 void il_cancel_scan_deferred_work(struct il_priv *il);
1785 
1786 /* For faster active scanning, scan will move to the next channel if fewer than
1787  * PLCP_QUIET_THRESH packets are heard on this channel within
1788  * ACTIVE_QUIET_TIME after sending probe request.  This shortens the dwell
1789  * time if it's a quiet channel (nothing responded to our probe, and there's
1790  * no other traffic).
1791  * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
1792 #define IL_ACTIVE_QUIET_TIME       cpu_to_le16(10)	/* msec */
1793 #define IL_PLCP_QUIET_THRESH       cpu_to_le16(1)	/* packets */
1794 
1795 #define IL_SCAN_CHECK_WATCHDOG		(HZ * 7)
1796 
1797 /*****************************************************
1798  *   S e n d i n g     H o s t     C o m m a n d s   *
1799  *****************************************************/
1800 
1801 const char *il_get_cmd_string(u8 cmd);
1802 int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
1803 int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
1804 int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
1805 				 const void *data);
1806 int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1807 			  void (*callback) (struct il_priv *il,
1808 					    struct il_device_cmd *cmd,
1809 					    struct il_rx_pkt *pkt));
1810 
1811 int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
1812 
1813 /*****************************************************
1814  * PCI						     *
1815  *****************************************************/
1816 
1817 void il_bg_watchdog(struct timer_list *t);
1818 u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
1819 __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
1820 			  u32 beacon_interval);
1821 
1822 #ifdef CONFIG_PM_SLEEP
1823 extern const struct dev_pm_ops il_pm_ops;
1824 
1825 #define IL_LEGACY_PM_OPS	(&il_pm_ops)
1826 
1827 #else /* !CONFIG_PM_SLEEP */
1828 
1829 #define IL_LEGACY_PM_OPS	NULL
1830 
1831 #endif /* !CONFIG_PM_SLEEP */
1832 
1833 /*****************************************************
1834 *  Error Handling Debugging
1835 ******************************************************/
1836 void il4965_dump_nic_error_log(struct il_priv *il);
1837 #ifdef CONFIG_IWLEGACY_DEBUG
1838 void il_print_rx_config_cmd(struct il_priv *il);
1839 #else
1840 static inline void
1841 il_print_rx_config_cmd(struct il_priv *il)
1842 {
1843 }
1844 #endif
1845 
1846 void il_clear_isr_stats(struct il_priv *il);
1847 
1848 /*****************************************************
1849 *  GEOS
1850 ******************************************************/
1851 int il_init_geos(struct il_priv *il);
1852 void il_free_geos(struct il_priv *il);
1853 
1854 /*************** DRIVER STATUS FUNCTIONS   *****/
1855 
1856 #define S_HCMD_ACTIVE	0	/* host command in progress */
1857 /* 1 is unused (used to be S_HCMD_SYNC_ACTIVE) */
1858 #define S_INT_ENABLED	2
1859 #define S_RFKILL	3
1860 #define S_CT_KILL		4
1861 #define S_INIT		5
1862 #define S_ALIVE		6
1863 #define S_READY		7
1864 #define S_TEMPERATURE	8
1865 #define S_GEO_CONFIGURED	9
1866 #define S_EXIT_PENDING	10
1867 #define S_STATS		12
1868 #define S_SCANNING		13
1869 #define S_SCAN_ABORTING	14
1870 #define S_SCAN_HW		15
1871 #define S_POWER_PMI	16
1872 #define S_FW_ERROR		17
1873 #define S_CHANNEL_SWITCH_PENDING 18
1874 
1875 static inline int
1876 il_is_ready(struct il_priv *il)
1877 {
1878 	/* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
1879 	 * set but EXIT_PENDING is not */
1880 	return test_bit(S_READY, &il->status) &&
1881 	    test_bit(S_GEO_CONFIGURED, &il->status) &&
1882 	    !test_bit(S_EXIT_PENDING, &il->status);
1883 }
1884 
1885 static inline int
1886 il_is_alive(struct il_priv *il)
1887 {
1888 	return test_bit(S_ALIVE, &il->status);
1889 }
1890 
1891 static inline int
1892 il_is_init(struct il_priv *il)
1893 {
1894 	return test_bit(S_INIT, &il->status);
1895 }
1896 
1897 static inline int
1898 il_is_rfkill(struct il_priv *il)
1899 {
1900 	return test_bit(S_RFKILL, &il->status);
1901 }
1902 
1903 static inline int
1904 il_is_ctkill(struct il_priv *il)
1905 {
1906 	return test_bit(S_CT_KILL, &il->status);
1907 }
1908 
1909 static inline int
1910 il_is_ready_rf(struct il_priv *il)
1911 {
1912 
1913 	if (il_is_rfkill(il))
1914 		return 0;
1915 
1916 	return il_is_ready(il);
1917 }
1918 
1919 void il_send_bt_config(struct il_priv *il);
1920 int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
1921 void il_apm_stop(struct il_priv *il);
1922 void _il_apm_stop(struct il_priv *il);
1923 
1924 int il_apm_init(struct il_priv *il);
1925 
1926 int il_send_rxon_timing(struct il_priv *il);
1927 
1928 static inline int
1929 il_send_rxon_assoc(struct il_priv *il)
1930 {
1931 	return il->ops->rxon_assoc(il);
1932 }
1933 
1934 static inline int
1935 il_commit_rxon(struct il_priv *il)
1936 {
1937 	return il->ops->commit_rxon(il);
1938 }
1939 
1940 static inline const struct ieee80211_supported_band *
1941 il_get_hw_mode(struct il_priv *il, enum nl80211_band band)
1942 {
1943 	return il->hw->wiphy->bands[band];
1944 }
1945 
1946 /* mac80211 handlers */
1947 int il_mac_config(struct ieee80211_hw *hw, u32 changed);
1948 void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1949 void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1950 			     struct ieee80211_bss_conf *bss_conf, u32 changes);
1951 void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1952 			  __le16 fc, __le32 *tx_flags);
1953 
1954 irqreturn_t il_isr(int irq, void *data);
1955 
1956 void il_set_bit(struct il_priv *p, u32 r, u32 m);
1957 void il_clear_bit(struct il_priv *p, u32 r, u32 m);
1958 bool _il_grab_nic_access(struct il_priv *il);
1959 int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout);
1960 int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout);
1961 u32 il_rd_prph(struct il_priv *il, u32 reg);
1962 void il_wr_prph(struct il_priv *il, u32 addr, u32 val);
1963 u32 il_read_targ_mem(struct il_priv *il, u32 addr);
1964 void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val);
1965 
1966 static inline bool il_need_reclaim(struct il_priv *il, struct il_rx_pkt *pkt)
1967 {
1968 	/* Reclaim a command buffer only if this packet is a response
1969 	 * to a (driver-originated) command. If the packet (e.g. Rx frame)
1970 	 * originated from uCode, there is no command buffer to reclaim.
1971 	 * Ucode should set SEQ_RX_FRAME bit if ucode-originated, but
1972 	 * apparently a few don't get set; catch them here.
1973 	 */
1974 	return !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1975 	       pkt->hdr.cmd != N_STATS && pkt->hdr.cmd != C_TX &&
1976 	       pkt->hdr.cmd != N_RX_PHY && pkt->hdr.cmd != N_RX &&
1977 	       pkt->hdr.cmd != N_RX_MPDU && pkt->hdr.cmd != N_COMPRESSED_BA;
1978 }
1979 
1980 static inline void
1981 _il_write8(struct il_priv *il, u32 ofs, u8 val)
1982 {
1983 	writeb(val, il->hw_base + ofs);
1984 }
1985 #define il_write8(il, ofs, val) _il_write8(il, ofs, val)
1986 
1987 static inline void
1988 _il_wr(struct il_priv *il, u32 ofs, u32 val)
1989 {
1990 	writel(val, il->hw_base + ofs);
1991 }
1992 
1993 static inline u32
1994 _il_rd(struct il_priv *il, u32 ofs)
1995 {
1996 	return readl(il->hw_base + ofs);
1997 }
1998 
1999 static inline void
2000 _il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2001 {
2002 	_il_wr(il, reg, _il_rd(il, reg) & ~mask);
2003 }
2004 
2005 static inline void
2006 _il_set_bit(struct il_priv *il, u32 reg, u32 mask)
2007 {
2008 	_il_wr(il, reg, _il_rd(il, reg) | mask);
2009 }
2010 
2011 static inline void
2012 _il_release_nic_access(struct il_priv *il)
2013 {
2014 	_il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2015 }
2016 
2017 static inline u32
2018 il_rd(struct il_priv *il, u32 reg)
2019 {
2020 	u32 value;
2021 	unsigned long reg_flags;
2022 
2023 	spin_lock_irqsave(&il->reg_lock, reg_flags);
2024 	_il_grab_nic_access(il);
2025 	value = _il_rd(il, reg);
2026 	_il_release_nic_access(il);
2027 	spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2028 	return value;
2029 }
2030 
2031 static inline void
2032 il_wr(struct il_priv *il, u32 reg, u32 value)
2033 {
2034 	unsigned long reg_flags;
2035 
2036 	spin_lock_irqsave(&il->reg_lock, reg_flags);
2037 	if (likely(_il_grab_nic_access(il))) {
2038 		_il_wr(il, reg, value);
2039 		_il_release_nic_access(il);
2040 	}
2041 	spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2042 }
2043 
2044 static inline u32
2045 _il_rd_prph(struct il_priv *il, u32 reg)
2046 {
2047 	_il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2048 	return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2049 }
2050 
2051 static inline void
2052 _il_wr_prph(struct il_priv *il, u32 addr, u32 val)
2053 {
2054 	_il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
2055 	_il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2056 }
2057 
2058 static inline void
2059 il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2060 {
2061 	unsigned long reg_flags;
2062 
2063 	spin_lock_irqsave(&il->reg_lock, reg_flags);
2064 	if (likely(_il_grab_nic_access(il))) {
2065 		_il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask));
2066 		_il_release_nic_access(il);
2067 	}
2068 	spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2069 }
2070 
2071 static inline void
2072 il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
2073 {
2074 	unsigned long reg_flags;
2075 
2076 	spin_lock_irqsave(&il->reg_lock, reg_flags);
2077 	if (likely(_il_grab_nic_access(il))) {
2078 		_il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits));
2079 		_il_release_nic_access(il);
2080 	}
2081 	spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2082 }
2083 
2084 static inline void
2085 il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2086 {
2087 	unsigned long reg_flags;
2088 	u32 val;
2089 
2090 	spin_lock_irqsave(&il->reg_lock, reg_flags);
2091 	if (likely(_il_grab_nic_access(il))) {
2092 		val = _il_rd_prph(il, reg);
2093 		_il_wr_prph(il, reg, (val & ~mask));
2094 		_il_release_nic_access(il);
2095 	}
2096 	spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2097 }
2098 
2099 #define HW_KEY_DYNAMIC 0
2100 #define HW_KEY_DEFAULT 1
2101 
2102 #define IL_STA_DRIVER_ACTIVE BIT(0)	/* driver entry is active */
2103 #define IL_STA_UCODE_ACTIVE  BIT(1)	/* ucode entry is active */
2104 #define IL_STA_UCODE_INPROGRESS  BIT(2)	/* ucode entry is in process of
2105 					   being activated */
2106 #define IL_STA_LOCAL BIT(3)	/* station state not directed by mac80211;
2107 				   (this is for the IBSS BSSID stations) */
2108 #define IL_STA_BCAST BIT(4)	/* this station is the special bcast station */
2109 
2110 void il_restore_stations(struct il_priv *il);
2111 void il_clear_ucode_stations(struct il_priv *il);
2112 void il_dealloc_bcast_stations(struct il_priv *il);
2113 int il_get_free_ucode_key_idx(struct il_priv *il);
2114 int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
2115 int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
2116 			  struct ieee80211_sta *sta, u8 *sta_id_r);
2117 int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2118 int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2119 		      struct ieee80211_sta *sta);
2120 
2121 u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
2122 		   struct ieee80211_sta *sta);
2123 
2124 int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2125 		   u8 flags, bool init);
2126 
2127 /**
2128  * il_clear_driver_stations - clear knowledge of all stations from driver
2129  * @il: iwl il struct
2130  *
2131  * This is called during il_down() to make sure that in the case
2132  * we're coming there from a hardware restart mac80211 will be
2133  * able to reconfigure stations -- if we're getting there in the
2134  * normal down flow then the stations will already be cleared.
2135  */
2136 static inline void
2137 il_clear_driver_stations(struct il_priv *il)
2138 {
2139 	unsigned long flags;
2140 
2141 	spin_lock_irqsave(&il->sta_lock, flags);
2142 	memset(il->stations, 0, sizeof(il->stations));
2143 	il->num_stations = 0;
2144 	il->ucode_key_table = 0;
2145 	spin_unlock_irqrestore(&il->sta_lock, flags);
2146 }
2147 
2148 static inline int
2149 il_sta_id(struct ieee80211_sta *sta)
2150 {
2151 	if (WARN_ON(!sta))
2152 		return IL_INVALID_STATION;
2153 
2154 	return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2155 }
2156 
2157 /**
2158  * il_sta_id_or_broadcast - return sta_id or broadcast sta
2159  * @il: iwl il
2160  * @context: the current context
2161  * @sta: mac80211 station
2162  *
2163  * In certain circumstances mac80211 passes a station pointer
2164  * that may be %NULL, for example during TX or key setup. In
2165  * that case, we need to use the broadcast station, so this
2166  * inline wraps that pattern.
2167  */
2168 static inline int
2169 il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta)
2170 {
2171 	int sta_id;
2172 
2173 	if (!sta)
2174 		return il->hw_params.bcast_id;
2175 
2176 	sta_id = il_sta_id(sta);
2177 
2178 	/*
2179 	 * mac80211 should not be passing a partially
2180 	 * initialised station!
2181 	 */
2182 	WARN_ON(sta_id == IL_INVALID_STATION);
2183 
2184 	return sta_id;
2185 }
2186 
2187 /**
2188  * il_queue_inc_wrap - increment queue idx, wrap back to beginning
2189  * @idx -- current idx
2190  * @n_bd -- total number of entries in queue (must be power of 2)
2191  */
2192 static inline int
2193 il_queue_inc_wrap(int idx, int n_bd)
2194 {
2195 	return ++idx & (n_bd - 1);
2196 }
2197 
2198 /**
2199  * il_queue_dec_wrap - decrement queue idx, wrap back to end
2200  * @idx -- current idx
2201  * @n_bd -- total number of entries in queue (must be power of 2)
2202  */
2203 static inline int
2204 il_queue_dec_wrap(int idx, int n_bd)
2205 {
2206 	return --idx & (n_bd - 1);
2207 }
2208 
2209 /* TODO: Move fw_desc functions to iwl-pci.ko */
2210 static inline void
2211 il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2212 {
2213 	if (desc->v_addr)
2214 		dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2215 				  desc->p_addr);
2216 	desc->v_addr = NULL;
2217 	desc->len = 0;
2218 }
2219 
2220 static inline int
2221 il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2222 {
2223 	if (!desc->len) {
2224 		desc->v_addr = NULL;
2225 		return -EINVAL;
2226 	}
2227 
2228 	desc->v_addr = dma_alloc_coherent(&pci_dev->dev, desc->len,
2229 					  &desc->p_addr, GFP_KERNEL);
2230 	return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2231 }
2232 
2233 /*
2234  * we have 8 bits used like this:
2235  *
2236  * 7 6 5 4 3 2 1 0
2237  * | | | | | | | |
2238  * | | | | | | +-+-------- AC queue (0-3)
2239  * | | | | | |
2240  * | +-+-+-+-+------------ HW queue ID
2241  * |
2242  * +---------------------- unused
2243  */
2244 static inline void
2245 il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2246 {
2247 	BUG_ON(ac > 3);		/* only have 2 bits */
2248 	BUG_ON(hwq > 31);	/* only use 5 bits */
2249 
2250 	txq->swq_id = (hwq << 2) | ac;
2251 }
2252 
2253 static inline void
2254 _il_wake_queue(struct il_priv *il, u8 ac)
2255 {
2256 	if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2257 		ieee80211_wake_queue(il->hw, ac);
2258 }
2259 
2260 static inline void
2261 _il_stop_queue(struct il_priv *il, u8 ac)
2262 {
2263 	if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2264 		ieee80211_stop_queue(il->hw, ac);
2265 }
2266 static inline void
2267 il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
2268 {
2269 	u8 queue = txq->swq_id;
2270 	u8 ac = queue & 3;
2271 	u8 hwq = (queue >> 2) & 0x1f;
2272 
2273 	if (test_and_clear_bit(hwq, il->queue_stopped))
2274 		_il_wake_queue(il, ac);
2275 }
2276 
2277 static inline void
2278 il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
2279 {
2280 	u8 queue = txq->swq_id;
2281 	u8 ac = queue & 3;
2282 	u8 hwq = (queue >> 2) & 0x1f;
2283 
2284 	if (!test_and_set_bit(hwq, il->queue_stopped))
2285 		_il_stop_queue(il, ac);
2286 }
2287 
2288 static inline void
2289 il_wake_queues_by_reason(struct il_priv *il, int reason)
2290 {
2291 	u8 ac;
2292 
2293 	if (test_and_clear_bit(reason, &il->stop_reason))
2294 		for (ac = 0; ac < 4; ac++)
2295 			_il_wake_queue(il, ac);
2296 }
2297 
2298 static inline void
2299 il_stop_queues_by_reason(struct il_priv *il, int reason)
2300 {
2301 	u8 ac;
2302 
2303 	if (!test_and_set_bit(reason, &il->stop_reason))
2304 		for (ac = 0; ac < 4; ac++)
2305 			_il_stop_queue(il, ac);
2306 }
2307 
2308 #ifdef ieee80211_stop_queue
2309 #undef ieee80211_stop_queue
2310 #endif
2311 
2312 #define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2313 
2314 #ifdef ieee80211_wake_queue
2315 #undef ieee80211_wake_queue
2316 #endif
2317 
2318 #define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2319 
2320 static inline void
2321 il_disable_interrupts(struct il_priv *il)
2322 {
2323 	clear_bit(S_INT_ENABLED, &il->status);
2324 
2325 	/* disable interrupts from uCode/NIC to host */
2326 	_il_wr(il, CSR_INT_MASK, 0x00000000);
2327 
2328 	/* acknowledge/clear/reset any interrupts still pending
2329 	 * from uCode or flow handler (Rx/Tx DMA) */
2330 	_il_wr(il, CSR_INT, 0xffffffff);
2331 	_il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
2332 }
2333 
2334 static inline void
2335 il_enable_rfkill_int(struct il_priv *il)
2336 {
2337 	_il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2338 }
2339 
2340 static inline void
2341 il_enable_interrupts(struct il_priv *il)
2342 {
2343 	set_bit(S_INT_ENABLED, &il->status);
2344 	_il_wr(il, CSR_INT_MASK, il->inta_mask);
2345 }
2346 
2347 /**
2348  * il_beacon_time_mask_low - mask of lower 32 bit of beacon time
2349  * @il -- pointer to il_priv data structure
2350  * @tsf_bits -- number of bits need to shift for masking)
2351  */
2352 static inline u32
2353 il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
2354 {
2355 	return (1 << tsf_bits) - 1;
2356 }
2357 
2358 /**
2359  * il_beacon_time_mask_high - mask of higher 32 bit of beacon time
2360  * @il -- pointer to il_priv data structure
2361  * @tsf_bits -- number of bits need to shift for masking)
2362  */
2363 static inline u32
2364 il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
2365 {
2366 	return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2367 }
2368 
2369 /**
2370  * struct il_rb_status - reseve buffer status host memory mapped FH registers
2371  *
2372  * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed
2373  * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed
2374  * @finished_rb_num [0:11] - Indicates the idx of the current RB
2375  *			     in which the last frame was written to
2376  * @finished_fr_num [0:11] - Indicates the idx of the RX Frame
2377  *			     which was transferred
2378  */
2379 struct il_rb_status {
2380 	__le16 closed_rb_num;
2381 	__le16 closed_fr_num;
2382 	__le16 finished_rb_num;
2383 	__le16 finished_fr_nam;
2384 	__le32 __unused;	/* 3945 only */
2385 } __packed;
2386 
2387 #define TFD_QUEUE_SIZE_MAX      256
2388 #define TFD_QUEUE_SIZE_BC_DUP	64
2389 #define TFD_QUEUE_BC_SIZE	(TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2390 #define IL_TX_DMA_MASK		DMA_BIT_MASK(36)
2391 #define IL_NUM_OF_TBS		20
2392 
2393 static inline u8
2394 il_get_dma_hi_addr(dma_addr_t addr)
2395 {
2396 	return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2397 }
2398 
2399 /**
2400  * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor
2401  *
2402  * This structure contains dma address and length of transmission address
2403  *
2404  * @lo: low [31:0] portion of the dma address of TX buffer every even is
2405  *	unaligned on 16 bit boundary
2406  * @hi_n_len: 0-3 [35:32] portion of dma
2407  *	      4-15 length of the tx buffer
2408  */
2409 struct il_tfd_tb {
2410 	__le32 lo;
2411 	__le16 hi_n_len;
2412 } __packed;
2413 
2414 /**
2415  * struct il_tfd
2416  *
2417  * Transmit Frame Descriptor (TFD)
2418  *
2419  * @ __reserved1[3] reserved
2420  * @ num_tbs 0-4 number of active tbs
2421  *	     5   reserved
2422  * 	     6-7 padding (not used)
2423  * @ tbs[20]	transmit frame buffer descriptors
2424  * @ __pad	padding
2425  *
2426  * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
2427  * Both driver and device share these circular buffers, each of which must be
2428  * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
2429  *
2430  * Driver must indicate the physical address of the base of each
2431  * circular buffer via the FH49_MEM_CBBC_QUEUE registers.
2432  *
2433  * Each TFD contains pointer/size information for up to 20 data buffers
2434  * in host DRAM.  These buffers collectively contain the (one) frame described
2435  * by the TFD.  Each buffer must be a single contiguous block of memory within
2436  * itself, but buffers may be scattered in host DRAM.  Each buffer has max size
2437  * of (4K - 4).  The concatenates all of a TFD's buffers into a single
2438  * Tx frame, up to 8 KBytes in size.
2439  *
2440  * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
2441  */
2442 struct il_tfd {
2443 	u8 __reserved1[3];
2444 	u8 num_tbs;
2445 	struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2446 	__le32 __pad;
2447 } __packed;
2448 /* PCI registers */
2449 #define PCI_CFG_RETRY_TIMEOUT	0x041
2450 
2451 struct il_rate_info {
2452 	u8 plcp;		/* uCode API:  RATE_6M_PLCP, etc. */
2453 	u8 plcp_siso;		/* uCode API:  RATE_SISO_6M_PLCP, etc. */
2454 	u8 plcp_mimo2;		/* uCode API:  RATE_MIMO2_6M_PLCP, etc. */
2455 	u8 ieee;		/* MAC header:  RATE_6M_IEEE, etc. */
2456 	u8 prev_ieee;		/* previous rate in IEEE speeds */
2457 	u8 next_ieee;		/* next rate in IEEE speeds */
2458 	u8 prev_rs;		/* previous rate used in rs algo */
2459 	u8 next_rs;		/* next rate used in rs algo */
2460 	u8 prev_rs_tgg;		/* previous rate used in TGG rs algo */
2461 	u8 next_rs_tgg;		/* next rate used in TGG rs algo */
2462 };
2463 
2464 struct il3945_rate_info {
2465 	u8 plcp;		/* uCode API:  RATE_6M_PLCP, etc. */
2466 	u8 ieee;		/* MAC header:  RATE_6M_IEEE, etc. */
2467 	u8 prev_ieee;		/* previous rate in IEEE speeds */
2468 	u8 next_ieee;		/* next rate in IEEE speeds */
2469 	u8 prev_rs;		/* previous rate used in rs algo */
2470 	u8 next_rs;		/* next rate used in rs algo */
2471 	u8 prev_rs_tgg;		/* previous rate used in TGG rs algo */
2472 	u8 next_rs_tgg;		/* next rate used in TGG rs algo */
2473 	u8 table_rs_idx;	/* idx in rate scale table cmd */
2474 	u8 prev_table_rs;	/* prev in rate table cmd */
2475 };
2476 
2477 /*
2478  * These serve as idxes into
2479  * struct il_rate_info il_rates[RATE_COUNT];
2480  */
2481 enum {
2482 	RATE_1M_IDX = 0,
2483 	RATE_2M_IDX,
2484 	RATE_5M_IDX,
2485 	RATE_11M_IDX,
2486 	RATE_6M_IDX,
2487 	RATE_9M_IDX,
2488 	RATE_12M_IDX,
2489 	RATE_18M_IDX,
2490 	RATE_24M_IDX,
2491 	RATE_36M_IDX,
2492 	RATE_48M_IDX,
2493 	RATE_54M_IDX,
2494 	RATE_60M_IDX,
2495 	RATE_COUNT,
2496 	RATE_COUNT_LEGACY = RATE_COUNT - 1,	/* Excluding 60M */
2497 	RATE_COUNT_3945 = RATE_COUNT - 1,
2498 	RATE_INVM_IDX = RATE_COUNT,
2499 	RATE_INVALID = RATE_COUNT,
2500 };
2501 
2502 enum {
2503 	RATE_6M_IDX_TBL = 0,
2504 	RATE_9M_IDX_TBL,
2505 	RATE_12M_IDX_TBL,
2506 	RATE_18M_IDX_TBL,
2507 	RATE_24M_IDX_TBL,
2508 	RATE_36M_IDX_TBL,
2509 	RATE_48M_IDX_TBL,
2510 	RATE_54M_IDX_TBL,
2511 	RATE_1M_IDX_TBL,
2512 	RATE_2M_IDX_TBL,
2513 	RATE_5M_IDX_TBL,
2514 	RATE_11M_IDX_TBL,
2515 	RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2516 };
2517 
2518 enum {
2519 	IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2520 	IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2521 	IL_LAST_OFDM_RATE = RATE_60M_IDX,
2522 	IL_FIRST_CCK_RATE = RATE_1M_IDX,
2523 	IL_LAST_CCK_RATE = RATE_11M_IDX,
2524 };
2525 
2526 /* #define vs. enum to keep from defaulting to 'large integer' */
2527 #define	RATE_6M_MASK   (1 << RATE_6M_IDX)
2528 #define	RATE_9M_MASK   (1 << RATE_9M_IDX)
2529 #define	RATE_12M_MASK  (1 << RATE_12M_IDX)
2530 #define	RATE_18M_MASK  (1 << RATE_18M_IDX)
2531 #define	RATE_24M_MASK  (1 << RATE_24M_IDX)
2532 #define	RATE_36M_MASK  (1 << RATE_36M_IDX)
2533 #define	RATE_48M_MASK  (1 << RATE_48M_IDX)
2534 #define	RATE_54M_MASK  (1 << RATE_54M_IDX)
2535 #define RATE_60M_MASK  (1 << RATE_60M_IDX)
2536 #define	RATE_1M_MASK   (1 << RATE_1M_IDX)
2537 #define	RATE_2M_MASK   (1 << RATE_2M_IDX)
2538 #define	RATE_5M_MASK   (1 << RATE_5M_IDX)
2539 #define	RATE_11M_MASK  (1 << RATE_11M_IDX)
2540 
2541 /* uCode API values for legacy bit rates, both OFDM and CCK */
2542 enum {
2543 	RATE_6M_PLCP = 13,
2544 	RATE_9M_PLCP = 15,
2545 	RATE_12M_PLCP = 5,
2546 	RATE_18M_PLCP = 7,
2547 	RATE_24M_PLCP = 9,
2548 	RATE_36M_PLCP = 11,
2549 	RATE_48M_PLCP = 1,
2550 	RATE_54M_PLCP = 3,
2551 	RATE_60M_PLCP = 3,	/*FIXME:RS:should be removed */
2552 	RATE_1M_PLCP = 10,
2553 	RATE_2M_PLCP = 20,
2554 	RATE_5M_PLCP = 55,
2555 	RATE_11M_PLCP = 110,
2556 	/*FIXME:RS:add RATE_LEGACY_INVM_PLCP = 0, */
2557 };
2558 
2559 /* uCode API values for OFDM high-throughput (HT) bit rates */
2560 enum {
2561 	RATE_SISO_6M_PLCP = 0,
2562 	RATE_SISO_12M_PLCP = 1,
2563 	RATE_SISO_18M_PLCP = 2,
2564 	RATE_SISO_24M_PLCP = 3,
2565 	RATE_SISO_36M_PLCP = 4,
2566 	RATE_SISO_48M_PLCP = 5,
2567 	RATE_SISO_54M_PLCP = 6,
2568 	RATE_SISO_60M_PLCP = 7,
2569 	RATE_MIMO2_6M_PLCP = 0x8,
2570 	RATE_MIMO2_12M_PLCP = 0x9,
2571 	RATE_MIMO2_18M_PLCP = 0xa,
2572 	RATE_MIMO2_24M_PLCP = 0xb,
2573 	RATE_MIMO2_36M_PLCP = 0xc,
2574 	RATE_MIMO2_48M_PLCP = 0xd,
2575 	RATE_MIMO2_54M_PLCP = 0xe,
2576 	RATE_MIMO2_60M_PLCP = 0xf,
2577 	RATE_SISO_INVM_PLCP,
2578 	RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2579 };
2580 
2581 /* MAC header values for bit rates */
2582 enum {
2583 	RATE_6M_IEEE = 12,
2584 	RATE_9M_IEEE = 18,
2585 	RATE_12M_IEEE = 24,
2586 	RATE_18M_IEEE = 36,
2587 	RATE_24M_IEEE = 48,
2588 	RATE_36M_IEEE = 72,
2589 	RATE_48M_IEEE = 96,
2590 	RATE_54M_IEEE = 108,
2591 	RATE_60M_IEEE = 120,
2592 	RATE_1M_IEEE = 2,
2593 	RATE_2M_IEEE = 4,
2594 	RATE_5M_IEEE = 11,
2595 	RATE_11M_IEEE = 22,
2596 };
2597 
2598 #define IL_CCK_BASIC_RATES_MASK    \
2599 	(RATE_1M_MASK          | \
2600 	RATE_2M_MASK)
2601 
2602 #define IL_CCK_RATES_MASK          \
2603 	(IL_CCK_BASIC_RATES_MASK  | \
2604 	RATE_5M_MASK          | \
2605 	RATE_11M_MASK)
2606 
2607 #define IL_OFDM_BASIC_RATES_MASK   \
2608 	(RATE_6M_MASK         | \
2609 	RATE_12M_MASK         | \
2610 	RATE_24M_MASK)
2611 
2612 #define IL_OFDM_RATES_MASK         \
2613 	(IL_OFDM_BASIC_RATES_MASK | \
2614 	RATE_9M_MASK          | \
2615 	RATE_18M_MASK         | \
2616 	RATE_36M_MASK         | \
2617 	RATE_48M_MASK         | \
2618 	RATE_54M_MASK)
2619 
2620 #define IL_BASIC_RATES_MASK         \
2621 	(IL_OFDM_BASIC_RATES_MASK | \
2622 	 IL_CCK_BASIC_RATES_MASK)
2623 
2624 #define RATES_MASK ((1 << RATE_COUNT) - 1)
2625 #define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2626 
2627 #define IL_INVALID_VALUE    -1
2628 
2629 #define IL_MIN_RSSI_VAL                 -100
2630 #define IL_MAX_RSSI_VAL                    0
2631 
2632 /* These values specify how many Tx frame attempts before
2633  * searching for a new modulation mode */
2634 #define IL_LEGACY_FAILURE_LIMIT	160
2635 #define IL_LEGACY_SUCCESS_LIMIT	480
2636 #define IL_LEGACY_TBL_COUNT		160
2637 
2638 #define IL_NONE_LEGACY_FAILURE_LIMIT	400
2639 #define IL_NONE_LEGACY_SUCCESS_LIMIT	4500
2640 #define IL_NONE_LEGACY_TBL_COUNT	1500
2641 
2642 /* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */
2643 #define IL_RS_GOOD_RATIO		12800	/* 100% */
2644 #define RATE_SCALE_SWITCH		10880	/*  85% */
2645 #define RATE_HIGH_TH		10880	/*  85% */
2646 #define RATE_INCREASE_TH		6400	/*  50% */
2647 #define RATE_DECREASE_TH		1920	/*  15% */
2648 
2649 /* possible actions when in legacy mode */
2650 #define IL_LEGACY_SWITCH_ANTENNA1      0
2651 #define IL_LEGACY_SWITCH_ANTENNA2      1
2652 #define IL_LEGACY_SWITCH_SISO          2
2653 #define IL_LEGACY_SWITCH_MIMO2_AB      3
2654 #define IL_LEGACY_SWITCH_MIMO2_AC      4
2655 #define IL_LEGACY_SWITCH_MIMO2_BC      5
2656 
2657 /* possible actions when in siso mode */
2658 #define IL_SISO_SWITCH_ANTENNA1        0
2659 #define IL_SISO_SWITCH_ANTENNA2        1
2660 #define IL_SISO_SWITCH_MIMO2_AB        2
2661 #define IL_SISO_SWITCH_MIMO2_AC        3
2662 #define IL_SISO_SWITCH_MIMO2_BC        4
2663 #define IL_SISO_SWITCH_GI              5
2664 
2665 /* possible actions when in mimo mode */
2666 #define IL_MIMO2_SWITCH_ANTENNA1       0
2667 #define IL_MIMO2_SWITCH_ANTENNA2       1
2668 #define IL_MIMO2_SWITCH_SISO_A         2
2669 #define IL_MIMO2_SWITCH_SISO_B         3
2670 #define IL_MIMO2_SWITCH_SISO_C         4
2671 #define IL_MIMO2_SWITCH_GI             5
2672 
2673 #define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
2674 
2675 #define IL_ACTION_LIMIT		3	/* # possible actions */
2676 
2677 #define LQ_SIZE		2	/* 2 mode tables:  "Active" and "Search" */
2678 
2679 /* load per tid defines for A-MPDU activation */
2680 #define IL_AGG_TPT_THREHOLD	0
2681 #define IL_AGG_LOAD_THRESHOLD	10
2682 #define IL_AGG_ALL_TID		0xff
2683 #define TID_QUEUE_CELL_SPACING	50	/*mS */
2684 #define TID_QUEUE_MAX_SIZE	20
2685 #define TID_ROUND_VALUE		5	/* mS */
2686 #define TID_MAX_LOAD_COUNT	8
2687 
2688 #define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
2689 #define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
2690 
2691 extern const struct il_rate_info il_rates[RATE_COUNT];
2692 
2693 enum il_table_type {
2694 	LQ_NONE,
2695 	LQ_G,			/* legacy types */
2696 	LQ_A,
2697 	LQ_SISO,		/* high-throughput types */
2698 	LQ_MIMO2,
2699 	LQ_MAX,
2700 };
2701 
2702 #define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
2703 #define is_siso(tbl) ((tbl) == LQ_SISO)
2704 #define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
2705 #define is_mimo(tbl) (is_mimo2(tbl))
2706 #define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
2707 #define is_a_band(tbl) ((tbl) == LQ_A)
2708 #define is_g_and(tbl) ((tbl) == LQ_G)
2709 
2710 #define	ANT_NONE	0x0
2711 #define	ANT_A		BIT(0)
2712 #define	ANT_B		BIT(1)
2713 #define	ANT_AB		(ANT_A | ANT_B)
2714 #define ANT_C		BIT(2)
2715 #define	ANT_AC		(ANT_A | ANT_C)
2716 #define ANT_BC		(ANT_B | ANT_C)
2717 #define ANT_ABC		(ANT_AB | ANT_C)
2718 
2719 #define IL_MAX_MCS_DISPLAY_SIZE	12
2720 
2721 struct il_rate_mcs_info {
2722 	char mbps[IL_MAX_MCS_DISPLAY_SIZE];
2723 	char mcs[IL_MAX_MCS_DISPLAY_SIZE];
2724 };
2725 
2726 /**
2727  * struct il_rate_scale_data -- tx success history for one rate
2728  */
2729 struct il_rate_scale_data {
2730 	u64 data;		/* bitmap of successful frames */
2731 	s32 success_counter;	/* number of frames successful */
2732 	s32 success_ratio;	/* per-cent * 128  */
2733 	s32 counter;		/* number of frames attempted */
2734 	s32 average_tpt;	/* success ratio * expected throughput */
2735 	unsigned long stamp;
2736 };
2737 
2738 /**
2739  * struct il_scale_tbl_info -- tx params and success history for all rates
2740  *
2741  * There are two of these in struct il_lq_sta,
2742  * one for "active", and one for "search".
2743  */
2744 struct il_scale_tbl_info {
2745 	enum il_table_type lq_type;
2746 	u8 ant_type;
2747 	u8 is_SGI;		/* 1 = short guard interval */
2748 	u8 is_ht40;		/* 1 = 40 MHz channel width */
2749 	u8 is_dup;		/* 1 = duplicated data streams */
2750 	u8 action;		/* change modulation; IL_[LEGACY/SISO/MIMO]_SWITCH_* */
2751 	u8 max_search;		/* maximun number of tables we can search */
2752 	s32 *expected_tpt;	/* throughput metrics; expected_tpt_G, etc. */
2753 	u32 current_rate;	/* rate_n_flags, uCode API format */
2754 	struct il_rate_scale_data win[RATE_COUNT];	/* rate histories */
2755 };
2756 
2757 struct il_traffic_load {
2758 	unsigned long time_stamp;	/* age of the oldest stats */
2759 	u32 packet_count[TID_QUEUE_MAX_SIZE];	/* packet count in this time
2760 						 * slice */
2761 	u32 total;		/* total num of packets during the
2762 				 * last TID_MAX_TIME_DIFF */
2763 	u8 queue_count;		/* number of queues that has
2764 				 * been used since the last cleanup */
2765 	u8 head;		/* start of the circular buffer */
2766 };
2767 
2768 /**
2769  * struct il_lq_sta -- driver's rate scaling ilate structure
2770  *
2771  * Pointer to this gets passed back and forth between driver and mac80211.
2772  */
2773 struct il_lq_sta {
2774 	u8 active_tbl;		/* idx of active table, range 0-1 */
2775 	u8 enable_counter;	/* indicates HT mode */
2776 	u8 stay_in_tbl;		/* 1: disallow, 0: allow search for new mode */
2777 	u8 search_better_tbl;	/* 1: currently trying alternate mode */
2778 	s32 last_tpt;
2779 
2780 	/* The following determine when to search for a new mode */
2781 	u32 table_count_limit;
2782 	u32 max_failure_limit;	/* # failed frames before new search */
2783 	u32 max_success_limit;	/* # successful frames before new search */
2784 	u32 table_count;
2785 	u32 total_failed;	/* total failed frames, any/all rates */
2786 	u32 total_success;	/* total successful frames, any/all rates */
2787 	u64 flush_timer;	/* time staying in mode before new search */
2788 
2789 	u8 action_counter;	/* # mode-switch actions tried */
2790 	u8 is_green;
2791 	u8 is_dup;
2792 	enum nl80211_band band;
2793 
2794 	/* The following are bitmaps of rates; RATE_6M_MASK, etc. */
2795 	u32 supp_rates;
2796 	u16 active_legacy_rate;
2797 	u16 active_siso_rate;
2798 	u16 active_mimo2_rate;
2799 	s8 max_rate_idx;	/* Max rate set by user */
2800 	u8 missed_rate_counter;
2801 
2802 	struct il_link_quality_cmd lq;
2803 	struct il_scale_tbl_info lq_info[LQ_SIZE];	/* "active", "search" */
2804 	struct il_traffic_load load[TID_MAX_LOAD_COUNT];
2805 	u8 tx_agg_tid_en;
2806 #ifdef CONFIG_MAC80211_DEBUGFS
2807 	u32 dbg_fixed_rate;
2808 #endif
2809 	struct il_priv *drv;
2810 
2811 	/* used to be in sta_info */
2812 	int last_txrate_idx;
2813 	/* last tx rate_n_flags */
2814 	u32 last_rate_n_flags;
2815 	/* packets destined for this STA are aggregated */
2816 	u8 is_agg;
2817 };
2818 
2819 /*
2820  * il_station_priv: Driver's ilate station information
2821  *
2822  * When mac80211 creates a station it reserves some space (hw->sta_data_size)
2823  * in the structure for use by driver. This structure is places in that
2824  * space.
2825  *
2826  * The common struct MUST be first because it is shared between
2827  * 3945 and 4965!
2828  */
2829 struct il_station_priv {
2830 	struct il_station_priv_common common;
2831 	struct il_lq_sta lq_sta;
2832 	atomic_t pending_frames;
2833 	bool client;
2834 	bool asleep;
2835 };
2836 
2837 static inline u8
2838 il4965_num_of_ant(u8 m)
2839 {
2840 	return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
2841 }
2842 
2843 static inline u8
2844 il4965_first_antenna(u8 mask)
2845 {
2846 	if (mask & ANT_A)
2847 		return ANT_A;
2848 	if (mask & ANT_B)
2849 		return ANT_B;
2850 	return ANT_C;
2851 }
2852 
2853 /**
2854  * il3945_rate_scale_init - Initialize the rate scale table based on assoc info
2855  *
2856  * The specific throughput table used is based on the type of network
2857  * the associated with, including A, B, G, and G w/ TGG protection
2858  */
2859 void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
2860 
2861 /* Initialize station's rate scaling information after adding station */
2862 void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2863 			 u8 sta_id);
2864 void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2865 			 u8 sta_id);
2866 
2867 /**
2868  * il_rate_control_register - Register the rate control algorithm callbacks
2869  *
2870  * Since the rate control algorithm is hardware specific, there is no need
2871  * or reason to place it as a stand alone module.  The driver can call
2872  * il_rate_control_register in order to register the rate control callbacks
2873  * with the mac80211 subsystem.  This should be performed prior to calling
2874  * ieee80211_register_hw
2875  *
2876  */
2877 int il4965_rate_control_register(void);
2878 int il3945_rate_control_register(void);
2879 
2880 /**
2881  * il_rate_control_unregister - Unregister the rate control callbacks
2882  *
2883  * This should be called after calling ieee80211_unregister_hw, but before
2884  * the driver is unloaded.
2885  */
2886 void il4965_rate_control_unregister(void);
2887 void il3945_rate_control_unregister(void);
2888 
2889 int il_power_update_mode(struct il_priv *il, bool force);
2890 void il_power_initialize(struct il_priv *il);
2891 
2892 extern u32 il_debug_level;
2893 
2894 #ifdef CONFIG_IWLEGACY_DEBUG
2895 /*
2896  * il_get_debug_level: Return active debug level for device
2897  *
2898  * Using sysfs it is possible to set per device debug level. This debug
2899  * level will be used if set, otherwise the global debug level which can be
2900  * set via module parameter is used.
2901  */
2902 static inline u32
2903 il_get_debug_level(struct il_priv *il)
2904 {
2905 	if (il->debug_level)
2906 		return il->debug_level;
2907 	else
2908 		return il_debug_level;
2909 }
2910 #else
2911 static inline u32
2912 il_get_debug_level(struct il_priv *il)
2913 {
2914 	return il_debug_level;
2915 }
2916 #endif
2917 
2918 #define il_print_hex_error(il, p, len)					\
2919 do {									\
2920 	print_hex_dump(KERN_ERR, "iwl data: ",				\
2921 		       DUMP_PREFIX_OFFSET, 16, 1, p, len, 1);		\
2922 } while (0)
2923 
2924 #ifdef CONFIG_IWLEGACY_DEBUG
2925 #define IL_DBG(level, fmt, args...)					\
2926 do {									\
2927 	if (il_get_debug_level(il) & level)				\
2928 		dev_err(&il->hw->wiphy->dev, "%s " fmt, __func__,	\
2929 			 ##args);					\
2930 } while (0)
2931 
2932 #define il_print_hex_dump(il, level, p, len)				\
2933 do {									\
2934 	if (il_get_debug_level(il) & level)				\
2935 		print_hex_dump(KERN_DEBUG, "iwl data: ",		\
2936 			       DUMP_PREFIX_OFFSET, 16, 1, p, len, 1);	\
2937 } while (0)
2938 
2939 #else
2940 #define IL_DBG(level, fmt, args...)
2941 static inline void
2942 il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
2943 {
2944 }
2945 #endif /* CONFIG_IWLEGACY_DEBUG */
2946 
2947 #ifdef CONFIG_IWLEGACY_DEBUGFS
2948 void il_dbgfs_register(struct il_priv *il, const char *name);
2949 void il_dbgfs_unregister(struct il_priv *il);
2950 #else
2951 static inline void il_dbgfs_register(struct il_priv *il, const char *name)
2952 {
2953 }
2954 
2955 static inline void
2956 il_dbgfs_unregister(struct il_priv *il)
2957 {
2958 }
2959 #endif /* CONFIG_IWLEGACY_DEBUGFS */
2960 
2961 /*
2962  * To use the debug system:
2963  *
2964  * If you are defining a new debug classification, simply add it to the #define
2965  * list here in the form of
2966  *
2967  * #define IL_DL_xxxx VALUE
2968  *
2969  * where xxxx should be the name of the classification (for example, WEP).
2970  *
2971  * You then need to either add a IL_xxxx_DEBUG() macro definition for your
2972  * classification, or use IL_DBG(IL_DL_xxxx, ...) whenever you want
2973  * to send output to that classification.
2974  *
2975  * The active debug levels can be accessed via files
2976  *
2977  *	/sys/module/iwl4965/parameters/debug
2978  *	/sys/module/iwl3945/parameters/debug
2979  *	/sys/class/net/wlan0/device/debug_level
2980  *
2981  * when CONFIG_IWLEGACY_DEBUG=y.
2982  */
2983 
2984 /* 0x0000000F - 0x00000001 */
2985 #define IL_DL_INFO		(1 << 0)
2986 #define IL_DL_MAC80211		(1 << 1)
2987 #define IL_DL_HCMD		(1 << 2)
2988 #define IL_DL_STATE		(1 << 3)
2989 /* 0x000000F0 - 0x00000010 */
2990 #define IL_DL_MACDUMP		(1 << 4)
2991 #define IL_DL_HCMD_DUMP		(1 << 5)
2992 #define IL_DL_EEPROM		(1 << 6)
2993 #define IL_DL_RADIO		(1 << 7)
2994 /* 0x00000F00 - 0x00000100 */
2995 #define IL_DL_POWER		(1 << 8)
2996 #define IL_DL_TEMP		(1 << 9)
2997 #define IL_DL_NOTIF		(1 << 10)
2998 #define IL_DL_SCAN		(1 << 11)
2999 /* 0x0000F000 - 0x00001000 */
3000 #define IL_DL_ASSOC		(1 << 12)
3001 #define IL_DL_DROP		(1 << 13)
3002 #define IL_DL_TXPOWER		(1 << 14)
3003 #define IL_DL_AP		(1 << 15)
3004 /* 0x000F0000 - 0x00010000 */
3005 #define IL_DL_FW		(1 << 16)
3006 #define IL_DL_RF_KILL		(1 << 17)
3007 #define IL_DL_FW_ERRORS		(1 << 18)
3008 #define IL_DL_LED		(1 << 19)
3009 /* 0x00F00000 - 0x00100000 */
3010 #define IL_DL_RATE		(1 << 20)
3011 #define IL_DL_CALIB		(1 << 21)
3012 #define IL_DL_WEP		(1 << 22)
3013 #define IL_DL_TX		(1 << 23)
3014 /* 0x0F000000 - 0x01000000 */
3015 #define IL_DL_RX		(1 << 24)
3016 #define IL_DL_ISR		(1 << 25)
3017 #define IL_DL_HT		(1 << 26)
3018 /* 0xF0000000 - 0x10000000 */
3019 #define IL_DL_11H		(1 << 28)
3020 #define IL_DL_STATS		(1 << 29)
3021 #define IL_DL_TX_REPLY		(1 << 30)
3022 #define IL_DL_QOS		(1 << 31)
3023 
3024 #define D_INFO(f, a...)		IL_DBG(IL_DL_INFO, f, ## a)
3025 #define D_MAC80211(f, a...)	IL_DBG(IL_DL_MAC80211, f, ## a)
3026 #define D_MACDUMP(f, a...)	IL_DBG(IL_DL_MACDUMP, f, ## a)
3027 #define D_TEMP(f, a...)		IL_DBG(IL_DL_TEMP, f, ## a)
3028 #define D_SCAN(f, a...)		IL_DBG(IL_DL_SCAN, f, ## a)
3029 #define D_RX(f, a...)		IL_DBG(IL_DL_RX, f, ## a)
3030 #define D_TX(f, a...)		IL_DBG(IL_DL_TX, f, ## a)
3031 #define D_ISR(f, a...)		IL_DBG(IL_DL_ISR, f, ## a)
3032 #define D_LED(f, a...)		IL_DBG(IL_DL_LED, f, ## a)
3033 #define D_WEP(f, a...)		IL_DBG(IL_DL_WEP, f, ## a)
3034 #define D_HC(f, a...)		IL_DBG(IL_DL_HCMD, f, ## a)
3035 #define D_HC_DUMP(f, a...)	IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3036 #define D_EEPROM(f, a...)	IL_DBG(IL_DL_EEPROM, f, ## a)
3037 #define D_CALIB(f, a...)	IL_DBG(IL_DL_CALIB, f, ## a)
3038 #define D_FW(f, a...)		IL_DBG(IL_DL_FW, f, ## a)
3039 #define D_RF_KILL(f, a...)	IL_DBG(IL_DL_RF_KILL, f, ## a)
3040 #define D_DROP(f, a...)		IL_DBG(IL_DL_DROP, f, ## a)
3041 #define D_AP(f, a...)		IL_DBG(IL_DL_AP, f, ## a)
3042 #define D_TXPOWER(f, a...)	IL_DBG(IL_DL_TXPOWER, f, ## a)
3043 #define D_RATE(f, a...)		IL_DBG(IL_DL_RATE, f, ## a)
3044 #define D_NOTIF(f, a...)	IL_DBG(IL_DL_NOTIF, f, ## a)
3045 #define D_ASSOC(f, a...)	IL_DBG(IL_DL_ASSOC, f, ## a)
3046 #define D_HT(f, a...)		IL_DBG(IL_DL_HT, f, ## a)
3047 #define D_STATS(f, a...)	IL_DBG(IL_DL_STATS, f, ## a)
3048 #define D_TX_REPLY(f, a...)	IL_DBG(IL_DL_TX_REPLY, f, ## a)
3049 #define D_QOS(f, a...)		IL_DBG(IL_DL_QOS, f, ## a)
3050 #define D_RADIO(f, a...)	IL_DBG(IL_DL_RADIO, f, ## a)
3051 #define D_POWER(f, a...)	IL_DBG(IL_DL_POWER, f, ## a)
3052 #define D_11H(f, a...)		IL_DBG(IL_DL_11H, f, ## a)
3053 
3054 #endif /* __il_core_h__ */
3055