1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  *  Intel Linux Wireless <ilw@linux.intel.com>
23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24  *
25  *****************************************************************************/
26 #ifndef __il_core_h__
27 #define __il_core_h__
28 
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>		/* for struct pci_device_id */
31 #include <linux/kernel.h>
32 #include <linux/leds.h>
33 #include <linux/wait.h>
34 #include <linux/io.h>
35 #include <net/mac80211.h>
36 #include <net/ieee80211_radiotap.h>
37 
38 #include "commands.h"
39 #include "csr.h"
40 #include "prph.h"
41 
42 struct il_host_cmd;
43 struct il_cmd;
44 struct il_tx_queue;
45 
46 #define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
47 #define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
48 #define IL_WARN_ONCE(f, a...) dev_warn_once(&il->pci_dev->dev, f, ## a)
49 #define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
50 
51 #define RX_QUEUE_SIZE                         256
52 #define RX_QUEUE_MASK                         255
53 #define RX_QUEUE_SIZE_LOG                     8
54 
55 /*
56  * RX related structures and functions
57  */
58 #define RX_FREE_BUFFERS 64
59 #define RX_LOW_WATERMARK 8
60 
61 #define U32_PAD(n)		((4-(n))&0x3)
62 
63 /* CT-KILL constants */
64 #define CT_KILL_THRESHOLD_LEGACY   110	/* in Celsius */
65 
66 /* Default noise level to report when noise measurement is not available.
67  *   This may be because we're:
68  *   1)  Not associated (4965, no beacon stats being sent to driver)
69  *   2)  Scanning (noise measurement does not apply to associated channel)
70  *   3)  Receiving CCK (3945 delivers noise info only for OFDM frames)
71  * Use default noise value of -127 ... this is below the range of measurable
72  *   Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
73  *   Also, -127 works better than 0 when averaging frames with/without
74  *   noise info (e.g. averaging might be done in app); measured dBm values are
75  *   always negative ... using a negative value as the default keeps all
76  *   averages within an s8's (used in some apps) range of negative values. */
77 #define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
78 
79 /*
80  * RTS threshold here is total size [2347] minus 4 FCS bytes
81  * Per spec:
82  *   a value of 0 means RTS on all data/management packets
83  *   a value > max MSDU size means no RTS
84  * else RTS for data/management frames where MPDU is larger
85  *   than RTS value.
86  */
87 #define DEFAULT_RTS_THRESHOLD     2347U
88 #define MIN_RTS_THRESHOLD         0U
89 #define MAX_RTS_THRESHOLD         2347U
90 #define MAX_MSDU_SIZE		  2304U
91 #define MAX_MPDU_SIZE		  2346U
92 #define DEFAULT_BEACON_INTERVAL   100U
93 #define	DEFAULT_SHORT_RETRY_LIMIT 7U
94 #define	DEFAULT_LONG_RETRY_LIMIT  4U
95 
96 struct il_rx_buf {
97 	dma_addr_t page_dma;
98 	struct page *page;
99 	struct list_head list;
100 };
101 
102 #define rxb_addr(r) page_address(r->page)
103 
104 /* defined below */
105 struct il_device_cmd;
106 
107 struct il_cmd_meta {
108 	/* only for SYNC commands, iff the reply skb is wanted */
109 	struct il_host_cmd *source;
110 	/*
111 	 * only for ASYNC commands
112 	 * (which is somewhat stupid -- look at common.c for instance
113 	 * which duplicates a bunch of code because the callback isn't
114 	 * invoked for SYNC commands, if it were and its result passed
115 	 * through it would be simpler...)
116 	 */
117 	void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
118 			  struct il_rx_pkt *pkt);
119 
120 	/* The CMD_SIZE_HUGE flag bit indicates that the command
121 	 * structure is stored at the end of the shared queue memory. */
122 	u32 flags;
123 
124 	 DEFINE_DMA_UNMAP_ADDR(mapping);
125 	 DEFINE_DMA_UNMAP_LEN(len);
126 };
127 
128 /*
129  * Generic queue structure
130  *
131  * Contains common data for Rx and Tx queues
132  */
133 struct il_queue {
134 	int n_bd;		/* number of BDs in this queue */
135 	int write_ptr;		/* 1-st empty entry (idx) host_w */
136 	int read_ptr;		/* last used entry (idx) host_r */
137 	/* use for monitoring and recovering the stuck queue */
138 	dma_addr_t dma_addr;	/* physical addr for BD's */
139 	int n_win;		/* safe queue win */
140 	u32 id;
141 	int low_mark;		/* low watermark, resume queue if free
142 				 * space more than this */
143 	int high_mark;		/* high watermark, stop queue if free
144 				 * space less than this */
145 };
146 
147 /**
148  * struct il_tx_queue - Tx Queue for DMA
149  * @q: generic Rx/Tx queue descriptor
150  * @bd: base of circular buffer of TFDs
151  * @cmd: array of command/TX buffer pointers
152  * @meta: array of meta data for each command/tx buffer
153  * @dma_addr_cmd: physical address of cmd/tx buffer array
154  * @skbs: array of per-TFD socket buffer pointers
155  * @time_stamp: time (in jiffies) of last read_ptr change
156  * @need_update: indicates need to update read/write idx
157  * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
158  *
159  * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
160  * descriptors) and required locking structures.
161  */
162 #define TFD_TX_CMD_SLOTS 256
163 #define TFD_CMD_SLOTS 32
164 
165 struct il_tx_queue {
166 	struct il_queue q;
167 	void *tfds;
168 	struct il_device_cmd **cmd;
169 	struct il_cmd_meta *meta;
170 	struct sk_buff **skbs;
171 	unsigned long time_stamp;
172 	u8 need_update;
173 	u8 sched_retry;
174 	u8 active;
175 	u8 swq_id;
176 };
177 
178 /*
179  * EEPROM access time values:
180  *
181  * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
182  * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
183  * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
184  * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
185  */
186 #define IL_EEPROM_ACCESS_TIMEOUT	5000	/* uSec */
187 
188 #define IL_EEPROM_SEM_TIMEOUT		10	/* microseconds */
189 #define IL_EEPROM_SEM_RETRY_LIMIT	1000	/* number of attempts (not time) */
190 
191 /*
192  * Regulatory channel usage flags in EEPROM struct il4965_eeprom_channel.flags.
193  *
194  * IBSS and/or AP operation is allowed *only* on those channels with
195  * (VALID && IBSS && ACTIVE && !RADAR).  This restriction is in place because
196  * RADAR detection is not supported by the 4965 driver, but is a
197  * requirement for establishing a new network for legal operation on channels
198  * requiring RADAR detection or restricting ACTIVE scanning.
199  *
200  * NOTE:  "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
201  *        It only indicates that 20 MHz channel use is supported; HT40 channel
202  *        usage is indicated by a separate set of regulatory flags for each
203  *        HT40 channel pair.
204  *
205  * NOTE:  Using a channel inappropriately will result in a uCode error!
206  */
207 #define IL_NUM_TX_CALIB_GROUPS 5
208 enum {
209 	EEPROM_CHANNEL_VALID = (1 << 0),	/* usable for this SKU/geo */
210 	EEPROM_CHANNEL_IBSS = (1 << 1),	/* usable as an IBSS channel */
211 	/* Bit 2 Reserved */
212 	EEPROM_CHANNEL_ACTIVE = (1 << 3),	/* active scanning allowed */
213 	EEPROM_CHANNEL_RADAR = (1 << 4),	/* radar detection required */
214 	EEPROM_CHANNEL_WIDE = (1 << 5),	/* 20 MHz channel okay */
215 	/* Bit 6 Reserved (was Narrow Channel) */
216 	EEPROM_CHANNEL_DFS = (1 << 7),	/* dynamic freq selection candidate */
217 };
218 
219 /* SKU Capabilities */
220 /* 3945 only */
221 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE                (1 << 0)
222 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE                (1 << 1)
223 
224 /* *regulatory* channel data format in eeprom, one for each channel.
225  * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
226 struct il_eeprom_channel {
227 	u8 flags;		/* EEPROM_CHANNEL_* flags copied from EEPROM */
228 	s8 max_power_avg;	/* max power (dBm) on this chnl, limit 31 */
229 } __packed;
230 
231 /* 3945 Specific */
232 #define EEPROM_3945_EEPROM_VERSION	(0x2f)
233 
234 /* 4965 has two radio transmitters (and 3 radio receivers) */
235 #define EEPROM_TX_POWER_TX_CHAINS      (2)
236 
237 /* 4965 has room for up to 8 sets of txpower calibration data */
238 #define EEPROM_TX_POWER_BANDS          (8)
239 
240 /* 4965 factory calibration measures txpower gain settings for
241  * each of 3 target output levels */
242 #define EEPROM_TX_POWER_MEASUREMENTS   (3)
243 
244 /* 4965 Specific */
245 /* 4965 driver does not work with txpower calibration version < 5 */
246 #define EEPROM_4965_TX_POWER_VERSION    (5)
247 #define EEPROM_4965_EEPROM_VERSION	(0x2f)
248 #define EEPROM_4965_CALIB_VERSION_OFFSET       (2*0xB6)	/* 2 bytes */
249 #define EEPROM_4965_CALIB_TXPOWER_OFFSET       (2*0xE8)	/* 48  bytes */
250 #define EEPROM_4965_BOARD_REVISION             (2*0x4F)	/* 2 bytes */
251 #define EEPROM_4965_BOARD_PBA                  (2*0x56+1)	/* 9 bytes */
252 
253 /* 2.4 GHz */
254 extern const u8 il_eeprom_band_1[14];
255 
256 /*
257  * factory calibration data for one txpower level, on one channel,
258  * measured on one of the 2 tx chains (radio transmitter and associated
259  * antenna).  EEPROM contains:
260  *
261  * 1)  Temperature (degrees Celsius) of device when measurement was made.
262  *
263  * 2)  Gain table idx used to achieve the target measurement power.
264  *     This refers to the "well-known" gain tables (see 4965.h).
265  *
266  * 3)  Actual measured output power, in half-dBm ("34" = 17 dBm).
267  *
268  * 4)  RF power amplifier detector level measurement (not used).
269  */
270 struct il_eeprom_calib_measure {
271 	u8 temperature;		/* Device temperature (Celsius) */
272 	u8 gain_idx;		/* Index into gain table */
273 	u8 actual_pow;		/* Measured RF output power, half-dBm */
274 	s8 pa_det;		/* Power amp detector level (not used) */
275 } __packed;
276 
277 /*
278  * measurement set for one channel.  EEPROM contains:
279  *
280  * 1)  Channel number measured
281  *
282  * 2)  Measurements for each of 3 power levels for each of 2 radio transmitters
283  *     (a.k.a. "tx chains") (6 measurements altogether)
284  */
285 struct il_eeprom_calib_ch_info {
286 	u8 ch_num;
287 	struct il_eeprom_calib_measure
288 	    measurements[EEPROM_TX_POWER_TX_CHAINS]
289 	    [EEPROM_TX_POWER_MEASUREMENTS];
290 } __packed;
291 
292 /*
293  * txpower subband info.
294  *
295  * For each frequency subband, EEPROM contains the following:
296  *
297  * 1)  First and last channels within range of the subband.  "0" values
298  *     indicate that this sample set is not being used.
299  *
300  * 2)  Sample measurement sets for 2 channels close to the range endpoints.
301  */
302 struct il_eeprom_calib_subband_info {
303 	u8 ch_from;		/* channel number of lowest channel in subband */
304 	u8 ch_to;		/* channel number of highest channel in subband */
305 	struct il_eeprom_calib_ch_info ch1;
306 	struct il_eeprom_calib_ch_info ch2;
307 } __packed;
308 
309 /*
310  * txpower calibration info.  EEPROM contains:
311  *
312  * 1)  Factory-measured saturation power levels (maximum levels at which
313  *     tx power amplifier can output a signal without too much distortion).
314  *     There is one level for 2.4 GHz band and one for 5 GHz band.  These
315  *     values apply to all channels within each of the bands.
316  *
317  * 2)  Factory-measured power supply voltage level.  This is assumed to be
318  *     constant (i.e. same value applies to all channels/bands) while the
319  *     factory measurements are being made.
320  *
321  * 3)  Up to 8 sets of factory-measured txpower calibration values.
322  *     These are for different frequency ranges, since txpower gain
323  *     characteristics of the analog radio circuitry vary with frequency.
324  *
325  *     Not all sets need to be filled with data;
326  *     struct il_eeprom_calib_subband_info contains range of channels
327  *     (0 if unused) for each set of data.
328  */
329 struct il_eeprom_calib_info {
330 	u8 saturation_power24;	/* half-dBm (e.g. "34" = 17 dBm) */
331 	u8 saturation_power52;	/* half-dBm */
332 	__le16 voltage;		/* signed */
333 	struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
334 } __packed;
335 
336 /* General */
337 #define EEPROM_DEVICE_ID                    (2*0x08)	/* 2 bytes */
338 #define EEPROM_MAC_ADDRESS                  (2*0x15)	/* 6  bytes */
339 #define EEPROM_BOARD_REVISION               (2*0x35)	/* 2  bytes */
340 #define EEPROM_BOARD_PBA_NUMBER             (2*0x3B+1)	/* 9  bytes */
341 #define EEPROM_VERSION                      (2*0x44)	/* 2  bytes */
342 #define EEPROM_SKU_CAP                      (2*0x45)	/* 2  bytes */
343 #define EEPROM_OEM_MODE                     (2*0x46)	/* 2  bytes */
344 #define EEPROM_WOWLAN_MODE                  (2*0x47)	/* 2  bytes */
345 #define EEPROM_RADIO_CONFIG                 (2*0x48)	/* 2  bytes */
346 #define EEPROM_NUM_MAC_ADDRESS              (2*0x4C)	/* 2  bytes */
347 
348 /* The following masks are to be applied on EEPROM_RADIO_CONFIG */
349 #define EEPROM_RF_CFG_TYPE_MSK(x)   (x & 0x3)	/* bits 0-1   */
350 #define EEPROM_RF_CFG_STEP_MSK(x)   ((x >> 2)  & 0x3)	/* bits 2-3   */
351 #define EEPROM_RF_CFG_DASH_MSK(x)   ((x >> 4)  & 0x3)	/* bits 4-5   */
352 #define EEPROM_RF_CFG_PNUM_MSK(x)   ((x >> 6)  & 0x3)	/* bits 6-7   */
353 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8)  & 0xF)	/* bits 8-11  */
354 #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF)	/* bits 12-15 */
355 
356 #define EEPROM_3945_RF_CFG_TYPE_MAX  0x0
357 #define EEPROM_4965_RF_CFG_TYPE_MAX  0x1
358 
359 /*
360  * Per-channel regulatory data.
361  *
362  * Each channel that *might* be supported by iwl has a fixed location
363  * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
364  * txpower (MSB).
365  *
366  * Entries immediately below are for 20 MHz channel width.  HT40 (40 MHz)
367  * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
368  *
369  * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
370  */
371 #define EEPROM_REGULATORY_SKU_ID            (2*0x60)	/* 4  bytes */
372 #define EEPROM_REGULATORY_BAND_1            (2*0x62)	/* 2  bytes */
373 #define EEPROM_REGULATORY_BAND_1_CHANNELS   (2*0x63)	/* 28 bytes */
374 
375 /*
376  * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
377  * 5.0 GHz channels 7, 8, 11, 12, 16
378  * (4915-5080MHz) (none of these is ever supported)
379  */
380 #define EEPROM_REGULATORY_BAND_2            (2*0x71)	/* 2  bytes */
381 #define EEPROM_REGULATORY_BAND_2_CHANNELS   (2*0x72)	/* 26 bytes */
382 
383 /*
384  * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
385  * (5170-5320MHz)
386  */
387 #define EEPROM_REGULATORY_BAND_3            (2*0x7F)	/* 2  bytes */
388 #define EEPROM_REGULATORY_BAND_3_CHANNELS   (2*0x80)	/* 24 bytes */
389 
390 /*
391  * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
392  * (5500-5700MHz)
393  */
394 #define EEPROM_REGULATORY_BAND_4            (2*0x8C)	/* 2  bytes */
395 #define EEPROM_REGULATORY_BAND_4_CHANNELS   (2*0x8D)	/* 22 bytes */
396 
397 /*
398  * 5.7 GHz channels 145, 149, 153, 157, 161, 165
399  * (5725-5825MHz)
400  */
401 #define EEPROM_REGULATORY_BAND_5            (2*0x98)	/* 2  bytes */
402 #define EEPROM_REGULATORY_BAND_5_CHANNELS   (2*0x99)	/* 12 bytes */
403 
404 /*
405  * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
406  *
407  * The channel listed is the center of the lower 20 MHz half of the channel.
408  * The overall center frequency is actually 2 channels (10 MHz) above that,
409  * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away
410  * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5,
411  * and the overall HT40 channel width centers on channel 3.
412  *
413  * NOTE:  The RXON command uses 20 MHz channel numbers to specify the
414  *        control channel to which to tune.  RXON also specifies whether the
415  *        control channel is the upper or lower half of a HT40 channel.
416  *
417  * NOTE:  4965 does not support HT40 channels on 2.4 GHz.
418  */
419 #define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0)	/* 14 bytes */
420 
421 /*
422  * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64),
423  * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
424  */
425 #define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8)	/* 22 bytes */
426 
427 #define EEPROM_REGULATORY_BAND_NO_HT40			(0)
428 
429 int il_eeprom_init(struct il_priv *il);
430 void il_eeprom_free(struct il_priv *il);
431 const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
432 u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
433 int il_init_channel_map(struct il_priv *il);
434 void il_free_channel_map(struct il_priv *il);
435 const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
436 						  enum nl80211_band band,
437 						  u16 channel);
438 
439 #define IL_NUM_SCAN_RATES         (2)
440 
441 struct il4965_channel_tgd_info {
442 	u8 type;
443 	s8 max_power;
444 };
445 
446 struct il4965_channel_tgh_info {
447 	s64 last_radar_time;
448 };
449 
450 #define IL4965_MAX_RATE (33)
451 
452 struct il3945_clip_group {
453 	/* maximum power level to prevent clipping for each rate, derived by
454 	 *   us from this band's saturation power in EEPROM */
455 	const s8 clip_powers[IL_MAX_RATES];
456 };
457 
458 /* current Tx power values to use, one for each rate for each channel.
459  * requested power is limited by:
460  * -- regulatory EEPROM limits for this channel
461  * -- hardware capabilities (clip-powers)
462  * -- spectrum management
463  * -- user preference (e.g. iwconfig)
464  * when requested power is set, base power idx must also be set. */
465 struct il3945_channel_power_info {
466 	struct il3945_tx_power tpc;	/* actual radio and DSP gain settings */
467 	s8 power_table_idx;	/* actual (compenst'd) idx into gain table */
468 	s8 base_power_idx;	/* gain idx for power at factory temp. */
469 	s8 requested_power;	/* power (dBm) requested for this chnl/rate */
470 };
471 
472 /* current scan Tx power values to use, one for each scan rate for each
473  * channel. */
474 struct il3945_scan_power_info {
475 	struct il3945_tx_power tpc;	/* actual radio and DSP gain settings */
476 	s8 power_table_idx;	/* actual (compenst'd) idx into gain table */
477 	s8 requested_power;	/* scan pwr (dBm) requested for chnl/rate */
478 };
479 
480 /*
481  * One for each channel, holds all channel setup data
482  * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
483  *     with one another!
484  */
485 struct il_channel_info {
486 	struct il4965_channel_tgd_info tgd;
487 	struct il4965_channel_tgh_info tgh;
488 	struct il_eeprom_channel eeprom;	/* EEPROM regulatory limit */
489 	struct il_eeprom_channel ht40_eeprom;	/* EEPROM regulatory limit for
490 						 * HT40 channel */
491 
492 	u8 channel;		/* channel number */
493 	u8 flags;		/* flags copied from EEPROM */
494 	s8 max_power_avg;	/* (dBm) regul. eeprom, normal Tx, any rate */
495 	s8 curr_txpow;		/* (dBm) regulatory/spectrum/user (not h/w) limit */
496 	s8 min_power;		/* always 0 */
497 	s8 scan_power;		/* (dBm) regul. eeprom, direct scans, any rate */
498 
499 	u8 group_idx;		/* 0-4, maps channel to group1/2/3/4/5 */
500 	u8 band_idx;		/* 0-4, maps channel to band1/2/3/4/5 */
501 	enum nl80211_band band;
502 
503 	/* HT40 channel info */
504 	s8 ht40_max_power_avg;	/* (dBm) regul. eeprom, normal Tx, any rate */
505 	u8 ht40_flags;		/* flags copied from EEPROM */
506 	u8 ht40_extension_channel;	/* HT_IE_EXT_CHANNEL_* */
507 
508 	/* Radio/DSP gain settings for each "normal" data Tx rate.
509 	 * These include, in addition to RF and DSP gain, a few fields for
510 	 *   remembering/modifying gain settings (idxes). */
511 	struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
512 
513 	/* Radio/DSP gain settings for each scan rate, for directed scans. */
514 	struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
515 };
516 
517 #define IL_TX_FIFO_BK		0	/* shared */
518 #define IL_TX_FIFO_BE		1
519 #define IL_TX_FIFO_VI		2	/* shared */
520 #define IL_TX_FIFO_VO		3
521 #define IL_TX_FIFO_UNUSED	-1
522 
523 /* Minimum number of queues. MAX_NUM is defined in hw specific files.
524  * Set the minimum to accommodate the 4 standard TX queues, 1 command
525  * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
526 #define IL_MIN_NUM_QUEUES	10
527 
528 #define IL_DEFAULT_CMD_QUEUE_NUM	4
529 
530 #define IEEE80211_DATA_LEN              2304
531 #define IEEE80211_4ADDR_LEN             30
532 #define IEEE80211_HLEN                  (IEEE80211_4ADDR_LEN)
533 #define IEEE80211_FRAME_LEN             (IEEE80211_DATA_LEN + IEEE80211_HLEN)
534 
535 struct il_frame {
536 	union {
537 		struct ieee80211_hdr frame;
538 		struct il_tx_beacon_cmd beacon;
539 		u8 raw[IEEE80211_FRAME_LEN];
540 		u8 cmd[360];
541 	} u;
542 	struct list_head list;
543 };
544 
545 enum {
546 	CMD_SYNC = 0,
547 	CMD_SIZE_NORMAL = 0,
548 	CMD_NO_SKB = 0,
549 	CMD_SIZE_HUGE = (1 << 0),
550 	CMD_ASYNC = (1 << 1),
551 	CMD_WANT_SKB = (1 << 2),
552 	CMD_MAPPED = (1 << 3),
553 };
554 
555 #define DEF_CMD_PAYLOAD_SIZE 320
556 
557 /**
558  * struct il_device_cmd
559  *
560  * For allocation of the command and tx queues, this establishes the overall
561  * size of the largest command we send to uCode, except for a scan command
562  * (which is relatively huge; space is allocated separately).
563  */
564 struct il_device_cmd {
565 	struct il_cmd_header hdr;	/* uCode API */
566 	union {
567 		u32 flags;
568 		u8 val8;
569 		u16 val16;
570 		u32 val32;
571 		struct il_tx_cmd tx;
572 		u8 payload[DEF_CMD_PAYLOAD_SIZE];
573 	} __packed cmd;
574 } __packed;
575 
576 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
577 
578 struct il_host_cmd {
579 	const void *data;
580 	unsigned long reply_page;
581 	void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
582 			  struct il_rx_pkt *pkt);
583 	u32 flags;
584 	u16 len;
585 	u8 id;
586 };
587 
588 #define SUP_RATE_11A_MAX_NUM_CHANNELS  8
589 #define SUP_RATE_11B_MAX_NUM_CHANNELS  4
590 #define SUP_RATE_11G_MAX_NUM_CHANNELS  12
591 
592 /**
593  * struct il_rx_queue - Rx queue
594  * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
595  * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
596  * @read: Shared idx to newest available Rx buffer
597  * @write: Shared idx to oldest written Rx packet
598  * @free_count: Number of pre-allocated buffers in rx_free
599  * @rx_free: list of free SKBs for use
600  * @rx_used: List of Rx buffers with no SKB
601  * @need_update: flag to indicate we need to update read/write idx
602  * @rb_stts: driver's pointer to receive buffer status
603  * @rb_stts_dma: bus address of receive buffer status
604  *
605  * NOTE:  rx_free and rx_used are used as a FIFO for il_rx_bufs
606  */
607 struct il_rx_queue {
608 	__le32 *bd;
609 	dma_addr_t bd_dma;
610 	struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
611 	struct il_rx_buf *queue[RX_QUEUE_SIZE];
612 	u32 read;
613 	u32 write;
614 	u32 free_count;
615 	u32 write_actual;
616 	struct list_head rx_free;
617 	struct list_head rx_used;
618 	int need_update;
619 	struct il_rb_status *rb_stts;
620 	dma_addr_t rb_stts_dma;
621 	spinlock_t lock;
622 };
623 
624 #define IL_SUPPORTED_RATES_IE_LEN         8
625 
626 #define MAX_TID_COUNT        9
627 
628 #define IL_INVALID_RATE     0xFF
629 #define IL_INVALID_VALUE    -1
630 
631 /**
632  * struct il_ht_agg -- aggregation status while waiting for block-ack
633  * @txq_id: Tx queue used for Tx attempt
634  * @frame_count: # frames attempted by Tx command
635  * @wait_for_ba: Expect block-ack before next Tx reply
636  * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win
637  * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win
638  * @bitmap1: High order, one bit for each frame pending ACK in Tx win
639  * @rate_n_flags: Rate at which Tx was attempted
640  *
641  * If C_TX indicates that aggregation was attempted, driver must wait
642  * for block ack (N_COMPRESSED_BA).  This struct stores tx reply info
643  * until block ack arrives.
644  */
645 struct il_ht_agg {
646 	u16 txq_id;
647 	u16 frame_count;
648 	u16 wait_for_ba;
649 	u16 start_idx;
650 	u64 bitmap;
651 	u32 rate_n_flags;
652 #define IL_AGG_OFF 0
653 #define IL_AGG_ON 1
654 #define IL_EMPTYING_HW_QUEUE_ADDBA 2
655 #define IL_EMPTYING_HW_QUEUE_DELBA 3
656 	u8 state;
657 };
658 
659 struct il_tid_data {
660 	u16 seq_number;		/* 4965 only */
661 	u16 tfds_in_queue;
662 	struct il_ht_agg agg;
663 };
664 
665 struct il_hw_key {
666 	u32 cipher;
667 	int keylen;
668 	u8 keyidx;
669 	u8 key[32];
670 };
671 
672 union il_ht_rate_supp {
673 	u16 rates;
674 	struct {
675 		u8 siso_rate;
676 		u8 mimo_rate;
677 	};
678 };
679 
680 #define CFG_HT_RX_AMPDU_FACTOR_8K   (0x0)
681 #define CFG_HT_RX_AMPDU_FACTOR_16K  (0x1)
682 #define CFG_HT_RX_AMPDU_FACTOR_32K  (0x2)
683 #define CFG_HT_RX_AMPDU_FACTOR_64K  (0x3)
684 #define CFG_HT_RX_AMPDU_FACTOR_DEF  CFG_HT_RX_AMPDU_FACTOR_64K
685 #define CFG_HT_RX_AMPDU_FACTOR_MAX  CFG_HT_RX_AMPDU_FACTOR_64K
686 #define CFG_HT_RX_AMPDU_FACTOR_MIN  CFG_HT_RX_AMPDU_FACTOR_8K
687 
688 /*
689  * Maximal MPDU density for TX aggregation
690  * 4 - 2us density
691  * 5 - 4us density
692  * 6 - 8us density
693  * 7 - 16us density
694  */
695 #define CFG_HT_MPDU_DENSITY_2USEC   (0x4)
696 #define CFG_HT_MPDU_DENSITY_4USEC   (0x5)
697 #define CFG_HT_MPDU_DENSITY_8USEC   (0x6)
698 #define CFG_HT_MPDU_DENSITY_16USEC  (0x7)
699 #define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
700 #define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
701 #define CFG_HT_MPDU_DENSITY_MIN     (0x1)
702 
703 struct il_ht_config {
704 	bool single_chain_sufficient;
705 	enum ieee80211_smps_mode smps;	/* current smps mode */
706 };
707 
708 /* QoS structures */
709 struct il_qos_info {
710 	int qos_active;
711 	struct il_qosparam_cmd def_qos_parm;
712 };
713 
714 /*
715  * Structure should be accessed with sta_lock held. When station addition
716  * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only
717  * the commands (il_addsta_cmd and il_link_quality_cmd) without
718  * sta_lock held.
719  */
720 struct il_station_entry {
721 	struct il_addsta_cmd sta;
722 	struct il_tid_data tid[MAX_TID_COUNT];
723 	u8 used;
724 	struct il_hw_key keyinfo;
725 	struct il_link_quality_cmd *lq;
726 };
727 
728 struct il_station_priv_common {
729 	u8 sta_id;
730 };
731 
732 /**
733  * struct il_vif_priv - driver's ilate per-interface information
734  *
735  * When mac80211 allocates a virtual interface, it can allocate
736  * space for us to put data into.
737  */
738 struct il_vif_priv {
739 	u8 ibss_bssid_sta_id;
740 };
741 
742 /* one for each uCode image (inst/data, boot/init/runtime) */
743 struct fw_desc {
744 	void *v_addr;		/* access by driver */
745 	dma_addr_t p_addr;	/* access by card's busmaster DMA */
746 	u32 len;		/* bytes */
747 };
748 
749 /* uCode file layout */
750 struct il_ucode_header {
751 	__le32 ver;		/* major/minor/API/serial */
752 	struct {
753 		__le32 inst_size;	/* bytes of runtime code */
754 		__le32 data_size;	/* bytes of runtime data */
755 		__le32 init_size;	/* bytes of init code */
756 		__le32 init_data_size;	/* bytes of init data */
757 		__le32 boot_size;	/* bytes of bootstrap code */
758 		u8 data[0];	/* in same order as sizes */
759 	} v1;
760 };
761 
762 struct il4965_ibss_seq {
763 	u8 mac[ETH_ALEN];
764 	u16 seq_num;
765 	u16 frag_num;
766 	unsigned long packet_time;
767 	struct list_head list;
768 };
769 
770 struct il_sensitivity_ranges {
771 	u16 min_nrg_cck;
772 	u16 max_nrg_cck;
773 
774 	u16 nrg_th_cck;
775 	u16 nrg_th_ofdm;
776 
777 	u16 auto_corr_min_ofdm;
778 	u16 auto_corr_min_ofdm_mrc;
779 	u16 auto_corr_min_ofdm_x1;
780 	u16 auto_corr_min_ofdm_mrc_x1;
781 
782 	u16 auto_corr_max_ofdm;
783 	u16 auto_corr_max_ofdm_mrc;
784 	u16 auto_corr_max_ofdm_x1;
785 	u16 auto_corr_max_ofdm_mrc_x1;
786 
787 	u16 auto_corr_max_cck;
788 	u16 auto_corr_max_cck_mrc;
789 	u16 auto_corr_min_cck;
790 	u16 auto_corr_min_cck_mrc;
791 
792 	u16 barker_corr_th_min;
793 	u16 barker_corr_th_min_mrc;
794 	u16 nrg_th_cca;
795 };
796 
797 #define KELVIN_TO_CELSIUS(x) ((x)-273)
798 #define CELSIUS_TO_KELVIN(x) ((x)+273)
799 
800 /**
801  * struct il_hw_params
802  * @bcast_id: f/w broadcast station ID
803  * @max_txq_num: Max # Tx queues supported
804  * @dma_chnl_num: Number of Tx DMA/FIFO channels
805  * @scd_bc_tbls_size: size of scheduler byte count tables
806  * @tfd_size: TFD size
807  * @tx/rx_chains_num: Number of TX/RX chains
808  * @valid_tx/rx_ant: usable antennas
809  * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
810  * @max_rxq_log: Log-base-2 of max_rxq_size
811  * @rx_page_order: Rx buffer page order
812  * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
813  * @max_stations:
814  * @ht40_channel: is 40MHz width possible in band 2.4
815  * BIT(NL80211_BAND_5GHZ) BIT(NL80211_BAND_5GHZ)
816  * @sw_crypto: 0 for hw, 1 for sw
817  * @max_xxx_size: for ucode uses
818  * @ct_kill_threshold: temperature threshold
819  * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
820  * @struct il_sensitivity_ranges: range of sensitivity values
821  */
822 struct il_hw_params {
823 	u8 bcast_id;
824 	u8 max_txq_num;
825 	u8 dma_chnl_num;
826 	u16 scd_bc_tbls_size;
827 	u32 tfd_size;
828 	u8 tx_chains_num;
829 	u8 rx_chains_num;
830 	u8 valid_tx_ant;
831 	u8 valid_rx_ant;
832 	u16 max_rxq_size;
833 	u16 max_rxq_log;
834 	u32 rx_page_order;
835 	u32 rx_wrt_ptr_reg;
836 	u8 max_stations;
837 	u8 ht40_channel;
838 	u8 max_beacon_itrvl;	/* in 1024 ms */
839 	u32 max_inst_size;
840 	u32 max_data_size;
841 	u32 max_bsm_size;
842 	u32 ct_kill_threshold;	/* value in hw-dependent units */
843 	u16 beacon_time_tsf_bits;
844 	const struct il_sensitivity_ranges *sens;
845 };
846 
847 /******************************************************************************
848  *
849  * Functions implemented in core module which are forward declared here
850  * for use by iwl-[4-5].c
851  *
852  * NOTE:  The implementation of these functions are not hardware specific
853  * which is why they are in the core module files.
854  *
855  * Naming convention --
856  * il_         <-- Is part of iwlwifi
857  * iwlXXXX_     <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
858  * il4965_bg_      <-- Called from work queue context
859  * il4965_mac_     <-- mac80211 callback
860  *
861  ****************************************************************************/
862 void il4965_update_chain_flags(struct il_priv *il);
863 extern const u8 il_bcast_addr[ETH_ALEN];
864 int il_queue_space(const struct il_queue *q);
865 static inline int
866 il_queue_used(const struct il_queue *q, int i)
867 {
868 	return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
869 					      i < q->write_ptr) : !(i <
870 								    q->read_ptr
871 								    && i >=
872 								    q->
873 								    write_ptr);
874 }
875 
876 static inline u8
877 il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
878 {
879 	/*
880 	 * This is for init calibration result and scan command which
881 	 * required buffer > TFD_MAX_PAYLOAD_SIZE,
882 	 * the big buffer at end of command array
883 	 */
884 	if (is_huge)
885 		return q->n_win;	/* must be power of 2 */
886 
887 	/* Otherwise, use normal size buffers */
888 	return idx & (q->n_win - 1);
889 }
890 
891 struct il_dma_ptr {
892 	dma_addr_t dma;
893 	void *addr;
894 	size_t size;
895 };
896 
897 #define IL_OPERATION_MODE_AUTO     0
898 #define IL_OPERATION_MODE_HT_ONLY  1
899 #define IL_OPERATION_MODE_MIXED    2
900 #define IL_OPERATION_MODE_20MHZ    3
901 
902 #define IL_TX_CRC_SIZE 4
903 #define IL_TX_DELIMITER_SIZE 4
904 
905 #define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
906 
907 /* Sensitivity and chain noise calibration */
908 #define INITIALIZATION_VALUE		0xFFFF
909 #define IL4965_CAL_NUM_BEACONS		20
910 #define IL_CAL_NUM_BEACONS		16
911 #define MAXIMUM_ALLOWED_PATHLOSS	15
912 
913 #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
914 
915 #define MAX_FA_OFDM  50
916 #define MIN_FA_OFDM  5
917 #define MAX_FA_CCK   50
918 #define MIN_FA_CCK   5
919 
920 #define AUTO_CORR_STEP_OFDM       1
921 
922 #define AUTO_CORR_STEP_CCK     3
923 #define AUTO_CORR_MAX_TH_CCK   160
924 
925 #define NRG_DIFF               2
926 #define NRG_STEP_CCK           2
927 #define NRG_MARGIN             8
928 #define MAX_NUMBER_CCK_NO_FA 100
929 
930 #define AUTO_CORR_CCK_MIN_VAL_DEF    (125)
931 
932 #define CHAIN_A             0
933 #define CHAIN_B             1
934 #define CHAIN_C             2
935 #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
936 #define ALL_BAND_FILTER			0xFF00
937 #define IN_BAND_FILTER			0xFF
938 #define MIN_AVERAGE_NOISE_MAX_VALUE	0xFFFFFFFF
939 
940 #define NRG_NUM_PREV_STAT_L     20
941 #define NUM_RX_CHAINS           3
942 
943 enum il4965_false_alarm_state {
944 	IL_FA_TOO_MANY = 0,
945 	IL_FA_TOO_FEW = 1,
946 	IL_FA_GOOD_RANGE = 2,
947 };
948 
949 enum il4965_chain_noise_state {
950 	IL_CHAIN_NOISE_ALIVE = 0,	/* must be 0 */
951 	IL_CHAIN_NOISE_ACCUMULATE,
952 	IL_CHAIN_NOISE_CALIBRATED,
953 	IL_CHAIN_NOISE_DONE,
954 };
955 
956 enum ucode_type {
957 	UCODE_NONE = 0,
958 	UCODE_INIT,
959 	UCODE_RT
960 };
961 
962 /* Sensitivity calib data */
963 struct il_sensitivity_data {
964 	u32 auto_corr_ofdm;
965 	u32 auto_corr_ofdm_mrc;
966 	u32 auto_corr_ofdm_x1;
967 	u32 auto_corr_ofdm_mrc_x1;
968 	u32 auto_corr_cck;
969 	u32 auto_corr_cck_mrc;
970 
971 	u32 last_bad_plcp_cnt_ofdm;
972 	u32 last_fa_cnt_ofdm;
973 	u32 last_bad_plcp_cnt_cck;
974 	u32 last_fa_cnt_cck;
975 
976 	u32 nrg_curr_state;
977 	u32 nrg_prev_state;
978 	u32 nrg_value[10];
979 	u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
980 	u32 nrg_silence_ref;
981 	u32 nrg_energy_idx;
982 	u32 nrg_silence_idx;
983 	u32 nrg_th_cck;
984 	s32 nrg_auto_corr_silence_diff;
985 	u32 num_in_cck_no_fa;
986 	u32 nrg_th_ofdm;
987 
988 	u16 barker_corr_th_min;
989 	u16 barker_corr_th_min_mrc;
990 	u16 nrg_th_cca;
991 };
992 
993 /* Chain noise (differential Rx gain) calib data */
994 struct il_chain_noise_data {
995 	u32 active_chains;
996 	u32 chain_noise_a;
997 	u32 chain_noise_b;
998 	u32 chain_noise_c;
999 	u32 chain_signal_a;
1000 	u32 chain_signal_b;
1001 	u32 chain_signal_c;
1002 	u16 beacon_count;
1003 	u8 disconn_array[NUM_RX_CHAINS];
1004 	u8 delta_gain_code[NUM_RX_CHAINS];
1005 	u8 radio_write;
1006 	u8 state;
1007 };
1008 
1009 #define	EEPROM_SEM_TIMEOUT 10	/* milliseconds */
1010 #define EEPROM_SEM_RETRY_LIMIT 1000	/* number of attempts (not time) */
1011 
1012 #define IL_TRAFFIC_ENTRIES	(256)
1013 #define IL_TRAFFIC_ENTRY_SIZE  (64)
1014 
1015 enum {
1016 	MEASUREMENT_READY = (1 << 0),
1017 	MEASUREMENT_ACTIVE = (1 << 1),
1018 };
1019 
1020 /* interrupt stats */
1021 struct isr_stats {
1022 	u32 hw;
1023 	u32 sw;
1024 	u32 err_code;
1025 	u32 sch;
1026 	u32 alive;
1027 	u32 rfkill;
1028 	u32 ctkill;
1029 	u32 wakeup;
1030 	u32 rx;
1031 	u32 handlers[IL_CN_MAX];
1032 	u32 tx;
1033 	u32 unhandled;
1034 };
1035 
1036 /* management stats */
1037 enum il_mgmt_stats {
1038 	MANAGEMENT_ASSOC_REQ = 0,
1039 	MANAGEMENT_ASSOC_RESP,
1040 	MANAGEMENT_REASSOC_REQ,
1041 	MANAGEMENT_REASSOC_RESP,
1042 	MANAGEMENT_PROBE_REQ,
1043 	MANAGEMENT_PROBE_RESP,
1044 	MANAGEMENT_BEACON,
1045 	MANAGEMENT_ATIM,
1046 	MANAGEMENT_DISASSOC,
1047 	MANAGEMENT_AUTH,
1048 	MANAGEMENT_DEAUTH,
1049 	MANAGEMENT_ACTION,
1050 	MANAGEMENT_MAX,
1051 };
1052 /* control stats */
1053 enum il_ctrl_stats {
1054 	CONTROL_BACK_REQ = 0,
1055 	CONTROL_BACK,
1056 	CONTROL_PSPOLL,
1057 	CONTROL_RTS,
1058 	CONTROL_CTS,
1059 	CONTROL_ACK,
1060 	CONTROL_CFEND,
1061 	CONTROL_CFENDACK,
1062 	CONTROL_MAX,
1063 };
1064 
1065 struct traffic_stats {
1066 #ifdef CONFIG_IWLEGACY_DEBUGFS
1067 	u32 mgmt[MANAGEMENT_MAX];
1068 	u32 ctrl[CONTROL_MAX];
1069 	u32 data_cnt;
1070 	u64 data_bytes;
1071 #endif
1072 };
1073 
1074 /*
1075  * host interrupt timeout value
1076  * used with setting interrupt coalescing timer
1077  * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1078  *
1079  * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1080  * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1081  */
1082 #define IL_HOST_INT_TIMEOUT_MAX	(0xFF)
1083 #define IL_HOST_INT_TIMEOUT_DEF	(0x40)
1084 #define IL_HOST_INT_TIMEOUT_MIN	(0x0)
1085 #define IL_HOST_INT_CALIB_TIMEOUT_MAX	(0xFF)
1086 #define IL_HOST_INT_CALIB_TIMEOUT_DEF	(0x10)
1087 #define IL_HOST_INT_CALIB_TIMEOUT_MIN	(0x0)
1088 
1089 #define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1090 
1091 /* TX queue watchdog timeouts in mSecs */
1092 #define IL_DEF_WD_TIMEOUT	(2000)
1093 #define IL_LONG_WD_TIMEOUT	(10000)
1094 #define IL_MAX_WD_TIMEOUT	(120000)
1095 
1096 struct il_force_reset {
1097 	int reset_request_count;
1098 	int reset_success_count;
1099 	int reset_reject_count;
1100 	unsigned long reset_duration;
1101 	unsigned long last_force_reset_jiffies;
1102 };
1103 
1104 /* extend beacon time format bit shifting  */
1105 /*
1106  * for _3945 devices
1107  * bits 31:24 - extended
1108  * bits 23:0  - interval
1109  */
1110 #define IL3945_EXT_BEACON_TIME_POS	24
1111 /*
1112  * for _4965 devices
1113  * bits 31:22 - extended
1114  * bits 21:0  - interval
1115  */
1116 #define IL4965_EXT_BEACON_TIME_POS	22
1117 
1118 struct il_rxon_context {
1119 	struct ieee80211_vif *vif;
1120 };
1121 
1122 struct il_power_mgr {
1123 	struct il_powertable_cmd sleep_cmd;
1124 	struct il_powertable_cmd sleep_cmd_next;
1125 	int debug_sleep_level_override;
1126 	bool pci_pm;
1127 	bool ps_disabled;
1128 };
1129 
1130 struct il_priv {
1131 	struct ieee80211_hw *hw;
1132 	struct ieee80211_channel *ieee_channels;
1133 	struct ieee80211_rate *ieee_rates;
1134 
1135 	struct il_cfg *cfg;
1136 	const struct il_ops *ops;
1137 #ifdef CONFIG_IWLEGACY_DEBUGFS
1138 	const struct il_debugfs_ops *debugfs_ops;
1139 #endif
1140 
1141 	/* temporary frame storage list */
1142 	struct list_head free_frames;
1143 	int frames_count;
1144 
1145 	enum nl80211_band band;
1146 	int alloc_rxb_page;
1147 
1148 	void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1149 				     struct il_rx_buf *rxb);
1150 
1151 	struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1152 
1153 	/* spectrum measurement report caching */
1154 	struct il_spectrum_notification measure_report;
1155 	u8 measurement_status;
1156 
1157 	/* ucode beacon time */
1158 	u32 ucode_beacon_time;
1159 	int missed_beacon_threshold;
1160 
1161 	/* track IBSS manager (last beacon) status */
1162 	u32 ibss_manager;
1163 
1164 	/* force reset */
1165 	struct il_force_reset force_reset;
1166 
1167 	/* we allocate array of il_channel_info for NIC's valid channels.
1168 	 *    Access via channel # using indirect idx array */
1169 	struct il_channel_info *channel_info;	/* channel info array */
1170 	u8 channel_count;	/* # of channels */
1171 
1172 	/* thermal calibration */
1173 	s32 temperature;	/* degrees Kelvin */
1174 	s32 last_temperature;
1175 
1176 	/* Scan related variables */
1177 	unsigned long scan_start;
1178 	unsigned long scan_start_tsf;
1179 	void *scan_cmd;
1180 	enum nl80211_band scan_band;
1181 	struct cfg80211_scan_request *scan_request;
1182 	struct ieee80211_vif *scan_vif;
1183 	u8 scan_tx_ant[NUM_NL80211_BANDS];
1184 	u8 mgmt_tx_ant;
1185 
1186 	/* spinlock */
1187 	spinlock_t lock;	/* protect general shared data */
1188 	spinlock_t hcmd_lock;	/* protect hcmd */
1189 	spinlock_t reg_lock;	/* protect hw register access */
1190 	struct mutex mutex;
1191 
1192 	/* basic pci-network driver stuff */
1193 	struct pci_dev *pci_dev;
1194 
1195 	/* pci hardware address support */
1196 	void __iomem *hw_base;
1197 	u32 hw_rev;
1198 	u32 hw_wa_rev;
1199 	u8 rev_id;
1200 
1201 	/* command queue number */
1202 	u8 cmd_queue;
1203 
1204 	/* max number of station keys */
1205 	u8 sta_key_max_num;
1206 
1207 	/* EEPROM MAC addresses */
1208 	struct mac_address addresses[1];
1209 
1210 	/* uCode images, save to reload in case of failure */
1211 	int fw_idx;		/* firmware we're trying to load */
1212 	u32 ucode_ver;		/* version of ucode, copy of
1213 				   il_ucode.ver */
1214 	struct fw_desc ucode_code;	/* runtime inst */
1215 	struct fw_desc ucode_data;	/* runtime data original */
1216 	struct fw_desc ucode_data_backup;	/* runtime data save/restore */
1217 	struct fw_desc ucode_init;	/* initialization inst */
1218 	struct fw_desc ucode_init_data;	/* initialization data */
1219 	struct fw_desc ucode_boot;	/* bootstrap inst */
1220 	enum ucode_type ucode_type;
1221 	u8 ucode_write_complete;	/* the image write is complete */
1222 	char firmware_name[25];
1223 
1224 	struct ieee80211_vif *vif;
1225 
1226 	struct il_qos_info qos_data;
1227 
1228 	struct {
1229 		bool enabled;
1230 		bool is_40mhz;
1231 		bool non_gf_sta_present;
1232 		u8 protection;
1233 		u8 extension_chan_offset;
1234 	} ht;
1235 
1236 	/*
1237 	 * We declare this const so it can only be
1238 	 * changed via explicit cast within the
1239 	 * routines that actually update the physical
1240 	 * hardware.
1241 	 */
1242 	const struct il_rxon_cmd active;
1243 	struct il_rxon_cmd staging;
1244 
1245 	struct il_rxon_time_cmd timing;
1246 
1247 	__le16 switch_channel;
1248 
1249 	/* 1st responses from initialize and runtime uCode images.
1250 	 * _4965's initialize alive response contains some calibration data. */
1251 	struct il_init_alive_resp card_alive_init;
1252 	struct il_alive_resp card_alive;
1253 
1254 	u16 active_rate;
1255 
1256 	u8 start_calib;
1257 	struct il_sensitivity_data sensitivity_data;
1258 	struct il_chain_noise_data chain_noise_data;
1259 	__le16 sensitivity_tbl[HD_TBL_SIZE];
1260 
1261 	struct il_ht_config current_ht_config;
1262 
1263 	/* Rate scaling data */
1264 	u8 retry_rate;
1265 
1266 	wait_queue_head_t wait_command_queue;
1267 
1268 	int activity_timer_active;
1269 
1270 	/* Rx and Tx DMA processing queues */
1271 	struct il_rx_queue rxq;
1272 	struct il_tx_queue *txq;
1273 	unsigned long txq_ctx_active_msk;
1274 	struct il_dma_ptr kw;	/* keep warm address */
1275 	struct il_dma_ptr scd_bc_tbls;
1276 
1277 	u32 scd_base_addr;	/* scheduler sram base address */
1278 
1279 	unsigned long status;
1280 
1281 	/* counts mgmt, ctl, and data packets */
1282 	struct traffic_stats tx_stats;
1283 	struct traffic_stats rx_stats;
1284 
1285 	/* counts interrupts */
1286 	struct isr_stats isr_stats;
1287 
1288 	struct il_power_mgr power_data;
1289 
1290 	/* context information */
1291 	u8 bssid[ETH_ALEN];	/* used only on 3945 but filled by core */
1292 
1293 	/* station table variables */
1294 
1295 	/* Note: if lock and sta_lock are needed, lock must be acquired first */
1296 	spinlock_t sta_lock;
1297 	int num_stations;
1298 	struct il_station_entry stations[IL_STATION_COUNT];
1299 	unsigned long ucode_key_table;
1300 
1301 	/* queue refcounts */
1302 #define IL_MAX_HW_QUEUES	32
1303 	unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1304 #define IL_STOP_REASON_PASSIVE	0
1305 	unsigned long stop_reason;
1306 	/* for each AC */
1307 	atomic_t queue_stop_count[4];
1308 
1309 	/* Indication if ieee80211_ops->open has been called */
1310 	u8 is_open;
1311 
1312 	u8 mac80211_registered;
1313 
1314 	/* eeprom -- this is in the card's little endian byte order */
1315 	u8 *eeprom;
1316 	struct il_eeprom_calib_info *calib_info;
1317 
1318 	enum nl80211_iftype iw_mode;
1319 
1320 	/* Last Rx'd beacon timestamp */
1321 	u64 timestamp;
1322 
1323 	union {
1324 #if IS_ENABLED(CONFIG_IWL3945)
1325 		struct {
1326 			void *shared_virt;
1327 			dma_addr_t shared_phys;
1328 
1329 			struct delayed_work thermal_periodic;
1330 			struct delayed_work rfkill_poll;
1331 
1332 			struct il3945_notif_stats stats;
1333 #ifdef CONFIG_IWLEGACY_DEBUGFS
1334 			struct il3945_notif_stats accum_stats;
1335 			struct il3945_notif_stats delta_stats;
1336 			struct il3945_notif_stats max_delta;
1337 #endif
1338 
1339 			u32 sta_supp_rates;
1340 			int last_rx_rssi;	/* From Rx packet stats */
1341 
1342 			/* Rx'd packet timing information */
1343 			u32 last_beacon_time;
1344 			u64 last_tsf;
1345 
1346 			/*
1347 			 * each calibration channel group in the
1348 			 * EEPROM has a derived clip setting for
1349 			 * each rate.
1350 			 */
1351 			const struct il3945_clip_group clip_groups[5];
1352 
1353 		} _3945;
1354 #endif
1355 #if IS_ENABLED(CONFIG_IWL4965)
1356 		struct {
1357 			struct il_rx_phy_res last_phy_res;
1358 			bool last_phy_res_valid;
1359 			u32 ampdu_ref;
1360 
1361 			struct completion firmware_loading_complete;
1362 
1363 			/*
1364 			 * chain noise reset and gain commands are the
1365 			 * two extra calibration commands follows the standard
1366 			 * phy calibration commands
1367 			 */
1368 			u8 phy_calib_chain_noise_reset_cmd;
1369 			u8 phy_calib_chain_noise_gain_cmd;
1370 
1371 			u8 key_mapping_keys;
1372 			struct il_wep_key wep_keys[WEP_KEYS_MAX];
1373 
1374 			struct il_notif_stats stats;
1375 #ifdef CONFIG_IWLEGACY_DEBUGFS
1376 			struct il_notif_stats accum_stats;
1377 			struct il_notif_stats delta_stats;
1378 			struct il_notif_stats max_delta;
1379 #endif
1380 
1381 		} _4965;
1382 #endif
1383 	};
1384 
1385 	struct il_hw_params hw_params;
1386 
1387 	u32 inta_mask;
1388 
1389 	struct workqueue_struct *workqueue;
1390 
1391 	struct work_struct restart;
1392 	struct work_struct scan_completed;
1393 	struct work_struct rx_replenish;
1394 	struct work_struct abort_scan;
1395 
1396 	bool beacon_enabled;
1397 	struct sk_buff *beacon_skb;
1398 
1399 	struct work_struct tx_flush;
1400 
1401 	struct tasklet_struct irq_tasklet;
1402 
1403 	struct delayed_work init_alive_start;
1404 	struct delayed_work alive_start;
1405 	struct delayed_work scan_check;
1406 
1407 	/* TX Power */
1408 	s8 tx_power_user_lmt;
1409 	s8 tx_power_device_lmt;
1410 	s8 tx_power_next;
1411 
1412 #ifdef CONFIG_IWLEGACY_DEBUG
1413 	/* debugging info */
1414 	u32 debug_level;	/* per device debugging will override global
1415 				   il_debug_level if set */
1416 #endif				/* CONFIG_IWLEGACY_DEBUG */
1417 #ifdef CONFIG_IWLEGACY_DEBUGFS
1418 	/* debugfs */
1419 	u16 tx_traffic_idx;
1420 	u16 rx_traffic_idx;
1421 	u8 *tx_traffic;
1422 	u8 *rx_traffic;
1423 	struct dentry *debugfs_dir;
1424 	u32 dbgfs_sram_offset, dbgfs_sram_len;
1425 	bool disable_ht40;
1426 #endif				/* CONFIG_IWLEGACY_DEBUGFS */
1427 
1428 	struct work_struct txpower_work;
1429 	bool disable_sens_cal;
1430 	bool disable_chain_noise_cal;
1431 	bool disable_tx_power_cal;
1432 	struct work_struct run_time_calib_work;
1433 	struct timer_list stats_periodic;
1434 	struct timer_list watchdog;
1435 	bool hw_ready;
1436 
1437 	struct led_classdev led;
1438 	unsigned long blink_on, blink_off;
1439 	bool led_registered;
1440 };				/*il_priv */
1441 
1442 static inline void
1443 il_txq_ctx_activate(struct il_priv *il, int txq_id)
1444 {
1445 	set_bit(txq_id, &il->txq_ctx_active_msk);
1446 }
1447 
1448 static inline void
1449 il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
1450 {
1451 	clear_bit(txq_id, &il->txq_ctx_active_msk);
1452 }
1453 
1454 static inline int
1455 il_is_associated(struct il_priv *il)
1456 {
1457 	return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1458 }
1459 
1460 static inline int
1461 il_is_any_associated(struct il_priv *il)
1462 {
1463 	return il_is_associated(il);
1464 }
1465 
1466 static inline int
1467 il_is_channel_valid(const struct il_channel_info *ch_info)
1468 {
1469 	if (ch_info == NULL)
1470 		return 0;
1471 	return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1472 }
1473 
1474 static inline int
1475 il_is_channel_radar(const struct il_channel_info *ch_info)
1476 {
1477 	return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1478 }
1479 
1480 static inline u8
1481 il_is_channel_a_band(const struct il_channel_info *ch_info)
1482 {
1483 	return ch_info->band == NL80211_BAND_5GHZ;
1484 }
1485 
1486 static inline int
1487 il_is_channel_passive(const struct il_channel_info *ch)
1488 {
1489 	return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1490 }
1491 
1492 static inline int
1493 il_is_channel_ibss(const struct il_channel_info *ch)
1494 {
1495 	return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1496 }
1497 
1498 static inline void
1499 __il_free_pages(struct il_priv *il, struct page *page)
1500 {
1501 	__free_pages(page, il->hw_params.rx_page_order);
1502 	il->alloc_rxb_page--;
1503 }
1504 
1505 static inline void
1506 il_free_pages(struct il_priv *il, unsigned long page)
1507 {
1508 	free_pages(page, il->hw_params.rx_page_order);
1509 	il->alloc_rxb_page--;
1510 }
1511 
1512 #define IWLWIFI_VERSION "in-tree:"
1513 #define DRV_COPYRIGHT	"Copyright(c) 2003-2011 Intel Corporation"
1514 #define DRV_AUTHOR     "<ilw@linux.intel.com>"
1515 
1516 #define IL_PCI_DEVICE(dev, subdev, cfg) \
1517 	.vendor = PCI_VENDOR_ID_INTEL,  .device = (dev), \
1518 	.subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1519 	.driver_data = (kernel_ulong_t)&(cfg)
1520 
1521 #define TIME_UNIT		1024
1522 
1523 #define IL_SKU_G       0x1
1524 #define IL_SKU_A       0x2
1525 #define IL_SKU_N       0x8
1526 
1527 #define IL_CMD(x) case x: return #x
1528 
1529 /* Size of one Rx buffer in host DRAM */
1530 #define IL_RX_BUF_SIZE_3K (3 * 1000)	/* 3945 only */
1531 #define IL_RX_BUF_SIZE_4K (4 * 1024)
1532 #define IL_RX_BUF_SIZE_8K (8 * 1024)
1533 
1534 #ifdef CONFIG_IWLEGACY_DEBUGFS
1535 struct il_debugfs_ops {
1536 	ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1537 				 size_t count, loff_t *ppos);
1538 	ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1539 				 size_t count, loff_t *ppos);
1540 	ssize_t(*general_stats_read) (struct file *file,
1541 				      char __user *user_buf, size_t count,
1542 				      loff_t *ppos);
1543 };
1544 #endif
1545 
1546 struct il_ops {
1547 	/* Handling TX */
1548 	void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1549 					 struct il_tx_queue *txq,
1550 					 u16 byte_cnt);
1551 	int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1552 				      struct il_tx_queue *txq, dma_addr_t addr,
1553 				      u16 len, u8 reset, u8 pad);
1554 	void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1555 	int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
1556 	/* alive notification after init uCode load */
1557 	void (*init_alive_start) (struct il_priv *il);
1558 	/* check validity of rtc data address */
1559 	int (*is_valid_rtc_data_addr) (u32 addr);
1560 	/* 1st ucode load */
1561 	int (*load_ucode) (struct il_priv *il);
1562 
1563 	void (*dump_nic_error_log) (struct il_priv *il);
1564 	int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1565 	int (*set_channel_switch) (struct il_priv *il,
1566 				   struct ieee80211_channel_switch *ch_switch);
1567 	/* power management */
1568 	int (*apm_init) (struct il_priv *il);
1569 
1570 	/* tx power */
1571 	int (*send_tx_power) (struct il_priv *il);
1572 	void (*update_chain_flags) (struct il_priv *il);
1573 
1574 	/* eeprom operations */
1575 	int (*eeprom_acquire_semaphore) (struct il_priv *il);
1576 	void (*eeprom_release_semaphore) (struct il_priv *il);
1577 
1578 	int (*rxon_assoc) (struct il_priv *il);
1579 	int (*commit_rxon) (struct il_priv *il);
1580 	void (*set_rxon_chain) (struct il_priv *il);
1581 
1582 	u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1583 	u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1584 
1585 	int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1586 	void (*post_scan) (struct il_priv *il);
1587 	void (*post_associate) (struct il_priv *il);
1588 	void (*config_ap) (struct il_priv *il);
1589 	/* station management */
1590 	int (*update_bcast_stations) (struct il_priv *il);
1591 	int (*manage_ibss_station) (struct il_priv *il,
1592 				    struct ieee80211_vif *vif, bool add);
1593 
1594 	int (*send_led_cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
1595 };
1596 
1597 struct il_mod_params {
1598 	int sw_crypto;		/* def: 0 = using hardware encryption */
1599 	int disable_hw_scan;	/* def: 0 = use h/w scan */
1600 	int num_of_queues;	/* def: HW dependent */
1601 	int disable_11n;	/* def: 0 = 11n capabilities enabled */
1602 	int amsdu_size_8K;	/* def: 0 = disable 8K amsdu size */
1603 	int antenna;		/* def: 0 = both antennas (use diversity) */
1604 	int restart_fw;		/* def: 1 = restart firmware */
1605 };
1606 
1607 #define IL_LED_SOLID 11
1608 #define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1609 
1610 #define IL_LED_ACTIVITY       (0<<1)
1611 #define IL_LED_LINK           (1<<1)
1612 
1613 /*
1614  * LED mode
1615  *    IL_LED_DEFAULT:  use device default
1616  *    IL_LED_RF_STATE: turn LED on/off based on RF state
1617  *			LED ON  = RF ON
1618  *			LED OFF = RF OFF
1619  *    IL_LED_BLINK:    adjust led blink rate based on blink table
1620  */
1621 enum il_led_mode {
1622 	IL_LED_DEFAULT,
1623 	IL_LED_RF_STATE,
1624 	IL_LED_BLINK,
1625 };
1626 
1627 void il_leds_init(struct il_priv *il);
1628 void il_leds_exit(struct il_priv *il);
1629 
1630 /**
1631  * struct il_cfg
1632  * @fw_name_pre: Firmware filename prefix. The api version and extension
1633  *	(.ucode) will be added to filename before loading from disk. The
1634  *	filename is constructed as fw_name_pre<api>.ucode.
1635  * @ucode_api_max: Highest version of uCode API supported by driver.
1636  * @ucode_api_min: Lowest version of uCode API supported by driver.
1637  * @scan_antennas: available antenna for scan operation
1638  * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
1639  *
1640  * We enable the driver to be backward compatible wrt API version. The
1641  * driver specifies which APIs it supports (with @ucode_api_max being the
1642  * highest and @ucode_api_min the lowest). Firmware will only be loaded if
1643  * it has a supported API version. The firmware's API version will be
1644  * stored in @il_priv, enabling the driver to make runtime changes based
1645  * on firmware version used.
1646  *
1647  * For example,
1648  * if (IL_UCODE_API(il->ucode_ver) >= 2) {
1649  *	Driver interacts with Firmware API version >= 2.
1650  * } else {
1651  *	Driver interacts with Firmware API version 1.
1652  * }
1653  *
1654  * The ideal usage of this infrastructure is to treat a new ucode API
1655  * release as a new hardware revision. That is, through utilizing the
1656  * il_hcmd_utils_ops etc. we accommodate different command structures
1657  * and flows between hardware versions as well as their API
1658  * versions.
1659  *
1660  */
1661 struct il_cfg {
1662 	/* params specific to an individual device within a device family */
1663 	const char *name;
1664 	const char *fw_name_pre;
1665 	const unsigned int ucode_api_max;
1666 	const unsigned int ucode_api_min;
1667 	u8 valid_tx_ant;
1668 	u8 valid_rx_ant;
1669 	unsigned int sku;
1670 	u16 eeprom_ver;
1671 	u16 eeprom_calib_ver;
1672 	/* module based parameters which can be set from modprobe cmd */
1673 	const struct il_mod_params *mod_params;
1674 	/* params not likely to change within a device family */
1675 	struct il_base_params *base_params;
1676 	/* params likely to change within a device family */
1677 	u8 scan_rx_antennas[NUM_NL80211_BANDS];
1678 	enum il_led_mode led_mode;
1679 
1680 	int eeprom_size;
1681 	int num_of_queues;		/* def: HW dependent */
1682 	int num_of_ampdu_queues;	/* def: HW dependent */
1683 	/* for il_apm_init() */
1684 	u32 pll_cfg_val;
1685 	bool set_l0s;
1686 	bool use_bsm;
1687 
1688 	u16 led_compensation;
1689 	int chain_noise_num_beacons;
1690 	unsigned int wd_timeout;
1691 	bool temperature_kelvin;
1692 	const bool ucode_tracing;
1693 	const bool sensitivity_calib_by_driver;
1694 	const bool chain_noise_calib_by_driver;
1695 
1696 	const u32 regulatory_bands[7];
1697 };
1698 
1699 /***************************
1700  *   L i b                 *
1701  ***************************/
1702 
1703 int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1704 		   u16 queue, const struct ieee80211_tx_queue_params *params);
1705 int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
1706 
1707 void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt);
1708 int il_check_rxon_cmd(struct il_priv *il);
1709 int il_full_rxon_required(struct il_priv *il);
1710 int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch);
1711 void il_set_flags_for_band(struct il_priv *il, enum nl80211_band band,
1712 			   struct ieee80211_vif *vif);
1713 u8 il_get_single_channel_number(struct il_priv *il, enum nl80211_band band);
1714 void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
1715 bool il_is_ht40_tx_allowed(struct il_priv *il,
1716 			   struct ieee80211_sta_ht_cap *ht_cap);
1717 void il_connection_init_rx_config(struct il_priv *il);
1718 void il_set_rate(struct il_priv *il);
1719 int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1720 			  u32 decrypt_res, struct ieee80211_rx_status *stats);
1721 void il_irq_handle_error(struct il_priv *il);
1722 int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1723 void il_mac_remove_interface(struct ieee80211_hw *hw,
1724 			     struct ieee80211_vif *vif);
1725 int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1726 			    enum nl80211_iftype newtype, bool newp2p);
1727 void il_mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1728 		  u32 queues, bool drop);
1729 int il_alloc_txq_mem(struct il_priv *il);
1730 void il_free_txq_mem(struct il_priv *il);
1731 
1732 #ifdef CONFIG_IWLEGACY_DEBUGFS
1733 void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
1734 #else
1735 static inline void
1736 il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
1737 {
1738 }
1739 #endif
1740 
1741 /*****************************************************
1742  * Handlers
1743  ***************************************************/
1744 void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1745 void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1746 void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
1747 void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
1748 
1749 /*****************************************************
1750 * RX
1751 ******************************************************/
1752 void il_cmd_queue_unmap(struct il_priv *il);
1753 void il_cmd_queue_free(struct il_priv *il);
1754 int il_rx_queue_alloc(struct il_priv *il);
1755 void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
1756 int il_rx_queue_space(const struct il_rx_queue *q);
1757 void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
1758 
1759 void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1760 void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
1761 void il_chswitch_done(struct il_priv *il, bool is_success);
1762 
1763 /*****************************************************
1764 * TX
1765 ******************************************************/
1766 void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1767 int il_tx_queue_init(struct il_priv *il, u32 txq_id);
1768 void il_tx_queue_reset(struct il_priv *il, u32 txq_id);
1769 void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1770 void il_tx_queue_free(struct il_priv *il, int txq_id);
1771 void il_setup_watchdog(struct il_priv *il);
1772 /*****************************************************
1773  * TX power
1774  ****************************************************/
1775 int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
1776 
1777 /*******************************************************************************
1778  * Rate
1779  ******************************************************************************/
1780 
1781 u8 il_get_lowest_plcp(struct il_priv *il);
1782 
1783 /*******************************************************************************
1784  * Scanning
1785  ******************************************************************************/
1786 void il_init_scan_params(struct il_priv *il);
1787 int il_scan_cancel(struct il_priv *il);
1788 int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1789 void il_force_scan_end(struct il_priv *il);
1790 int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1791 		   struct ieee80211_scan_request *hw_req);
1792 void il_internal_short_hw_scan(struct il_priv *il);
1793 int il_force_reset(struct il_priv *il, bool external);
1794 u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1795 		      const u8 *ta, const u8 *ie, int ie_len, int left);
1796 void il_setup_rx_scan_handlers(struct il_priv *il);
1797 u16 il_get_active_dwell_time(struct il_priv *il, enum nl80211_band band,
1798 			     u8 n_probes);
1799 u16 il_get_passive_dwell_time(struct il_priv *il, enum nl80211_band band,
1800 			      struct ieee80211_vif *vif);
1801 void il_setup_scan_deferred_work(struct il_priv *il);
1802 void il_cancel_scan_deferred_work(struct il_priv *il);
1803 
1804 /* For faster active scanning, scan will move to the next channel if fewer than
1805  * PLCP_QUIET_THRESH packets are heard on this channel within
1806  * ACTIVE_QUIET_TIME after sending probe request.  This shortens the dwell
1807  * time if it's a quiet channel (nothing responded to our probe, and there's
1808  * no other traffic).
1809  * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
1810 #define IL_ACTIVE_QUIET_TIME       cpu_to_le16(10)	/* msec */
1811 #define IL_PLCP_QUIET_THRESH       cpu_to_le16(1)	/* packets */
1812 
1813 #define IL_SCAN_CHECK_WATCHDOG		(HZ * 7)
1814 
1815 /*****************************************************
1816  *   S e n d i n g     H o s t     C o m m a n d s   *
1817  *****************************************************/
1818 
1819 const char *il_get_cmd_string(u8 cmd);
1820 int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
1821 int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
1822 int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
1823 				 const void *data);
1824 int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1825 			  void (*callback) (struct il_priv *il,
1826 					    struct il_device_cmd *cmd,
1827 					    struct il_rx_pkt *pkt));
1828 
1829 int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
1830 
1831 /*****************************************************
1832  * PCI						     *
1833  *****************************************************/
1834 
1835 void il_bg_watchdog(struct timer_list *t);
1836 u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
1837 __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
1838 			  u32 beacon_interval);
1839 
1840 #ifdef CONFIG_PM_SLEEP
1841 extern const struct dev_pm_ops il_pm_ops;
1842 
1843 #define IL_LEGACY_PM_OPS	(&il_pm_ops)
1844 
1845 #else /* !CONFIG_PM_SLEEP */
1846 
1847 #define IL_LEGACY_PM_OPS	NULL
1848 
1849 #endif /* !CONFIG_PM_SLEEP */
1850 
1851 /*****************************************************
1852 *  Error Handling Debugging
1853 ******************************************************/
1854 void il4965_dump_nic_error_log(struct il_priv *il);
1855 #ifdef CONFIG_IWLEGACY_DEBUG
1856 void il_print_rx_config_cmd(struct il_priv *il);
1857 #else
1858 static inline void
1859 il_print_rx_config_cmd(struct il_priv *il)
1860 {
1861 }
1862 #endif
1863 
1864 void il_clear_isr_stats(struct il_priv *il);
1865 
1866 /*****************************************************
1867 *  GEOS
1868 ******************************************************/
1869 int il_init_geos(struct il_priv *il);
1870 void il_free_geos(struct il_priv *il);
1871 
1872 /*************** DRIVER STATUS FUNCTIONS   *****/
1873 
1874 #define S_HCMD_ACTIVE	0	/* host command in progress */
1875 /* 1 is unused (used to be S_HCMD_SYNC_ACTIVE) */
1876 #define S_INT_ENABLED	2
1877 #define S_RFKILL	3
1878 #define S_CT_KILL		4
1879 #define S_INIT		5
1880 #define S_ALIVE		6
1881 #define S_READY		7
1882 #define S_TEMPERATURE	8
1883 #define S_GEO_CONFIGURED	9
1884 #define S_EXIT_PENDING	10
1885 #define S_STATS		12
1886 #define S_SCANNING		13
1887 #define S_SCAN_ABORTING	14
1888 #define S_SCAN_HW		15
1889 #define S_POWER_PMI	16
1890 #define S_FW_ERROR		17
1891 #define S_CHANNEL_SWITCH_PENDING 18
1892 
1893 static inline int
1894 il_is_ready(struct il_priv *il)
1895 {
1896 	/* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
1897 	 * set but EXIT_PENDING is not */
1898 	return test_bit(S_READY, &il->status) &&
1899 	    test_bit(S_GEO_CONFIGURED, &il->status) &&
1900 	    !test_bit(S_EXIT_PENDING, &il->status);
1901 }
1902 
1903 static inline int
1904 il_is_alive(struct il_priv *il)
1905 {
1906 	return test_bit(S_ALIVE, &il->status);
1907 }
1908 
1909 static inline int
1910 il_is_init(struct il_priv *il)
1911 {
1912 	return test_bit(S_INIT, &il->status);
1913 }
1914 
1915 static inline int
1916 il_is_rfkill(struct il_priv *il)
1917 {
1918 	return test_bit(S_RFKILL, &il->status);
1919 }
1920 
1921 static inline int
1922 il_is_ctkill(struct il_priv *il)
1923 {
1924 	return test_bit(S_CT_KILL, &il->status);
1925 }
1926 
1927 static inline int
1928 il_is_ready_rf(struct il_priv *il)
1929 {
1930 
1931 	if (il_is_rfkill(il))
1932 		return 0;
1933 
1934 	return il_is_ready(il);
1935 }
1936 
1937 void il_send_bt_config(struct il_priv *il);
1938 int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
1939 void il_apm_stop(struct il_priv *il);
1940 void _il_apm_stop(struct il_priv *il);
1941 
1942 int il_apm_init(struct il_priv *il);
1943 
1944 int il_send_rxon_timing(struct il_priv *il);
1945 
1946 static inline int
1947 il_send_rxon_assoc(struct il_priv *il)
1948 {
1949 	return il->ops->rxon_assoc(il);
1950 }
1951 
1952 static inline int
1953 il_commit_rxon(struct il_priv *il)
1954 {
1955 	return il->ops->commit_rxon(il);
1956 }
1957 
1958 static inline const struct ieee80211_supported_band *
1959 il_get_hw_mode(struct il_priv *il, enum nl80211_band band)
1960 {
1961 	return il->hw->wiphy->bands[band];
1962 }
1963 
1964 /* mac80211 handlers */
1965 int il_mac_config(struct ieee80211_hw *hw, u32 changed);
1966 void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1967 void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1968 			     struct ieee80211_bss_conf *bss_conf, u32 changes);
1969 void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1970 			  __le16 fc, __le32 *tx_flags);
1971 
1972 irqreturn_t il_isr(int irq, void *data);
1973 
1974 void il_set_bit(struct il_priv *p, u32 r, u32 m);
1975 void il_clear_bit(struct il_priv *p, u32 r, u32 m);
1976 bool _il_grab_nic_access(struct il_priv *il);
1977 int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout);
1978 int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout);
1979 u32 il_rd_prph(struct il_priv *il, u32 reg);
1980 void il_wr_prph(struct il_priv *il, u32 addr, u32 val);
1981 u32 il_read_targ_mem(struct il_priv *il, u32 addr);
1982 void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val);
1983 
1984 static inline bool il_need_reclaim(struct il_priv *il, struct il_rx_pkt *pkt)
1985 {
1986 	/* Reclaim a command buffer only if this packet is a response
1987 	 * to a (driver-originated) command. If the packet (e.g. Rx frame)
1988 	 * originated from uCode, there is no command buffer to reclaim.
1989 	 * Ucode should set SEQ_RX_FRAME bit if ucode-originated, but
1990 	 * apparently a few don't get set; catch them here.
1991 	 */
1992 	return !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1993 	       pkt->hdr.cmd != N_STATS && pkt->hdr.cmd != C_TX &&
1994 	       pkt->hdr.cmd != N_RX_PHY && pkt->hdr.cmd != N_RX &&
1995 	       pkt->hdr.cmd != N_RX_MPDU && pkt->hdr.cmd != N_COMPRESSED_BA;
1996 }
1997 
1998 static inline void
1999 _il_write8(struct il_priv *il, u32 ofs, u8 val)
2000 {
2001 	writeb(val, il->hw_base + ofs);
2002 }
2003 #define il_write8(il, ofs, val) _il_write8(il, ofs, val)
2004 
2005 static inline void
2006 _il_wr(struct il_priv *il, u32 ofs, u32 val)
2007 {
2008 	writel(val, il->hw_base + ofs);
2009 }
2010 
2011 static inline u32
2012 _il_rd(struct il_priv *il, u32 ofs)
2013 {
2014 	return readl(il->hw_base + ofs);
2015 }
2016 
2017 static inline void
2018 _il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2019 {
2020 	_il_wr(il, reg, _il_rd(il, reg) & ~mask);
2021 }
2022 
2023 static inline void
2024 _il_set_bit(struct il_priv *il, u32 reg, u32 mask)
2025 {
2026 	_il_wr(il, reg, _il_rd(il, reg) | mask);
2027 }
2028 
2029 static inline void
2030 _il_release_nic_access(struct il_priv *il)
2031 {
2032 	_il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2033 	/*
2034 	 * In above we are reading CSR_GP_CNTRL register, what will flush any
2035 	 * previous writes, but still want write, which clear MAC_ACCESS_REQ
2036 	 * bit, be performed on PCI bus before any other writes scheduled on
2037 	 * different CPUs (after we drop reg_lock).
2038 	 */
2039 	mmiowb();
2040 }
2041 
2042 static inline u32
2043 il_rd(struct il_priv *il, u32 reg)
2044 {
2045 	u32 value;
2046 	unsigned long reg_flags;
2047 
2048 	spin_lock_irqsave(&il->reg_lock, reg_flags);
2049 	_il_grab_nic_access(il);
2050 	value = _il_rd(il, reg);
2051 	_il_release_nic_access(il);
2052 	spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2053 	return value;
2054 }
2055 
2056 static inline void
2057 il_wr(struct il_priv *il, u32 reg, u32 value)
2058 {
2059 	unsigned long reg_flags;
2060 
2061 	spin_lock_irqsave(&il->reg_lock, reg_flags);
2062 	if (likely(_il_grab_nic_access(il))) {
2063 		_il_wr(il, reg, value);
2064 		_il_release_nic_access(il);
2065 	}
2066 	spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2067 }
2068 
2069 static inline u32
2070 _il_rd_prph(struct il_priv *il, u32 reg)
2071 {
2072 	_il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2073 	return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2074 }
2075 
2076 static inline void
2077 _il_wr_prph(struct il_priv *il, u32 addr, u32 val)
2078 {
2079 	_il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
2080 	_il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2081 }
2082 
2083 static inline void
2084 il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2085 {
2086 	unsigned long reg_flags;
2087 
2088 	spin_lock_irqsave(&il->reg_lock, reg_flags);
2089 	if (likely(_il_grab_nic_access(il))) {
2090 		_il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask));
2091 		_il_release_nic_access(il);
2092 	}
2093 	spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2094 }
2095 
2096 static inline void
2097 il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
2098 {
2099 	unsigned long reg_flags;
2100 
2101 	spin_lock_irqsave(&il->reg_lock, reg_flags);
2102 	if (likely(_il_grab_nic_access(il))) {
2103 		_il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits));
2104 		_il_release_nic_access(il);
2105 	}
2106 	spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2107 }
2108 
2109 static inline void
2110 il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2111 {
2112 	unsigned long reg_flags;
2113 	u32 val;
2114 
2115 	spin_lock_irqsave(&il->reg_lock, reg_flags);
2116 	if (likely(_il_grab_nic_access(il))) {
2117 		val = _il_rd_prph(il, reg);
2118 		_il_wr_prph(il, reg, (val & ~mask));
2119 		_il_release_nic_access(il);
2120 	}
2121 	spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2122 }
2123 
2124 #define HW_KEY_DYNAMIC 0
2125 #define HW_KEY_DEFAULT 1
2126 
2127 #define IL_STA_DRIVER_ACTIVE BIT(0)	/* driver entry is active */
2128 #define IL_STA_UCODE_ACTIVE  BIT(1)	/* ucode entry is active */
2129 #define IL_STA_UCODE_INPROGRESS  BIT(2)	/* ucode entry is in process of
2130 					   being activated */
2131 #define IL_STA_LOCAL BIT(3)	/* station state not directed by mac80211;
2132 				   (this is for the IBSS BSSID stations) */
2133 #define IL_STA_BCAST BIT(4)	/* this station is the special bcast station */
2134 
2135 void il_restore_stations(struct il_priv *il);
2136 void il_clear_ucode_stations(struct il_priv *il);
2137 void il_dealloc_bcast_stations(struct il_priv *il);
2138 int il_get_free_ucode_key_idx(struct il_priv *il);
2139 int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
2140 int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
2141 			  struct ieee80211_sta *sta, u8 *sta_id_r);
2142 int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2143 int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2144 		      struct ieee80211_sta *sta);
2145 
2146 u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
2147 		   struct ieee80211_sta *sta);
2148 
2149 int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2150 		   u8 flags, bool init);
2151 
2152 /**
2153  * il_clear_driver_stations - clear knowledge of all stations from driver
2154  * @il: iwl il struct
2155  *
2156  * This is called during il_down() to make sure that in the case
2157  * we're coming there from a hardware restart mac80211 will be
2158  * able to reconfigure stations -- if we're getting there in the
2159  * normal down flow then the stations will already be cleared.
2160  */
2161 static inline void
2162 il_clear_driver_stations(struct il_priv *il)
2163 {
2164 	unsigned long flags;
2165 
2166 	spin_lock_irqsave(&il->sta_lock, flags);
2167 	memset(il->stations, 0, sizeof(il->stations));
2168 	il->num_stations = 0;
2169 	il->ucode_key_table = 0;
2170 	spin_unlock_irqrestore(&il->sta_lock, flags);
2171 }
2172 
2173 static inline int
2174 il_sta_id(struct ieee80211_sta *sta)
2175 {
2176 	if (WARN_ON(!sta))
2177 		return IL_INVALID_STATION;
2178 
2179 	return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2180 }
2181 
2182 /**
2183  * il_sta_id_or_broadcast - return sta_id or broadcast sta
2184  * @il: iwl il
2185  * @context: the current context
2186  * @sta: mac80211 station
2187  *
2188  * In certain circumstances mac80211 passes a station pointer
2189  * that may be %NULL, for example during TX or key setup. In
2190  * that case, we need to use the broadcast station, so this
2191  * inline wraps that pattern.
2192  */
2193 static inline int
2194 il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta)
2195 {
2196 	int sta_id;
2197 
2198 	if (!sta)
2199 		return il->hw_params.bcast_id;
2200 
2201 	sta_id = il_sta_id(sta);
2202 
2203 	/*
2204 	 * mac80211 should not be passing a partially
2205 	 * initialised station!
2206 	 */
2207 	WARN_ON(sta_id == IL_INVALID_STATION);
2208 
2209 	return sta_id;
2210 }
2211 
2212 /**
2213  * il_queue_inc_wrap - increment queue idx, wrap back to beginning
2214  * @idx -- current idx
2215  * @n_bd -- total number of entries in queue (must be power of 2)
2216  */
2217 static inline int
2218 il_queue_inc_wrap(int idx, int n_bd)
2219 {
2220 	return ++idx & (n_bd - 1);
2221 }
2222 
2223 /**
2224  * il_queue_dec_wrap - decrement queue idx, wrap back to end
2225  * @idx -- current idx
2226  * @n_bd -- total number of entries in queue (must be power of 2)
2227  */
2228 static inline int
2229 il_queue_dec_wrap(int idx, int n_bd)
2230 {
2231 	return --idx & (n_bd - 1);
2232 }
2233 
2234 /* TODO: Move fw_desc functions to iwl-pci.ko */
2235 static inline void
2236 il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2237 {
2238 	if (desc->v_addr)
2239 		dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2240 				  desc->p_addr);
2241 	desc->v_addr = NULL;
2242 	desc->len = 0;
2243 }
2244 
2245 static inline int
2246 il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2247 {
2248 	if (!desc->len) {
2249 		desc->v_addr = NULL;
2250 		return -EINVAL;
2251 	}
2252 
2253 	desc->v_addr = dma_alloc_coherent(&pci_dev->dev, desc->len,
2254 					  &desc->p_addr, GFP_KERNEL);
2255 	return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2256 }
2257 
2258 /*
2259  * we have 8 bits used like this:
2260  *
2261  * 7 6 5 4 3 2 1 0
2262  * | | | | | | | |
2263  * | | | | | | +-+-------- AC queue (0-3)
2264  * | | | | | |
2265  * | +-+-+-+-+------------ HW queue ID
2266  * |
2267  * +---------------------- unused
2268  */
2269 static inline void
2270 il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2271 {
2272 	BUG_ON(ac > 3);		/* only have 2 bits */
2273 	BUG_ON(hwq > 31);	/* only use 5 bits */
2274 
2275 	txq->swq_id = (hwq << 2) | ac;
2276 }
2277 
2278 static inline void
2279 _il_wake_queue(struct il_priv *il, u8 ac)
2280 {
2281 	if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2282 		ieee80211_wake_queue(il->hw, ac);
2283 }
2284 
2285 static inline void
2286 _il_stop_queue(struct il_priv *il, u8 ac)
2287 {
2288 	if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2289 		ieee80211_stop_queue(il->hw, ac);
2290 }
2291 static inline void
2292 il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
2293 {
2294 	u8 queue = txq->swq_id;
2295 	u8 ac = queue & 3;
2296 	u8 hwq = (queue >> 2) & 0x1f;
2297 
2298 	if (test_and_clear_bit(hwq, il->queue_stopped))
2299 		_il_wake_queue(il, ac);
2300 }
2301 
2302 static inline void
2303 il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
2304 {
2305 	u8 queue = txq->swq_id;
2306 	u8 ac = queue & 3;
2307 	u8 hwq = (queue >> 2) & 0x1f;
2308 
2309 	if (!test_and_set_bit(hwq, il->queue_stopped))
2310 		_il_stop_queue(il, ac);
2311 }
2312 
2313 static inline void
2314 il_wake_queues_by_reason(struct il_priv *il, int reason)
2315 {
2316 	u8 ac;
2317 
2318 	if (test_and_clear_bit(reason, &il->stop_reason))
2319 		for (ac = 0; ac < 4; ac++)
2320 			_il_wake_queue(il, ac);
2321 }
2322 
2323 static inline void
2324 il_stop_queues_by_reason(struct il_priv *il, int reason)
2325 {
2326 	u8 ac;
2327 
2328 	if (!test_and_set_bit(reason, &il->stop_reason))
2329 		for (ac = 0; ac < 4; ac++)
2330 			_il_stop_queue(il, ac);
2331 }
2332 
2333 #ifdef ieee80211_stop_queue
2334 #undef ieee80211_stop_queue
2335 #endif
2336 
2337 #define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2338 
2339 #ifdef ieee80211_wake_queue
2340 #undef ieee80211_wake_queue
2341 #endif
2342 
2343 #define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2344 
2345 static inline void
2346 il_disable_interrupts(struct il_priv *il)
2347 {
2348 	clear_bit(S_INT_ENABLED, &il->status);
2349 
2350 	/* disable interrupts from uCode/NIC to host */
2351 	_il_wr(il, CSR_INT_MASK, 0x00000000);
2352 
2353 	/* acknowledge/clear/reset any interrupts still pending
2354 	 * from uCode or flow handler (Rx/Tx DMA) */
2355 	_il_wr(il, CSR_INT, 0xffffffff);
2356 	_il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
2357 }
2358 
2359 static inline void
2360 il_enable_rfkill_int(struct il_priv *il)
2361 {
2362 	_il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2363 }
2364 
2365 static inline void
2366 il_enable_interrupts(struct il_priv *il)
2367 {
2368 	set_bit(S_INT_ENABLED, &il->status);
2369 	_il_wr(il, CSR_INT_MASK, il->inta_mask);
2370 }
2371 
2372 /**
2373  * il_beacon_time_mask_low - mask of lower 32 bit of beacon time
2374  * @il -- pointer to il_priv data structure
2375  * @tsf_bits -- number of bits need to shift for masking)
2376  */
2377 static inline u32
2378 il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
2379 {
2380 	return (1 << tsf_bits) - 1;
2381 }
2382 
2383 /**
2384  * il_beacon_time_mask_high - mask of higher 32 bit of beacon time
2385  * @il -- pointer to il_priv data structure
2386  * @tsf_bits -- number of bits need to shift for masking)
2387  */
2388 static inline u32
2389 il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
2390 {
2391 	return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2392 }
2393 
2394 /**
2395  * struct il_rb_status - reseve buffer status host memory mapped FH registers
2396  *
2397  * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed
2398  * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed
2399  * @finished_rb_num [0:11] - Indicates the idx of the current RB
2400  *			     in which the last frame was written to
2401  * @finished_fr_num [0:11] - Indicates the idx of the RX Frame
2402  *			     which was transferred
2403  */
2404 struct il_rb_status {
2405 	__le16 closed_rb_num;
2406 	__le16 closed_fr_num;
2407 	__le16 finished_rb_num;
2408 	__le16 finished_fr_nam;
2409 	__le32 __unused;	/* 3945 only */
2410 } __packed;
2411 
2412 #define TFD_QUEUE_SIZE_MAX      256
2413 #define TFD_QUEUE_SIZE_BC_DUP	64
2414 #define TFD_QUEUE_BC_SIZE	(TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2415 #define IL_TX_DMA_MASK		DMA_BIT_MASK(36)
2416 #define IL_NUM_OF_TBS		20
2417 
2418 static inline u8
2419 il_get_dma_hi_addr(dma_addr_t addr)
2420 {
2421 	return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2422 }
2423 
2424 /**
2425  * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor
2426  *
2427  * This structure contains dma address and length of transmission address
2428  *
2429  * @lo: low [31:0] portion of the dma address of TX buffer every even is
2430  *	unaligned on 16 bit boundary
2431  * @hi_n_len: 0-3 [35:32] portion of dma
2432  *	      4-15 length of the tx buffer
2433  */
2434 struct il_tfd_tb {
2435 	__le32 lo;
2436 	__le16 hi_n_len;
2437 } __packed;
2438 
2439 /**
2440  * struct il_tfd
2441  *
2442  * Transmit Frame Descriptor (TFD)
2443  *
2444  * @ __reserved1[3] reserved
2445  * @ num_tbs 0-4 number of active tbs
2446  *	     5   reserved
2447  * 	     6-7 padding (not used)
2448  * @ tbs[20]	transmit frame buffer descriptors
2449  * @ __pad	padding
2450  *
2451  * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
2452  * Both driver and device share these circular buffers, each of which must be
2453  * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
2454  *
2455  * Driver must indicate the physical address of the base of each
2456  * circular buffer via the FH49_MEM_CBBC_QUEUE registers.
2457  *
2458  * Each TFD contains pointer/size information for up to 20 data buffers
2459  * in host DRAM.  These buffers collectively contain the (one) frame described
2460  * by the TFD.  Each buffer must be a single contiguous block of memory within
2461  * itself, but buffers may be scattered in host DRAM.  Each buffer has max size
2462  * of (4K - 4).  The concatenates all of a TFD's buffers into a single
2463  * Tx frame, up to 8 KBytes in size.
2464  *
2465  * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
2466  */
2467 struct il_tfd {
2468 	u8 __reserved1[3];
2469 	u8 num_tbs;
2470 	struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2471 	__le32 __pad;
2472 } __packed;
2473 /* PCI registers */
2474 #define PCI_CFG_RETRY_TIMEOUT	0x041
2475 
2476 struct il_rate_info {
2477 	u8 plcp;		/* uCode API:  RATE_6M_PLCP, etc. */
2478 	u8 plcp_siso;		/* uCode API:  RATE_SISO_6M_PLCP, etc. */
2479 	u8 plcp_mimo2;		/* uCode API:  RATE_MIMO2_6M_PLCP, etc. */
2480 	u8 ieee;		/* MAC header:  RATE_6M_IEEE, etc. */
2481 	u8 prev_ieee;		/* previous rate in IEEE speeds */
2482 	u8 next_ieee;		/* next rate in IEEE speeds */
2483 	u8 prev_rs;		/* previous rate used in rs algo */
2484 	u8 next_rs;		/* next rate used in rs algo */
2485 	u8 prev_rs_tgg;		/* previous rate used in TGG rs algo */
2486 	u8 next_rs_tgg;		/* next rate used in TGG rs algo */
2487 };
2488 
2489 struct il3945_rate_info {
2490 	u8 plcp;		/* uCode API:  RATE_6M_PLCP, etc. */
2491 	u8 ieee;		/* MAC header:  RATE_6M_IEEE, etc. */
2492 	u8 prev_ieee;		/* previous rate in IEEE speeds */
2493 	u8 next_ieee;		/* next rate in IEEE speeds */
2494 	u8 prev_rs;		/* previous rate used in rs algo */
2495 	u8 next_rs;		/* next rate used in rs algo */
2496 	u8 prev_rs_tgg;		/* previous rate used in TGG rs algo */
2497 	u8 next_rs_tgg;		/* next rate used in TGG rs algo */
2498 	u8 table_rs_idx;	/* idx in rate scale table cmd */
2499 	u8 prev_table_rs;	/* prev in rate table cmd */
2500 };
2501 
2502 /*
2503  * These serve as idxes into
2504  * struct il_rate_info il_rates[RATE_COUNT];
2505  */
2506 enum {
2507 	RATE_1M_IDX = 0,
2508 	RATE_2M_IDX,
2509 	RATE_5M_IDX,
2510 	RATE_11M_IDX,
2511 	RATE_6M_IDX,
2512 	RATE_9M_IDX,
2513 	RATE_12M_IDX,
2514 	RATE_18M_IDX,
2515 	RATE_24M_IDX,
2516 	RATE_36M_IDX,
2517 	RATE_48M_IDX,
2518 	RATE_54M_IDX,
2519 	RATE_60M_IDX,
2520 	RATE_COUNT,
2521 	RATE_COUNT_LEGACY = RATE_COUNT - 1,	/* Excluding 60M */
2522 	RATE_COUNT_3945 = RATE_COUNT - 1,
2523 	RATE_INVM_IDX = RATE_COUNT,
2524 	RATE_INVALID = RATE_COUNT,
2525 };
2526 
2527 enum {
2528 	RATE_6M_IDX_TBL = 0,
2529 	RATE_9M_IDX_TBL,
2530 	RATE_12M_IDX_TBL,
2531 	RATE_18M_IDX_TBL,
2532 	RATE_24M_IDX_TBL,
2533 	RATE_36M_IDX_TBL,
2534 	RATE_48M_IDX_TBL,
2535 	RATE_54M_IDX_TBL,
2536 	RATE_1M_IDX_TBL,
2537 	RATE_2M_IDX_TBL,
2538 	RATE_5M_IDX_TBL,
2539 	RATE_11M_IDX_TBL,
2540 	RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2541 };
2542 
2543 enum {
2544 	IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2545 	IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2546 	IL_LAST_OFDM_RATE = RATE_60M_IDX,
2547 	IL_FIRST_CCK_RATE = RATE_1M_IDX,
2548 	IL_LAST_CCK_RATE = RATE_11M_IDX,
2549 };
2550 
2551 /* #define vs. enum to keep from defaulting to 'large integer' */
2552 #define	RATE_6M_MASK   (1 << RATE_6M_IDX)
2553 #define	RATE_9M_MASK   (1 << RATE_9M_IDX)
2554 #define	RATE_12M_MASK  (1 << RATE_12M_IDX)
2555 #define	RATE_18M_MASK  (1 << RATE_18M_IDX)
2556 #define	RATE_24M_MASK  (1 << RATE_24M_IDX)
2557 #define	RATE_36M_MASK  (1 << RATE_36M_IDX)
2558 #define	RATE_48M_MASK  (1 << RATE_48M_IDX)
2559 #define	RATE_54M_MASK  (1 << RATE_54M_IDX)
2560 #define RATE_60M_MASK  (1 << RATE_60M_IDX)
2561 #define	RATE_1M_MASK   (1 << RATE_1M_IDX)
2562 #define	RATE_2M_MASK   (1 << RATE_2M_IDX)
2563 #define	RATE_5M_MASK   (1 << RATE_5M_IDX)
2564 #define	RATE_11M_MASK  (1 << RATE_11M_IDX)
2565 
2566 /* uCode API values for legacy bit rates, both OFDM and CCK */
2567 enum {
2568 	RATE_6M_PLCP = 13,
2569 	RATE_9M_PLCP = 15,
2570 	RATE_12M_PLCP = 5,
2571 	RATE_18M_PLCP = 7,
2572 	RATE_24M_PLCP = 9,
2573 	RATE_36M_PLCP = 11,
2574 	RATE_48M_PLCP = 1,
2575 	RATE_54M_PLCP = 3,
2576 	RATE_60M_PLCP = 3,	/*FIXME:RS:should be removed */
2577 	RATE_1M_PLCP = 10,
2578 	RATE_2M_PLCP = 20,
2579 	RATE_5M_PLCP = 55,
2580 	RATE_11M_PLCP = 110,
2581 	/*FIXME:RS:add RATE_LEGACY_INVM_PLCP = 0, */
2582 };
2583 
2584 /* uCode API values for OFDM high-throughput (HT) bit rates */
2585 enum {
2586 	RATE_SISO_6M_PLCP = 0,
2587 	RATE_SISO_12M_PLCP = 1,
2588 	RATE_SISO_18M_PLCP = 2,
2589 	RATE_SISO_24M_PLCP = 3,
2590 	RATE_SISO_36M_PLCP = 4,
2591 	RATE_SISO_48M_PLCP = 5,
2592 	RATE_SISO_54M_PLCP = 6,
2593 	RATE_SISO_60M_PLCP = 7,
2594 	RATE_MIMO2_6M_PLCP = 0x8,
2595 	RATE_MIMO2_12M_PLCP = 0x9,
2596 	RATE_MIMO2_18M_PLCP = 0xa,
2597 	RATE_MIMO2_24M_PLCP = 0xb,
2598 	RATE_MIMO2_36M_PLCP = 0xc,
2599 	RATE_MIMO2_48M_PLCP = 0xd,
2600 	RATE_MIMO2_54M_PLCP = 0xe,
2601 	RATE_MIMO2_60M_PLCP = 0xf,
2602 	RATE_SISO_INVM_PLCP,
2603 	RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2604 };
2605 
2606 /* MAC header values for bit rates */
2607 enum {
2608 	RATE_6M_IEEE = 12,
2609 	RATE_9M_IEEE = 18,
2610 	RATE_12M_IEEE = 24,
2611 	RATE_18M_IEEE = 36,
2612 	RATE_24M_IEEE = 48,
2613 	RATE_36M_IEEE = 72,
2614 	RATE_48M_IEEE = 96,
2615 	RATE_54M_IEEE = 108,
2616 	RATE_60M_IEEE = 120,
2617 	RATE_1M_IEEE = 2,
2618 	RATE_2M_IEEE = 4,
2619 	RATE_5M_IEEE = 11,
2620 	RATE_11M_IEEE = 22,
2621 };
2622 
2623 #define IL_CCK_BASIC_RATES_MASK    \
2624 	(RATE_1M_MASK          | \
2625 	RATE_2M_MASK)
2626 
2627 #define IL_CCK_RATES_MASK          \
2628 	(IL_CCK_BASIC_RATES_MASK  | \
2629 	RATE_5M_MASK          | \
2630 	RATE_11M_MASK)
2631 
2632 #define IL_OFDM_BASIC_RATES_MASK   \
2633 	(RATE_6M_MASK         | \
2634 	RATE_12M_MASK         | \
2635 	RATE_24M_MASK)
2636 
2637 #define IL_OFDM_RATES_MASK         \
2638 	(IL_OFDM_BASIC_RATES_MASK | \
2639 	RATE_9M_MASK          | \
2640 	RATE_18M_MASK         | \
2641 	RATE_36M_MASK         | \
2642 	RATE_48M_MASK         | \
2643 	RATE_54M_MASK)
2644 
2645 #define IL_BASIC_RATES_MASK         \
2646 	(IL_OFDM_BASIC_RATES_MASK | \
2647 	 IL_CCK_BASIC_RATES_MASK)
2648 
2649 #define RATES_MASK ((1 << RATE_COUNT) - 1)
2650 #define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2651 
2652 #define IL_INVALID_VALUE    -1
2653 
2654 #define IL_MIN_RSSI_VAL                 -100
2655 #define IL_MAX_RSSI_VAL                    0
2656 
2657 /* These values specify how many Tx frame attempts before
2658  * searching for a new modulation mode */
2659 #define IL_LEGACY_FAILURE_LIMIT	160
2660 #define IL_LEGACY_SUCCESS_LIMIT	480
2661 #define IL_LEGACY_TBL_COUNT		160
2662 
2663 #define IL_NONE_LEGACY_FAILURE_LIMIT	400
2664 #define IL_NONE_LEGACY_SUCCESS_LIMIT	4500
2665 #define IL_NONE_LEGACY_TBL_COUNT	1500
2666 
2667 /* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */
2668 #define IL_RS_GOOD_RATIO		12800	/* 100% */
2669 #define RATE_SCALE_SWITCH		10880	/*  85% */
2670 #define RATE_HIGH_TH		10880	/*  85% */
2671 #define RATE_INCREASE_TH		6400	/*  50% */
2672 #define RATE_DECREASE_TH		1920	/*  15% */
2673 
2674 /* possible actions when in legacy mode */
2675 #define IL_LEGACY_SWITCH_ANTENNA1      0
2676 #define IL_LEGACY_SWITCH_ANTENNA2      1
2677 #define IL_LEGACY_SWITCH_SISO          2
2678 #define IL_LEGACY_SWITCH_MIMO2_AB      3
2679 #define IL_LEGACY_SWITCH_MIMO2_AC      4
2680 #define IL_LEGACY_SWITCH_MIMO2_BC      5
2681 
2682 /* possible actions when in siso mode */
2683 #define IL_SISO_SWITCH_ANTENNA1        0
2684 #define IL_SISO_SWITCH_ANTENNA2        1
2685 #define IL_SISO_SWITCH_MIMO2_AB        2
2686 #define IL_SISO_SWITCH_MIMO2_AC        3
2687 #define IL_SISO_SWITCH_MIMO2_BC        4
2688 #define IL_SISO_SWITCH_GI              5
2689 
2690 /* possible actions when in mimo mode */
2691 #define IL_MIMO2_SWITCH_ANTENNA1       0
2692 #define IL_MIMO2_SWITCH_ANTENNA2       1
2693 #define IL_MIMO2_SWITCH_SISO_A         2
2694 #define IL_MIMO2_SWITCH_SISO_B         3
2695 #define IL_MIMO2_SWITCH_SISO_C         4
2696 #define IL_MIMO2_SWITCH_GI             5
2697 
2698 #define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
2699 
2700 #define IL_ACTION_LIMIT		3	/* # possible actions */
2701 
2702 #define LQ_SIZE		2	/* 2 mode tables:  "Active" and "Search" */
2703 
2704 /* load per tid defines for A-MPDU activation */
2705 #define IL_AGG_TPT_THREHOLD	0
2706 #define IL_AGG_LOAD_THRESHOLD	10
2707 #define IL_AGG_ALL_TID		0xff
2708 #define TID_QUEUE_CELL_SPACING	50	/*mS */
2709 #define TID_QUEUE_MAX_SIZE	20
2710 #define TID_ROUND_VALUE		5	/* mS */
2711 #define TID_MAX_LOAD_COUNT	8
2712 
2713 #define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
2714 #define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
2715 
2716 extern const struct il_rate_info il_rates[RATE_COUNT];
2717 
2718 enum il_table_type {
2719 	LQ_NONE,
2720 	LQ_G,			/* legacy types */
2721 	LQ_A,
2722 	LQ_SISO,		/* high-throughput types */
2723 	LQ_MIMO2,
2724 	LQ_MAX,
2725 };
2726 
2727 #define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
2728 #define is_siso(tbl) ((tbl) == LQ_SISO)
2729 #define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
2730 #define is_mimo(tbl) (is_mimo2(tbl))
2731 #define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
2732 #define is_a_band(tbl) ((tbl) == LQ_A)
2733 #define is_g_and(tbl) ((tbl) == LQ_G)
2734 
2735 #define	ANT_NONE	0x0
2736 #define	ANT_A		BIT(0)
2737 #define	ANT_B		BIT(1)
2738 #define	ANT_AB		(ANT_A | ANT_B)
2739 #define ANT_C		BIT(2)
2740 #define	ANT_AC		(ANT_A | ANT_C)
2741 #define ANT_BC		(ANT_B | ANT_C)
2742 #define ANT_ABC		(ANT_AB | ANT_C)
2743 
2744 #define IL_MAX_MCS_DISPLAY_SIZE	12
2745 
2746 struct il_rate_mcs_info {
2747 	char mbps[IL_MAX_MCS_DISPLAY_SIZE];
2748 	char mcs[IL_MAX_MCS_DISPLAY_SIZE];
2749 };
2750 
2751 /**
2752  * struct il_rate_scale_data -- tx success history for one rate
2753  */
2754 struct il_rate_scale_data {
2755 	u64 data;		/* bitmap of successful frames */
2756 	s32 success_counter;	/* number of frames successful */
2757 	s32 success_ratio;	/* per-cent * 128  */
2758 	s32 counter;		/* number of frames attempted */
2759 	s32 average_tpt;	/* success ratio * expected throughput */
2760 	unsigned long stamp;
2761 };
2762 
2763 /**
2764  * struct il_scale_tbl_info -- tx params and success history for all rates
2765  *
2766  * There are two of these in struct il_lq_sta,
2767  * one for "active", and one for "search".
2768  */
2769 struct il_scale_tbl_info {
2770 	enum il_table_type lq_type;
2771 	u8 ant_type;
2772 	u8 is_SGI;		/* 1 = short guard interval */
2773 	u8 is_ht40;		/* 1 = 40 MHz channel width */
2774 	u8 is_dup;		/* 1 = duplicated data streams */
2775 	u8 action;		/* change modulation; IL_[LEGACY/SISO/MIMO]_SWITCH_* */
2776 	u8 max_search;		/* maximun number of tables we can search */
2777 	s32 *expected_tpt;	/* throughput metrics; expected_tpt_G, etc. */
2778 	u32 current_rate;	/* rate_n_flags, uCode API format */
2779 	struct il_rate_scale_data win[RATE_COUNT];	/* rate histories */
2780 };
2781 
2782 struct il_traffic_load {
2783 	unsigned long time_stamp;	/* age of the oldest stats */
2784 	u32 packet_count[TID_QUEUE_MAX_SIZE];	/* packet count in this time
2785 						 * slice */
2786 	u32 total;		/* total num of packets during the
2787 				 * last TID_MAX_TIME_DIFF */
2788 	u8 queue_count;		/* number of queues that has
2789 				 * been used since the last cleanup */
2790 	u8 head;		/* start of the circular buffer */
2791 };
2792 
2793 /**
2794  * struct il_lq_sta -- driver's rate scaling ilate structure
2795  *
2796  * Pointer to this gets passed back and forth between driver and mac80211.
2797  */
2798 struct il_lq_sta {
2799 	u8 active_tbl;		/* idx of active table, range 0-1 */
2800 	u8 enable_counter;	/* indicates HT mode */
2801 	u8 stay_in_tbl;		/* 1: disallow, 0: allow search for new mode */
2802 	u8 search_better_tbl;	/* 1: currently trying alternate mode */
2803 	s32 last_tpt;
2804 
2805 	/* The following determine when to search for a new mode */
2806 	u32 table_count_limit;
2807 	u32 max_failure_limit;	/* # failed frames before new search */
2808 	u32 max_success_limit;	/* # successful frames before new search */
2809 	u32 table_count;
2810 	u32 total_failed;	/* total failed frames, any/all rates */
2811 	u32 total_success;	/* total successful frames, any/all rates */
2812 	u64 flush_timer;	/* time staying in mode before new search */
2813 
2814 	u8 action_counter;	/* # mode-switch actions tried */
2815 	u8 is_green;
2816 	u8 is_dup;
2817 	enum nl80211_band band;
2818 
2819 	/* The following are bitmaps of rates; RATE_6M_MASK, etc. */
2820 	u32 supp_rates;
2821 	u16 active_legacy_rate;
2822 	u16 active_siso_rate;
2823 	u16 active_mimo2_rate;
2824 	s8 max_rate_idx;	/* Max rate set by user */
2825 	u8 missed_rate_counter;
2826 
2827 	struct il_link_quality_cmd lq;
2828 	struct il_scale_tbl_info lq_info[LQ_SIZE];	/* "active", "search" */
2829 	struct il_traffic_load load[TID_MAX_LOAD_COUNT];
2830 	u8 tx_agg_tid_en;
2831 #ifdef CONFIG_MAC80211_DEBUGFS
2832 	struct dentry *rs_sta_dbgfs_scale_table_file;
2833 	struct dentry *rs_sta_dbgfs_stats_table_file;
2834 	struct dentry *rs_sta_dbgfs_rate_scale_data_file;
2835 	struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file;
2836 	u32 dbg_fixed_rate;
2837 #endif
2838 	struct il_priv *drv;
2839 
2840 	/* used to be in sta_info */
2841 	int last_txrate_idx;
2842 	/* last tx rate_n_flags */
2843 	u32 last_rate_n_flags;
2844 	/* packets destined for this STA are aggregated */
2845 	u8 is_agg;
2846 };
2847 
2848 /*
2849  * il_station_priv: Driver's ilate station information
2850  *
2851  * When mac80211 creates a station it reserves some space (hw->sta_data_size)
2852  * in the structure for use by driver. This structure is places in that
2853  * space.
2854  *
2855  * The common struct MUST be first because it is shared between
2856  * 3945 and 4965!
2857  */
2858 struct il_station_priv {
2859 	struct il_station_priv_common common;
2860 	struct il_lq_sta lq_sta;
2861 	atomic_t pending_frames;
2862 	bool client;
2863 	bool asleep;
2864 };
2865 
2866 static inline u8
2867 il4965_num_of_ant(u8 m)
2868 {
2869 	return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
2870 }
2871 
2872 static inline u8
2873 il4965_first_antenna(u8 mask)
2874 {
2875 	if (mask & ANT_A)
2876 		return ANT_A;
2877 	if (mask & ANT_B)
2878 		return ANT_B;
2879 	return ANT_C;
2880 }
2881 
2882 /**
2883  * il3945_rate_scale_init - Initialize the rate scale table based on assoc info
2884  *
2885  * The specific throughput table used is based on the type of network
2886  * the associated with, including A, B, G, and G w/ TGG protection
2887  */
2888 void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
2889 
2890 /* Initialize station's rate scaling information after adding station */
2891 void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2892 			 u8 sta_id);
2893 void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2894 			 u8 sta_id);
2895 
2896 /**
2897  * il_rate_control_register - Register the rate control algorithm callbacks
2898  *
2899  * Since the rate control algorithm is hardware specific, there is no need
2900  * or reason to place it as a stand alone module.  The driver can call
2901  * il_rate_control_register in order to register the rate control callbacks
2902  * with the mac80211 subsystem.  This should be performed prior to calling
2903  * ieee80211_register_hw
2904  *
2905  */
2906 int il4965_rate_control_register(void);
2907 int il3945_rate_control_register(void);
2908 
2909 /**
2910  * il_rate_control_unregister - Unregister the rate control callbacks
2911  *
2912  * This should be called after calling ieee80211_unregister_hw, but before
2913  * the driver is unloaded.
2914  */
2915 void il4965_rate_control_unregister(void);
2916 void il3945_rate_control_unregister(void);
2917 
2918 int il_power_update_mode(struct il_priv *il, bool force);
2919 void il_power_initialize(struct il_priv *il);
2920 
2921 extern u32 il_debug_level;
2922 
2923 #ifdef CONFIG_IWLEGACY_DEBUG
2924 /*
2925  * il_get_debug_level: Return active debug level for device
2926  *
2927  * Using sysfs it is possible to set per device debug level. This debug
2928  * level will be used if set, otherwise the global debug level which can be
2929  * set via module parameter is used.
2930  */
2931 static inline u32
2932 il_get_debug_level(struct il_priv *il)
2933 {
2934 	if (il->debug_level)
2935 		return il->debug_level;
2936 	else
2937 		return il_debug_level;
2938 }
2939 #else
2940 static inline u32
2941 il_get_debug_level(struct il_priv *il)
2942 {
2943 	return il_debug_level;
2944 }
2945 #endif
2946 
2947 #define il_print_hex_error(il, p, len)					\
2948 do {									\
2949 	print_hex_dump(KERN_ERR, "iwl data: ",				\
2950 		       DUMP_PREFIX_OFFSET, 16, 1, p, len, 1);		\
2951 } while (0)
2952 
2953 #ifdef CONFIG_IWLEGACY_DEBUG
2954 #define IL_DBG(level, fmt, args...)					\
2955 do {									\
2956 	if (il_get_debug_level(il) & level)				\
2957 		dev_err(&il->hw->wiphy->dev, "%c %s " fmt,		\
2958 			in_interrupt() ? 'I' : 'U', __func__ , ##args); \
2959 } while (0)
2960 
2961 #define il_print_hex_dump(il, level, p, len)				\
2962 do {									\
2963 	if (il_get_debug_level(il) & level)				\
2964 		print_hex_dump(KERN_DEBUG, "iwl data: ",		\
2965 			       DUMP_PREFIX_OFFSET, 16, 1, p, len, 1);	\
2966 } while (0)
2967 
2968 #else
2969 #define IL_DBG(level, fmt, args...)
2970 static inline void
2971 il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
2972 {
2973 }
2974 #endif /* CONFIG_IWLEGACY_DEBUG */
2975 
2976 #ifdef CONFIG_IWLEGACY_DEBUGFS
2977 int il_dbgfs_register(struct il_priv *il, const char *name);
2978 void il_dbgfs_unregister(struct il_priv *il);
2979 #else
2980 static inline int
2981 il_dbgfs_register(struct il_priv *il, const char *name)
2982 {
2983 	return 0;
2984 }
2985 
2986 static inline void
2987 il_dbgfs_unregister(struct il_priv *il)
2988 {
2989 }
2990 #endif /* CONFIG_IWLEGACY_DEBUGFS */
2991 
2992 /*
2993  * To use the debug system:
2994  *
2995  * If you are defining a new debug classification, simply add it to the #define
2996  * list here in the form of
2997  *
2998  * #define IL_DL_xxxx VALUE
2999  *
3000  * where xxxx should be the name of the classification (for example, WEP).
3001  *
3002  * You then need to either add a IL_xxxx_DEBUG() macro definition for your
3003  * classification, or use IL_DBG(IL_DL_xxxx, ...) whenever you want
3004  * to send output to that classification.
3005  *
3006  * The active debug levels can be accessed via files
3007  *
3008  *	/sys/module/iwl4965/parameters/debug
3009  *	/sys/module/iwl3945/parameters/debug
3010  *	/sys/class/net/wlan0/device/debug_level
3011  *
3012  * when CONFIG_IWLEGACY_DEBUG=y.
3013  */
3014 
3015 /* 0x0000000F - 0x00000001 */
3016 #define IL_DL_INFO		(1 << 0)
3017 #define IL_DL_MAC80211		(1 << 1)
3018 #define IL_DL_HCMD		(1 << 2)
3019 #define IL_DL_STATE		(1 << 3)
3020 /* 0x000000F0 - 0x00000010 */
3021 #define IL_DL_MACDUMP		(1 << 4)
3022 #define IL_DL_HCMD_DUMP		(1 << 5)
3023 #define IL_DL_EEPROM		(1 << 6)
3024 #define IL_DL_RADIO		(1 << 7)
3025 /* 0x00000F00 - 0x00000100 */
3026 #define IL_DL_POWER		(1 << 8)
3027 #define IL_DL_TEMP		(1 << 9)
3028 #define IL_DL_NOTIF		(1 << 10)
3029 #define IL_DL_SCAN		(1 << 11)
3030 /* 0x0000F000 - 0x00001000 */
3031 #define IL_DL_ASSOC		(1 << 12)
3032 #define IL_DL_DROP		(1 << 13)
3033 #define IL_DL_TXPOWER		(1 << 14)
3034 #define IL_DL_AP		(1 << 15)
3035 /* 0x000F0000 - 0x00010000 */
3036 #define IL_DL_FW		(1 << 16)
3037 #define IL_DL_RF_KILL		(1 << 17)
3038 #define IL_DL_FW_ERRORS		(1 << 18)
3039 #define IL_DL_LED		(1 << 19)
3040 /* 0x00F00000 - 0x00100000 */
3041 #define IL_DL_RATE		(1 << 20)
3042 #define IL_DL_CALIB		(1 << 21)
3043 #define IL_DL_WEP		(1 << 22)
3044 #define IL_DL_TX		(1 << 23)
3045 /* 0x0F000000 - 0x01000000 */
3046 #define IL_DL_RX		(1 << 24)
3047 #define IL_DL_ISR		(1 << 25)
3048 #define IL_DL_HT		(1 << 26)
3049 /* 0xF0000000 - 0x10000000 */
3050 #define IL_DL_11H		(1 << 28)
3051 #define IL_DL_STATS		(1 << 29)
3052 #define IL_DL_TX_REPLY		(1 << 30)
3053 #define IL_DL_QOS		(1 << 31)
3054 
3055 #define D_INFO(f, a...)		IL_DBG(IL_DL_INFO, f, ## a)
3056 #define D_MAC80211(f, a...)	IL_DBG(IL_DL_MAC80211, f, ## a)
3057 #define D_MACDUMP(f, a...)	IL_DBG(IL_DL_MACDUMP, f, ## a)
3058 #define D_TEMP(f, a...)		IL_DBG(IL_DL_TEMP, f, ## a)
3059 #define D_SCAN(f, a...)		IL_DBG(IL_DL_SCAN, f, ## a)
3060 #define D_RX(f, a...)		IL_DBG(IL_DL_RX, f, ## a)
3061 #define D_TX(f, a...)		IL_DBG(IL_DL_TX, f, ## a)
3062 #define D_ISR(f, a...)		IL_DBG(IL_DL_ISR, f, ## a)
3063 #define D_LED(f, a...)		IL_DBG(IL_DL_LED, f, ## a)
3064 #define D_WEP(f, a...)		IL_DBG(IL_DL_WEP, f, ## a)
3065 #define D_HC(f, a...)		IL_DBG(IL_DL_HCMD, f, ## a)
3066 #define D_HC_DUMP(f, a...)	IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3067 #define D_EEPROM(f, a...)	IL_DBG(IL_DL_EEPROM, f, ## a)
3068 #define D_CALIB(f, a...)	IL_DBG(IL_DL_CALIB, f, ## a)
3069 #define D_FW(f, a...)		IL_DBG(IL_DL_FW, f, ## a)
3070 #define D_RF_KILL(f, a...)	IL_DBG(IL_DL_RF_KILL, f, ## a)
3071 #define D_DROP(f, a...)		IL_DBG(IL_DL_DROP, f, ## a)
3072 #define D_AP(f, a...)		IL_DBG(IL_DL_AP, f, ## a)
3073 #define D_TXPOWER(f, a...)	IL_DBG(IL_DL_TXPOWER, f, ## a)
3074 #define D_RATE(f, a...)		IL_DBG(IL_DL_RATE, f, ## a)
3075 #define D_NOTIF(f, a...)	IL_DBG(IL_DL_NOTIF, f, ## a)
3076 #define D_ASSOC(f, a...)	IL_DBG(IL_DL_ASSOC, f, ## a)
3077 #define D_HT(f, a...)		IL_DBG(IL_DL_HT, f, ## a)
3078 #define D_STATS(f, a...)	IL_DBG(IL_DL_STATS, f, ## a)
3079 #define D_TX_REPLY(f, a...)	IL_DBG(IL_DL_TX_REPLY, f, ## a)
3080 #define D_QOS(f, a...)		IL_DBG(IL_DL_QOS, f, ## a)
3081 #define D_RADIO(f, a...)	IL_DBG(IL_DL_RADIO, f, ## a)
3082 #define D_POWER(f, a...)	IL_DBG(IL_DL_POWER, f, ## a)
3083 #define D_11H(f, a...)		IL_DBG(IL_DL_11H, f, ## a)
3084 
3085 #endif /* __il_core_h__ */
3086