1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4  *
5  * Portions of this file are derived from the ipw3945 project, as well
6  * as portions of the ieee80211 subsystem header files.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of version 2 of the GNU General Public License as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20  *
21  * The full GNU General Public License is included in this distribution in the
22  * file called LICENSE.
23  *
24  * Contact Information:
25  *  Intel Linux Wireless <ilw@linux.intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  *****************************************************************************/
29 
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/firmware.h>
44 #include <linux/etherdevice.h>
45 #include <linux/if_arp.h>
46 
47 #include <net/mac80211.h>
48 
49 #include <asm/div64.h>
50 
51 #define DRV_NAME        "iwl4965"
52 
53 #include "common.h"
54 #include "4965.h"
55 
56 /******************************************************************************
57  *
58  * module boiler plate
59  *
60  ******************************************************************************/
61 
62 /*
63  * module name, copyright, version, etc.
64  */
65 #define DRV_DESCRIPTION	"Intel(R) Wireless WiFi 4965 driver for Linux"
66 
67 #ifdef CONFIG_IWLEGACY_DEBUG
68 #define VD "d"
69 #else
70 #define VD
71 #endif
72 
73 #define DRV_VERSION     IWLWIFI_VERSION VD
74 
75 MODULE_DESCRIPTION(DRV_DESCRIPTION);
76 MODULE_VERSION(DRV_VERSION);
77 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
78 MODULE_LICENSE("GPL");
79 MODULE_ALIAS("iwl4965");
80 
81 void
82 il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status)
83 {
84 	if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
85 		IL_ERR("Tx flush command to flush out all frames\n");
86 		if (!test_bit(S_EXIT_PENDING, &il->status))
87 			queue_work(il->workqueue, &il->tx_flush);
88 	}
89 }
90 
91 /*
92  * EEPROM
93  */
94 struct il_mod_params il4965_mod_params = {
95 	.restart_fw = 1,
96 	/* the rest are 0 by default */
97 };
98 
99 void
100 il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
101 {
102 	unsigned long flags;
103 	int i;
104 	spin_lock_irqsave(&rxq->lock, flags);
105 	INIT_LIST_HEAD(&rxq->rx_free);
106 	INIT_LIST_HEAD(&rxq->rx_used);
107 	/* Fill the rx_used queue with _all_ of the Rx buffers */
108 	for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
109 		/* In the reset function, these buffers may have been allocated
110 		 * to an SKB, so we need to unmap and free potential storage */
111 		if (rxq->pool[i].page != NULL) {
112 			pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
113 				       PAGE_SIZE << il->hw_params.rx_page_order,
114 				       PCI_DMA_FROMDEVICE);
115 			__il_free_pages(il, rxq->pool[i].page);
116 			rxq->pool[i].page = NULL;
117 		}
118 		list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
119 	}
120 
121 	for (i = 0; i < RX_QUEUE_SIZE; i++)
122 		rxq->queue[i] = NULL;
123 
124 	/* Set us so that we have processed and used all buffers, but have
125 	 * not restocked the Rx queue with fresh buffers */
126 	rxq->read = rxq->write = 0;
127 	rxq->write_actual = 0;
128 	rxq->free_count = 0;
129 	spin_unlock_irqrestore(&rxq->lock, flags);
130 }
131 
132 int
133 il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
134 {
135 	u32 rb_size;
136 	const u32 rfdnlog = RX_QUEUE_SIZE_LOG;	/* 256 RBDs */
137 	u32 rb_timeout = 0;
138 
139 	if (il->cfg->mod_params->amsdu_size_8K)
140 		rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
141 	else
142 		rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
143 
144 	/* Stop Rx DMA */
145 	il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
146 
147 	/* Reset driver's Rx queue write idx */
148 	il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
149 
150 	/* Tell device where to find RBD circular buffer in DRAM */
151 	il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8));
152 
153 	/* Tell device where in DRAM to update its Rx status */
154 	il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4);
155 
156 	/* Enable Rx DMA
157 	 * Direct rx interrupts to hosts
158 	 * Rx buffer size 4 or 8k
159 	 * RB timeout 0x10
160 	 * 256 RBDs
161 	 */
162 	il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
163 	      FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
164 	      FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
165 	      FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
166 	      rb_size |
167 	      (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
168 	      (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
169 
170 	/* Set interrupt coalescing timer to default (2048 usecs) */
171 	il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
172 
173 	return 0;
174 }
175 
176 static void
177 il4965_set_pwr_vmain(struct il_priv *il)
178 {
179 /*
180  * (for documentation purposes)
181  * to set power to V_AUX, do:
182 
183 		if (pci_pme_capable(il->pci_dev, PCI_D3cold))
184 			il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
185 					       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
186 					       ~APMG_PS_CTRL_MSK_PWR_SRC);
187  */
188 
189 	il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
190 			      APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
191 			      ~APMG_PS_CTRL_MSK_PWR_SRC);
192 }
193 
194 int
195 il4965_hw_nic_init(struct il_priv *il)
196 {
197 	unsigned long flags;
198 	struct il_rx_queue *rxq = &il->rxq;
199 	int ret;
200 
201 	spin_lock_irqsave(&il->lock, flags);
202 	il_apm_init(il);
203 	/* Set interrupt coalescing calibration timer to default (512 usecs) */
204 	il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF);
205 	spin_unlock_irqrestore(&il->lock, flags);
206 
207 	il4965_set_pwr_vmain(il);
208 	il4965_nic_config(il);
209 
210 	/* Allocate the RX queue, or reset if it is already allocated */
211 	if (!rxq->bd) {
212 		ret = il_rx_queue_alloc(il);
213 		if (ret) {
214 			IL_ERR("Unable to initialize Rx queue\n");
215 			return -ENOMEM;
216 		}
217 	} else
218 		il4965_rx_queue_reset(il, rxq);
219 
220 	il4965_rx_replenish(il);
221 
222 	il4965_rx_init(il, rxq);
223 
224 	spin_lock_irqsave(&il->lock, flags);
225 
226 	rxq->need_update = 1;
227 	il_rx_queue_update_write_ptr(il, rxq);
228 
229 	spin_unlock_irqrestore(&il->lock, flags);
230 
231 	/* Allocate or reset and init all Tx and Command queues */
232 	if (!il->txq) {
233 		ret = il4965_txq_ctx_alloc(il);
234 		if (ret)
235 			return ret;
236 	} else
237 		il4965_txq_ctx_reset(il);
238 
239 	set_bit(S_INIT, &il->status);
240 
241 	return 0;
242 }
243 
244 /**
245  * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
246  */
247 static inline __le32
248 il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
249 {
250 	return cpu_to_le32((u32) (dma_addr >> 8));
251 }
252 
253 /**
254  * il4965_rx_queue_restock - refill RX queue from pre-allocated pool
255  *
256  * If there are slots in the RX queue that need to be restocked,
257  * and we have free pre-allocated buffers, fill the ranks as much
258  * as we can, pulling from rx_free.
259  *
260  * This moves the 'write' idx forward to catch up with 'processed', and
261  * also updates the memory address in the firmware to reference the new
262  * target buffer.
263  */
264 void
265 il4965_rx_queue_restock(struct il_priv *il)
266 {
267 	struct il_rx_queue *rxq = &il->rxq;
268 	struct list_head *element;
269 	struct il_rx_buf *rxb;
270 	unsigned long flags;
271 
272 	spin_lock_irqsave(&rxq->lock, flags);
273 	while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
274 		/* The overwritten rxb must be a used one */
275 		rxb = rxq->queue[rxq->write];
276 		BUG_ON(rxb && rxb->page);
277 
278 		/* Get next free Rx buffer, remove from free list */
279 		element = rxq->rx_free.next;
280 		rxb = list_entry(element, struct il_rx_buf, list);
281 		list_del(element);
282 
283 		/* Point to Rx buffer via next RBD in circular buffer */
284 		rxq->bd[rxq->write] =
285 		    il4965_dma_addr2rbd_ptr(il, rxb->page_dma);
286 		rxq->queue[rxq->write] = rxb;
287 		rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
288 		rxq->free_count--;
289 	}
290 	spin_unlock_irqrestore(&rxq->lock, flags);
291 	/* If the pre-allocated buffer pool is dropping low, schedule to
292 	 * refill it */
293 	if (rxq->free_count <= RX_LOW_WATERMARK)
294 		queue_work(il->workqueue, &il->rx_replenish);
295 
296 	/* If we've added more space for the firmware to place data, tell it.
297 	 * Increment device's write pointer in multiples of 8. */
298 	if (rxq->write_actual != (rxq->write & ~0x7)) {
299 		spin_lock_irqsave(&rxq->lock, flags);
300 		rxq->need_update = 1;
301 		spin_unlock_irqrestore(&rxq->lock, flags);
302 		il_rx_queue_update_write_ptr(il, rxq);
303 	}
304 }
305 
306 /**
307  * il4965_rx_replenish - Move all used packet from rx_used to rx_free
308  *
309  * When moving to rx_free an SKB is allocated for the slot.
310  *
311  * Also restock the Rx queue via il_rx_queue_restock.
312  * This is called as a scheduled work item (except for during initialization)
313  */
314 static void
315 il4965_rx_allocate(struct il_priv *il, gfp_t priority)
316 {
317 	struct il_rx_queue *rxq = &il->rxq;
318 	struct list_head *element;
319 	struct il_rx_buf *rxb;
320 	struct page *page;
321 	dma_addr_t page_dma;
322 	unsigned long flags;
323 	gfp_t gfp_mask = priority;
324 
325 	while (1) {
326 		spin_lock_irqsave(&rxq->lock, flags);
327 		if (list_empty(&rxq->rx_used)) {
328 			spin_unlock_irqrestore(&rxq->lock, flags);
329 			return;
330 		}
331 		spin_unlock_irqrestore(&rxq->lock, flags);
332 
333 		if (rxq->free_count > RX_LOW_WATERMARK)
334 			gfp_mask |= __GFP_NOWARN;
335 
336 		if (il->hw_params.rx_page_order > 0)
337 			gfp_mask |= __GFP_COMP;
338 
339 		/* Alloc a new receive buffer */
340 		page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
341 		if (!page) {
342 			if (net_ratelimit())
343 				D_INFO("alloc_pages failed, " "order: %d\n",
344 				       il->hw_params.rx_page_order);
345 
346 			if (rxq->free_count <= RX_LOW_WATERMARK &&
347 			    net_ratelimit())
348 				IL_ERR("Failed to alloc_pages with %s. "
349 				       "Only %u free buffers remaining.\n",
350 				       priority ==
351 				       GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
352 				       rxq->free_count);
353 			/* We don't reschedule replenish work here -- we will
354 			 * call the restock method and if it still needs
355 			 * more buffers it will schedule replenish */
356 			return;
357 		}
358 
359 		/* Get physical address of the RB */
360 		page_dma =
361 		    pci_map_page(il->pci_dev, page, 0,
362 				 PAGE_SIZE << il->hw_params.rx_page_order,
363 				 PCI_DMA_FROMDEVICE);
364 		if (unlikely(pci_dma_mapping_error(il->pci_dev, page_dma))) {
365 			__free_pages(page, il->hw_params.rx_page_order);
366 			break;
367 		}
368 
369 		spin_lock_irqsave(&rxq->lock, flags);
370 
371 		if (list_empty(&rxq->rx_used)) {
372 			spin_unlock_irqrestore(&rxq->lock, flags);
373 			pci_unmap_page(il->pci_dev, page_dma,
374 				       PAGE_SIZE << il->hw_params.rx_page_order,
375 				       PCI_DMA_FROMDEVICE);
376 			__free_pages(page, il->hw_params.rx_page_order);
377 			return;
378 		}
379 
380 		element = rxq->rx_used.next;
381 		rxb = list_entry(element, struct il_rx_buf, list);
382 		list_del(element);
383 
384 		BUG_ON(rxb->page);
385 
386 		rxb->page = page;
387 		rxb->page_dma = page_dma;
388 		list_add_tail(&rxb->list, &rxq->rx_free);
389 		rxq->free_count++;
390 		il->alloc_rxb_page++;
391 
392 		spin_unlock_irqrestore(&rxq->lock, flags);
393 	}
394 }
395 
396 void
397 il4965_rx_replenish(struct il_priv *il)
398 {
399 	unsigned long flags;
400 
401 	il4965_rx_allocate(il, GFP_KERNEL);
402 
403 	spin_lock_irqsave(&il->lock, flags);
404 	il4965_rx_queue_restock(il);
405 	spin_unlock_irqrestore(&il->lock, flags);
406 }
407 
408 void
409 il4965_rx_replenish_now(struct il_priv *il)
410 {
411 	il4965_rx_allocate(il, GFP_ATOMIC);
412 
413 	il4965_rx_queue_restock(il);
414 }
415 
416 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
417  * If an SKB has been detached, the POOL needs to have its SKB set to NULL
418  * This free routine walks the list of POOL entries and if SKB is set to
419  * non NULL it is unmapped and freed
420  */
421 void
422 il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
423 {
424 	int i;
425 	for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
426 		if (rxq->pool[i].page != NULL) {
427 			pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
428 				       PAGE_SIZE << il->hw_params.rx_page_order,
429 				       PCI_DMA_FROMDEVICE);
430 			__il_free_pages(il, rxq->pool[i].page);
431 			rxq->pool[i].page = NULL;
432 		}
433 	}
434 
435 	dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
436 			  rxq->bd_dma);
437 	dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
438 			  rxq->rb_stts, rxq->rb_stts_dma);
439 	rxq->bd = NULL;
440 	rxq->rb_stts = NULL;
441 }
442 
443 int
444 il4965_rxq_stop(struct il_priv *il)
445 {
446 	int ret;
447 
448 	_il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
449 	ret = _il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG,
450 			   FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
451 			   FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
452 			   1000);
453 	if (ret < 0)
454 		IL_ERR("Can't stop Rx DMA.\n");
455 
456 	return 0;
457 }
458 
459 int
460 il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum nl80211_band band)
461 {
462 	int idx = 0;
463 	int band_offset = 0;
464 
465 	/* HT rate format: mac80211 wants an MCS number, which is just LSB */
466 	if (rate_n_flags & RATE_MCS_HT_MSK) {
467 		idx = (rate_n_flags & 0xff);
468 		return idx;
469 		/* Legacy rate format, search for match in table */
470 	} else {
471 		if (band == NL80211_BAND_5GHZ)
472 			band_offset = IL_FIRST_OFDM_RATE;
473 		for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++)
474 			if (il_rates[idx].plcp == (rate_n_flags & 0xFF))
475 				return idx - band_offset;
476 	}
477 
478 	return -1;
479 }
480 
481 static int
482 il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp)
483 {
484 	/* data from PHY/DSP regarding signal strength, etc.,
485 	 *   contents are always there, not configurable by host.  */
486 	struct il4965_rx_non_cfg_phy *ncphy =
487 	    (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
488 	u32 agc =
489 	    (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >>
490 	    IL49_AGC_DB_POS;
491 
492 	u32 valid_antennae =
493 	    (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK)
494 	    >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
495 	u8 max_rssi = 0;
496 	u32 i;
497 
498 	/* Find max rssi among 3 possible receivers.
499 	 * These values are measured by the digital signal processor (DSP).
500 	 * They should stay fairly constant even as the signal strength varies,
501 	 *   if the radio's automatic gain control (AGC) is working right.
502 	 * AGC value (see below) will provide the "interesting" info. */
503 	for (i = 0; i < 3; i++)
504 		if (valid_antennae & (1 << i))
505 			max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
506 
507 	D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
508 		ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
509 		max_rssi, agc);
510 
511 	/* dBm = max_rssi dB - agc dB - constant.
512 	 * Higher AGC (higher radio gain) means lower signal. */
513 	return max_rssi - agc - IL4965_RSSI_OFFSET;
514 }
515 
516 static u32
517 il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in)
518 {
519 	u32 decrypt_out = 0;
520 
521 	if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
522 	    RX_RES_STATUS_STATION_FOUND)
523 		decrypt_out |=
524 		    (RX_RES_STATUS_STATION_FOUND |
525 		     RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
526 
527 	decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
528 
529 	/* packet was not encrypted */
530 	if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
531 	    RX_RES_STATUS_SEC_TYPE_NONE)
532 		return decrypt_out;
533 
534 	/* packet was encrypted with unknown alg */
535 	if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
536 	    RX_RES_STATUS_SEC_TYPE_ERR)
537 		return decrypt_out;
538 
539 	/* decryption was not done in HW */
540 	if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
541 	    RX_MPDU_RES_STATUS_DEC_DONE_MSK)
542 		return decrypt_out;
543 
544 	switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
545 
546 	case RX_RES_STATUS_SEC_TYPE_CCMP:
547 		/* alg is CCM: check MIC only */
548 		if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
549 			/* Bad MIC */
550 			decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
551 		else
552 			decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
553 
554 		break;
555 
556 	case RX_RES_STATUS_SEC_TYPE_TKIP:
557 		if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
558 			/* Bad TTAK */
559 			decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
560 			break;
561 		}
562 		/* fall through if TTAK OK */
563 	default:
564 		if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
565 			decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
566 		else
567 			decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
568 		break;
569 	}
570 
571 	D_RX("decrypt_in:0x%x  decrypt_out = 0x%x\n", decrypt_in, decrypt_out);
572 
573 	return decrypt_out;
574 }
575 
576 #define SMALL_PACKET_SIZE 256
577 
578 static void
579 il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr,
580 			       u32 len, u32 ampdu_status, struct il_rx_buf *rxb,
581 			       struct ieee80211_rx_status *stats)
582 {
583 	struct sk_buff *skb;
584 	__le16 fc = hdr->frame_control;
585 
586 	/* We only process data packets if the interface is open */
587 	if (unlikely(!il->is_open)) {
588 		D_DROP("Dropping packet while interface is not open.\n");
589 		return;
590 	}
591 
592 	if (unlikely(test_bit(IL_STOP_REASON_PASSIVE, &il->stop_reason))) {
593 		il_wake_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
594 		D_INFO("Woke queues - frame received on passive channel\n");
595 	}
596 
597 	/* In case of HW accelerated crypto and bad decryption, drop */
598 	if (!il->cfg->mod_params->sw_crypto &&
599 	    il_set_decrypted_flag(il, hdr, ampdu_status, stats))
600 		return;
601 
602 	skb = dev_alloc_skb(SMALL_PACKET_SIZE);
603 	if (!skb) {
604 		IL_ERR("dev_alloc_skb failed\n");
605 		return;
606 	}
607 
608 	if (len <= SMALL_PACKET_SIZE) {
609 		memcpy(skb_put(skb, len), hdr, len);
610 	} else {
611 		skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb),
612 				len, PAGE_SIZE << il->hw_params.rx_page_order);
613 		il->alloc_rxb_page--;
614 		rxb->page = NULL;
615 	}
616 
617 	il_update_stats(il, false, fc, len);
618 	memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
619 
620 	ieee80211_rx(il->hw, skb);
621 }
622 
623 /* Called for N_RX (legacy ABG frames), or
624  * N_RX_MPDU (HT high-throughput N frames). */
625 static void
626 il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
627 {
628 	struct ieee80211_hdr *header;
629 	struct ieee80211_rx_status rx_status = {};
630 	struct il_rx_pkt *pkt = rxb_addr(rxb);
631 	struct il_rx_phy_res *phy_res;
632 	__le32 rx_pkt_status;
633 	struct il_rx_mpdu_res_start *amsdu;
634 	u32 len;
635 	u32 ampdu_status;
636 	u32 rate_n_flags;
637 
638 	/**
639 	 * N_RX and N_RX_MPDU are handled differently.
640 	 *	N_RX: physical layer info is in this buffer
641 	 *	N_RX_MPDU: physical layer info was sent in separate
642 	 *		command and cached in il->last_phy_res
643 	 *
644 	 * Here we set up local variables depending on which command is
645 	 * received.
646 	 */
647 	if (pkt->hdr.cmd == N_RX) {
648 		phy_res = (struct il_rx_phy_res *)pkt->u.raw;
649 		header =
650 		    (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) +
651 					     phy_res->cfg_phy_cnt);
652 
653 		len = le16_to_cpu(phy_res->byte_count);
654 		rx_pkt_status =
655 		    *(__le32 *) (pkt->u.raw + sizeof(*phy_res) +
656 				 phy_res->cfg_phy_cnt + len);
657 		ampdu_status = le32_to_cpu(rx_pkt_status);
658 	} else {
659 		if (!il->_4965.last_phy_res_valid) {
660 			IL_ERR("MPDU frame without cached PHY data\n");
661 			return;
662 		}
663 		phy_res = &il->_4965.last_phy_res;
664 		amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw;
665 		header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
666 		len = le16_to_cpu(amsdu->byte_count);
667 		rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len);
668 		ampdu_status =
669 		    il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status));
670 	}
671 
672 	if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
673 		D_DROP("dsp size out of range [0,20]: %d\n",
674 		       phy_res->cfg_phy_cnt);
675 		return;
676 	}
677 
678 	if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
679 	    !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
680 		D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status));
681 		return;
682 	}
683 
684 	/* This will be used in several places later */
685 	rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
686 
687 	/* rx_status carries information about the packet to mac80211 */
688 	rx_status.mactime = le64_to_cpu(phy_res->timestamp);
689 	rx_status.band =
690 	    (phy_res->
691 	     phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? NL80211_BAND_2GHZ :
692 	    NL80211_BAND_5GHZ;
693 	rx_status.freq =
694 	    ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
695 					   rx_status.band);
696 	rx_status.rate_idx =
697 	    il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
698 	rx_status.flag = 0;
699 
700 	/* TSF isn't reliable. In order to allow smooth user experience,
701 	 * this W/A doesn't propagate it to the mac80211 */
702 	/*rx_status.flag |= RX_FLAG_MACTIME_START; */
703 
704 	il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
705 
706 	/* Find max signal strength (dBm) among 3 antenna/receiver chains */
707 	rx_status.signal = il4965_calc_rssi(il, phy_res);
708 
709 	D_STATS("Rssi %d, TSF %llu\n", rx_status.signal,
710 		(unsigned long long)rx_status.mactime);
711 
712 	/*
713 	 * "antenna number"
714 	 *
715 	 * It seems that the antenna field in the phy flags value
716 	 * is actually a bit field. This is undefined by radiotap,
717 	 * it wants an actual antenna number but I always get "7"
718 	 * for most legacy frames I receive indicating that the
719 	 * same frame was received on all three RX chains.
720 	 *
721 	 * I think this field should be removed in favor of a
722 	 * new 802.11n radiotap field "RX chains" that is defined
723 	 * as a bitmask.
724 	 */
725 	rx_status.antenna =
726 	    (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
727 	    RX_RES_PHY_FLAGS_ANTENNA_POS;
728 
729 	/* set the preamble flag if appropriate */
730 	if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
731 		rx_status.enc_flags |= RX_ENC_FLAG_SHORTPRE;
732 
733 	/* Set up the HT phy flags */
734 	if (rate_n_flags & RATE_MCS_HT_MSK)
735 		rx_status.encoding = RX_ENC_HT;
736 	if (rate_n_flags & RATE_MCS_HT40_MSK)
737 		rx_status.bw = RATE_INFO_BW_40;
738 	else
739 		rx_status.bw = RATE_INFO_BW_20;
740 	if (rate_n_flags & RATE_MCS_SGI_MSK)
741 		rx_status.enc_flags |= RX_ENC_FLAG_SHORT_GI;
742 
743 	if (phy_res->phy_flags & RX_RES_PHY_FLAGS_AGG_MSK) {
744 		/* We know which subframes of an A-MPDU belong
745 		 * together since we get a single PHY response
746 		 * from the firmware for all of them.
747 		 */
748 
749 		rx_status.flag |= RX_FLAG_AMPDU_DETAILS;
750 		rx_status.ampdu_reference = il->_4965.ampdu_ref;
751 	}
752 
753 	il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb,
754 				       &rx_status);
755 }
756 
757 /* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY).
758  * This will be used later in il_hdl_rx() for N_RX_MPDU. */
759 static void
760 il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb)
761 {
762 	struct il_rx_pkt *pkt = rxb_addr(rxb);
763 	il->_4965.last_phy_res_valid = true;
764 	il->_4965.ampdu_ref++;
765 	memcpy(&il->_4965.last_phy_res, pkt->u.raw,
766 	       sizeof(struct il_rx_phy_res));
767 }
768 
769 static int
770 il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif,
771 			     enum nl80211_band band, u8 is_active,
772 			     u8 n_probes, struct il_scan_channel *scan_ch)
773 {
774 	struct ieee80211_channel *chan;
775 	const struct ieee80211_supported_band *sband;
776 	const struct il_channel_info *ch_info;
777 	u16 passive_dwell = 0;
778 	u16 active_dwell = 0;
779 	int added, i;
780 	u16 channel;
781 
782 	sband = il_get_hw_mode(il, band);
783 	if (!sband)
784 		return 0;
785 
786 	active_dwell = il_get_active_dwell_time(il, band, n_probes);
787 	passive_dwell = il_get_passive_dwell_time(il, band, vif);
788 
789 	if (passive_dwell <= active_dwell)
790 		passive_dwell = active_dwell + 1;
791 
792 	for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
793 		chan = il->scan_request->channels[i];
794 
795 		if (chan->band != band)
796 			continue;
797 
798 		channel = chan->hw_value;
799 		scan_ch->channel = cpu_to_le16(channel);
800 
801 		ch_info = il_get_channel_info(il, band, channel);
802 		if (!il_is_channel_valid(ch_info)) {
803 			D_SCAN("Channel %d is INVALID for this band.\n",
804 			       channel);
805 			continue;
806 		}
807 
808 		if (!is_active || il_is_channel_passive(ch_info) ||
809 		    (chan->flags & IEEE80211_CHAN_NO_IR))
810 			scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
811 		else
812 			scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
813 
814 		if (n_probes)
815 			scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes);
816 
817 		scan_ch->active_dwell = cpu_to_le16(active_dwell);
818 		scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
819 
820 		/* Set txpower levels to defaults */
821 		scan_ch->dsp_atten = 110;
822 
823 		/* NOTE: if we were doing 6Mb OFDM for scans we'd use
824 		 * power level:
825 		 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
826 		 */
827 		if (band == NL80211_BAND_5GHZ)
828 			scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
829 		else
830 			scan_ch->tx_gain = ((1 << 5) | (5 << 3));
831 
832 		D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel,
833 		       le32_to_cpu(scan_ch->type),
834 		       (scan_ch->
835 			type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE",
836 		       (scan_ch->
837 			type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell :
838 		       passive_dwell);
839 
840 		scan_ch++;
841 		added++;
842 	}
843 
844 	D_SCAN("total channels to scan %d\n", added);
845 	return added;
846 }
847 
848 static void
849 il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid)
850 {
851 	int i;
852 	u8 ind = *ant;
853 
854 	for (i = 0; i < RATE_ANT_NUM - 1; i++) {
855 		ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
856 		if (valid & BIT(ind)) {
857 			*ant = ind;
858 			return;
859 		}
860 	}
861 }
862 
863 int
864 il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
865 {
866 	struct il_host_cmd cmd = {
867 		.id = C_SCAN,
868 		.len = sizeof(struct il_scan_cmd),
869 		.flags = CMD_SIZE_HUGE,
870 	};
871 	struct il_scan_cmd *scan;
872 	u32 rate_flags = 0;
873 	u16 cmd_len;
874 	u16 rx_chain = 0;
875 	enum nl80211_band band;
876 	u8 n_probes = 0;
877 	u8 rx_ant = il->hw_params.valid_rx_ant;
878 	u8 rate;
879 	bool is_active = false;
880 	int chan_mod;
881 	u8 active_chains;
882 	u8 scan_tx_antennas = il->hw_params.valid_tx_ant;
883 	int ret;
884 
885 	lockdep_assert_held(&il->mutex);
886 
887 	if (!il->scan_cmd) {
888 		il->scan_cmd =
889 		    kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE,
890 			    GFP_KERNEL);
891 		if (!il->scan_cmd) {
892 			D_SCAN("fail to allocate memory for scan\n");
893 			return -ENOMEM;
894 		}
895 	}
896 	scan = il->scan_cmd;
897 	memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE);
898 
899 	scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
900 	scan->quiet_time = IL_ACTIVE_QUIET_TIME;
901 
902 	if (il_is_any_associated(il)) {
903 		u16 interval;
904 		u32 extra;
905 		u32 suspend_time = 100;
906 		u32 scan_suspend_time = 100;
907 
908 		D_INFO("Scanning while associated...\n");
909 		interval = vif->bss_conf.beacon_int;
910 
911 		scan->suspend_time = 0;
912 		scan->max_out_time = cpu_to_le32(200 * 1024);
913 		if (!interval)
914 			interval = suspend_time;
915 
916 		extra = (suspend_time / interval) << 22;
917 		scan_suspend_time =
918 		    (extra | ((suspend_time % interval) * 1024));
919 		scan->suspend_time = cpu_to_le32(scan_suspend_time);
920 		D_SCAN("suspend_time 0x%X beacon interval %d\n",
921 		       scan_suspend_time, interval);
922 	}
923 
924 	if (il->scan_request->n_ssids) {
925 		int i, p = 0;
926 		D_SCAN("Kicking off active scan\n");
927 		for (i = 0; i < il->scan_request->n_ssids; i++) {
928 			/* always does wildcard anyway */
929 			if (!il->scan_request->ssids[i].ssid_len)
930 				continue;
931 			scan->direct_scan[p].id = WLAN_EID_SSID;
932 			scan->direct_scan[p].len =
933 			    il->scan_request->ssids[i].ssid_len;
934 			memcpy(scan->direct_scan[p].ssid,
935 			       il->scan_request->ssids[i].ssid,
936 			       il->scan_request->ssids[i].ssid_len);
937 			n_probes++;
938 			p++;
939 		}
940 		is_active = true;
941 	} else
942 		D_SCAN("Start passive scan.\n");
943 
944 	scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
945 	scan->tx_cmd.sta_id = il->hw_params.bcast_id;
946 	scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
947 
948 	switch (il->scan_band) {
949 	case NL80211_BAND_2GHZ:
950 		scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
951 		chan_mod =
952 		    le32_to_cpu(il->active.flags & RXON_FLG_CHANNEL_MODE_MSK) >>
953 		    RXON_FLG_CHANNEL_MODE_POS;
954 		if (chan_mod == CHANNEL_MODE_PURE_40) {
955 			rate = RATE_6M_PLCP;
956 		} else {
957 			rate = RATE_1M_PLCP;
958 			rate_flags = RATE_MCS_CCK_MSK;
959 		}
960 		break;
961 	case NL80211_BAND_5GHZ:
962 		rate = RATE_6M_PLCP;
963 		break;
964 	default:
965 		IL_WARN("Invalid scan band\n");
966 		return -EIO;
967 	}
968 
969 	/*
970 	 * If active scanning is requested but a certain channel is
971 	 * marked passive, we can do active scanning if we detect
972 	 * transmissions.
973 	 *
974 	 * There is an issue with some firmware versions that triggers
975 	 * a sysassert on a "good CRC threshold" of zero (== disabled),
976 	 * on a radar channel even though this means that we should NOT
977 	 * send probes.
978 	 *
979 	 * The "good CRC threshold" is the number of frames that we
980 	 * need to receive during our dwell time on a channel before
981 	 * sending out probes -- setting this to a huge value will
982 	 * mean we never reach it, but at the same time work around
983 	 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER
984 	 * here instead of IL_GOOD_CRC_TH_DISABLED.
985 	 */
986 	scan->good_CRC_th =
987 	    is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
988 
989 	band = il->scan_band;
990 
991 	if (il->cfg->scan_rx_antennas[band])
992 		rx_ant = il->cfg->scan_rx_antennas[band];
993 
994 	il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas);
995 	rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS;
996 	scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags);
997 
998 	/* In power save mode use one chain, otherwise use all chains */
999 	if (test_bit(S_POWER_PMI, &il->status)) {
1000 		/* rx_ant has been set to all valid chains previously */
1001 		active_chains =
1002 		    rx_ant & ((u8) (il->chain_noise_data.active_chains));
1003 		if (!active_chains)
1004 			active_chains = rx_ant;
1005 
1006 		D_SCAN("chain_noise_data.active_chains: %u\n",
1007 		       il->chain_noise_data.active_chains);
1008 
1009 		rx_ant = il4965_first_antenna(active_chains);
1010 	}
1011 
1012 	/* MIMO is not used here, but value is required */
1013 	rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1014 	rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1015 	rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1016 	rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1017 	scan->rx_chain = cpu_to_le16(rx_chain);
1018 
1019 	cmd_len =
1020 	    il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
1021 			      vif->addr, il->scan_request->ie,
1022 			      il->scan_request->ie_len,
1023 			      IL_MAX_SCAN_SIZE - sizeof(*scan));
1024 	scan->tx_cmd.len = cpu_to_le16(cmd_len);
1025 
1026 	scan->filter_flags |=
1027 	    (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK);
1028 
1029 	scan->channel_count =
1030 	    il4965_get_channels_for_scan(il, vif, band, is_active, n_probes,
1031 					 (void *)&scan->data[cmd_len]);
1032 	if (scan->channel_count == 0) {
1033 		D_SCAN("channel count %d\n", scan->channel_count);
1034 		return -EIO;
1035 	}
1036 
1037 	cmd.len +=
1038 	    le16_to_cpu(scan->tx_cmd.len) +
1039 	    scan->channel_count * sizeof(struct il_scan_channel);
1040 	cmd.data = scan;
1041 	scan->len = cpu_to_le16(cmd.len);
1042 
1043 	set_bit(S_SCAN_HW, &il->status);
1044 
1045 	ret = il_send_cmd_sync(il, &cmd);
1046 	if (ret)
1047 		clear_bit(S_SCAN_HW, &il->status);
1048 
1049 	return ret;
1050 }
1051 
1052 int
1053 il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
1054 			   bool add)
1055 {
1056 	struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1057 
1058 	if (add)
1059 		return il4965_add_bssid_station(il, vif->bss_conf.bssid,
1060 						&vif_priv->ibss_bssid_sta_id);
1061 	return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
1062 				 vif->bss_conf.bssid);
1063 }
1064 
1065 void
1066 il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed)
1067 {
1068 	lockdep_assert_held(&il->sta_lock);
1069 
1070 	if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1071 		il->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1072 	else {
1073 		D_TX("free more than tfds_in_queue (%u:%d)\n",
1074 		     il->stations[sta_id].tid[tid].tfds_in_queue, freed);
1075 		il->stations[sta_id].tid[tid].tfds_in_queue = 0;
1076 	}
1077 }
1078 
1079 #define IL_TX_QUEUE_MSK	0xfffff
1080 
1081 static bool
1082 il4965_is_single_rx_stream(struct il_priv *il)
1083 {
1084 	return il->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1085 	    il->current_ht_config.single_chain_sufficient;
1086 }
1087 
1088 #define IL_NUM_RX_CHAINS_MULTIPLE	3
1089 #define IL_NUM_RX_CHAINS_SINGLE	2
1090 #define IL_NUM_IDLE_CHAINS_DUAL	2
1091 #define IL_NUM_IDLE_CHAINS_SINGLE	1
1092 
1093 /*
1094  * Determine how many receiver/antenna chains to use.
1095  *
1096  * More provides better reception via diversity.  Fewer saves power
1097  * at the expense of throughput, but only when not in powersave to
1098  * start with.
1099  *
1100  * MIMO (dual stream) requires at least 2, but works better with 3.
1101  * This does not determine *which* chains to use, just how many.
1102  */
1103 static int
1104 il4965_get_active_rx_chain_count(struct il_priv *il)
1105 {
1106 	/* # of Rx chains to use when expecting MIMO. */
1107 	if (il4965_is_single_rx_stream(il))
1108 		return IL_NUM_RX_CHAINS_SINGLE;
1109 	else
1110 		return IL_NUM_RX_CHAINS_MULTIPLE;
1111 }
1112 
1113 /*
1114  * When we are in power saving mode, unless device support spatial
1115  * multiplexing power save, use the active count for rx chain count.
1116  */
1117 static int
1118 il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt)
1119 {
1120 	/* # Rx chains when idling, depending on SMPS mode */
1121 	switch (il->current_ht_config.smps) {
1122 	case IEEE80211_SMPS_STATIC:
1123 	case IEEE80211_SMPS_DYNAMIC:
1124 		return IL_NUM_IDLE_CHAINS_SINGLE;
1125 	case IEEE80211_SMPS_OFF:
1126 		return active_cnt;
1127 	default:
1128 		WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps);
1129 		return active_cnt;
1130 	}
1131 }
1132 
1133 /* up to 4 chains */
1134 static u8
1135 il4965_count_chain_bitmap(u32 chain_bitmap)
1136 {
1137 	u8 res;
1138 	res = (chain_bitmap & BIT(0)) >> 0;
1139 	res += (chain_bitmap & BIT(1)) >> 1;
1140 	res += (chain_bitmap & BIT(2)) >> 2;
1141 	res += (chain_bitmap & BIT(3)) >> 3;
1142 	return res;
1143 }
1144 
1145 /**
1146  * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1147  *
1148  * Selects how many and which Rx receivers/antennas/chains to use.
1149  * This should not be used for scan command ... it puts data in wrong place.
1150  */
1151 void
1152 il4965_set_rxon_chain(struct il_priv *il)
1153 {
1154 	bool is_single = il4965_is_single_rx_stream(il);
1155 	bool is_cam = !test_bit(S_POWER_PMI, &il->status);
1156 	u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1157 	u32 active_chains;
1158 	u16 rx_chain;
1159 
1160 	/* Tell uCode which antennas are actually connected.
1161 	 * Before first association, we assume all antennas are connected.
1162 	 * Just after first association, il4965_chain_noise_calibration()
1163 	 *    checks which antennas actually *are* connected. */
1164 	if (il->chain_noise_data.active_chains)
1165 		active_chains = il->chain_noise_data.active_chains;
1166 	else
1167 		active_chains = il->hw_params.valid_rx_ant;
1168 
1169 	rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1170 
1171 	/* How many receivers should we use? */
1172 	active_rx_cnt = il4965_get_active_rx_chain_count(il);
1173 	idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt);
1174 
1175 	/* correct rx chain count according hw settings
1176 	 * and chain noise calibration
1177 	 */
1178 	valid_rx_cnt = il4965_count_chain_bitmap(active_chains);
1179 	if (valid_rx_cnt < active_rx_cnt)
1180 		active_rx_cnt = valid_rx_cnt;
1181 
1182 	if (valid_rx_cnt < idle_rx_cnt)
1183 		idle_rx_cnt = valid_rx_cnt;
1184 
1185 	rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1186 	rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1187 
1188 	il->staging.rx_chain = cpu_to_le16(rx_chain);
1189 
1190 	if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam)
1191 		il->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1192 	else
1193 		il->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1194 
1195 	D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain,
1196 		active_rx_cnt, idle_rx_cnt);
1197 
1198 	WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1199 		active_rx_cnt < idle_rx_cnt);
1200 }
1201 
1202 static const char *
1203 il4965_get_fh_string(int cmd)
1204 {
1205 	switch (cmd) {
1206 		IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG);
1207 		IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG);
1208 		IL_CMD(FH49_RSCSR_CHNL0_WPTR);
1209 		IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG);
1210 		IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG);
1211 		IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG);
1212 		IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1213 		IL_CMD(FH49_TSSR_TX_STATUS_REG);
1214 		IL_CMD(FH49_TSSR_TX_ERROR_REG);
1215 	default:
1216 		return "UNKNOWN";
1217 	}
1218 }
1219 
1220 int
1221 il4965_dump_fh(struct il_priv *il, char **buf, bool display)
1222 {
1223 	int i;
1224 #ifdef CONFIG_IWLEGACY_DEBUG
1225 	int pos = 0;
1226 	size_t bufsz = 0;
1227 #endif
1228 	static const u32 fh_tbl[] = {
1229 		FH49_RSCSR_CHNL0_STTS_WPTR_REG,
1230 		FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
1231 		FH49_RSCSR_CHNL0_WPTR,
1232 		FH49_MEM_RCSR_CHNL0_CONFIG_REG,
1233 		FH49_MEM_RSSR_SHARED_CTRL_REG,
1234 		FH49_MEM_RSSR_RX_STATUS_REG,
1235 		FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1236 		FH49_TSSR_TX_STATUS_REG,
1237 		FH49_TSSR_TX_ERROR_REG
1238 	};
1239 #ifdef CONFIG_IWLEGACY_DEBUG
1240 	if (display) {
1241 		bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1242 		*buf = kmalloc(bufsz, GFP_KERNEL);
1243 		if (!*buf)
1244 			return -ENOMEM;
1245 		pos +=
1246 		    scnprintf(*buf + pos, bufsz - pos, "FH register values:\n");
1247 		for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1248 			pos +=
1249 			    scnprintf(*buf + pos, bufsz - pos,
1250 				      "  %34s: 0X%08x\n",
1251 				      il4965_get_fh_string(fh_tbl[i]),
1252 				      il_rd(il, fh_tbl[i]));
1253 		}
1254 		return pos;
1255 	}
1256 #endif
1257 	IL_ERR("FH register values:\n");
1258 	for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1259 		IL_ERR("  %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]),
1260 		       il_rd(il, fh_tbl[i]));
1261 	}
1262 	return 0;
1263 }
1264 
1265 static void
1266 il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb)
1267 {
1268 	struct il_rx_pkt *pkt = rxb_addr(rxb);
1269 	struct il_missed_beacon_notif *missed_beacon;
1270 
1271 	missed_beacon = &pkt->u.missed_beacon;
1272 	if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
1273 	    il->missed_beacon_threshold) {
1274 		D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
1275 			le32_to_cpu(missed_beacon->consecutive_missed_beacons),
1276 			le32_to_cpu(missed_beacon->total_missed_becons),
1277 			le32_to_cpu(missed_beacon->num_recvd_beacons),
1278 			le32_to_cpu(missed_beacon->num_expected_beacons));
1279 		if (!test_bit(S_SCANNING, &il->status))
1280 			il4965_init_sensitivity(il);
1281 	}
1282 }
1283 
1284 /* Calculate noise level, based on measurements during network silence just
1285  *   before arriving beacon.  This measurement can be done only if we know
1286  *   exactly when to expect beacons, therefore only when we're associated. */
1287 static void
1288 il4965_rx_calc_noise(struct il_priv *il)
1289 {
1290 	struct stats_rx_non_phy *rx_info;
1291 	int num_active_rx = 0;
1292 	int total_silence = 0;
1293 	int bcn_silence_a, bcn_silence_b, bcn_silence_c;
1294 	int last_rx_noise;
1295 
1296 	rx_info = &(il->_4965.stats.rx.general);
1297 	bcn_silence_a =
1298 	    le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
1299 	bcn_silence_b =
1300 	    le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
1301 	bcn_silence_c =
1302 	    le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
1303 
1304 	if (bcn_silence_a) {
1305 		total_silence += bcn_silence_a;
1306 		num_active_rx++;
1307 	}
1308 	if (bcn_silence_b) {
1309 		total_silence += bcn_silence_b;
1310 		num_active_rx++;
1311 	}
1312 	if (bcn_silence_c) {
1313 		total_silence += bcn_silence_c;
1314 		num_active_rx++;
1315 	}
1316 
1317 	/* Average among active antennas */
1318 	if (num_active_rx)
1319 		last_rx_noise = (total_silence / num_active_rx) - 107;
1320 	else
1321 		last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE;
1322 
1323 	D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a,
1324 		bcn_silence_b, bcn_silence_c, last_rx_noise);
1325 }
1326 
1327 #ifdef CONFIG_IWLEGACY_DEBUGFS
1328 /*
1329  *  based on the assumption of all stats counter are in DWORD
1330  *  FIXME: This function is for debugging, do not deal with
1331  *  the case of counters roll-over.
1332  */
1333 static void
1334 il4965_accumulative_stats(struct il_priv *il, __le32 * stats)
1335 {
1336 	int i, size;
1337 	__le32 *prev_stats;
1338 	u32 *accum_stats;
1339 	u32 *delta, *max_delta;
1340 	struct stats_general_common *general, *accum_general;
1341 	struct stats_tx *tx, *accum_tx;
1342 
1343 	prev_stats = (__le32 *) &il->_4965.stats;
1344 	accum_stats = (u32 *) &il->_4965.accum_stats;
1345 	size = sizeof(struct il_notif_stats);
1346 	general = &il->_4965.stats.general.common;
1347 	accum_general = &il->_4965.accum_stats.general.common;
1348 	tx = &il->_4965.stats.tx;
1349 	accum_tx = &il->_4965.accum_stats.tx;
1350 	delta = (u32 *) &il->_4965.delta_stats;
1351 	max_delta = (u32 *) &il->_4965.max_delta;
1352 
1353 	for (i = sizeof(__le32); i < size;
1354 	     i +=
1355 	     sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
1356 	     accum_stats++) {
1357 		if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
1358 			*delta =
1359 			    (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
1360 			*accum_stats += *delta;
1361 			if (*delta > *max_delta)
1362 				*max_delta = *delta;
1363 		}
1364 	}
1365 
1366 	/* reset accumulative stats for "no-counter" type stats */
1367 	accum_general->temperature = general->temperature;
1368 	accum_general->ttl_timestamp = general->ttl_timestamp;
1369 }
1370 #endif
1371 
1372 static void
1373 il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
1374 {
1375 	const int recalib_seconds = 60;
1376 	bool change;
1377 	struct il_rx_pkt *pkt = rxb_addr(rxb);
1378 
1379 	D_RX("Statistics notification received (%d vs %d).\n",
1380 	     (int)sizeof(struct il_notif_stats),
1381 	     le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
1382 
1383 	change =
1384 	    ((il->_4965.stats.general.common.temperature !=
1385 	      pkt->u.stats.general.common.temperature) ||
1386 	     ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) !=
1387 	      (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK)));
1388 #ifdef CONFIG_IWLEGACY_DEBUGFS
1389 	il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats);
1390 #endif
1391 
1392 	/* TODO: reading some of stats is unneeded */
1393 	memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats));
1394 
1395 	set_bit(S_STATS, &il->status);
1396 
1397 	/*
1398 	 * Reschedule the stats timer to occur in recalib_seconds to ensure
1399 	 * we get a thermal update even if the uCode doesn't give us one
1400 	 */
1401 	mod_timer(&il->stats_periodic,
1402 		  jiffies + msecs_to_jiffies(recalib_seconds * 1000));
1403 
1404 	if (unlikely(!test_bit(S_SCANNING, &il->status)) &&
1405 	    (pkt->hdr.cmd == N_STATS)) {
1406 		il4965_rx_calc_noise(il);
1407 		queue_work(il->workqueue, &il->run_time_calib_work);
1408 	}
1409 
1410 	if (change)
1411 		il4965_temperature_calib(il);
1412 }
1413 
1414 static void
1415 il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
1416 {
1417 	struct il_rx_pkt *pkt = rxb_addr(rxb);
1418 
1419 	if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) {
1420 #ifdef CONFIG_IWLEGACY_DEBUGFS
1421 		memset(&il->_4965.accum_stats, 0,
1422 		       sizeof(struct il_notif_stats));
1423 		memset(&il->_4965.delta_stats, 0,
1424 		       sizeof(struct il_notif_stats));
1425 		memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats));
1426 #endif
1427 		D_RX("Statistics have been cleared\n");
1428 	}
1429 	il4965_hdl_stats(il, rxb);
1430 }
1431 
1432 
1433 /*
1434  * mac80211 queues, ACs, hardware queues, FIFOs.
1435  *
1436  * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
1437  *
1438  * Mac80211 uses the following numbers, which we get as from it
1439  * by way of skb_get_queue_mapping(skb):
1440  *
1441  *     VO      0
1442  *     VI      1
1443  *     BE      2
1444  *     BK      3
1445  *
1446  *
1447  * Regular (not A-MPDU) frames are put into hardware queues corresponding
1448  * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
1449  * own queue per aggregation session (RA/TID combination), such queues are
1450  * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
1451  * order to map frames to the right queue, we also need an AC->hw queue
1452  * mapping. This is implemented here.
1453  *
1454  * Due to the way hw queues are set up (by the hw specific modules like
1455  * 4965.c), the AC->hw queue mapping is the identity
1456  * mapping.
1457  */
1458 
1459 static const u8 tid_to_ac[] = {
1460 	IEEE80211_AC_BE,
1461 	IEEE80211_AC_BK,
1462 	IEEE80211_AC_BK,
1463 	IEEE80211_AC_BE,
1464 	IEEE80211_AC_VI,
1465 	IEEE80211_AC_VI,
1466 	IEEE80211_AC_VO,
1467 	IEEE80211_AC_VO
1468 };
1469 
1470 static inline int
1471 il4965_get_ac_from_tid(u16 tid)
1472 {
1473 	if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1474 		return tid_to_ac[tid];
1475 
1476 	/* no support for TIDs 8-15 yet */
1477 	return -EINVAL;
1478 }
1479 
1480 static inline int
1481 il4965_get_fifo_from_tid(u16 tid)
1482 {
1483 	const u8 ac_to_fifo[] = {
1484 		IL_TX_FIFO_VO,
1485 		IL_TX_FIFO_VI,
1486 		IL_TX_FIFO_BE,
1487 		IL_TX_FIFO_BK,
1488 	};
1489 
1490 	if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1491 		return ac_to_fifo[tid_to_ac[tid]];
1492 
1493 	/* no support for TIDs 8-15 yet */
1494 	return -EINVAL;
1495 }
1496 
1497 /*
1498  * handle build C_TX command notification.
1499  */
1500 static void
1501 il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb,
1502 			  struct il_tx_cmd *tx_cmd,
1503 			  struct ieee80211_tx_info *info,
1504 			  struct ieee80211_hdr *hdr, u8 std_id)
1505 {
1506 	__le16 fc = hdr->frame_control;
1507 	__le32 tx_flags = tx_cmd->tx_flags;
1508 
1509 	tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1510 	if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
1511 		tx_flags |= TX_CMD_FLG_ACK_MSK;
1512 		if (ieee80211_is_mgmt(fc))
1513 			tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1514 		if (ieee80211_is_probe_resp(fc) &&
1515 		    !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
1516 			tx_flags |= TX_CMD_FLG_TSF_MSK;
1517 	} else {
1518 		tx_flags &= (~TX_CMD_FLG_ACK_MSK);
1519 		tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1520 	}
1521 
1522 	if (ieee80211_is_back_req(fc))
1523 		tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
1524 
1525 	tx_cmd->sta_id = std_id;
1526 	if (ieee80211_has_morefrags(fc))
1527 		tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
1528 
1529 	if (ieee80211_is_data_qos(fc)) {
1530 		u8 *qc = ieee80211_get_qos_ctl(hdr);
1531 		tx_cmd->tid_tspec = qc[0] & 0xf;
1532 		tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
1533 	} else {
1534 		tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1535 	}
1536 
1537 	il_tx_cmd_protection(il, info, fc, &tx_flags);
1538 
1539 	tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
1540 	if (ieee80211_is_mgmt(fc)) {
1541 		if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
1542 			tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
1543 		else
1544 			tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
1545 	} else {
1546 		tx_cmd->timeout.pm_frame_timeout = 0;
1547 	}
1548 
1549 	tx_cmd->driver_txop = 0;
1550 	tx_cmd->tx_flags = tx_flags;
1551 	tx_cmd->next_frame_len = 0;
1552 }
1553 
1554 static void
1555 il4965_tx_cmd_build_rate(struct il_priv *il,
1556 			 struct il_tx_cmd *tx_cmd,
1557 			 struct ieee80211_tx_info *info,
1558 			 struct ieee80211_sta *sta,
1559 			 __le16 fc)
1560 {
1561 	const u8 rts_retry_limit = 60;
1562 	u32 rate_flags;
1563 	int rate_idx;
1564 	u8 data_retry_limit;
1565 	u8 rate_plcp;
1566 
1567 	/* Set retry limit on DATA packets and Probe Responses */
1568 	if (ieee80211_is_probe_resp(fc))
1569 		data_retry_limit = 3;
1570 	else
1571 		data_retry_limit = IL4965_DEFAULT_TX_RETRY;
1572 	tx_cmd->data_retry_limit = data_retry_limit;
1573 	/* Set retry limit on RTS packets */
1574 	tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
1575 
1576 	/* DATA packets will use the uCode station table for rate/antenna
1577 	 * selection */
1578 	if (ieee80211_is_data(fc)) {
1579 		tx_cmd->initial_rate_idx = 0;
1580 		tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
1581 		return;
1582 	}
1583 
1584 	/**
1585 	 * If the current TX rate stored in mac80211 has the MCS bit set, it's
1586 	 * not really a TX rate.  Thus, we use the lowest supported rate for
1587 	 * this band.  Also use the lowest supported rate if the stored rate
1588 	 * idx is invalid.
1589 	 */
1590 	rate_idx = info->control.rates[0].idx;
1591 	if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0
1592 	    || rate_idx > RATE_COUNT_LEGACY)
1593 		rate_idx = rate_lowest_index(&il->bands[info->band], sta);
1594 	/* For 5 GHZ band, remap mac80211 rate indices into driver indices */
1595 	if (info->band == NL80211_BAND_5GHZ)
1596 		rate_idx += IL_FIRST_OFDM_RATE;
1597 	/* Get PLCP rate for tx_cmd->rate_n_flags */
1598 	rate_plcp = il_rates[rate_idx].plcp;
1599 	/* Zero out flags for this packet */
1600 	rate_flags = 0;
1601 
1602 	/* Set CCK flag as needed */
1603 	if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE)
1604 		rate_flags |= RATE_MCS_CCK_MSK;
1605 
1606 	/* Set up antennas */
1607 	il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
1608 	rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
1609 
1610 	/* Set the rate in the TX cmd */
1611 	tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags);
1612 }
1613 
1614 static void
1615 il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
1616 			     struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag,
1617 			     int sta_id)
1618 {
1619 	struct ieee80211_key_conf *keyconf = info->control.hw_key;
1620 
1621 	switch (keyconf->cipher) {
1622 	case WLAN_CIPHER_SUITE_CCMP:
1623 		tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
1624 		memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
1625 		if (info->flags & IEEE80211_TX_CTL_AMPDU)
1626 			tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
1627 		D_TX("tx_cmd with AES hwcrypto\n");
1628 		break;
1629 
1630 	case WLAN_CIPHER_SUITE_TKIP:
1631 		tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
1632 		ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
1633 		D_TX("tx_cmd with tkip hwcrypto\n");
1634 		break;
1635 
1636 	case WLAN_CIPHER_SUITE_WEP104:
1637 		tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
1638 		/* fall through */
1639 	case WLAN_CIPHER_SUITE_WEP40:
1640 		tx_cmd->sec_ctl |=
1641 		    (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) <<
1642 		     TX_CMD_SEC_SHIFT);
1643 
1644 		memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
1645 
1646 		D_TX("Configuring packet for WEP encryption " "with key %d\n",
1647 		     keyconf->keyidx);
1648 		break;
1649 
1650 	default:
1651 		IL_ERR("Unknown encode cipher %x\n", keyconf->cipher);
1652 		break;
1653 	}
1654 }
1655 
1656 /*
1657  * start C_TX command process
1658  */
1659 int
1660 il4965_tx_skb(struct il_priv *il,
1661 	      struct ieee80211_sta *sta,
1662 	      struct sk_buff *skb)
1663 {
1664 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1665 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1666 	struct il_station_priv *sta_priv = NULL;
1667 	struct il_tx_queue *txq;
1668 	struct il_queue *q;
1669 	struct il_device_cmd *out_cmd;
1670 	struct il_cmd_meta *out_meta;
1671 	struct il_tx_cmd *tx_cmd;
1672 	int txq_id;
1673 	dma_addr_t phys_addr;
1674 	dma_addr_t txcmd_phys;
1675 	dma_addr_t scratch_phys;
1676 	u16 len, firstlen, secondlen;
1677 	u16 seq_number = 0;
1678 	__le16 fc;
1679 	u8 hdr_len;
1680 	u8 sta_id;
1681 	u8 wait_write_ptr = 0;
1682 	u8 tid = 0;
1683 	u8 *qc = NULL;
1684 	unsigned long flags;
1685 	bool is_agg = false;
1686 
1687 	spin_lock_irqsave(&il->lock, flags);
1688 	if (il_is_rfkill(il)) {
1689 		D_DROP("Dropping - RF KILL\n");
1690 		goto drop_unlock;
1691 	}
1692 
1693 	fc = hdr->frame_control;
1694 
1695 #ifdef CONFIG_IWLEGACY_DEBUG
1696 	if (ieee80211_is_auth(fc))
1697 		D_TX("Sending AUTH frame\n");
1698 	else if (ieee80211_is_assoc_req(fc))
1699 		D_TX("Sending ASSOC frame\n");
1700 	else if (ieee80211_is_reassoc_req(fc))
1701 		D_TX("Sending REASSOC frame\n");
1702 #endif
1703 
1704 	hdr_len = ieee80211_hdrlen(fc);
1705 
1706 	/* For management frames use broadcast id to do not break aggregation */
1707 	if (!ieee80211_is_data(fc))
1708 		sta_id = il->hw_params.bcast_id;
1709 	else {
1710 		/* Find idx into station table for destination station */
1711 		sta_id = il_sta_id_or_broadcast(il, sta);
1712 
1713 		if (sta_id == IL_INVALID_STATION) {
1714 			D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
1715 			goto drop_unlock;
1716 		}
1717 	}
1718 
1719 	D_TX("station Id %d\n", sta_id);
1720 
1721 	if (sta)
1722 		sta_priv = (void *)sta->drv_priv;
1723 
1724 	if (sta_priv && sta_priv->asleep &&
1725 	    (info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER)) {
1726 		/*
1727 		 * This sends an asynchronous command to the device,
1728 		 * but we can rely on it being processed before the
1729 		 * next frame is processed -- and the next frame to
1730 		 * this station is the one that will consume this
1731 		 * counter.
1732 		 * For now set the counter to just 1 since we do not
1733 		 * support uAPSD yet.
1734 		 */
1735 		il4965_sta_modify_sleep_tx_count(il, sta_id, 1);
1736 	}
1737 
1738 	/* FIXME: remove me ? */
1739 	WARN_ON_ONCE(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM);
1740 
1741 	/* Access category (AC) is also the queue number */
1742 	txq_id = skb_get_queue_mapping(skb);
1743 
1744 	/* irqs already disabled/saved above when locking il->lock */
1745 	spin_lock(&il->sta_lock);
1746 
1747 	if (ieee80211_is_data_qos(fc)) {
1748 		qc = ieee80211_get_qos_ctl(hdr);
1749 		tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1750 		if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
1751 			spin_unlock(&il->sta_lock);
1752 			goto drop_unlock;
1753 		}
1754 		seq_number = il->stations[sta_id].tid[tid].seq_number;
1755 		seq_number &= IEEE80211_SCTL_SEQ;
1756 		hdr->seq_ctrl =
1757 		    hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG);
1758 		hdr->seq_ctrl |= cpu_to_le16(seq_number);
1759 		seq_number += 0x10;
1760 		/* aggregation is on for this <sta,tid> */
1761 		if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1762 		    il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) {
1763 			txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
1764 			is_agg = true;
1765 		}
1766 	}
1767 
1768 	txq = &il->txq[txq_id];
1769 	q = &txq->q;
1770 
1771 	if (unlikely(il_queue_space(q) < q->high_mark)) {
1772 		spin_unlock(&il->sta_lock);
1773 		goto drop_unlock;
1774 	}
1775 
1776 	if (ieee80211_is_data_qos(fc)) {
1777 		il->stations[sta_id].tid[tid].tfds_in_queue++;
1778 		if (!ieee80211_has_morefrags(fc))
1779 			il->stations[sta_id].tid[tid].seq_number = seq_number;
1780 	}
1781 
1782 	spin_unlock(&il->sta_lock);
1783 
1784 	txq->skbs[q->write_ptr] = skb;
1785 
1786 	/* Set up first empty entry in queue's array of Tx/cmd buffers */
1787 	out_cmd = txq->cmd[q->write_ptr];
1788 	out_meta = &txq->meta[q->write_ptr];
1789 	tx_cmd = &out_cmd->cmd.tx;
1790 	memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
1791 	memset(tx_cmd, 0, sizeof(struct il_tx_cmd));
1792 
1793 	/*
1794 	 * Set up the Tx-command (not MAC!) header.
1795 	 * Store the chosen Tx queue and TFD idx within the sequence field;
1796 	 * after Tx, uCode's Tx response will return this value so driver can
1797 	 * locate the frame within the tx queue and do post-tx processing.
1798 	 */
1799 	out_cmd->hdr.cmd = C_TX;
1800 	out_cmd->hdr.sequence =
1801 	    cpu_to_le16((u16)
1802 			(QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
1803 
1804 	/* Copy MAC header from skb into command buffer */
1805 	memcpy(tx_cmd->hdr, hdr, hdr_len);
1806 
1807 	/* Total # bytes to be transmitted */
1808 	tx_cmd->len = cpu_to_le16((u16) skb->len);
1809 
1810 	if (info->control.hw_key)
1811 		il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id);
1812 
1813 	/* TODO need this for burst mode later on */
1814 	il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id);
1815 
1816 	il4965_tx_cmd_build_rate(il, tx_cmd, info, sta, fc);
1817 
1818 	/*
1819 	 * Use the first empty entry in this queue's command buffer array
1820 	 * to contain the Tx command and MAC header concatenated together
1821 	 * (payload data will be in another buffer).
1822 	 * Size of this varies, due to varying MAC header length.
1823 	 * If end is not dword aligned, we'll have 2 extra bytes at the end
1824 	 * of the MAC header (device reads on dword boundaries).
1825 	 * We'll tell device about this padding later.
1826 	 */
1827 	len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len;
1828 	firstlen = (len + 3) & ~3;
1829 
1830 	/* Tell NIC about any 2-byte padding after MAC header */
1831 	if (firstlen != len)
1832 		tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1833 
1834 	/* Physical address of this Tx command's header (not MAC header!),
1835 	 * within command buffer array. */
1836 	txcmd_phys =
1837 	    pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
1838 			   PCI_DMA_BIDIRECTIONAL);
1839 	if (unlikely(pci_dma_mapping_error(il->pci_dev, txcmd_phys)))
1840 		goto drop_unlock;
1841 
1842 	/* Set up TFD's 2nd entry to point directly to remainder of skb,
1843 	 * if any (802.11 null frames have no payload). */
1844 	secondlen = skb->len - hdr_len;
1845 	if (secondlen > 0) {
1846 		phys_addr =
1847 		    pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
1848 				   PCI_DMA_TODEVICE);
1849 		if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr)))
1850 			goto drop_unlock;
1851 	}
1852 
1853 	/* Add buffer containing Tx command and MAC(!) header to TFD's
1854 	 * first entry */
1855 	il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
1856 	dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1857 	dma_unmap_len_set(out_meta, len, firstlen);
1858 	if (secondlen)
1859 		il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen,
1860 					       0, 0);
1861 
1862 	if (!ieee80211_has_morefrags(hdr->frame_control)) {
1863 		txq->need_update = 1;
1864 	} else {
1865 		wait_write_ptr = 1;
1866 		txq->need_update = 0;
1867 	}
1868 
1869 	scratch_phys =
1870 	    txcmd_phys + sizeof(struct il_cmd_header) +
1871 	    offsetof(struct il_tx_cmd, scratch);
1872 
1873 	/* take back ownership of DMA buffer to enable update */
1874 	pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys, firstlen,
1875 				    PCI_DMA_BIDIRECTIONAL);
1876 	tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1877 	tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys);
1878 
1879 	il_update_stats(il, true, fc, skb->len);
1880 
1881 	D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
1882 	D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1883 	il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd));
1884 	il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len);
1885 
1886 	/* Set up entry for this TFD in Tx byte-count array */
1887 	if (info->flags & IEEE80211_TX_CTL_AMPDU)
1888 		il->ops->txq_update_byte_cnt_tbl(il, txq, le16_to_cpu(tx_cmd->len));
1889 
1890 	pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys, firstlen,
1891 				       PCI_DMA_BIDIRECTIONAL);
1892 
1893 	/* Tell device the write idx *just past* this latest filled TFD */
1894 	q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
1895 	il_txq_update_write_ptr(il, txq);
1896 	spin_unlock_irqrestore(&il->lock, flags);
1897 
1898 	/*
1899 	 * At this point the frame is "transmitted" successfully
1900 	 * and we will get a TX status notification eventually,
1901 	 * regardless of the value of ret. "ret" only indicates
1902 	 * whether or not we should update the write pointer.
1903 	 */
1904 
1905 	/*
1906 	 * Avoid atomic ops if it isn't an associated client.
1907 	 * Also, if this is a packet for aggregation, don't
1908 	 * increase the counter because the ucode will stop
1909 	 * aggregation queues when their respective station
1910 	 * goes to sleep.
1911 	 */
1912 	if (sta_priv && sta_priv->client && !is_agg)
1913 		atomic_inc(&sta_priv->pending_frames);
1914 
1915 	if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
1916 		if (wait_write_ptr) {
1917 			spin_lock_irqsave(&il->lock, flags);
1918 			txq->need_update = 1;
1919 			il_txq_update_write_ptr(il, txq);
1920 			spin_unlock_irqrestore(&il->lock, flags);
1921 		} else {
1922 			il_stop_queue(il, txq);
1923 		}
1924 	}
1925 
1926 	return 0;
1927 
1928 drop_unlock:
1929 	spin_unlock_irqrestore(&il->lock, flags);
1930 	return -1;
1931 }
1932 
1933 static inline int
1934 il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size)
1935 {
1936 	ptr->addr = dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma,
1937 				       GFP_KERNEL);
1938 	if (!ptr->addr)
1939 		return -ENOMEM;
1940 	ptr->size = size;
1941 	return 0;
1942 }
1943 
1944 static inline void
1945 il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr)
1946 {
1947 	if (unlikely(!ptr->addr))
1948 		return;
1949 
1950 	dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
1951 	memset(ptr, 0, sizeof(*ptr));
1952 }
1953 
1954 /**
1955  * il4965_hw_txq_ctx_free - Free TXQ Context
1956  *
1957  * Destroy all TX DMA queues and structures
1958  */
1959 void
1960 il4965_hw_txq_ctx_free(struct il_priv *il)
1961 {
1962 	int txq_id;
1963 
1964 	/* Tx queues */
1965 	if (il->txq) {
1966 		for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1967 			if (txq_id == il->cmd_queue)
1968 				il_cmd_queue_free(il);
1969 			else
1970 				il_tx_queue_free(il, txq_id);
1971 	}
1972 	il4965_free_dma_ptr(il, &il->kw);
1973 
1974 	il4965_free_dma_ptr(il, &il->scd_bc_tbls);
1975 
1976 	/* free tx queue structure */
1977 	il_free_txq_mem(il);
1978 }
1979 
1980 /**
1981  * il4965_txq_ctx_alloc - allocate TX queue context
1982  * Allocate all Tx DMA structures and initialize them
1983  *
1984  * @param il
1985  * @return error code
1986  */
1987 int
1988 il4965_txq_ctx_alloc(struct il_priv *il)
1989 {
1990 	int ret, txq_id;
1991 	unsigned long flags;
1992 
1993 	/* Free all tx/cmd queues and keep-warm buffer */
1994 	il4965_hw_txq_ctx_free(il);
1995 
1996 	ret =
1997 	    il4965_alloc_dma_ptr(il, &il->scd_bc_tbls,
1998 				 il->hw_params.scd_bc_tbls_size);
1999 	if (ret) {
2000 		IL_ERR("Scheduler BC Table allocation failed\n");
2001 		goto error_bc_tbls;
2002 	}
2003 	/* Alloc keep-warm buffer */
2004 	ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE);
2005 	if (ret) {
2006 		IL_ERR("Keep Warm allocation failed\n");
2007 		goto error_kw;
2008 	}
2009 
2010 	/* allocate tx queue structure */
2011 	ret = il_alloc_txq_mem(il);
2012 	if (ret)
2013 		goto error;
2014 
2015 	spin_lock_irqsave(&il->lock, flags);
2016 
2017 	/* Turn off all Tx DMA fifos */
2018 	il4965_txq_set_sched(il, 0);
2019 
2020 	/* Tell NIC where to find the "keep warm" buffer */
2021 	il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
2022 
2023 	spin_unlock_irqrestore(&il->lock, flags);
2024 
2025 	/* Alloc and init all Tx queues, including the command queue (#4/#9) */
2026 	for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
2027 		ret = il_tx_queue_init(il, txq_id);
2028 		if (ret) {
2029 			IL_ERR("Tx %d queue init failed\n", txq_id);
2030 			goto error;
2031 		}
2032 	}
2033 
2034 	return ret;
2035 
2036 error:
2037 	il4965_hw_txq_ctx_free(il);
2038 	il4965_free_dma_ptr(il, &il->kw);
2039 error_kw:
2040 	il4965_free_dma_ptr(il, &il->scd_bc_tbls);
2041 error_bc_tbls:
2042 	return ret;
2043 }
2044 
2045 void
2046 il4965_txq_ctx_reset(struct il_priv *il)
2047 {
2048 	int txq_id;
2049 	unsigned long flags;
2050 
2051 	spin_lock_irqsave(&il->lock, flags);
2052 
2053 	/* Turn off all Tx DMA fifos */
2054 	il4965_txq_set_sched(il, 0);
2055 	/* Tell NIC where to find the "keep warm" buffer */
2056 	il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
2057 
2058 	spin_unlock_irqrestore(&il->lock, flags);
2059 
2060 	/* Alloc and init all Tx queues, including the command queue (#4) */
2061 	for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2062 		il_tx_queue_reset(il, txq_id);
2063 }
2064 
2065 static void
2066 il4965_txq_ctx_unmap(struct il_priv *il)
2067 {
2068 	int txq_id;
2069 
2070 	if (!il->txq)
2071 		return;
2072 
2073 	/* Unmap DMA from host system and free skb's */
2074 	for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2075 		if (txq_id == il->cmd_queue)
2076 			il_cmd_queue_unmap(il);
2077 		else
2078 			il_tx_queue_unmap(il, txq_id);
2079 }
2080 
2081 /**
2082  * il4965_txq_ctx_stop - Stop all Tx DMA channels
2083  */
2084 void
2085 il4965_txq_ctx_stop(struct il_priv *il)
2086 {
2087 	int ch, ret;
2088 
2089 	_il_wr_prph(il, IL49_SCD_TXFACT, 0);
2090 
2091 	/* Stop each Tx DMA channel, and wait for it to be idle */
2092 	for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
2093 		_il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
2094 		ret =
2095 		    _il_poll_bit(il, FH49_TSSR_TX_STATUS_REG,
2096 				 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2097 				 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2098 				 1000);
2099 		if (ret < 0)
2100 			IL_ERR("Timeout stopping DMA channel %d [0x%08x]",
2101 			       ch, _il_rd(il, FH49_TSSR_TX_STATUS_REG));
2102 	}
2103 }
2104 
2105 /*
2106  * Find first available (lowest unused) Tx Queue, mark it "active".
2107  * Called only when finding queue for aggregation.
2108  * Should never return anything < 7, because they should already
2109  * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
2110  */
2111 static int
2112 il4965_txq_ctx_activate_free(struct il_priv *il)
2113 {
2114 	int txq_id;
2115 
2116 	for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2117 		if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
2118 			return txq_id;
2119 	return -1;
2120 }
2121 
2122 /**
2123  * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2124  */
2125 static void
2126 il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id)
2127 {
2128 	/* Simply stop the queue, but don't change any configuration;
2129 	 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
2130 	il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
2131 		   (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
2132 		   (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
2133 }
2134 
2135 /**
2136  * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
2137  */
2138 static int
2139 il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id)
2140 {
2141 	u32 tbl_dw_addr;
2142 	u32 tbl_dw;
2143 	u16 scd_q2ratid;
2144 
2145 	scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
2146 
2147 	tbl_dw_addr =
2148 	    il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
2149 
2150 	tbl_dw = il_read_targ_mem(il, tbl_dw_addr);
2151 
2152 	if (txq_id & 0x1)
2153 		tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
2154 	else
2155 		tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
2156 
2157 	il_write_targ_mem(il, tbl_dw_addr, tbl_dw);
2158 
2159 	return 0;
2160 }
2161 
2162 /**
2163  * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
2164  *
2165  * NOTE:  txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
2166  *        i.e. it must be one of the higher queues used for aggregation
2167  */
2168 static int
2169 il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id,
2170 		      int tid, u16 ssn_idx)
2171 {
2172 	unsigned long flags;
2173 	u16 ra_tid;
2174 	int ret;
2175 
2176 	if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2177 	    (IL49_FIRST_AMPDU_QUEUE +
2178 	     il->cfg->num_of_ampdu_queues <= txq_id)) {
2179 		IL_WARN("queue number out of range: %d, must be %d to %d\n",
2180 			txq_id, IL49_FIRST_AMPDU_QUEUE,
2181 			IL49_FIRST_AMPDU_QUEUE +
2182 			il->cfg->num_of_ampdu_queues - 1);
2183 		return -EINVAL;
2184 	}
2185 
2186 	ra_tid = BUILD_RAxTID(sta_id, tid);
2187 
2188 	/* Modify device's station table to Tx this TID */
2189 	ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid);
2190 	if (ret)
2191 		return ret;
2192 
2193 	spin_lock_irqsave(&il->lock, flags);
2194 
2195 	/* Stop this Tx queue before configuring it */
2196 	il4965_tx_queue_stop_scheduler(il, txq_id);
2197 
2198 	/* Map receiver-address / traffic-ID to this queue */
2199 	il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
2200 
2201 	/* Set this queue as a chain-building queue */
2202 	il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2203 
2204 	/* Place first TFD at idx corresponding to start sequence number.
2205 	 * Assumes that ssn_idx is valid (!= 0xFFF) */
2206 	il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2207 	il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2208 	il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2209 
2210 	/* Set up Tx win size and frame limit for this queue */
2211 	il_write_targ_mem(il,
2212 			  il->scd_base_addr +
2213 			  IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2214 			  (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS)
2215 			  & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
2216 
2217 	il_write_targ_mem(il,
2218 			  il->scd_base_addr +
2219 			  IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2220 			  (SCD_FRAME_LIMIT <<
2221 			   IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
2222 			  IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
2223 
2224 	il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2225 
2226 	/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
2227 	il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
2228 
2229 	spin_unlock_irqrestore(&il->lock, flags);
2230 
2231 	return 0;
2232 }
2233 
2234 int
2235 il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
2236 		    struct ieee80211_sta *sta, u16 tid, u16 * ssn)
2237 {
2238 	int sta_id;
2239 	int tx_fifo;
2240 	int txq_id;
2241 	int ret;
2242 	unsigned long flags;
2243 	struct il_tid_data *tid_data;
2244 
2245 	/* FIXME: warning if tx fifo not found ? */
2246 	tx_fifo = il4965_get_fifo_from_tid(tid);
2247 	if (unlikely(tx_fifo < 0))
2248 		return tx_fifo;
2249 
2250 	D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid);
2251 
2252 	sta_id = il_sta_id(sta);
2253 	if (sta_id == IL_INVALID_STATION) {
2254 		IL_ERR("Start AGG on invalid station\n");
2255 		return -ENXIO;
2256 	}
2257 	if (unlikely(tid >= MAX_TID_COUNT))
2258 		return -EINVAL;
2259 
2260 	if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) {
2261 		IL_ERR("Start AGG when state is not IL_AGG_OFF !\n");
2262 		return -ENXIO;
2263 	}
2264 
2265 	txq_id = il4965_txq_ctx_activate_free(il);
2266 	if (txq_id == -1) {
2267 		IL_ERR("No free aggregation queue available\n");
2268 		return -ENXIO;
2269 	}
2270 
2271 	spin_lock_irqsave(&il->sta_lock, flags);
2272 	tid_data = &il->stations[sta_id].tid[tid];
2273 	*ssn = IEEE80211_SEQ_TO_SN(tid_data->seq_number);
2274 	tid_data->agg.txq_id = txq_id;
2275 	il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id);
2276 	spin_unlock_irqrestore(&il->sta_lock, flags);
2277 
2278 	ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn);
2279 	if (ret)
2280 		return ret;
2281 
2282 	spin_lock_irqsave(&il->sta_lock, flags);
2283 	tid_data = &il->stations[sta_id].tid[tid];
2284 	if (tid_data->tfds_in_queue == 0) {
2285 		D_HT("HW queue is empty\n");
2286 		tid_data->agg.state = IL_AGG_ON;
2287 		ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2288 	} else {
2289 		D_HT("HW queue is NOT empty: %d packets in HW queue\n",
2290 		     tid_data->tfds_in_queue);
2291 		tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA;
2292 	}
2293 	spin_unlock_irqrestore(&il->sta_lock, flags);
2294 	return ret;
2295 }
2296 
2297 /**
2298  * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
2299  * il->lock must be held by the caller
2300  */
2301 static int
2302 il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo)
2303 {
2304 	if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2305 	    (IL49_FIRST_AMPDU_QUEUE +
2306 	     il->cfg->num_of_ampdu_queues <= txq_id)) {
2307 		IL_WARN("queue number out of range: %d, must be %d to %d\n",
2308 			txq_id, IL49_FIRST_AMPDU_QUEUE,
2309 			IL49_FIRST_AMPDU_QUEUE +
2310 			il->cfg->num_of_ampdu_queues - 1);
2311 		return -EINVAL;
2312 	}
2313 
2314 	il4965_tx_queue_stop_scheduler(il, txq_id);
2315 
2316 	il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2317 
2318 	il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2319 	il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2320 	/* supposes that ssn_idx is valid (!= 0xFFF) */
2321 	il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2322 
2323 	il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2324 	il_txq_ctx_deactivate(il, txq_id);
2325 	il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
2326 
2327 	return 0;
2328 }
2329 
2330 int
2331 il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
2332 		   struct ieee80211_sta *sta, u16 tid)
2333 {
2334 	int tx_fifo_id, txq_id, sta_id, ssn;
2335 	struct il_tid_data *tid_data;
2336 	int write_ptr, read_ptr;
2337 	unsigned long flags;
2338 
2339 	/* FIXME: warning if tx_fifo_id not found ? */
2340 	tx_fifo_id = il4965_get_fifo_from_tid(tid);
2341 	if (unlikely(tx_fifo_id < 0))
2342 		return tx_fifo_id;
2343 
2344 	sta_id = il_sta_id(sta);
2345 
2346 	if (sta_id == IL_INVALID_STATION) {
2347 		IL_ERR("Invalid station for AGG tid %d\n", tid);
2348 		return -ENXIO;
2349 	}
2350 
2351 	spin_lock_irqsave(&il->sta_lock, flags);
2352 
2353 	tid_data = &il->stations[sta_id].tid[tid];
2354 	ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
2355 	txq_id = tid_data->agg.txq_id;
2356 
2357 	switch (il->stations[sta_id].tid[tid].agg.state) {
2358 	case IL_EMPTYING_HW_QUEUE_ADDBA:
2359 		/*
2360 		 * This can happen if the peer stops aggregation
2361 		 * again before we've had a chance to drain the
2362 		 * queue we selected previously, i.e. before the
2363 		 * session was really started completely.
2364 		 */
2365 		D_HT("AGG stop before setup done\n");
2366 		goto turn_off;
2367 	case IL_AGG_ON:
2368 		break;
2369 	default:
2370 		IL_WARN("Stopping AGG while state not ON or starting\n");
2371 	}
2372 
2373 	write_ptr = il->txq[txq_id].q.write_ptr;
2374 	read_ptr = il->txq[txq_id].q.read_ptr;
2375 
2376 	/* The queue is not empty */
2377 	if (write_ptr != read_ptr) {
2378 		D_HT("Stopping a non empty AGG HW QUEUE\n");
2379 		il->stations[sta_id].tid[tid].agg.state =
2380 		    IL_EMPTYING_HW_QUEUE_DELBA;
2381 		spin_unlock_irqrestore(&il->sta_lock, flags);
2382 		return 0;
2383 	}
2384 
2385 	D_HT("HW queue is empty\n");
2386 turn_off:
2387 	il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF;
2388 
2389 	/* do not restore/save irqs */
2390 	spin_unlock(&il->sta_lock);
2391 	spin_lock(&il->lock);
2392 
2393 	/*
2394 	 * the only reason this call can fail is queue number out of range,
2395 	 * which can happen if uCode is reloaded and all the station
2396 	 * information are lost. if it is outside the range, there is no need
2397 	 * to deactivate the uCode queue, just return "success" to allow
2398 	 *  mac80211 to clean up it own data.
2399 	 */
2400 	il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
2401 	spin_unlock_irqrestore(&il->lock, flags);
2402 
2403 	ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2404 
2405 	return 0;
2406 }
2407 
2408 int
2409 il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id)
2410 {
2411 	struct il_queue *q = &il->txq[txq_id].q;
2412 	u8 *addr = il->stations[sta_id].sta.sta.addr;
2413 	struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid];
2414 
2415 	lockdep_assert_held(&il->sta_lock);
2416 
2417 	switch (il->stations[sta_id].tid[tid].agg.state) {
2418 	case IL_EMPTYING_HW_QUEUE_DELBA:
2419 		/* We are reclaiming the last packet of the */
2420 		/* aggregated HW queue */
2421 		if (txq_id == tid_data->agg.txq_id &&
2422 		    q->read_ptr == q->write_ptr) {
2423 			u16 ssn = IEEE80211_SEQ_TO_SN(tid_data->seq_number);
2424 			int tx_fifo = il4965_get_fifo_from_tid(tid);
2425 			D_HT("HW queue empty: continue DELBA flow\n");
2426 			il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
2427 			tid_data->agg.state = IL_AGG_OFF;
2428 			ieee80211_stop_tx_ba_cb_irqsafe(il->vif, addr, tid);
2429 		}
2430 		break;
2431 	case IL_EMPTYING_HW_QUEUE_ADDBA:
2432 		/* We are reclaiming the last packet of the queue */
2433 		if (tid_data->tfds_in_queue == 0) {
2434 			D_HT("HW queue empty: continue ADDBA flow\n");
2435 			tid_data->agg.state = IL_AGG_ON;
2436 			ieee80211_start_tx_ba_cb_irqsafe(il->vif, addr, tid);
2437 		}
2438 		break;
2439 	}
2440 
2441 	return 0;
2442 }
2443 
2444 static void
2445 il4965_non_agg_tx_status(struct il_priv *il, const u8 *addr1)
2446 {
2447 	struct ieee80211_sta *sta;
2448 	struct il_station_priv *sta_priv;
2449 
2450 	rcu_read_lock();
2451 	sta = ieee80211_find_sta(il->vif, addr1);
2452 	if (sta) {
2453 		sta_priv = (void *)sta->drv_priv;
2454 		/* avoid atomic ops if this isn't a client */
2455 		if (sta_priv->client &&
2456 		    atomic_dec_return(&sta_priv->pending_frames) == 0)
2457 			ieee80211_sta_block_awake(il->hw, sta, false);
2458 	}
2459 	rcu_read_unlock();
2460 }
2461 
2462 static void
2463 il4965_tx_status(struct il_priv *il, struct sk_buff *skb, bool is_agg)
2464 {
2465 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2466 
2467 	if (!is_agg)
2468 		il4965_non_agg_tx_status(il, hdr->addr1);
2469 
2470 	ieee80211_tx_status_irqsafe(il->hw, skb);
2471 }
2472 
2473 int
2474 il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
2475 {
2476 	struct il_tx_queue *txq = &il->txq[txq_id];
2477 	struct il_queue *q = &txq->q;
2478 	int nfreed = 0;
2479 	struct ieee80211_hdr *hdr;
2480 	struct sk_buff *skb;
2481 
2482 	if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
2483 		IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
2484 		       "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
2485 		       q->write_ptr, q->read_ptr);
2486 		return 0;
2487 	}
2488 
2489 	for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
2490 	     q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
2491 
2492 		skb = txq->skbs[txq->q.read_ptr];
2493 
2494 		if (WARN_ON_ONCE(skb == NULL))
2495 			continue;
2496 
2497 		hdr = (struct ieee80211_hdr *) skb->data;
2498 		if (ieee80211_is_data_qos(hdr->frame_control))
2499 			nfreed++;
2500 
2501 		il4965_tx_status(il, skb, txq_id >= IL4965_FIRST_AMPDU_QUEUE);
2502 
2503 		txq->skbs[txq->q.read_ptr] = NULL;
2504 		il->ops->txq_free_tfd(il, txq);
2505 	}
2506 	return nfreed;
2507 }
2508 
2509 /**
2510  * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2511  *
2512  * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2513  * ACK vs. not.  This gets sent to mac80211, then to rate scaling algo.
2514  */
2515 static int
2516 il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg,
2517 				     struct il_compressed_ba_resp *ba_resp)
2518 {
2519 	int i, sh, ack;
2520 	u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2521 	u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2522 	int successes = 0;
2523 	struct ieee80211_tx_info *info;
2524 	u64 bitmap, sent_bitmap;
2525 
2526 	if (unlikely(!agg->wait_for_ba)) {
2527 		if (unlikely(ba_resp->bitmap))
2528 			IL_ERR("Received BA when not expected\n");
2529 		return -EINVAL;
2530 	}
2531 
2532 	/* Mark that the expected block-ack response arrived */
2533 	agg->wait_for_ba = 0;
2534 	D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
2535 
2536 	/* Calculate shift to align block-ack bits with our Tx win bits */
2537 	sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4);
2538 	if (sh < 0)		/* tbw something is wrong with indices */
2539 		sh += 0x100;
2540 
2541 	if (agg->frame_count > (64 - sh)) {
2542 		D_TX_REPLY("more frames than bitmap size");
2543 		return -1;
2544 	}
2545 
2546 	/* don't use 64-bit values for now */
2547 	bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
2548 
2549 	/* check for success or failure according to the
2550 	 * transmitted bitmap and block-ack bitmap */
2551 	sent_bitmap = bitmap & agg->bitmap;
2552 
2553 	/* For each frame attempted in aggregation,
2554 	 * update driver's record of tx frame's status. */
2555 	i = 0;
2556 	while (sent_bitmap) {
2557 		ack = sent_bitmap & 1ULL;
2558 		successes += ack;
2559 		D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK",
2560 			   i, (agg->start_idx + i) & 0xff, agg->start_idx + i);
2561 		sent_bitmap >>= 1;
2562 		++i;
2563 	}
2564 
2565 	D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
2566 
2567 	info = IEEE80211_SKB_CB(il->txq[scd_flow].skbs[agg->start_idx]);
2568 	memset(&info->status, 0, sizeof(info->status));
2569 	info->flags |= IEEE80211_TX_STAT_ACK;
2570 	info->flags |= IEEE80211_TX_STAT_AMPDU;
2571 	info->status.ampdu_ack_len = successes;
2572 	info->status.ampdu_len = agg->frame_count;
2573 	il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info);
2574 
2575 	return 0;
2576 }
2577 
2578 static inline bool
2579 il4965_is_tx_success(u32 status)
2580 {
2581 	status &= TX_STATUS_MSK;
2582 	return (status == TX_STATUS_SUCCESS || status == TX_STATUS_DIRECT_DONE);
2583 }
2584 
2585 static u8
2586 il4965_find_station(struct il_priv *il, const u8 *addr)
2587 {
2588 	int i;
2589 	int start = 0;
2590 	int ret = IL_INVALID_STATION;
2591 	unsigned long flags;
2592 
2593 	if (il->iw_mode == NL80211_IFTYPE_ADHOC)
2594 		start = IL_STA_ID;
2595 
2596 	if (is_broadcast_ether_addr(addr))
2597 		return il->hw_params.bcast_id;
2598 
2599 	spin_lock_irqsave(&il->sta_lock, flags);
2600 	for (i = start; i < il->hw_params.max_stations; i++)
2601 		if (il->stations[i].used &&
2602 		    ether_addr_equal(il->stations[i].sta.sta.addr, addr)) {
2603 			ret = i;
2604 			goto out;
2605 		}
2606 
2607 	D_ASSOC("can not find STA %pM total %d\n", addr, il->num_stations);
2608 
2609 out:
2610 	/*
2611 	 * It may be possible that more commands interacting with stations
2612 	 * arrive before we completed processing the adding of
2613 	 * station
2614 	 */
2615 	if (ret != IL_INVALID_STATION &&
2616 	    (!(il->stations[ret].used & IL_STA_UCODE_ACTIVE) ||
2617 	     ((il->stations[ret].used & IL_STA_UCODE_ACTIVE) &&
2618 	      (il->stations[ret].used & IL_STA_UCODE_INPROGRESS)))) {
2619 		IL_ERR("Requested station info for sta %d before ready.\n",
2620 		       ret);
2621 		ret = IL_INVALID_STATION;
2622 	}
2623 	spin_unlock_irqrestore(&il->sta_lock, flags);
2624 	return ret;
2625 }
2626 
2627 static int
2628 il4965_get_ra_sta_id(struct il_priv *il, struct ieee80211_hdr *hdr)
2629 {
2630 	if (il->iw_mode == NL80211_IFTYPE_STATION)
2631 		return IL_AP_ID;
2632 	else {
2633 		u8 *da = ieee80211_get_DA(hdr);
2634 
2635 		return il4965_find_station(il, da);
2636 	}
2637 }
2638 
2639 static inline u32
2640 il4965_get_scd_ssn(struct il4965_tx_resp *tx_resp)
2641 {
2642 	return le32_to_cpup(&tx_resp->u.status +
2643 			    tx_resp->frame_count) & IEEE80211_MAX_SN;
2644 }
2645 
2646 static inline u32
2647 il4965_tx_status_to_mac80211(u32 status)
2648 {
2649 	status &= TX_STATUS_MSK;
2650 
2651 	switch (status) {
2652 	case TX_STATUS_SUCCESS:
2653 	case TX_STATUS_DIRECT_DONE:
2654 		return IEEE80211_TX_STAT_ACK;
2655 	case TX_STATUS_FAIL_DEST_PS:
2656 		return IEEE80211_TX_STAT_TX_FILTERED;
2657 	default:
2658 		return 0;
2659 	}
2660 }
2661 
2662 /**
2663  * il4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
2664  */
2665 static int
2666 il4965_tx_status_reply_tx(struct il_priv *il, struct il_ht_agg *agg,
2667 			  struct il4965_tx_resp *tx_resp, int txq_id,
2668 			  u16 start_idx)
2669 {
2670 	u16 status;
2671 	struct agg_tx_status *frame_status = tx_resp->u.agg_status;
2672 	struct ieee80211_tx_info *info = NULL;
2673 	struct ieee80211_hdr *hdr = NULL;
2674 	u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
2675 	int i, sh, idx;
2676 	u16 seq;
2677 	if (agg->wait_for_ba)
2678 		D_TX_REPLY("got tx response w/o block-ack\n");
2679 
2680 	agg->frame_count = tx_resp->frame_count;
2681 	agg->start_idx = start_idx;
2682 	agg->rate_n_flags = rate_n_flags;
2683 	agg->bitmap = 0;
2684 
2685 	/* num frames attempted by Tx command */
2686 	if (agg->frame_count == 1) {
2687 		/* Only one frame was attempted; no block-ack will arrive */
2688 		status = le16_to_cpu(frame_status[0].status);
2689 		idx = start_idx;
2690 
2691 		D_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
2692 			   agg->frame_count, agg->start_idx, idx);
2693 
2694 		info = IEEE80211_SKB_CB(il->txq[txq_id].skbs[idx]);
2695 		info->status.rates[0].count = tx_resp->failure_frame + 1;
2696 		info->flags &= ~IEEE80211_TX_CTL_AMPDU;
2697 		info->flags |= il4965_tx_status_to_mac80211(status);
2698 		il4965_hwrate_to_tx_control(il, rate_n_flags, info);
2699 
2700 		D_TX_REPLY("1 Frame 0x%x failure :%d\n", status & 0xff,
2701 			   tx_resp->failure_frame);
2702 		D_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
2703 
2704 		agg->wait_for_ba = 0;
2705 	} else {
2706 		/* Two or more frames were attempted; expect block-ack */
2707 		u64 bitmap = 0;
2708 		int start = agg->start_idx;
2709 		struct sk_buff *skb;
2710 
2711 		/* Construct bit-map of pending frames within Tx win */
2712 		for (i = 0; i < agg->frame_count; i++) {
2713 			u16 sc;
2714 			status = le16_to_cpu(frame_status[i].status);
2715 			seq = le16_to_cpu(frame_status[i].sequence);
2716 			idx = SEQ_TO_IDX(seq);
2717 			txq_id = SEQ_TO_QUEUE(seq);
2718 
2719 			if (status &
2720 			    (AGG_TX_STATE_FEW_BYTES_MSK |
2721 			     AGG_TX_STATE_ABORT_MSK))
2722 				continue;
2723 
2724 			D_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2725 				   agg->frame_count, txq_id, idx);
2726 
2727 			skb = il->txq[txq_id].skbs[idx];
2728 			if (WARN_ON_ONCE(skb == NULL))
2729 				return -1;
2730 			hdr = (struct ieee80211_hdr *) skb->data;
2731 
2732 			sc = le16_to_cpu(hdr->seq_ctrl);
2733 			if (idx != (IEEE80211_SEQ_TO_SN(sc) & 0xff)) {
2734 				IL_ERR("BUG_ON idx doesn't match seq control"
2735 				       " idx=%d, seq_idx=%d, seq=%d\n", idx,
2736 				       IEEE80211_SEQ_TO_SN(sc), hdr->seq_ctrl);
2737 				return -1;
2738 			}
2739 
2740 			D_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", i, idx,
2741 				   IEEE80211_SEQ_TO_SN(sc));
2742 
2743 			sh = idx - start;
2744 			if (sh > 64) {
2745 				sh = (start - idx) + 0xff;
2746 				bitmap = bitmap << sh;
2747 				sh = 0;
2748 				start = idx;
2749 			} else if (sh < -64)
2750 				sh = 0xff - (start - idx);
2751 			else if (sh < 0) {
2752 				sh = start - idx;
2753 				start = idx;
2754 				bitmap = bitmap << sh;
2755 				sh = 0;
2756 			}
2757 			bitmap |= 1ULL << sh;
2758 			D_TX_REPLY("start=%d bitmap=0x%llx\n", start,
2759 				   (unsigned long long)bitmap);
2760 		}
2761 
2762 		agg->bitmap = bitmap;
2763 		agg->start_idx = start;
2764 		D_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
2765 			   agg->frame_count, agg->start_idx,
2766 			   (unsigned long long)agg->bitmap);
2767 
2768 		if (bitmap)
2769 			agg->wait_for_ba = 1;
2770 	}
2771 	return 0;
2772 }
2773 
2774 /**
2775  * il4965_hdl_tx - Handle standard (non-aggregation) Tx response
2776  */
2777 static void
2778 il4965_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
2779 {
2780 	struct il_rx_pkt *pkt = rxb_addr(rxb);
2781 	u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2782 	int txq_id = SEQ_TO_QUEUE(sequence);
2783 	int idx = SEQ_TO_IDX(sequence);
2784 	struct il_tx_queue *txq = &il->txq[txq_id];
2785 	struct sk_buff *skb;
2786 	struct ieee80211_hdr *hdr;
2787 	struct ieee80211_tx_info *info;
2788 	struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2789 	u32 status = le32_to_cpu(tx_resp->u.status);
2790 	int uninitialized_var(tid);
2791 	int sta_id;
2792 	int freed;
2793 	u8 *qc = NULL;
2794 	unsigned long flags;
2795 
2796 	if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
2797 		IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
2798 		       "is out of range [0-%d] %d %d\n", txq_id, idx,
2799 		       txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr);
2800 		return;
2801 	}
2802 
2803 	txq->time_stamp = jiffies;
2804 
2805 	skb = txq->skbs[txq->q.read_ptr];
2806 	info = IEEE80211_SKB_CB(skb);
2807 	memset(&info->status, 0, sizeof(info->status));
2808 
2809 	hdr = (struct ieee80211_hdr *) skb->data;
2810 	if (ieee80211_is_data_qos(hdr->frame_control)) {
2811 		qc = ieee80211_get_qos_ctl(hdr);
2812 		tid = qc[0] & 0xf;
2813 	}
2814 
2815 	sta_id = il4965_get_ra_sta_id(il, hdr);
2816 	if (txq->sched_retry && unlikely(sta_id == IL_INVALID_STATION)) {
2817 		IL_ERR("Station not known\n");
2818 		return;
2819 	}
2820 
2821 	/*
2822 	 * Firmware will not transmit frame on passive channel, if it not yet
2823 	 * received some valid frame on that channel. When this error happen
2824 	 * we have to wait until firmware will unblock itself i.e. when we
2825 	 * note received beacon or other frame. We unblock queues in
2826 	 * il4965_pass_packet_to_mac80211 or in il_mac_bss_info_changed.
2827 	 */
2828 	if (unlikely((status & TX_STATUS_MSK) == TX_STATUS_FAIL_PASSIVE_NO_RX) &&
2829 	    il->iw_mode == NL80211_IFTYPE_STATION) {
2830 		il_stop_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
2831 		D_INFO("Stopped queues - RX waiting on passive channel\n");
2832 	}
2833 
2834 	spin_lock_irqsave(&il->sta_lock, flags);
2835 	if (txq->sched_retry) {
2836 		const u32 scd_ssn = il4965_get_scd_ssn(tx_resp);
2837 		struct il_ht_agg *agg = NULL;
2838 		WARN_ON(!qc);
2839 
2840 		agg = &il->stations[sta_id].tid[tid].agg;
2841 
2842 		il4965_tx_status_reply_tx(il, agg, tx_resp, txq_id, idx);
2843 
2844 		/* check if BAR is needed */
2845 		if (tx_resp->frame_count == 1 &&
2846 		    !il4965_is_tx_success(status))
2847 			info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2848 
2849 		if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2850 			idx = il_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2851 			D_TX_REPLY("Retry scheduler reclaim scd_ssn "
2852 				   "%d idx %d\n", scd_ssn, idx);
2853 			freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2854 			if (qc)
2855 				il4965_free_tfds_in_queue(il, sta_id, tid,
2856 							  freed);
2857 
2858 			if (il->mac80211_registered &&
2859 			    il_queue_space(&txq->q) > txq->q.low_mark &&
2860 			    agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2861 				il_wake_queue(il, txq);
2862 		}
2863 	} else {
2864 		info->status.rates[0].count = tx_resp->failure_frame + 1;
2865 		info->flags |= il4965_tx_status_to_mac80211(status);
2866 		il4965_hwrate_to_tx_control(il,
2867 					    le32_to_cpu(tx_resp->rate_n_flags),
2868 					    info);
2869 
2870 		D_TX_REPLY("TXQ %d status %s (0x%08x) "
2871 			   "rate_n_flags 0x%x retries %d\n", txq_id,
2872 			   il4965_get_tx_fail_reason(status), status,
2873 			   le32_to_cpu(tx_resp->rate_n_flags),
2874 			   tx_resp->failure_frame);
2875 
2876 		freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2877 		if (qc && likely(sta_id != IL_INVALID_STATION))
2878 			il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2879 		else if (sta_id == IL_INVALID_STATION)
2880 			D_TX_REPLY("Station not known\n");
2881 
2882 		if (il->mac80211_registered &&
2883 		    il_queue_space(&txq->q) > txq->q.low_mark)
2884 			il_wake_queue(il, txq);
2885 	}
2886 	if (qc && likely(sta_id != IL_INVALID_STATION))
2887 		il4965_txq_check_empty(il, sta_id, tid, txq_id);
2888 
2889 	il4965_check_abort_status(il, tx_resp->frame_count, status);
2890 
2891 	spin_unlock_irqrestore(&il->sta_lock, flags);
2892 }
2893 
2894 /**
2895  * translate ucode response to mac80211 tx status control values
2896  */
2897 void
2898 il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
2899 			    struct ieee80211_tx_info *info)
2900 {
2901 	struct ieee80211_tx_rate *r = &info->status.rates[0];
2902 
2903 	info->status.antenna =
2904 	    ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
2905 	if (rate_n_flags & RATE_MCS_HT_MSK)
2906 		r->flags |= IEEE80211_TX_RC_MCS;
2907 	if (rate_n_flags & RATE_MCS_GF_MSK)
2908 		r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
2909 	if (rate_n_flags & RATE_MCS_HT40_MSK)
2910 		r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
2911 	if (rate_n_flags & RATE_MCS_DUP_MSK)
2912 		r->flags |= IEEE80211_TX_RC_DUP_DATA;
2913 	if (rate_n_flags & RATE_MCS_SGI_MSK)
2914 		r->flags |= IEEE80211_TX_RC_SHORT_GI;
2915 	r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band);
2916 }
2917 
2918 /**
2919  * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA
2920  *
2921  * Handles block-acknowledge notification from device, which reports success
2922  * of frames sent via aggregation.
2923  */
2924 static void
2925 il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb)
2926 {
2927 	struct il_rx_pkt *pkt = rxb_addr(rxb);
2928 	struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
2929 	struct il_tx_queue *txq = NULL;
2930 	struct il_ht_agg *agg;
2931 	int idx;
2932 	int sta_id;
2933 	int tid;
2934 	unsigned long flags;
2935 
2936 	/* "flow" corresponds to Tx queue */
2937 	u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2938 
2939 	/* "ssn" is start of block-ack Tx win, corresponds to idx
2940 	 * (in Tx queue's circular buffer) of first TFD/frame in win */
2941 	u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
2942 
2943 	if (scd_flow >= il->hw_params.max_txq_num) {
2944 		IL_ERR("BUG_ON scd_flow is bigger than number of queues\n");
2945 		return;
2946 	}
2947 
2948 	txq = &il->txq[scd_flow];
2949 	sta_id = ba_resp->sta_id;
2950 	tid = ba_resp->tid;
2951 	agg = &il->stations[sta_id].tid[tid].agg;
2952 	if (unlikely(agg->txq_id != scd_flow)) {
2953 		/*
2954 		 * FIXME: this is a uCode bug which need to be addressed,
2955 		 * log the information and return for now!
2956 		 * since it is possible happen very often and in order
2957 		 * not to fill the syslog, don't enable the logging by default
2958 		 */
2959 		D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n",
2960 			   scd_flow, agg->txq_id);
2961 		return;
2962 	}
2963 
2964 	/* Find idx just before block-ack win */
2965 	idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
2966 
2967 	spin_lock_irqsave(&il->sta_lock, flags);
2968 
2969 	D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n",
2970 		   agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32,
2971 		   ba_resp->sta_id);
2972 	D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = "
2973 		   "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl,
2974 		   (unsigned long long)le64_to_cpu(ba_resp->bitmap),
2975 		   ba_resp->scd_flow, ba_resp->scd_ssn);
2976 	D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx,
2977 		   (unsigned long long)agg->bitmap);
2978 
2979 	/* Update driver's record of ACK vs. not for each frame in win */
2980 	il4965_tx_status_reply_compressed_ba(il, agg, ba_resp);
2981 
2982 	/* Release all TFDs before the SSN, i.e. all TFDs in front of
2983 	 * block-ack win (we assume that they've been successfully
2984 	 * transmitted ... if not, it's too late anyway). */
2985 	if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
2986 		/* calculate mac80211 ampdu sw queue to wake */
2987 		int freed = il4965_tx_queue_reclaim(il, scd_flow, idx);
2988 		il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2989 
2990 		if (il_queue_space(&txq->q) > txq->q.low_mark &&
2991 		    il->mac80211_registered &&
2992 		    agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2993 			il_wake_queue(il, txq);
2994 
2995 		il4965_txq_check_empty(il, sta_id, tid, scd_flow);
2996 	}
2997 
2998 	spin_unlock_irqrestore(&il->sta_lock, flags);
2999 }
3000 
3001 #ifdef CONFIG_IWLEGACY_DEBUG
3002 const char *
3003 il4965_get_tx_fail_reason(u32 status)
3004 {
3005 #define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
3006 #define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
3007 
3008 	switch (status & TX_STATUS_MSK) {
3009 	case TX_STATUS_SUCCESS:
3010 		return "SUCCESS";
3011 		TX_STATUS_POSTPONE(DELAY);
3012 		TX_STATUS_POSTPONE(FEW_BYTES);
3013 		TX_STATUS_POSTPONE(QUIET_PERIOD);
3014 		TX_STATUS_POSTPONE(CALC_TTAK);
3015 		TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
3016 		TX_STATUS_FAIL(SHORT_LIMIT);
3017 		TX_STATUS_FAIL(LONG_LIMIT);
3018 		TX_STATUS_FAIL(FIFO_UNDERRUN);
3019 		TX_STATUS_FAIL(DRAIN_FLOW);
3020 		TX_STATUS_FAIL(RFKILL_FLUSH);
3021 		TX_STATUS_FAIL(LIFE_EXPIRE);
3022 		TX_STATUS_FAIL(DEST_PS);
3023 		TX_STATUS_FAIL(HOST_ABORTED);
3024 		TX_STATUS_FAIL(BT_RETRY);
3025 		TX_STATUS_FAIL(STA_INVALID);
3026 		TX_STATUS_FAIL(FRAG_DROPPED);
3027 		TX_STATUS_FAIL(TID_DISABLE);
3028 		TX_STATUS_FAIL(FIFO_FLUSHED);
3029 		TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
3030 		TX_STATUS_FAIL(PASSIVE_NO_RX);
3031 		TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
3032 	}
3033 
3034 	return "UNKNOWN";
3035 
3036 #undef TX_STATUS_FAIL
3037 #undef TX_STATUS_POSTPONE
3038 }
3039 #endif /* CONFIG_IWLEGACY_DEBUG */
3040 
3041 static struct il_link_quality_cmd *
3042 il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id)
3043 {
3044 	int i, r;
3045 	struct il_link_quality_cmd *link_cmd;
3046 	u32 rate_flags = 0;
3047 	__le32 rate_n_flags;
3048 
3049 	link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL);
3050 	if (!link_cmd) {
3051 		IL_ERR("Unable to allocate memory for LQ cmd.\n");
3052 		return NULL;
3053 	}
3054 	/* Set up the rate scaling to start at selected rate, fall back
3055 	 * all the way down to 1M in IEEE order, and then spin on 1M */
3056 	if (il->band == NL80211_BAND_5GHZ)
3057 		r = RATE_6M_IDX;
3058 	else
3059 		r = RATE_1M_IDX;
3060 
3061 	if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE)
3062 		rate_flags |= RATE_MCS_CCK_MSK;
3063 
3064 	rate_flags |=
3065 	    il4965_first_antenna(il->hw_params.
3066 				 valid_tx_ant) << RATE_MCS_ANT_POS;
3067 	rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags);
3068 	for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
3069 		link_cmd->rs_table[i].rate_n_flags = rate_n_flags;
3070 
3071 	link_cmd->general_params.single_stream_ant_msk =
3072 	    il4965_first_antenna(il->hw_params.valid_tx_ant);
3073 
3074 	link_cmd->general_params.dual_stream_ant_msk =
3075 	    il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params.
3076 							       valid_tx_ant);
3077 	if (!link_cmd->general_params.dual_stream_ant_msk) {
3078 		link_cmd->general_params.dual_stream_ant_msk = ANT_AB;
3079 	} else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) {
3080 		link_cmd->general_params.dual_stream_ant_msk =
3081 		    il->hw_params.valid_tx_ant;
3082 	}
3083 
3084 	link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF;
3085 	link_cmd->agg_params.agg_time_limit =
3086 	    cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF);
3087 
3088 	link_cmd->sta_id = sta_id;
3089 
3090 	return link_cmd;
3091 }
3092 
3093 /*
3094  * il4965_add_bssid_station - Add the special IBSS BSSID station
3095  *
3096  * Function sleeps.
3097  */
3098 int
3099 il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r)
3100 {
3101 	int ret;
3102 	u8 sta_id;
3103 	struct il_link_quality_cmd *link_cmd;
3104 	unsigned long flags;
3105 
3106 	if (sta_id_r)
3107 		*sta_id_r = IL_INVALID_STATION;
3108 
3109 	ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
3110 	if (ret) {
3111 		IL_ERR("Unable to add station %pM\n", addr);
3112 		return ret;
3113 	}
3114 
3115 	if (sta_id_r)
3116 		*sta_id_r = sta_id;
3117 
3118 	spin_lock_irqsave(&il->sta_lock, flags);
3119 	il->stations[sta_id].used |= IL_STA_LOCAL;
3120 	spin_unlock_irqrestore(&il->sta_lock, flags);
3121 
3122 	/* Set up default rate scaling table in device's station table */
3123 	link_cmd = il4965_sta_alloc_lq(il, sta_id);
3124 	if (!link_cmd) {
3125 		IL_ERR("Unable to initialize rate scaling for station %pM.\n",
3126 		       addr);
3127 		return -ENOMEM;
3128 	}
3129 
3130 	ret = il_send_lq_cmd(il, link_cmd, CMD_SYNC, true);
3131 	if (ret)
3132 		IL_ERR("Link quality command failed (%d)\n", ret);
3133 
3134 	spin_lock_irqsave(&il->sta_lock, flags);
3135 	il->stations[sta_id].lq = link_cmd;
3136 	spin_unlock_irqrestore(&il->sta_lock, flags);
3137 
3138 	return 0;
3139 }
3140 
3141 static int
3142 il4965_static_wepkey_cmd(struct il_priv *il, bool send_if_empty)
3143 {
3144 	int i;
3145 	u8 buff[sizeof(struct il_wep_cmd) +
3146 		sizeof(struct il_wep_key) * WEP_KEYS_MAX];
3147 	struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff;
3148 	size_t cmd_size = sizeof(struct il_wep_cmd);
3149 	struct il_host_cmd cmd = {
3150 		.id = C_WEPKEY,
3151 		.data = wep_cmd,
3152 		.flags = CMD_SYNC,
3153 	};
3154 	bool not_empty = false;
3155 
3156 	might_sleep();
3157 
3158 	memset(wep_cmd, 0,
3159 	       cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX));
3160 
3161 	for (i = 0; i < WEP_KEYS_MAX; i++) {
3162 		u8 key_size = il->_4965.wep_keys[i].key_size;
3163 
3164 		wep_cmd->key[i].key_idx = i;
3165 		if (key_size) {
3166 			wep_cmd->key[i].key_offset = i;
3167 			not_empty = true;
3168 		} else
3169 			wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET;
3170 
3171 		wep_cmd->key[i].key_size = key_size;
3172 		memcpy(&wep_cmd->key[i].key[3], il->_4965.wep_keys[i].key, key_size);
3173 	}
3174 
3175 	wep_cmd->global_key_type = WEP_KEY_WEP_TYPE;
3176 	wep_cmd->num_keys = WEP_KEYS_MAX;
3177 
3178 	cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX;
3179 	cmd.len = cmd_size;
3180 
3181 	if (not_empty || send_if_empty)
3182 		return il_send_cmd(il, &cmd);
3183 	else
3184 		return 0;
3185 }
3186 
3187 int
3188 il4965_restore_default_wep_keys(struct il_priv *il)
3189 {
3190 	lockdep_assert_held(&il->mutex);
3191 
3192 	return il4965_static_wepkey_cmd(il, false);
3193 }
3194 
3195 int
3196 il4965_remove_default_wep_key(struct il_priv *il,
3197 			      struct ieee80211_key_conf *keyconf)
3198 {
3199 	int ret;
3200 	int idx = keyconf->keyidx;
3201 
3202 	lockdep_assert_held(&il->mutex);
3203 
3204 	D_WEP("Removing default WEP key: idx=%d\n", idx);
3205 
3206 	memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key));
3207 	if (il_is_rfkill(il)) {
3208 		D_WEP("Not sending C_WEPKEY command due to RFKILL.\n");
3209 		/* but keys in device are clear anyway so return success */
3210 		return 0;
3211 	}
3212 	ret = il4965_static_wepkey_cmd(il, 1);
3213 	D_WEP("Remove default WEP key: idx=%d ret=%d\n", idx, ret);
3214 
3215 	return ret;
3216 }
3217 
3218 int
3219 il4965_set_default_wep_key(struct il_priv *il,
3220 			   struct ieee80211_key_conf *keyconf)
3221 {
3222 	int ret;
3223 	int len = keyconf->keylen;
3224 	int idx = keyconf->keyidx;
3225 
3226 	lockdep_assert_held(&il->mutex);
3227 
3228 	if (len != WEP_KEY_LEN_128 && len != WEP_KEY_LEN_64) {
3229 		D_WEP("Bad WEP key length %d\n", keyconf->keylen);
3230 		return -EINVAL;
3231 	}
3232 
3233 	keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3234 	keyconf->hw_key_idx = HW_KEY_DEFAULT;
3235 	il->stations[IL_AP_ID].keyinfo.cipher = keyconf->cipher;
3236 
3237 	il->_4965.wep_keys[idx].key_size = len;
3238 	memcpy(&il->_4965.wep_keys[idx].key, &keyconf->key, len);
3239 
3240 	ret = il4965_static_wepkey_cmd(il, false);
3241 
3242 	D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", len, idx, ret);
3243 	return ret;
3244 }
3245 
3246 static int
3247 il4965_set_wep_dynamic_key_info(struct il_priv *il,
3248 				struct ieee80211_key_conf *keyconf, u8 sta_id)
3249 {
3250 	unsigned long flags;
3251 	__le16 key_flags = 0;
3252 	struct il_addsta_cmd sta_cmd;
3253 
3254 	lockdep_assert_held(&il->mutex);
3255 
3256 	keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3257 
3258 	key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK);
3259 	key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3260 	key_flags &= ~STA_KEY_FLG_INVALID;
3261 
3262 	if (keyconf->keylen == WEP_KEY_LEN_128)
3263 		key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
3264 
3265 	if (sta_id == il->hw_params.bcast_id)
3266 		key_flags |= STA_KEY_MULTICAST_MSK;
3267 
3268 	spin_lock_irqsave(&il->sta_lock, flags);
3269 
3270 	il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3271 	il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3272 	il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx;
3273 
3274 	memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
3275 
3276 	memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key,
3277 	       keyconf->keylen);
3278 
3279 	if ((il->stations[sta_id].sta.key.
3280 	     key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
3281 		il->stations[sta_id].sta.key.key_offset =
3282 		    il_get_free_ucode_key_idx(il);
3283 	/* else, we are overriding an existing key => no need to allocated room
3284 	 * in uCode. */
3285 
3286 	WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
3287 	     "no space for a new key");
3288 
3289 	il->stations[sta_id].sta.key.key_flags = key_flags;
3290 	il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3291 	il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3292 
3293 	memcpy(&sta_cmd, &il->stations[sta_id].sta,
3294 	       sizeof(struct il_addsta_cmd));
3295 	spin_unlock_irqrestore(&il->sta_lock, flags);
3296 
3297 	return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3298 }
3299 
3300 static int
3301 il4965_set_ccmp_dynamic_key_info(struct il_priv *il,
3302 				 struct ieee80211_key_conf *keyconf, u8 sta_id)
3303 {
3304 	unsigned long flags;
3305 	__le16 key_flags = 0;
3306 	struct il_addsta_cmd sta_cmd;
3307 
3308 	lockdep_assert_held(&il->mutex);
3309 
3310 	key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
3311 	key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3312 	key_flags &= ~STA_KEY_FLG_INVALID;
3313 
3314 	if (sta_id == il->hw_params.bcast_id)
3315 		key_flags |= STA_KEY_MULTICAST_MSK;
3316 
3317 	keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3318 
3319 	spin_lock_irqsave(&il->sta_lock, flags);
3320 	il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3321 	il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3322 
3323 	memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
3324 
3325 	memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
3326 
3327 	if ((il->stations[sta_id].sta.key.
3328 	     key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
3329 		il->stations[sta_id].sta.key.key_offset =
3330 		    il_get_free_ucode_key_idx(il);
3331 	/* else, we are overriding an existing key => no need to allocated room
3332 	 * in uCode. */
3333 
3334 	WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
3335 	     "no space for a new key");
3336 
3337 	il->stations[sta_id].sta.key.key_flags = key_flags;
3338 	il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3339 	il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3340 
3341 	memcpy(&sta_cmd, &il->stations[sta_id].sta,
3342 	       sizeof(struct il_addsta_cmd));
3343 	spin_unlock_irqrestore(&il->sta_lock, flags);
3344 
3345 	return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3346 }
3347 
3348 static int
3349 il4965_set_tkip_dynamic_key_info(struct il_priv *il,
3350 				 struct ieee80211_key_conf *keyconf, u8 sta_id)
3351 {
3352 	unsigned long flags;
3353 	int ret = 0;
3354 	__le16 key_flags = 0;
3355 
3356 	key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
3357 	key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3358 	key_flags &= ~STA_KEY_FLG_INVALID;
3359 
3360 	if (sta_id == il->hw_params.bcast_id)
3361 		key_flags |= STA_KEY_MULTICAST_MSK;
3362 
3363 	keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3364 	keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3365 
3366 	spin_lock_irqsave(&il->sta_lock, flags);
3367 
3368 	il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3369 	il->stations[sta_id].keyinfo.keylen = 16;
3370 
3371 	if ((il->stations[sta_id].sta.key.
3372 	     key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
3373 		il->stations[sta_id].sta.key.key_offset =
3374 		    il_get_free_ucode_key_idx(il);
3375 	/* else, we are overriding an existing key => no need to allocated room
3376 	 * in uCode. */
3377 
3378 	WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
3379 	     "no space for a new key");
3380 
3381 	il->stations[sta_id].sta.key.key_flags = key_flags;
3382 
3383 	/* This copy is acutally not needed: we get the key with each TX */
3384 	memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16);
3385 
3386 	memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16);
3387 
3388 	spin_unlock_irqrestore(&il->sta_lock, flags);
3389 
3390 	return ret;
3391 }
3392 
3393 void
3394 il4965_update_tkip_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3395 		       struct ieee80211_sta *sta, u32 iv32, u16 *phase1key)
3396 {
3397 	u8 sta_id;
3398 	unsigned long flags;
3399 	int i;
3400 
3401 	if (il_scan_cancel(il)) {
3402 		/* cancel scan failed, just live w/ bad key and rely
3403 		   briefly on SW decryption */
3404 		return;
3405 	}
3406 
3407 	sta_id = il_sta_id_or_broadcast(il, sta);
3408 	if (sta_id == IL_INVALID_STATION)
3409 		return;
3410 
3411 	spin_lock_irqsave(&il->sta_lock, flags);
3412 
3413 	il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
3414 
3415 	for (i = 0; i < 5; i++)
3416 		il->stations[sta_id].sta.key.tkip_rx_ttak[i] =
3417 		    cpu_to_le16(phase1key[i]);
3418 
3419 	il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3420 	il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3421 
3422 	il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3423 
3424 	spin_unlock_irqrestore(&il->sta_lock, flags);
3425 }
3426 
3427 int
3428 il4965_remove_dynamic_key(struct il_priv *il,
3429 			  struct ieee80211_key_conf *keyconf, u8 sta_id)
3430 {
3431 	unsigned long flags;
3432 	u16 key_flags;
3433 	u8 keyidx;
3434 	struct il_addsta_cmd sta_cmd;
3435 
3436 	lockdep_assert_held(&il->mutex);
3437 
3438 	il->_4965.key_mapping_keys--;
3439 
3440 	spin_lock_irqsave(&il->sta_lock, flags);
3441 	key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags);
3442 	keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
3443 
3444 	D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id);
3445 
3446 	if (keyconf->keyidx != keyidx) {
3447 		/* We need to remove a key with idx different that the one
3448 		 * in the uCode. This means that the key we need to remove has
3449 		 * been replaced by another one with different idx.
3450 		 * Don't do anything and return ok
3451 		 */
3452 		spin_unlock_irqrestore(&il->sta_lock, flags);
3453 		return 0;
3454 	}
3455 
3456 	if (il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_INVALID) {
3457 		IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx,
3458 			key_flags);
3459 		spin_unlock_irqrestore(&il->sta_lock, flags);
3460 		return 0;
3461 	}
3462 
3463 	if (!test_and_clear_bit
3464 	    (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table))
3465 		IL_ERR("idx %d not used in uCode key table.\n",
3466 		       il->stations[sta_id].sta.key.key_offset);
3467 	memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
3468 	memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
3469 	il->stations[sta_id].sta.key.key_flags =
3470 	    STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
3471 	il->stations[sta_id].sta.key.key_offset = keyconf->hw_key_idx;
3472 	il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3473 	il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3474 
3475 	if (il_is_rfkill(il)) {
3476 		D_WEP
3477 		    ("Not sending C_ADD_STA command because RFKILL enabled.\n");
3478 		spin_unlock_irqrestore(&il->sta_lock, flags);
3479 		return 0;
3480 	}
3481 	memcpy(&sta_cmd, &il->stations[sta_id].sta,
3482 	       sizeof(struct il_addsta_cmd));
3483 	spin_unlock_irqrestore(&il->sta_lock, flags);
3484 
3485 	return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3486 }
3487 
3488 int
3489 il4965_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3490 		       u8 sta_id)
3491 {
3492 	int ret;
3493 
3494 	lockdep_assert_held(&il->mutex);
3495 
3496 	il->_4965.key_mapping_keys++;
3497 	keyconf->hw_key_idx = HW_KEY_DYNAMIC;
3498 
3499 	switch (keyconf->cipher) {
3500 	case WLAN_CIPHER_SUITE_CCMP:
3501 		ret =
3502 		    il4965_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
3503 		break;
3504 	case WLAN_CIPHER_SUITE_TKIP:
3505 		ret =
3506 		    il4965_set_tkip_dynamic_key_info(il, keyconf, sta_id);
3507 		break;
3508 	case WLAN_CIPHER_SUITE_WEP40:
3509 	case WLAN_CIPHER_SUITE_WEP104:
3510 		ret = il4965_set_wep_dynamic_key_info(il, keyconf, sta_id);
3511 		break;
3512 	default:
3513 		IL_ERR("Unknown alg: %s cipher = %x\n", __func__,
3514 		       keyconf->cipher);
3515 		ret = -EINVAL;
3516 	}
3517 
3518 	D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n",
3519 	      keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
3520 
3521 	return ret;
3522 }
3523 
3524 /**
3525  * il4965_alloc_bcast_station - add broadcast station into driver's station table.
3526  *
3527  * This adds the broadcast station into the driver's station table
3528  * and marks it driver active, so that it will be restored to the
3529  * device at the next best time.
3530  */
3531 int
3532 il4965_alloc_bcast_station(struct il_priv *il)
3533 {
3534 	struct il_link_quality_cmd *link_cmd;
3535 	unsigned long flags;
3536 	u8 sta_id;
3537 
3538 	spin_lock_irqsave(&il->sta_lock, flags);
3539 	sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
3540 	if (sta_id == IL_INVALID_STATION) {
3541 		IL_ERR("Unable to prepare broadcast station\n");
3542 		spin_unlock_irqrestore(&il->sta_lock, flags);
3543 
3544 		return -EINVAL;
3545 	}
3546 
3547 	il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
3548 	il->stations[sta_id].used |= IL_STA_BCAST;
3549 	spin_unlock_irqrestore(&il->sta_lock, flags);
3550 
3551 	link_cmd = il4965_sta_alloc_lq(il, sta_id);
3552 	if (!link_cmd) {
3553 		IL_ERR
3554 		    ("Unable to initialize rate scaling for bcast station.\n");
3555 		return -ENOMEM;
3556 	}
3557 
3558 	spin_lock_irqsave(&il->sta_lock, flags);
3559 	il->stations[sta_id].lq = link_cmd;
3560 	spin_unlock_irqrestore(&il->sta_lock, flags);
3561 
3562 	return 0;
3563 }
3564 
3565 /**
3566  * il4965_update_bcast_station - update broadcast station's LQ command
3567  *
3568  * Only used by iwl4965. Placed here to have all bcast station management
3569  * code together.
3570  */
3571 static int
3572 il4965_update_bcast_station(struct il_priv *il)
3573 {
3574 	unsigned long flags;
3575 	struct il_link_quality_cmd *link_cmd;
3576 	u8 sta_id = il->hw_params.bcast_id;
3577 
3578 	link_cmd = il4965_sta_alloc_lq(il, sta_id);
3579 	if (!link_cmd) {
3580 		IL_ERR("Unable to initialize rate scaling for bcast sta.\n");
3581 		return -ENOMEM;
3582 	}
3583 
3584 	spin_lock_irqsave(&il->sta_lock, flags);
3585 	if (il->stations[sta_id].lq)
3586 		kfree(il->stations[sta_id].lq);
3587 	else
3588 		D_INFO("Bcast sta rate scaling has not been initialized.\n");
3589 	il->stations[sta_id].lq = link_cmd;
3590 	spin_unlock_irqrestore(&il->sta_lock, flags);
3591 
3592 	return 0;
3593 }
3594 
3595 int
3596 il4965_update_bcast_stations(struct il_priv *il)
3597 {
3598 	return il4965_update_bcast_station(il);
3599 }
3600 
3601 /**
3602  * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table
3603  */
3604 int
3605 il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid)
3606 {
3607 	unsigned long flags;
3608 	struct il_addsta_cmd sta_cmd;
3609 
3610 	lockdep_assert_held(&il->mutex);
3611 
3612 	/* Remove "disable" flag, to enable Tx for this TID */
3613 	spin_lock_irqsave(&il->sta_lock, flags);
3614 	il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3615 	il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3616 	il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3617 	memcpy(&sta_cmd, &il->stations[sta_id].sta,
3618 	       sizeof(struct il_addsta_cmd));
3619 	spin_unlock_irqrestore(&il->sta_lock, flags);
3620 
3621 	return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3622 }
3623 
3624 int
3625 il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid,
3626 			u16 ssn)
3627 {
3628 	unsigned long flags;
3629 	int sta_id;
3630 	struct il_addsta_cmd sta_cmd;
3631 
3632 	lockdep_assert_held(&il->mutex);
3633 
3634 	sta_id = il_sta_id(sta);
3635 	if (sta_id == IL_INVALID_STATION)
3636 		return -ENXIO;
3637 
3638 	spin_lock_irqsave(&il->sta_lock, flags);
3639 	il->stations[sta_id].sta.station_flags_msk = 0;
3640 	il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
3641 	il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid;
3642 	il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3643 	il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3644 	memcpy(&sta_cmd, &il->stations[sta_id].sta,
3645 	       sizeof(struct il_addsta_cmd));
3646 	spin_unlock_irqrestore(&il->sta_lock, flags);
3647 
3648 	return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3649 }
3650 
3651 int
3652 il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid)
3653 {
3654 	unsigned long flags;
3655 	int sta_id;
3656 	struct il_addsta_cmd sta_cmd;
3657 
3658 	lockdep_assert_held(&il->mutex);
3659 
3660 	sta_id = il_sta_id(sta);
3661 	if (sta_id == IL_INVALID_STATION) {
3662 		IL_ERR("Invalid station for AGG tid %d\n", tid);
3663 		return -ENXIO;
3664 	}
3665 
3666 	spin_lock_irqsave(&il->sta_lock, flags);
3667 	il->stations[sta_id].sta.station_flags_msk = 0;
3668 	il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
3669 	il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid;
3670 	il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3671 	memcpy(&sta_cmd, &il->stations[sta_id].sta,
3672 	       sizeof(struct il_addsta_cmd));
3673 	spin_unlock_irqrestore(&il->sta_lock, flags);
3674 
3675 	return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3676 }
3677 
3678 void
3679 il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt)
3680 {
3681 	unsigned long flags;
3682 
3683 	spin_lock_irqsave(&il->sta_lock, flags);
3684 	il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK;
3685 	il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3686 	il->stations[sta_id].sta.sta.modify_mask =
3687 	    STA_MODIFY_SLEEP_TX_COUNT_MSK;
3688 	il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt);
3689 	il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3690 	il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3691 	spin_unlock_irqrestore(&il->sta_lock, flags);
3692 
3693 }
3694 
3695 void
3696 il4965_update_chain_flags(struct il_priv *il)
3697 {
3698 	if (il->ops->set_rxon_chain) {
3699 		il->ops->set_rxon_chain(il);
3700 		if (il->active.rx_chain != il->staging.rx_chain)
3701 			il_commit_rxon(il);
3702 	}
3703 }
3704 
3705 static void
3706 il4965_clear_free_frames(struct il_priv *il)
3707 {
3708 	struct list_head *element;
3709 
3710 	D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
3711 
3712 	while (!list_empty(&il->free_frames)) {
3713 		element = il->free_frames.next;
3714 		list_del(element);
3715 		kfree(list_entry(element, struct il_frame, list));
3716 		il->frames_count--;
3717 	}
3718 
3719 	if (il->frames_count) {
3720 		IL_WARN("%d frames still in use.  Did we lose one?\n",
3721 			il->frames_count);
3722 		il->frames_count = 0;
3723 	}
3724 }
3725 
3726 static struct il_frame *
3727 il4965_get_free_frame(struct il_priv *il)
3728 {
3729 	struct il_frame *frame;
3730 	struct list_head *element;
3731 	if (list_empty(&il->free_frames)) {
3732 		frame = kzalloc(sizeof(*frame), GFP_KERNEL);
3733 		if (!frame) {
3734 			IL_ERR("Could not allocate frame!\n");
3735 			return NULL;
3736 		}
3737 
3738 		il->frames_count++;
3739 		return frame;
3740 	}
3741 
3742 	element = il->free_frames.next;
3743 	list_del(element);
3744 	return list_entry(element, struct il_frame, list);
3745 }
3746 
3747 static void
3748 il4965_free_frame(struct il_priv *il, struct il_frame *frame)
3749 {
3750 	memset(frame, 0, sizeof(*frame));
3751 	list_add(&frame->list, &il->free_frames);
3752 }
3753 
3754 static u32
3755 il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
3756 			 int left)
3757 {
3758 	lockdep_assert_held(&il->mutex);
3759 
3760 	if (!il->beacon_skb)
3761 		return 0;
3762 
3763 	if (il->beacon_skb->len > left)
3764 		return 0;
3765 
3766 	memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
3767 
3768 	return il->beacon_skb->len;
3769 }
3770 
3771 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
3772 static void
3773 il4965_set_beacon_tim(struct il_priv *il,
3774 		      struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon,
3775 		      u32 frame_size)
3776 {
3777 	u16 tim_idx;
3778 	struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
3779 
3780 	/*
3781 	 * The idx is relative to frame start but we start looking at the
3782 	 * variable-length part of the beacon.
3783 	 */
3784 	tim_idx = mgmt->u.beacon.variable - beacon;
3785 
3786 	/* Parse variable-length elements of beacon to find WLAN_EID_TIM */
3787 	while ((tim_idx < (frame_size - 2)) &&
3788 	       (beacon[tim_idx] != WLAN_EID_TIM))
3789 		tim_idx += beacon[tim_idx + 1] + 2;
3790 
3791 	/* If TIM field was found, set variables */
3792 	if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
3793 		tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
3794 		tx_beacon_cmd->tim_size = beacon[tim_idx + 1];
3795 	} else
3796 		IL_WARN("Unable to find TIM Element in beacon\n");
3797 }
3798 
3799 static unsigned int
3800 il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame)
3801 {
3802 	struct il_tx_beacon_cmd *tx_beacon_cmd;
3803 	u32 frame_size;
3804 	u32 rate_flags;
3805 	u32 rate;
3806 	/*
3807 	 * We have to set up the TX command, the TX Beacon command, and the
3808 	 * beacon contents.
3809 	 */
3810 
3811 	lockdep_assert_held(&il->mutex);
3812 
3813 	if (!il->beacon_enabled) {
3814 		IL_ERR("Trying to build beacon without beaconing enabled\n");
3815 		return 0;
3816 	}
3817 
3818 	/* Initialize memory */
3819 	tx_beacon_cmd = &frame->u.beacon;
3820 	memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
3821 
3822 	/* Set up TX beacon contents */
3823 	frame_size =
3824 	    il4965_fill_beacon_frame(il, tx_beacon_cmd->frame,
3825 				     sizeof(frame->u) - sizeof(*tx_beacon_cmd));
3826 	if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
3827 		return 0;
3828 	if (!frame_size)
3829 		return 0;
3830 
3831 	/* Set up TX command fields */
3832 	tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
3833 	tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
3834 	tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
3835 	tx_beacon_cmd->tx.tx_flags =
3836 	    TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK |
3837 	    TX_CMD_FLG_STA_RATE_MSK;
3838 
3839 	/* Set up TX beacon command fields */
3840 	il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame,
3841 			      frame_size);
3842 
3843 	/* Set up packet rate and flags */
3844 	rate = il_get_lowest_plcp(il);
3845 	il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
3846 	rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
3847 	if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE))
3848 		rate_flags |= RATE_MCS_CCK_MSK;
3849 	tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags);
3850 
3851 	return sizeof(*tx_beacon_cmd) + frame_size;
3852 }
3853 
3854 int
3855 il4965_send_beacon_cmd(struct il_priv *il)
3856 {
3857 	struct il_frame *frame;
3858 	unsigned int frame_size;
3859 	int rc;
3860 
3861 	frame = il4965_get_free_frame(il);
3862 	if (!frame) {
3863 		IL_ERR("Could not obtain free frame buffer for beacon "
3864 		       "command.\n");
3865 		return -ENOMEM;
3866 	}
3867 
3868 	frame_size = il4965_hw_get_beacon_cmd(il, frame);
3869 	if (!frame_size) {
3870 		IL_ERR("Error configuring the beacon command\n");
3871 		il4965_free_frame(il, frame);
3872 		return -EINVAL;
3873 	}
3874 
3875 	rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
3876 
3877 	il4965_free_frame(il, frame);
3878 
3879 	return rc;
3880 }
3881 
3882 static inline dma_addr_t
3883 il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx)
3884 {
3885 	struct il_tfd_tb *tb = &tfd->tbs[idx];
3886 
3887 	dma_addr_t addr = get_unaligned_le32(&tb->lo);
3888 	if (sizeof(dma_addr_t) > sizeof(u32))
3889 		addr |=
3890 		    ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) <<
3891 		    16;
3892 
3893 	return addr;
3894 }
3895 
3896 static inline u16
3897 il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx)
3898 {
3899 	struct il_tfd_tb *tb = &tfd->tbs[idx];
3900 
3901 	return le16_to_cpu(tb->hi_n_len) >> 4;
3902 }
3903 
3904 static inline void
3905 il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len)
3906 {
3907 	struct il_tfd_tb *tb = &tfd->tbs[idx];
3908 	u16 hi_n_len = len << 4;
3909 
3910 	put_unaligned_le32(addr, &tb->lo);
3911 	if (sizeof(dma_addr_t) > sizeof(u32))
3912 		hi_n_len |= ((addr >> 16) >> 16) & 0xF;
3913 
3914 	tb->hi_n_len = cpu_to_le16(hi_n_len);
3915 
3916 	tfd->num_tbs = idx + 1;
3917 }
3918 
3919 static inline u8
3920 il4965_tfd_get_num_tbs(struct il_tfd *tfd)
3921 {
3922 	return tfd->num_tbs & 0x1f;
3923 }
3924 
3925 /**
3926  * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
3927  * @il - driver ilate data
3928  * @txq - tx queue
3929  *
3930  * Does NOT advance any TFD circular buffer read/write idxes
3931  * Does NOT free the TFD itself (which is within circular buffer)
3932  */
3933 void
3934 il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
3935 {
3936 	struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds;
3937 	struct il_tfd *tfd;
3938 	struct pci_dev *dev = il->pci_dev;
3939 	int idx = txq->q.read_ptr;
3940 	int i;
3941 	int num_tbs;
3942 
3943 	tfd = &tfd_tmp[idx];
3944 
3945 	/* Sanity check on number of chunks */
3946 	num_tbs = il4965_tfd_get_num_tbs(tfd);
3947 
3948 	if (num_tbs >= IL_NUM_OF_TBS) {
3949 		IL_ERR("Too many chunks: %i\n", num_tbs);
3950 		/* @todo issue fatal error, it is quite serious situation */
3951 		return;
3952 	}
3953 
3954 	/* Unmap tx_cmd */
3955 	if (num_tbs)
3956 		pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
3957 				 dma_unmap_len(&txq->meta[idx], len),
3958 				 PCI_DMA_BIDIRECTIONAL);
3959 
3960 	/* Unmap chunks, if any. */
3961 	for (i = 1; i < num_tbs; i++)
3962 		pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i),
3963 				 il4965_tfd_tb_get_len(tfd, i),
3964 				 PCI_DMA_TODEVICE);
3965 
3966 	/* free SKB */
3967 	if (txq->skbs) {
3968 		struct sk_buff *skb = txq->skbs[txq->q.read_ptr];
3969 
3970 		/* can be called from irqs-disabled context */
3971 		if (skb) {
3972 			dev_kfree_skb_any(skb);
3973 			txq->skbs[txq->q.read_ptr] = NULL;
3974 		}
3975 	}
3976 }
3977 
3978 int
3979 il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
3980 				dma_addr_t addr, u16 len, u8 reset, u8 pad)
3981 {
3982 	struct il_queue *q;
3983 	struct il_tfd *tfd, *tfd_tmp;
3984 	u32 num_tbs;
3985 
3986 	q = &txq->q;
3987 	tfd_tmp = (struct il_tfd *)txq->tfds;
3988 	tfd = &tfd_tmp[q->write_ptr];
3989 
3990 	if (reset)
3991 		memset(tfd, 0, sizeof(*tfd));
3992 
3993 	num_tbs = il4965_tfd_get_num_tbs(tfd);
3994 
3995 	/* Each TFD can point to a maximum 20 Tx buffers */
3996 	if (num_tbs >= IL_NUM_OF_TBS) {
3997 		IL_ERR("Error can not send more than %d chunks\n",
3998 		       IL_NUM_OF_TBS);
3999 		return -EINVAL;
4000 	}
4001 
4002 	BUG_ON(addr & ~DMA_BIT_MASK(36));
4003 	if (unlikely(addr & ~IL_TX_DMA_MASK))
4004 		IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr);
4005 
4006 	il4965_tfd_set_tb(tfd, num_tbs, addr, len);
4007 
4008 	return 0;
4009 }
4010 
4011 /*
4012  * Tell nic where to find circular buffer of Tx Frame Descriptors for
4013  * given Tx queue, and enable the DMA channel used for that queue.
4014  *
4015  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
4016  * channels supported in hardware.
4017  */
4018 int
4019 il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
4020 {
4021 	int txq_id = txq->q.id;
4022 
4023 	/* Circular buffer (TFD queue in DRAM) physical base address */
4024 	il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);
4025 
4026 	return 0;
4027 }
4028 
4029 /******************************************************************************
4030  *
4031  * Generic RX handler implementations
4032  *
4033  ******************************************************************************/
4034 static void
4035 il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
4036 {
4037 	struct il_rx_pkt *pkt = rxb_addr(rxb);
4038 	struct il_alive_resp *palive;
4039 	struct delayed_work *pwork;
4040 
4041 	palive = &pkt->u.alive_frame;
4042 
4043 	D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
4044 	       palive->is_valid, palive->ver_type, palive->ver_subtype);
4045 
4046 	if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
4047 		D_INFO("Initialization Alive received.\n");
4048 		memcpy(&il->card_alive_init, &pkt->u.alive_frame,
4049 		       sizeof(struct il_init_alive_resp));
4050 		pwork = &il->init_alive_start;
4051 	} else {
4052 		D_INFO("Runtime Alive received.\n");
4053 		memcpy(&il->card_alive, &pkt->u.alive_frame,
4054 		       sizeof(struct il_alive_resp));
4055 		pwork = &il->alive_start;
4056 	}
4057 
4058 	/* We delay the ALIVE response by 5ms to
4059 	 * give the HW RF Kill time to activate... */
4060 	if (palive->is_valid == UCODE_VALID_OK)
4061 		queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
4062 	else
4063 		IL_WARN("uCode did not respond OK.\n");
4064 }
4065 
4066 /**
4067  * il4965_bg_stats_periodic - Timer callback to queue stats
4068  *
4069  * This callback is provided in order to send a stats request.
4070  *
4071  * This timer function is continually reset to execute within
4072  * 60 seconds since the last N_STATS was received.  We need to
4073  * ensure we receive the stats in order to update the temperature
4074  * used for calibrating the TXPOWER.
4075  */
4076 static void
4077 il4965_bg_stats_periodic(unsigned long data)
4078 {
4079 	struct il_priv *il = (struct il_priv *)data;
4080 
4081 	if (test_bit(S_EXIT_PENDING, &il->status))
4082 		return;
4083 
4084 	/* dont send host command if rf-kill is on */
4085 	if (!il_is_ready_rf(il))
4086 		return;
4087 
4088 	il_send_stats_request(il, CMD_ASYNC, false);
4089 }
4090 
4091 static void
4092 il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
4093 {
4094 	struct il_rx_pkt *pkt = rxb_addr(rxb);
4095 	struct il4965_beacon_notif *beacon =
4096 	    (struct il4965_beacon_notif *)pkt->u.raw;
4097 #ifdef CONFIG_IWLEGACY_DEBUG
4098 	u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
4099 
4100 	D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n",
4101 	     le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
4102 	     beacon->beacon_notify_hdr.failure_frame,
4103 	     le32_to_cpu(beacon->ibss_mgr_status),
4104 	     le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
4105 #endif
4106 	il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
4107 }
4108 
4109 static void
4110 il4965_perform_ct_kill_task(struct il_priv *il)
4111 {
4112 	unsigned long flags;
4113 
4114 	D_POWER("Stop all queues\n");
4115 
4116 	if (il->mac80211_registered)
4117 		ieee80211_stop_queues(il->hw);
4118 
4119 	_il_wr(il, CSR_UCODE_DRV_GP1_SET,
4120 	       CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
4121 	_il_rd(il, CSR_UCODE_DRV_GP1);
4122 
4123 	spin_lock_irqsave(&il->reg_lock, flags);
4124 	if (likely(_il_grab_nic_access(il)))
4125 		_il_release_nic_access(il);
4126 	spin_unlock_irqrestore(&il->reg_lock, flags);
4127 }
4128 
4129 /* Handle notification from uCode that card's power state is changing
4130  * due to software, hardware, or critical temperature RFKILL */
4131 static void
4132 il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
4133 {
4134 	struct il_rx_pkt *pkt = rxb_addr(rxb);
4135 	u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
4136 	unsigned long status = il->status;
4137 
4138 	D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n",
4139 		  (flags & HW_CARD_DISABLED) ? "Kill" : "On",
4140 		  (flags & SW_CARD_DISABLED) ? "Kill" : "On",
4141 		  (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached");
4142 
4143 	if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) {
4144 
4145 		_il_wr(il, CSR_UCODE_DRV_GP1_SET,
4146 		       CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4147 
4148 		il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
4149 
4150 		if (!(flags & RXON_CARD_DISABLED)) {
4151 			_il_wr(il, CSR_UCODE_DRV_GP1_CLR,
4152 			       CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4153 			il_wr(il, HBUS_TARG_MBX_C,
4154 			      HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
4155 		}
4156 	}
4157 
4158 	if (flags & CT_CARD_DISABLED)
4159 		il4965_perform_ct_kill_task(il);
4160 
4161 	if (flags & HW_CARD_DISABLED)
4162 		set_bit(S_RFKILL, &il->status);
4163 	else
4164 		clear_bit(S_RFKILL, &il->status);
4165 
4166 	if (!(flags & RXON_CARD_DISABLED))
4167 		il_scan_cancel(il);
4168 
4169 	if ((test_bit(S_RFKILL, &status) !=
4170 	     test_bit(S_RFKILL, &il->status)))
4171 		wiphy_rfkill_set_hw_state(il->hw->wiphy,
4172 					  test_bit(S_RFKILL, &il->status));
4173 	else
4174 		wake_up(&il->wait_command_queue);
4175 }
4176 
4177 /**
4178  * il4965_setup_handlers - Initialize Rx handler callbacks
4179  *
4180  * Setup the RX handlers for each of the reply types sent from the uCode
4181  * to the host.
4182  *
4183  * This function chains into the hardware specific files for them to setup
4184  * any hardware specific handlers as well.
4185  */
4186 static void
4187 il4965_setup_handlers(struct il_priv *il)
4188 {
4189 	il->handlers[N_ALIVE] = il4965_hdl_alive;
4190 	il->handlers[N_ERROR] = il_hdl_error;
4191 	il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
4192 	il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
4193 	il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
4194 	il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
4195 	il->handlers[N_BEACON] = il4965_hdl_beacon;
4196 
4197 	/*
4198 	 * The same handler is used for both the REPLY to a discrete
4199 	 * stats request from the host as well as for the periodic
4200 	 * stats notifications (after received beacons) from the uCode.
4201 	 */
4202 	il->handlers[C_STATS] = il4965_hdl_c_stats;
4203 	il->handlers[N_STATS] = il4965_hdl_stats;
4204 
4205 	il_setup_rx_scan_handlers(il);
4206 
4207 	/* status change handler */
4208 	il->handlers[N_CARD_STATE] = il4965_hdl_card_state;
4209 
4210 	il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon;
4211 	/* Rx handlers */
4212 	il->handlers[N_RX_PHY] = il4965_hdl_rx_phy;
4213 	il->handlers[N_RX_MPDU] = il4965_hdl_rx;
4214 	il->handlers[N_RX] = il4965_hdl_rx;
4215 	/* block ack */
4216 	il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba;
4217 	/* Tx response */
4218 	il->handlers[C_TX] = il4965_hdl_tx;
4219 }
4220 
4221 /**
4222  * il4965_rx_handle - Main entry function for receiving responses from uCode
4223  *
4224  * Uses the il->handlers callback function array to invoke
4225  * the appropriate handlers, including command responses,
4226  * frame-received notifications, and other notifications.
4227  */
4228 void
4229 il4965_rx_handle(struct il_priv *il)
4230 {
4231 	struct il_rx_buf *rxb;
4232 	struct il_rx_pkt *pkt;
4233 	struct il_rx_queue *rxq = &il->rxq;
4234 	u32 r, i;
4235 	int reclaim;
4236 	unsigned long flags;
4237 	u8 fill_rx = 0;
4238 	u32 count = 8;
4239 	int total_empty;
4240 
4241 	/* uCode's read idx (stored in shared DRAM) indicates the last Rx
4242 	 * buffer that the driver may process (last buffer filled by ucode). */
4243 	r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
4244 	i = rxq->read;
4245 
4246 	/* Rx interrupt, but nothing sent from uCode */
4247 	if (i == r)
4248 		D_RX("r = %d, i = %d\n", r, i);
4249 
4250 	/* calculate total frames need to be restock after handling RX */
4251 	total_empty = r - rxq->write_actual;
4252 	if (total_empty < 0)
4253 		total_empty += RX_QUEUE_SIZE;
4254 
4255 	if (total_empty > (RX_QUEUE_SIZE / 2))
4256 		fill_rx = 1;
4257 
4258 	while (i != r) {
4259 		int len;
4260 
4261 		rxb = rxq->queue[i];
4262 
4263 		/* If an RXB doesn't have a Rx queue slot associated with it,
4264 		 * then a bug has been introduced in the queue refilling
4265 		 * routines -- catch it here */
4266 		BUG_ON(rxb == NULL);
4267 
4268 		rxq->queue[i] = NULL;
4269 
4270 		pci_unmap_page(il->pci_dev, rxb->page_dma,
4271 			       PAGE_SIZE << il->hw_params.rx_page_order,
4272 			       PCI_DMA_FROMDEVICE);
4273 		pkt = rxb_addr(rxb);
4274 
4275 		len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
4276 		len += sizeof(u32);	/* account for status word */
4277 
4278 		reclaim = il_need_reclaim(il, pkt);
4279 
4280 		/* Based on type of command response or notification,
4281 		 *   handle those that need handling via function in
4282 		 *   handlers table.  See il4965_setup_handlers() */
4283 		if (il->handlers[pkt->hdr.cmd]) {
4284 			D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
4285 			     il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4286 			il->isr_stats.handlers[pkt->hdr.cmd]++;
4287 			il->handlers[pkt->hdr.cmd] (il, rxb);
4288 		} else {
4289 			/* No handling needed */
4290 			D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
4291 			     i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4292 		}
4293 
4294 		/*
4295 		 * XXX: After here, we should always check rxb->page
4296 		 * against NULL before touching it or its virtual
4297 		 * memory (pkt). Because some handler might have
4298 		 * already taken or freed the pages.
4299 		 */
4300 
4301 		if (reclaim) {
4302 			/* Invoke any callbacks, transfer the buffer to caller,
4303 			 * and fire off the (possibly) blocking il_send_cmd()
4304 			 * as we reclaim the driver command queue */
4305 			if (rxb->page)
4306 				il_tx_cmd_complete(il, rxb);
4307 			else
4308 				IL_WARN("Claim null rxb?\n");
4309 		}
4310 
4311 		/* Reuse the page if possible. For notification packets and
4312 		 * SKBs that fail to Rx correctly, add them back into the
4313 		 * rx_free list for reuse later. */
4314 		spin_lock_irqsave(&rxq->lock, flags);
4315 		if (rxb->page != NULL) {
4316 			rxb->page_dma =
4317 			    pci_map_page(il->pci_dev, rxb->page, 0,
4318 					 PAGE_SIZE << il->hw_params.
4319 					 rx_page_order, PCI_DMA_FROMDEVICE);
4320 
4321 			if (unlikely(pci_dma_mapping_error(il->pci_dev,
4322 							   rxb->page_dma))) {
4323 				__il_free_pages(il, rxb->page);
4324 				rxb->page = NULL;
4325 				list_add_tail(&rxb->list, &rxq->rx_used);
4326 			} else {
4327 				list_add_tail(&rxb->list, &rxq->rx_free);
4328 				rxq->free_count++;
4329 			}
4330 		} else
4331 			list_add_tail(&rxb->list, &rxq->rx_used);
4332 
4333 		spin_unlock_irqrestore(&rxq->lock, flags);
4334 
4335 		i = (i + 1) & RX_QUEUE_MASK;
4336 		/* If there are a lot of unused frames,
4337 		 * restock the Rx queue so ucode wont assert. */
4338 		if (fill_rx) {
4339 			count++;
4340 			if (count >= 8) {
4341 				rxq->read = i;
4342 				il4965_rx_replenish_now(il);
4343 				count = 0;
4344 			}
4345 		}
4346 	}
4347 
4348 	/* Backtrack one entry */
4349 	rxq->read = i;
4350 	if (fill_rx)
4351 		il4965_rx_replenish_now(il);
4352 	else
4353 		il4965_rx_queue_restock(il);
4354 }
4355 
4356 /* call this function to flush any scheduled tasklet */
4357 static inline void
4358 il4965_synchronize_irq(struct il_priv *il)
4359 {
4360 	/* wait to make sure we flush pending tasklet */
4361 	synchronize_irq(il->pci_dev->irq);
4362 	tasklet_kill(&il->irq_tasklet);
4363 }
4364 
4365 static void
4366 il4965_irq_tasklet(struct il_priv *il)
4367 {
4368 	u32 inta, handled = 0;
4369 	u32 inta_fh;
4370 	unsigned long flags;
4371 	u32 i;
4372 #ifdef CONFIG_IWLEGACY_DEBUG
4373 	u32 inta_mask;
4374 #endif
4375 
4376 	spin_lock_irqsave(&il->lock, flags);
4377 
4378 	/* Ack/clear/reset pending uCode interrupts.
4379 	 * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4380 	 *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
4381 	inta = _il_rd(il, CSR_INT);
4382 	_il_wr(il, CSR_INT, inta);
4383 
4384 	/* Ack/clear/reset pending flow-handler (DMA) interrupts.
4385 	 * Any new interrupts that happen after this, either while we're
4386 	 * in this tasklet, or later, will show up in next ISR/tasklet. */
4387 	inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4388 	_il_wr(il, CSR_FH_INT_STATUS, inta_fh);
4389 
4390 #ifdef CONFIG_IWLEGACY_DEBUG
4391 	if (il_get_debug_level(il) & IL_DL_ISR) {
4392 		/* just for debug */
4393 		inta_mask = _il_rd(il, CSR_INT_MASK);
4394 		D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
4395 		      inta_mask, inta_fh);
4396 	}
4397 #endif
4398 
4399 	spin_unlock_irqrestore(&il->lock, flags);
4400 
4401 	/* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4402 	 * atomic, make sure that inta covers all the interrupts that
4403 	 * we've discovered, even if FH interrupt came in just after
4404 	 * reading CSR_INT. */
4405 	if (inta_fh & CSR49_FH_INT_RX_MASK)
4406 		inta |= CSR_INT_BIT_FH_RX;
4407 	if (inta_fh & CSR49_FH_INT_TX_MASK)
4408 		inta |= CSR_INT_BIT_FH_TX;
4409 
4410 	/* Now service all interrupt bits discovered above. */
4411 	if (inta & CSR_INT_BIT_HW_ERR) {
4412 		IL_ERR("Hardware error detected.  Restarting.\n");
4413 
4414 		/* Tell the device to stop sending interrupts */
4415 		il_disable_interrupts(il);
4416 
4417 		il->isr_stats.hw++;
4418 		il_irq_handle_error(il);
4419 
4420 		handled |= CSR_INT_BIT_HW_ERR;
4421 
4422 		return;
4423 	}
4424 #ifdef CONFIG_IWLEGACY_DEBUG
4425 	if (il_get_debug_level(il) & (IL_DL_ISR)) {
4426 		/* NIC fires this, but we don't use it, redundant with WAKEUP */
4427 		if (inta & CSR_INT_BIT_SCD) {
4428 			D_ISR("Scheduler finished to transmit "
4429 			      "the frame/frames.\n");
4430 			il->isr_stats.sch++;
4431 		}
4432 
4433 		/* Alive notification via Rx interrupt will do the real work */
4434 		if (inta & CSR_INT_BIT_ALIVE) {
4435 			D_ISR("Alive interrupt\n");
4436 			il->isr_stats.alive++;
4437 		}
4438 	}
4439 #endif
4440 	/* Safely ignore these bits for debug checks below */
4441 	inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
4442 
4443 	/* HW RF KILL switch toggled */
4444 	if (inta & CSR_INT_BIT_RF_KILL) {
4445 		int hw_rf_kill = 0;
4446 
4447 		if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4448 			hw_rf_kill = 1;
4449 
4450 		IL_WARN("RF_KILL bit toggled to %s.\n",
4451 			hw_rf_kill ? "disable radio" : "enable radio");
4452 
4453 		il->isr_stats.rfkill++;
4454 
4455 		/* driver only loads ucode once setting the interface up.
4456 		 * the driver allows loading the ucode even if the radio
4457 		 * is killed. Hence update the killswitch state here. The
4458 		 * rfkill handler will care about restarting if needed.
4459 		 */
4460 		if (hw_rf_kill) {
4461 			set_bit(S_RFKILL, &il->status);
4462 		} else {
4463 			clear_bit(S_RFKILL, &il->status);
4464 			il_force_reset(il, true);
4465 		}
4466 		wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill);
4467 
4468 		handled |= CSR_INT_BIT_RF_KILL;
4469 	}
4470 
4471 	/* Chip got too hot and stopped itself */
4472 	if (inta & CSR_INT_BIT_CT_KILL) {
4473 		IL_ERR("Microcode CT kill error detected.\n");
4474 		il->isr_stats.ctkill++;
4475 		handled |= CSR_INT_BIT_CT_KILL;
4476 	}
4477 
4478 	/* Error detected by uCode */
4479 	if (inta & CSR_INT_BIT_SW_ERR) {
4480 		IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n",
4481 		       inta);
4482 		il->isr_stats.sw++;
4483 		il_irq_handle_error(il);
4484 		handled |= CSR_INT_BIT_SW_ERR;
4485 	}
4486 
4487 	/*
4488 	 * uCode wakes up after power-down sleep.
4489 	 * Tell device about any new tx or host commands enqueued,
4490 	 * and about any Rx buffers made available while asleep.
4491 	 */
4492 	if (inta & CSR_INT_BIT_WAKEUP) {
4493 		D_ISR("Wakeup interrupt\n");
4494 		il_rx_queue_update_write_ptr(il, &il->rxq);
4495 		for (i = 0; i < il->hw_params.max_txq_num; i++)
4496 			il_txq_update_write_ptr(il, &il->txq[i]);
4497 		il->isr_stats.wakeup++;
4498 		handled |= CSR_INT_BIT_WAKEUP;
4499 	}
4500 
4501 	/* All uCode command responses, including Tx command responses,
4502 	 * Rx "responses" (frame-received notification), and other
4503 	 * notifications from uCode come through here*/
4504 	if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
4505 		il4965_rx_handle(il);
4506 		il->isr_stats.rx++;
4507 		handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4508 	}
4509 
4510 	/* This "Tx" DMA channel is used only for loading uCode */
4511 	if (inta & CSR_INT_BIT_FH_TX) {
4512 		D_ISR("uCode load interrupt\n");
4513 		il->isr_stats.tx++;
4514 		handled |= CSR_INT_BIT_FH_TX;
4515 		/* Wake up uCode load routine, now that load is complete */
4516 		il->ucode_write_complete = 1;
4517 		wake_up(&il->wait_command_queue);
4518 	}
4519 
4520 	if (inta & ~handled) {
4521 		IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4522 		il->isr_stats.unhandled++;
4523 	}
4524 
4525 	if (inta & ~(il->inta_mask)) {
4526 		IL_WARN("Disabled INTA bits 0x%08x were pending\n",
4527 			inta & ~il->inta_mask);
4528 		IL_WARN("   with FH49_INT = 0x%08x\n", inta_fh);
4529 	}
4530 
4531 	/* Re-enable all interrupts */
4532 	/* only Re-enable if disabled by irq */
4533 	if (test_bit(S_INT_ENABLED, &il->status))
4534 		il_enable_interrupts(il);
4535 	/* Re-enable RF_KILL if it occurred */
4536 	else if (handled & CSR_INT_BIT_RF_KILL)
4537 		il_enable_rfkill_int(il);
4538 
4539 #ifdef CONFIG_IWLEGACY_DEBUG
4540 	if (il_get_debug_level(il) & (IL_DL_ISR)) {
4541 		inta = _il_rd(il, CSR_INT);
4542 		inta_mask = _il_rd(il, CSR_INT_MASK);
4543 		inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4544 		D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4545 		      "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4546 	}
4547 #endif
4548 }
4549 
4550 /*****************************************************************************
4551  *
4552  * sysfs attributes
4553  *
4554  *****************************************************************************/
4555 
4556 #ifdef CONFIG_IWLEGACY_DEBUG
4557 
4558 /*
4559  * The following adds a new attribute to the sysfs representation
4560  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
4561  * used for controlling the debug level.
4562  *
4563  * See the level definitions in iwl for details.
4564  *
4565  * The debug_level being managed using sysfs below is a per device debug
4566  * level that is used instead of the global debug level if it (the per
4567  * device debug level) is set.
4568  */
4569 static ssize_t
4570 il4965_show_debug_level(struct device *d, struct device_attribute *attr,
4571 			char *buf)
4572 {
4573 	struct il_priv *il = dev_get_drvdata(d);
4574 	return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
4575 }
4576 
4577 static ssize_t
4578 il4965_store_debug_level(struct device *d, struct device_attribute *attr,
4579 			 const char *buf, size_t count)
4580 {
4581 	struct il_priv *il = dev_get_drvdata(d);
4582 	unsigned long val;
4583 	int ret;
4584 
4585 	ret = kstrtoul(buf, 0, &val);
4586 	if (ret)
4587 		IL_ERR("%s is not in hex or decimal form.\n", buf);
4588 	else
4589 		il->debug_level = val;
4590 
4591 	return strnlen(buf, count);
4592 }
4593 
4594 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il4965_show_debug_level,
4595 		   il4965_store_debug_level);
4596 
4597 #endif /* CONFIG_IWLEGACY_DEBUG */
4598 
4599 static ssize_t
4600 il4965_show_temperature(struct device *d, struct device_attribute *attr,
4601 			char *buf)
4602 {
4603 	struct il_priv *il = dev_get_drvdata(d);
4604 
4605 	if (!il_is_alive(il))
4606 		return -EAGAIN;
4607 
4608 	return sprintf(buf, "%d\n", il->temperature);
4609 }
4610 
4611 static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL);
4612 
4613 static ssize_t
4614 il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
4615 {
4616 	struct il_priv *il = dev_get_drvdata(d);
4617 
4618 	if (!il_is_ready_rf(il))
4619 		return sprintf(buf, "off\n");
4620 	else
4621 		return sprintf(buf, "%d\n", il->tx_power_user_lmt);
4622 }
4623 
4624 static ssize_t
4625 il4965_store_tx_power(struct device *d, struct device_attribute *attr,
4626 		      const char *buf, size_t count)
4627 {
4628 	struct il_priv *il = dev_get_drvdata(d);
4629 	unsigned long val;
4630 	int ret;
4631 
4632 	ret = kstrtoul(buf, 10, &val);
4633 	if (ret)
4634 		IL_INFO("%s is not in decimal form.\n", buf);
4635 	else {
4636 		ret = il_set_tx_power(il, val, false);
4637 		if (ret)
4638 			IL_ERR("failed setting tx power (0x%08x).\n", ret);
4639 		else
4640 			ret = count;
4641 	}
4642 	return ret;
4643 }
4644 
4645 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il4965_show_tx_power,
4646 		   il4965_store_tx_power);
4647 
4648 static struct attribute *il_sysfs_entries[] = {
4649 	&dev_attr_temperature.attr,
4650 	&dev_attr_tx_power.attr,
4651 #ifdef CONFIG_IWLEGACY_DEBUG
4652 	&dev_attr_debug_level.attr,
4653 #endif
4654 	NULL
4655 };
4656 
4657 static struct attribute_group il_attribute_group = {
4658 	.name = NULL,		/* put in device directory */
4659 	.attrs = il_sysfs_entries,
4660 };
4661 
4662 /******************************************************************************
4663  *
4664  * uCode download functions
4665  *
4666  ******************************************************************************/
4667 
4668 static void
4669 il4965_dealloc_ucode_pci(struct il_priv *il)
4670 {
4671 	il_free_fw_desc(il->pci_dev, &il->ucode_code);
4672 	il_free_fw_desc(il->pci_dev, &il->ucode_data);
4673 	il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
4674 	il_free_fw_desc(il->pci_dev, &il->ucode_init);
4675 	il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
4676 	il_free_fw_desc(il->pci_dev, &il->ucode_boot);
4677 }
4678 
4679 static void
4680 il4965_nic_start(struct il_priv *il)
4681 {
4682 	/* Remove all resets to allow NIC to operate */
4683 	_il_wr(il, CSR_RESET, 0);
4684 }
4685 
4686 static void il4965_ucode_callback(const struct firmware *ucode_raw,
4687 				  void *context);
4688 static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length);
4689 
4690 static int __must_check
4691 il4965_request_firmware(struct il_priv *il, bool first)
4692 {
4693 	const char *name_pre = il->cfg->fw_name_pre;
4694 	char tag[8];
4695 
4696 	if (first) {
4697 		il->fw_idx = il->cfg->ucode_api_max;
4698 		sprintf(tag, "%d", il->fw_idx);
4699 	} else {
4700 		il->fw_idx--;
4701 		sprintf(tag, "%d", il->fw_idx);
4702 	}
4703 
4704 	if (il->fw_idx < il->cfg->ucode_api_min) {
4705 		IL_ERR("no suitable firmware found!\n");
4706 		return -ENOENT;
4707 	}
4708 
4709 	sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
4710 
4711 	D_INFO("attempting to load firmware '%s'\n", il->firmware_name);
4712 
4713 	return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name,
4714 				       &il->pci_dev->dev, GFP_KERNEL, il,
4715 				       il4965_ucode_callback);
4716 }
4717 
4718 struct il4965_firmware_pieces {
4719 	const void *inst, *data, *init, *init_data, *boot;
4720 	size_t inst_size, data_size, init_size, init_data_size, boot_size;
4721 };
4722 
4723 static int
4724 il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw,
4725 		     struct il4965_firmware_pieces *pieces)
4726 {
4727 	struct il_ucode_header *ucode = (void *)ucode_raw->data;
4728 	u32 api_ver, hdr_size;
4729 	const u8 *src;
4730 
4731 	il->ucode_ver = le32_to_cpu(ucode->ver);
4732 	api_ver = IL_UCODE_API(il->ucode_ver);
4733 
4734 	switch (api_ver) {
4735 	default:
4736 	case 0:
4737 	case 1:
4738 	case 2:
4739 		hdr_size = 24;
4740 		if (ucode_raw->size < hdr_size) {
4741 			IL_ERR("File size too small!\n");
4742 			return -EINVAL;
4743 		}
4744 		pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
4745 		pieces->data_size = le32_to_cpu(ucode->v1.data_size);
4746 		pieces->init_size = le32_to_cpu(ucode->v1.init_size);
4747 		pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size);
4748 		pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
4749 		src = ucode->v1.data;
4750 		break;
4751 	}
4752 
4753 	/* Verify size of file vs. image size info in file's header */
4754 	if (ucode_raw->size !=
4755 	    hdr_size + pieces->inst_size + pieces->data_size +
4756 	    pieces->init_size + pieces->init_data_size + pieces->boot_size) {
4757 
4758 		IL_ERR("uCode file size %d does not match expected size\n",
4759 		       (int)ucode_raw->size);
4760 		return -EINVAL;
4761 	}
4762 
4763 	pieces->inst = src;
4764 	src += pieces->inst_size;
4765 	pieces->data = src;
4766 	src += pieces->data_size;
4767 	pieces->init = src;
4768 	src += pieces->init_size;
4769 	pieces->init_data = src;
4770 	src += pieces->init_data_size;
4771 	pieces->boot = src;
4772 	src += pieces->boot_size;
4773 
4774 	return 0;
4775 }
4776 
4777 /**
4778  * il4965_ucode_callback - callback when firmware was loaded
4779  *
4780  * If loaded successfully, copies the firmware into buffers
4781  * for the card to fetch (via DMA).
4782  */
4783 static void
4784 il4965_ucode_callback(const struct firmware *ucode_raw, void *context)
4785 {
4786 	struct il_priv *il = context;
4787 	struct il_ucode_header *ucode;
4788 	int err;
4789 	struct il4965_firmware_pieces pieces;
4790 	const unsigned int api_max = il->cfg->ucode_api_max;
4791 	const unsigned int api_min = il->cfg->ucode_api_min;
4792 	u32 api_ver;
4793 
4794 	u32 max_probe_length = 200;
4795 	u32 standard_phy_calibration_size =
4796 	    IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
4797 
4798 	memset(&pieces, 0, sizeof(pieces));
4799 
4800 	if (!ucode_raw) {
4801 		if (il->fw_idx <= il->cfg->ucode_api_max)
4802 			IL_ERR("request for firmware file '%s' failed.\n",
4803 			       il->firmware_name);
4804 		goto try_again;
4805 	}
4806 
4807 	D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name,
4808 	       ucode_raw->size);
4809 
4810 	/* Make sure that we got at least the API version number */
4811 	if (ucode_raw->size < 4) {
4812 		IL_ERR("File size way too small!\n");
4813 		goto try_again;
4814 	}
4815 
4816 	/* Data from ucode file:  header followed by uCode images */
4817 	ucode = (struct il_ucode_header *)ucode_raw->data;
4818 
4819 	err = il4965_load_firmware(il, ucode_raw, &pieces);
4820 
4821 	if (err)
4822 		goto try_again;
4823 
4824 	api_ver = IL_UCODE_API(il->ucode_ver);
4825 
4826 	/*
4827 	 * api_ver should match the api version forming part of the
4828 	 * firmware filename ... but we don't check for that and only rely
4829 	 * on the API version read from firmware header from here on forward
4830 	 */
4831 	if (api_ver < api_min || api_ver > api_max) {
4832 		IL_ERR("Driver unable to support your firmware API. "
4833 		       "Driver supports v%u, firmware is v%u.\n", api_max,
4834 		       api_ver);
4835 		goto try_again;
4836 	}
4837 
4838 	if (api_ver != api_max)
4839 		IL_ERR("Firmware has old API version. Expected v%u, "
4840 		       "got v%u. New firmware can be obtained "
4841 		       "from http://www.intellinuxwireless.org.\n", api_max,
4842 		       api_ver);
4843 
4844 	IL_INFO("loaded firmware version %u.%u.%u.%u\n",
4845 		IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
4846 		IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
4847 
4848 	snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
4849 		 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
4850 		 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
4851 		 IL_UCODE_SERIAL(il->ucode_ver));
4852 
4853 	/*
4854 	 * For any of the failures below (before allocating pci memory)
4855 	 * we will try to load a version with a smaller API -- maybe the
4856 	 * user just got a corrupted version of the latest API.
4857 	 */
4858 
4859 	D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
4860 	D_INFO("f/w package hdr runtime inst size = %zd\n", pieces.inst_size);
4861 	D_INFO("f/w package hdr runtime data size = %zd\n", pieces.data_size);
4862 	D_INFO("f/w package hdr init inst size = %zd\n", pieces.init_size);
4863 	D_INFO("f/w package hdr init data size = %zd\n", pieces.init_data_size);
4864 	D_INFO("f/w package hdr boot inst size = %zd\n", pieces.boot_size);
4865 
4866 	/* Verify that uCode images will fit in card's SRAM */
4867 	if (pieces.inst_size > il->hw_params.max_inst_size) {
4868 		IL_ERR("uCode instr len %zd too large to fit in\n",
4869 		       pieces.inst_size);
4870 		goto try_again;
4871 	}
4872 
4873 	if (pieces.data_size > il->hw_params.max_data_size) {
4874 		IL_ERR("uCode data len %zd too large to fit in\n",
4875 		       pieces.data_size);
4876 		goto try_again;
4877 	}
4878 
4879 	if (pieces.init_size > il->hw_params.max_inst_size) {
4880 		IL_ERR("uCode init instr len %zd too large to fit in\n",
4881 		       pieces.init_size);
4882 		goto try_again;
4883 	}
4884 
4885 	if (pieces.init_data_size > il->hw_params.max_data_size) {
4886 		IL_ERR("uCode init data len %zd too large to fit in\n",
4887 		       pieces.init_data_size);
4888 		goto try_again;
4889 	}
4890 
4891 	if (pieces.boot_size > il->hw_params.max_bsm_size) {
4892 		IL_ERR("uCode boot instr len %zd too large to fit in\n",
4893 		       pieces.boot_size);
4894 		goto try_again;
4895 	}
4896 
4897 	/* Allocate ucode buffers for card's bus-master loading ... */
4898 
4899 	/* Runtime instructions and 2 copies of data:
4900 	 * 1) unmodified from disk
4901 	 * 2) backup cache for save/restore during power-downs */
4902 	il->ucode_code.len = pieces.inst_size;
4903 	il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
4904 
4905 	il->ucode_data.len = pieces.data_size;
4906 	il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
4907 
4908 	il->ucode_data_backup.len = pieces.data_size;
4909 	il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
4910 
4911 	if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
4912 	    !il->ucode_data_backup.v_addr)
4913 		goto err_pci_alloc;
4914 
4915 	/* Initialization instructions and data */
4916 	if (pieces.init_size && pieces.init_data_size) {
4917 		il->ucode_init.len = pieces.init_size;
4918 		il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
4919 
4920 		il->ucode_init_data.len = pieces.init_data_size;
4921 		il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
4922 
4923 		if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
4924 			goto err_pci_alloc;
4925 	}
4926 
4927 	/* Bootstrap (instructions only, no data) */
4928 	if (pieces.boot_size) {
4929 		il->ucode_boot.len = pieces.boot_size;
4930 		il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
4931 
4932 		if (!il->ucode_boot.v_addr)
4933 			goto err_pci_alloc;
4934 	}
4935 
4936 	/* Now that we can no longer fail, copy information */
4937 
4938 	il->sta_key_max_num = STA_KEY_MAX_NUM;
4939 
4940 	/* Copy images into buffers for card's bus-master reads ... */
4941 
4942 	/* Runtime instructions (first block of data in file) */
4943 	D_INFO("Copying (but not loading) uCode instr len %zd\n",
4944 	       pieces.inst_size);
4945 	memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
4946 
4947 	D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
4948 	       il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
4949 
4950 	/*
4951 	 * Runtime data
4952 	 * NOTE:  Copy into backup buffer will be done in il_up()
4953 	 */
4954 	D_INFO("Copying (but not loading) uCode data len %zd\n",
4955 	       pieces.data_size);
4956 	memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size);
4957 	memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
4958 
4959 	/* Initialization instructions */
4960 	if (pieces.init_size) {
4961 		D_INFO("Copying (but not loading) init instr len %zd\n",
4962 		       pieces.init_size);
4963 		memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size);
4964 	}
4965 
4966 	/* Initialization data */
4967 	if (pieces.init_data_size) {
4968 		D_INFO("Copying (but not loading) init data len %zd\n",
4969 		       pieces.init_data_size);
4970 		memcpy(il->ucode_init_data.v_addr, pieces.init_data,
4971 		       pieces.init_data_size);
4972 	}
4973 
4974 	/* Bootstrap instructions */
4975 	D_INFO("Copying (but not loading) boot instr len %zd\n",
4976 	       pieces.boot_size);
4977 	memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
4978 
4979 	/*
4980 	 * figure out the offset of chain noise reset and gain commands
4981 	 * base on the size of standard phy calibration commands table size
4982 	 */
4983 	il->_4965.phy_calib_chain_noise_reset_cmd =
4984 	    standard_phy_calibration_size;
4985 	il->_4965.phy_calib_chain_noise_gain_cmd =
4986 	    standard_phy_calibration_size + 1;
4987 
4988 	/**************************************************
4989 	 * This is still part of probe() in a sense...
4990 	 *
4991 	 * 9. Setup and register with mac80211 and debugfs
4992 	 **************************************************/
4993 	err = il4965_mac_setup_register(il, max_probe_length);
4994 	if (err)
4995 		goto out_unbind;
4996 
4997 	err = il_dbgfs_register(il, DRV_NAME);
4998 	if (err)
4999 		IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
5000 		       err);
5001 
5002 	err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group);
5003 	if (err) {
5004 		IL_ERR("failed to create sysfs device attributes\n");
5005 		goto out_unbind;
5006 	}
5007 
5008 	/* We have our copies now, allow OS release its copies */
5009 	release_firmware(ucode_raw);
5010 	complete(&il->_4965.firmware_loading_complete);
5011 	return;
5012 
5013 try_again:
5014 	/* try next, if any */
5015 	if (il4965_request_firmware(il, false))
5016 		goto out_unbind;
5017 	release_firmware(ucode_raw);
5018 	return;
5019 
5020 err_pci_alloc:
5021 	IL_ERR("failed to allocate pci memory\n");
5022 	il4965_dealloc_ucode_pci(il);
5023 out_unbind:
5024 	complete(&il->_4965.firmware_loading_complete);
5025 	device_release_driver(&il->pci_dev->dev);
5026 	release_firmware(ucode_raw);
5027 }
5028 
5029 static const char *const desc_lookup_text[] = {
5030 	"OK",
5031 	"FAIL",
5032 	"BAD_PARAM",
5033 	"BAD_CHECKSUM",
5034 	"NMI_INTERRUPT_WDG",
5035 	"SYSASSERT",
5036 	"FATAL_ERROR",
5037 	"BAD_COMMAND",
5038 	"HW_ERROR_TUNE_LOCK",
5039 	"HW_ERROR_TEMPERATURE",
5040 	"ILLEGAL_CHAN_FREQ",
5041 	"VCC_NOT_STBL",
5042 	"FH49_ERROR",
5043 	"NMI_INTERRUPT_HOST",
5044 	"NMI_INTERRUPT_ACTION_PT",
5045 	"NMI_INTERRUPT_UNKNOWN",
5046 	"UCODE_VERSION_MISMATCH",
5047 	"HW_ERROR_ABS_LOCK",
5048 	"HW_ERROR_CAL_LOCK_FAIL",
5049 	"NMI_INTERRUPT_INST_ACTION_PT",
5050 	"NMI_INTERRUPT_DATA_ACTION_PT",
5051 	"NMI_TRM_HW_ER",
5052 	"NMI_INTERRUPT_TRM",
5053 	"NMI_INTERRUPT_BREAK_POINT",
5054 	"DEBUG_0",
5055 	"DEBUG_1",
5056 	"DEBUG_2",
5057 	"DEBUG_3",
5058 };
5059 
5060 static struct {
5061 	char *name;
5062 	u8 num;
5063 } advanced_lookup[] = {
5064 	{
5065 	"NMI_INTERRUPT_WDG", 0x34}, {
5066 	"SYSASSERT", 0x35}, {
5067 	"UCODE_VERSION_MISMATCH", 0x37}, {
5068 	"BAD_COMMAND", 0x38}, {
5069 	"NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, {
5070 	"FATAL_ERROR", 0x3D}, {
5071 	"NMI_TRM_HW_ERR", 0x46}, {
5072 	"NMI_INTERRUPT_TRM", 0x4C}, {
5073 	"NMI_INTERRUPT_BREAK_POINT", 0x54}, {
5074 	"NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, {
5075 	"NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, {
5076 	"NMI_INTERRUPT_HOST", 0x66}, {
5077 	"NMI_INTERRUPT_ACTION_PT", 0x7C}, {
5078 	"NMI_INTERRUPT_UNKNOWN", 0x84}, {
5079 	"NMI_INTERRUPT_INST_ACTION_PT", 0x86}, {
5080 "ADVANCED_SYSASSERT", 0},};
5081 
5082 static const char *
5083 il4965_desc_lookup(u32 num)
5084 {
5085 	int i;
5086 	int max = ARRAY_SIZE(desc_lookup_text);
5087 
5088 	if (num < max)
5089 		return desc_lookup_text[num];
5090 
5091 	max = ARRAY_SIZE(advanced_lookup) - 1;
5092 	for (i = 0; i < max; i++) {
5093 		if (advanced_lookup[i].num == num)
5094 			break;
5095 	}
5096 	return advanced_lookup[i].name;
5097 }
5098 
5099 #define ERROR_START_OFFSET  (1 * sizeof(u32))
5100 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
5101 
5102 void
5103 il4965_dump_nic_error_log(struct il_priv *il)
5104 {
5105 	u32 data2, line;
5106 	u32 desc, time, count, base, data1;
5107 	u32 blink1, blink2, ilink1, ilink2;
5108 	u32 pc, hcmd;
5109 
5110 	if (il->ucode_type == UCODE_INIT)
5111 		base = le32_to_cpu(il->card_alive_init.error_event_table_ptr);
5112 	else
5113 		base = le32_to_cpu(il->card_alive.error_event_table_ptr);
5114 
5115 	if (!il->ops->is_valid_rtc_data_addr(base)) {
5116 		IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n",
5117 		       base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT");
5118 		return;
5119 	}
5120 
5121 	count = il_read_targ_mem(il, base);
5122 
5123 	if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
5124 		IL_ERR("Start IWL Error Log Dump:\n");
5125 		IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
5126 	}
5127 
5128 	desc = il_read_targ_mem(il, base + 1 * sizeof(u32));
5129 	il->isr_stats.err_code = desc;
5130 	pc = il_read_targ_mem(il, base + 2 * sizeof(u32));
5131 	blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32));
5132 	blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32));
5133 	ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32));
5134 	ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32));
5135 	data1 = il_read_targ_mem(il, base + 7 * sizeof(u32));
5136 	data2 = il_read_targ_mem(il, base + 8 * sizeof(u32));
5137 	line = il_read_targ_mem(il, base + 9 * sizeof(u32));
5138 	time = il_read_targ_mem(il, base + 11 * sizeof(u32));
5139 	hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32));
5140 
5141 	IL_ERR("Desc                                  Time       "
5142 	       "data1      data2      line\n");
5143 	IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
5144 	       il4965_desc_lookup(desc), desc, time, data1, data2, line);
5145 	IL_ERR("pc      blink1  blink2  ilink1  ilink2  hcmd\n");
5146 	IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1,
5147 	       blink2, ilink1, ilink2, hcmd);
5148 }
5149 
5150 static void
5151 il4965_rf_kill_ct_config(struct il_priv *il)
5152 {
5153 	struct il_ct_kill_config cmd;
5154 	unsigned long flags;
5155 	int ret = 0;
5156 
5157 	spin_lock_irqsave(&il->lock, flags);
5158 	_il_wr(il, CSR_UCODE_DRV_GP1_CLR,
5159 	       CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
5160 	spin_unlock_irqrestore(&il->lock, flags);
5161 
5162 	cmd.critical_temperature_R =
5163 	    cpu_to_le32(il->hw_params.ct_kill_threshold);
5164 
5165 	ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd);
5166 	if (ret)
5167 		IL_ERR("C_CT_KILL_CONFIG failed\n");
5168 	else
5169 		D_INFO("C_CT_KILL_CONFIG " "succeeded, "
5170 		       "critical temperature is %d\n",
5171 		       il->hw_params.ct_kill_threshold);
5172 }
5173 
5174 static const s8 default_queue_to_tx_fifo[] = {
5175 	IL_TX_FIFO_VO,
5176 	IL_TX_FIFO_VI,
5177 	IL_TX_FIFO_BE,
5178 	IL_TX_FIFO_BK,
5179 	IL49_CMD_FIFO_NUM,
5180 	IL_TX_FIFO_UNUSED,
5181 	IL_TX_FIFO_UNUSED,
5182 };
5183 
5184 #define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
5185 
5186 static int
5187 il4965_alive_notify(struct il_priv *il)
5188 {
5189 	u32 a;
5190 	unsigned long flags;
5191 	int i, chan;
5192 	u32 reg_val;
5193 
5194 	spin_lock_irqsave(&il->lock, flags);
5195 
5196 	/* Clear 4965's internal Tx Scheduler data base */
5197 	il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR);
5198 	a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET;
5199 	for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
5200 		il_write_targ_mem(il, a, 0);
5201 	for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
5202 		il_write_targ_mem(il, a, 0);
5203 	for (;
5204 	     a <
5205 	     il->scd_base_addr +
5206 	     IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num);
5207 	     a += 4)
5208 		il_write_targ_mem(il, a, 0);
5209 
5210 	/* Tel 4965 where to find Tx byte count tables */
5211 	il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10);
5212 
5213 	/* Enable DMA channel */
5214 	for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++)
5215 		il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan),
5216 		      FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
5217 		      FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
5218 
5219 	/* Update FH chicken bits */
5220 	reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG);
5221 	il_wr(il, FH49_TX_CHICKEN_BITS_REG,
5222 	      reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
5223 
5224 	/* Disable chain mode for all queues */
5225 	il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
5226 
5227 	/* Initialize each Tx queue (including the command queue) */
5228 	for (i = 0; i < il->hw_params.max_txq_num; i++) {
5229 
5230 		/* TFD circular buffer read/write idxes */
5231 		il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0);
5232 		il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
5233 
5234 		/* Max Tx Window size for Scheduler-ACK mode */
5235 		il_write_targ_mem(il,
5236 				  il->scd_base_addr +
5237 				  IL49_SCD_CONTEXT_QUEUE_OFFSET(i),
5238 				  (SCD_WIN_SIZE <<
5239 				   IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
5240 				  IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
5241 
5242 		/* Frame limit */
5243 		il_write_targ_mem(il,
5244 				  il->scd_base_addr +
5245 				  IL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
5246 				  sizeof(u32),
5247 				  (SCD_FRAME_LIMIT <<
5248 				   IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
5249 				  IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
5250 
5251 	}
5252 	il_wr_prph(il, IL49_SCD_INTERRUPT_MASK,
5253 		   (1 << il->hw_params.max_txq_num) - 1);
5254 
5255 	/* Activate all Tx DMA/FIFO channels */
5256 	il4965_txq_set_sched(il, IL_MASK(0, 6));
5257 
5258 	il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0);
5259 
5260 	/* make sure all queue are not stopped */
5261 	memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped));
5262 	for (i = 0; i < 4; i++)
5263 		atomic_set(&il->queue_stop_count[i], 0);
5264 
5265 	/* reset to 0 to enable all the queue first */
5266 	il->txq_ctx_active_msk = 0;
5267 	/* Map each Tx/cmd queue to its corresponding fifo */
5268 	BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
5269 
5270 	for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
5271 		int ac = default_queue_to_tx_fifo[i];
5272 
5273 		il_txq_ctx_activate(il, i);
5274 
5275 		if (ac == IL_TX_FIFO_UNUSED)
5276 			continue;
5277 
5278 		il4965_tx_queue_set_status(il, &il->txq[i], ac, 0);
5279 	}
5280 
5281 	spin_unlock_irqrestore(&il->lock, flags);
5282 
5283 	return 0;
5284 }
5285 
5286 /**
5287  * il4965_alive_start - called after N_ALIVE notification received
5288  *                   from protocol/runtime uCode (initialization uCode's
5289  *                   Alive gets handled by il_init_alive_start()).
5290  */
5291 static void
5292 il4965_alive_start(struct il_priv *il)
5293 {
5294 	int ret = 0;
5295 
5296 	D_INFO("Runtime Alive received.\n");
5297 
5298 	if (il->card_alive.is_valid != UCODE_VALID_OK) {
5299 		/* We had an error bringing up the hardware, so take it
5300 		 * all the way back down so we can try again */
5301 		D_INFO("Alive failed.\n");
5302 		goto restart;
5303 	}
5304 
5305 	/* Initialize uCode has loaded Runtime uCode ... verify inst image.
5306 	 * This is a paranoid check, because we would not have gotten the
5307 	 * "runtime" alive if code weren't properly loaded.  */
5308 	if (il4965_verify_ucode(il)) {
5309 		/* Runtime instruction load was bad;
5310 		 * take it all the way back down so we can try again */
5311 		D_INFO("Bad runtime uCode load.\n");
5312 		goto restart;
5313 	}
5314 
5315 	ret = il4965_alive_notify(il);
5316 	if (ret) {
5317 		IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret);
5318 		goto restart;
5319 	}
5320 
5321 	/* After the ALIVE response, we can send host commands to the uCode */
5322 	set_bit(S_ALIVE, &il->status);
5323 
5324 	/* Enable watchdog to monitor the driver tx queues */
5325 	il_setup_watchdog(il);
5326 
5327 	if (il_is_rfkill(il))
5328 		return;
5329 
5330 	ieee80211_wake_queues(il->hw);
5331 
5332 	il->active_rate = RATES_MASK;
5333 
5334 	il_power_update_mode(il, true);
5335 	D_INFO("Updated power mode\n");
5336 
5337 	if (il_is_associated(il)) {
5338 		struct il_rxon_cmd *active_rxon =
5339 		    (struct il_rxon_cmd *)&il->active;
5340 		/* apply any changes in staging */
5341 		il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
5342 		active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5343 	} else {
5344 		/* Initialize our rx_config data */
5345 		il_connection_init_rx_config(il);
5346 
5347 		if (il->ops->set_rxon_chain)
5348 			il->ops->set_rxon_chain(il);
5349 	}
5350 
5351 	/* Configure bluetooth coexistence if enabled */
5352 	il_send_bt_config(il);
5353 
5354 	il4965_reset_run_time_calib(il);
5355 
5356 	set_bit(S_READY, &il->status);
5357 
5358 	/* Configure the adapter for unassociated operation */
5359 	il_commit_rxon(il);
5360 
5361 	/* At this point, the NIC is initialized and operational */
5362 	il4965_rf_kill_ct_config(il);
5363 
5364 	D_INFO("ALIVE processing complete.\n");
5365 	wake_up(&il->wait_command_queue);
5366 
5367 	return;
5368 
5369 restart:
5370 	queue_work(il->workqueue, &il->restart);
5371 }
5372 
5373 static void il4965_cancel_deferred_work(struct il_priv *il);
5374 
5375 static void
5376 __il4965_down(struct il_priv *il)
5377 {
5378 	unsigned long flags;
5379 	int exit_pending;
5380 
5381 	D_INFO(DRV_NAME " is going down\n");
5382 
5383 	il_scan_cancel_timeout(il, 200);
5384 
5385 	exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
5386 
5387 	/* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
5388 	 * to prevent rearm timer */
5389 	del_timer_sync(&il->watchdog);
5390 
5391 	il_clear_ucode_stations(il);
5392 
5393 	/* FIXME: race conditions ? */
5394 	spin_lock_irq(&il->sta_lock);
5395 	/*
5396 	 * Remove all key information that is not stored as part
5397 	 * of station information since mac80211 may not have had
5398 	 * a chance to remove all the keys. When device is
5399 	 * reconfigured by mac80211 after an error all keys will
5400 	 * be reconfigured.
5401 	 */
5402 	memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys));
5403 	il->_4965.key_mapping_keys = 0;
5404 	spin_unlock_irq(&il->sta_lock);
5405 
5406 	il_dealloc_bcast_stations(il);
5407 	il_clear_driver_stations(il);
5408 
5409 	/* Unblock any waiting calls */
5410 	wake_up_all(&il->wait_command_queue);
5411 
5412 	/* Wipe out the EXIT_PENDING status bit if we are not actually
5413 	 * exiting the module */
5414 	if (!exit_pending)
5415 		clear_bit(S_EXIT_PENDING, &il->status);
5416 
5417 	/* stop and reset the on-board processor */
5418 	_il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
5419 
5420 	/* tell the device to stop sending interrupts */
5421 	spin_lock_irqsave(&il->lock, flags);
5422 	il_disable_interrupts(il);
5423 	spin_unlock_irqrestore(&il->lock, flags);
5424 	il4965_synchronize_irq(il);
5425 
5426 	if (il->mac80211_registered)
5427 		ieee80211_stop_queues(il->hw);
5428 
5429 	/* If we have not previously called il_init() then
5430 	 * clear all bits but the RF Kill bit and return */
5431 	if (!il_is_init(il)) {
5432 		il->status =
5433 		    test_bit(S_RFKILL, &il->status) << S_RFKILL |
5434 		    test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
5435 		    test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
5436 		goto exit;
5437 	}
5438 
5439 	/* ...otherwise clear out all the status bits but the RF Kill
5440 	 * bit and continue taking the NIC down. */
5441 	il->status &=
5442 	    test_bit(S_RFKILL, &il->status) << S_RFKILL |
5443 	    test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
5444 	    test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
5445 	    test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
5446 
5447 	/*
5448 	 * We disabled and synchronized interrupt, and priv->mutex is taken, so
5449 	 * here is the only thread which will program device registers, but
5450 	 * still have lockdep assertions, so we are taking reg_lock.
5451 	 */
5452 	spin_lock_irq(&il->reg_lock);
5453 	/* FIXME: il_grab_nic_access if rfkill is off ? */
5454 
5455 	il4965_txq_ctx_stop(il);
5456 	il4965_rxq_stop(il);
5457 	/* Power-down device's busmaster DMA clocks */
5458 	_il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
5459 	udelay(5);
5460 	/* Make sure (redundant) we've released our request to stay awake */
5461 	_il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
5462 	/* Stop the device, and put it in low power state */
5463 	_il_apm_stop(il);
5464 
5465 	spin_unlock_irq(&il->reg_lock);
5466 
5467 	il4965_txq_ctx_unmap(il);
5468 exit:
5469 	memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
5470 
5471 	dev_kfree_skb(il->beacon_skb);
5472 	il->beacon_skb = NULL;
5473 
5474 	/* clear out any free frames */
5475 	il4965_clear_free_frames(il);
5476 }
5477 
5478 static void
5479 il4965_down(struct il_priv *il)
5480 {
5481 	mutex_lock(&il->mutex);
5482 	__il4965_down(il);
5483 	mutex_unlock(&il->mutex);
5484 
5485 	il4965_cancel_deferred_work(il);
5486 }
5487 
5488 
5489 static void
5490 il4965_set_hw_ready(struct il_priv *il)
5491 {
5492 	int ret;
5493 
5494 	il_set_bit(il, CSR_HW_IF_CONFIG_REG,
5495 		   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
5496 
5497 	/* See if we got it */
5498 	ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5499 			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5500 			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5501 			   100);
5502 	if (ret >= 0)
5503 		il->hw_ready = true;
5504 
5505 	D_INFO("hardware %s ready\n", (il->hw_ready) ? "" : "not");
5506 }
5507 
5508 static void
5509 il4965_prepare_card_hw(struct il_priv *il)
5510 {
5511 	int ret;
5512 
5513 	il->hw_ready = false;
5514 
5515 	il4965_set_hw_ready(il);
5516 	if (il->hw_ready)
5517 		return;
5518 
5519 	/* If HW is not ready, prepare the conditions to check again */
5520 	il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE);
5521 
5522 	ret =
5523 	    _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5524 			 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
5525 			 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
5526 
5527 	/* HW should be ready by now, check again. */
5528 	if (ret != -ETIMEDOUT)
5529 		il4965_set_hw_ready(il);
5530 }
5531 
5532 #define MAX_HW_RESTARTS 5
5533 
5534 static int
5535 __il4965_up(struct il_priv *il)
5536 {
5537 	int i;
5538 	int ret;
5539 
5540 	if (test_bit(S_EXIT_PENDING, &il->status)) {
5541 		IL_WARN("Exit pending; will not bring the NIC up\n");
5542 		return -EIO;
5543 	}
5544 
5545 	if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
5546 		IL_ERR("ucode not available for device bringup\n");
5547 		return -EIO;
5548 	}
5549 
5550 	ret = il4965_alloc_bcast_station(il);
5551 	if (ret) {
5552 		il_dealloc_bcast_stations(il);
5553 		return ret;
5554 	}
5555 
5556 	il4965_prepare_card_hw(il);
5557 	if (!il->hw_ready) {
5558 		il_dealloc_bcast_stations(il);
5559 		IL_ERR("HW not ready\n");
5560 		return -EIO;
5561 	}
5562 
5563 	/* If platform's RF_KILL switch is NOT set to KILL */
5564 	if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5565 		clear_bit(S_RFKILL, &il->status);
5566 	else {
5567 		set_bit(S_RFKILL, &il->status);
5568 		wiphy_rfkill_set_hw_state(il->hw->wiphy, true);
5569 
5570 		il_dealloc_bcast_stations(il);
5571 		il_enable_rfkill_int(il);
5572 		IL_WARN("Radio disabled by HW RF Kill switch\n");
5573 		return 0;
5574 	}
5575 
5576 	_il_wr(il, CSR_INT, 0xFFFFFFFF);
5577 
5578 	/* must be initialised before il_hw_nic_init */
5579 	il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM;
5580 
5581 	ret = il4965_hw_nic_init(il);
5582 	if (ret) {
5583 		IL_ERR("Unable to init nic\n");
5584 		il_dealloc_bcast_stations(il);
5585 		return ret;
5586 	}
5587 
5588 	/* make sure rfkill handshake bits are cleared */
5589 	_il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5590 	_il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5591 
5592 	/* clear (again), then enable host interrupts */
5593 	_il_wr(il, CSR_INT, 0xFFFFFFFF);
5594 	il_enable_interrupts(il);
5595 
5596 	/* really make sure rfkill handshake bits are cleared */
5597 	_il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5598 	_il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5599 
5600 	/* Copy original ucode data image from disk into backup cache.
5601 	 * This will be used to initialize the on-board processor's
5602 	 * data SRAM for a clean start when the runtime program first loads. */
5603 	memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
5604 	       il->ucode_data.len);
5605 
5606 	for (i = 0; i < MAX_HW_RESTARTS; i++) {
5607 
5608 		/* load bootstrap state machine,
5609 		 * load bootstrap program into processor's memory,
5610 		 * prepare to load the "initialize" uCode */
5611 		ret = il->ops->load_ucode(il);
5612 
5613 		if (ret) {
5614 			IL_ERR("Unable to set up bootstrap uCode: %d\n", ret);
5615 			continue;
5616 		}
5617 
5618 		/* start card; "initialize" will load runtime ucode */
5619 		il4965_nic_start(il);
5620 
5621 		D_INFO(DRV_NAME " is coming up\n");
5622 
5623 		return 0;
5624 	}
5625 
5626 	set_bit(S_EXIT_PENDING, &il->status);
5627 	__il4965_down(il);
5628 	clear_bit(S_EXIT_PENDING, &il->status);
5629 
5630 	/* tried to restart and config the device for as long as our
5631 	 * patience could withstand */
5632 	IL_ERR("Unable to initialize device after %d attempts.\n", i);
5633 	return -EIO;
5634 }
5635 
5636 /*****************************************************************************
5637  *
5638  * Workqueue callbacks
5639  *
5640  *****************************************************************************/
5641 
5642 static void
5643 il4965_bg_init_alive_start(struct work_struct *data)
5644 {
5645 	struct il_priv *il =
5646 	    container_of(data, struct il_priv, init_alive_start.work);
5647 
5648 	mutex_lock(&il->mutex);
5649 	if (test_bit(S_EXIT_PENDING, &il->status))
5650 		goto out;
5651 
5652 	il->ops->init_alive_start(il);
5653 out:
5654 	mutex_unlock(&il->mutex);
5655 }
5656 
5657 static void
5658 il4965_bg_alive_start(struct work_struct *data)
5659 {
5660 	struct il_priv *il =
5661 	    container_of(data, struct il_priv, alive_start.work);
5662 
5663 	mutex_lock(&il->mutex);
5664 	if (test_bit(S_EXIT_PENDING, &il->status))
5665 		goto out;
5666 
5667 	il4965_alive_start(il);
5668 out:
5669 	mutex_unlock(&il->mutex);
5670 }
5671 
5672 static void
5673 il4965_bg_run_time_calib_work(struct work_struct *work)
5674 {
5675 	struct il_priv *il = container_of(work, struct il_priv,
5676 					  run_time_calib_work);
5677 
5678 	mutex_lock(&il->mutex);
5679 
5680 	if (test_bit(S_EXIT_PENDING, &il->status) ||
5681 	    test_bit(S_SCANNING, &il->status)) {
5682 		mutex_unlock(&il->mutex);
5683 		return;
5684 	}
5685 
5686 	if (il->start_calib) {
5687 		il4965_chain_noise_calibration(il, (void *)&il->_4965.stats);
5688 		il4965_sensitivity_calibration(il, (void *)&il->_4965.stats);
5689 	}
5690 
5691 	mutex_unlock(&il->mutex);
5692 }
5693 
5694 static void
5695 il4965_bg_restart(struct work_struct *data)
5696 {
5697 	struct il_priv *il = container_of(data, struct il_priv, restart);
5698 
5699 	if (test_bit(S_EXIT_PENDING, &il->status))
5700 		return;
5701 
5702 	if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
5703 		mutex_lock(&il->mutex);
5704 		il->is_open = 0;
5705 
5706 		__il4965_down(il);
5707 
5708 		mutex_unlock(&il->mutex);
5709 		il4965_cancel_deferred_work(il);
5710 		ieee80211_restart_hw(il->hw);
5711 	} else {
5712 		il4965_down(il);
5713 
5714 		mutex_lock(&il->mutex);
5715 		if (test_bit(S_EXIT_PENDING, &il->status)) {
5716 			mutex_unlock(&il->mutex);
5717 			return;
5718 		}
5719 
5720 		__il4965_up(il);
5721 		mutex_unlock(&il->mutex);
5722 	}
5723 }
5724 
5725 static void
5726 il4965_bg_rx_replenish(struct work_struct *data)
5727 {
5728 	struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
5729 
5730 	if (test_bit(S_EXIT_PENDING, &il->status))
5731 		return;
5732 
5733 	mutex_lock(&il->mutex);
5734 	il4965_rx_replenish(il);
5735 	mutex_unlock(&il->mutex);
5736 }
5737 
5738 /*****************************************************************************
5739  *
5740  * mac80211 entry point functions
5741  *
5742  *****************************************************************************/
5743 
5744 #define UCODE_READY_TIMEOUT	(4 * HZ)
5745 
5746 /*
5747  * Not a mac80211 entry point function, but it fits in with all the
5748  * other mac80211 functions grouped here.
5749  */
5750 static int
5751 il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length)
5752 {
5753 	int ret;
5754 	struct ieee80211_hw *hw = il->hw;
5755 
5756 	hw->rate_control_algorithm = "iwl-4965-rs";
5757 
5758 	/* Tell mac80211 our characteristics */
5759 	ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
5760 	ieee80211_hw_set(hw, SUPPORTS_PS);
5761 	ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
5762 	ieee80211_hw_set(hw, SPECTRUM_MGMT);
5763 	ieee80211_hw_set(hw, NEED_DTIM_BEFORE_ASSOC);
5764 	ieee80211_hw_set(hw, SIGNAL_DBM);
5765 	ieee80211_hw_set(hw, AMPDU_AGGREGATION);
5766 	if (il->cfg->sku & IL_SKU_N)
5767 		hw->wiphy->features |= NL80211_FEATURE_DYNAMIC_SMPS |
5768 				       NL80211_FEATURE_STATIC_SMPS;
5769 
5770 	hw->sta_data_size = sizeof(struct il_station_priv);
5771 	hw->vif_data_size = sizeof(struct il_vif_priv);
5772 
5773 	hw->wiphy->interface_modes =
5774 	    BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
5775 
5776 	hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5777 	hw->wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG |
5778 				       REGULATORY_DISABLE_BEACON_HINTS;
5779 
5780 	/*
5781 	 * For now, disable PS by default because it affects
5782 	 * RX performance significantly.
5783 	 */
5784 	hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5785 
5786 	hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
5787 	/* we create the 802.11 header and a zero-length SSID element */
5788 	hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
5789 
5790 	/* Default value; 4 EDCA QOS priorities */
5791 	hw->queues = 4;
5792 
5793 	hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL;
5794 
5795 	if (il->bands[NL80211_BAND_2GHZ].n_channels)
5796 		il->hw->wiphy->bands[NL80211_BAND_2GHZ] =
5797 		    &il->bands[NL80211_BAND_2GHZ];
5798 	if (il->bands[NL80211_BAND_5GHZ].n_channels)
5799 		il->hw->wiphy->bands[NL80211_BAND_5GHZ] =
5800 		    &il->bands[NL80211_BAND_5GHZ];
5801 
5802 	il_leds_init(il);
5803 
5804 	wiphy_ext_feature_set(il->hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
5805 
5806 	ret = ieee80211_register_hw(il->hw);
5807 	if (ret) {
5808 		IL_ERR("Failed to register hw (error %d)\n", ret);
5809 		return ret;
5810 	}
5811 	il->mac80211_registered = 1;
5812 
5813 	return 0;
5814 }
5815 
5816 int
5817 il4965_mac_start(struct ieee80211_hw *hw)
5818 {
5819 	struct il_priv *il = hw->priv;
5820 	int ret;
5821 
5822 	D_MAC80211("enter\n");
5823 
5824 	/* we should be verifying the device is ready to be opened */
5825 	mutex_lock(&il->mutex);
5826 	ret = __il4965_up(il);
5827 	mutex_unlock(&il->mutex);
5828 
5829 	if (ret)
5830 		return ret;
5831 
5832 	if (il_is_rfkill(il))
5833 		goto out;
5834 
5835 	D_INFO("Start UP work done.\n");
5836 
5837 	/* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5838 	 * mac80211 will not be run successfully. */
5839 	ret = wait_event_timeout(il->wait_command_queue,
5840 				 test_bit(S_READY, &il->status),
5841 				 UCODE_READY_TIMEOUT);
5842 	if (!ret) {
5843 		if (!test_bit(S_READY, &il->status)) {
5844 			IL_ERR("START_ALIVE timeout after %dms.\n",
5845 				jiffies_to_msecs(UCODE_READY_TIMEOUT));
5846 			return -ETIMEDOUT;
5847 		}
5848 	}
5849 
5850 	il4965_led_enable(il);
5851 
5852 out:
5853 	il->is_open = 1;
5854 	D_MAC80211("leave\n");
5855 	return 0;
5856 }
5857 
5858 void
5859 il4965_mac_stop(struct ieee80211_hw *hw)
5860 {
5861 	struct il_priv *il = hw->priv;
5862 
5863 	D_MAC80211("enter\n");
5864 
5865 	if (!il->is_open)
5866 		return;
5867 
5868 	il->is_open = 0;
5869 
5870 	il4965_down(il);
5871 
5872 	flush_workqueue(il->workqueue);
5873 
5874 	/* User space software may expect getting rfkill changes
5875 	 * even if interface is down */
5876 	_il_wr(il, CSR_INT, 0xFFFFFFFF);
5877 	il_enable_rfkill_int(il);
5878 
5879 	D_MAC80211("leave\n");
5880 }
5881 
5882 void
5883 il4965_mac_tx(struct ieee80211_hw *hw,
5884 	      struct ieee80211_tx_control *control,
5885 	      struct sk_buff *skb)
5886 {
5887 	struct il_priv *il = hw->priv;
5888 
5889 	D_MACDUMP("enter\n");
5890 
5891 	D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
5892 	     ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
5893 
5894 	if (il4965_tx_skb(il, control->sta, skb))
5895 		dev_kfree_skb_any(skb);
5896 
5897 	D_MACDUMP("leave\n");
5898 }
5899 
5900 void
5901 il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5902 			   struct ieee80211_key_conf *keyconf,
5903 			   struct ieee80211_sta *sta, u32 iv32, u16 * phase1key)
5904 {
5905 	struct il_priv *il = hw->priv;
5906 
5907 	D_MAC80211("enter\n");
5908 
5909 	il4965_update_tkip_key(il, keyconf, sta, iv32, phase1key);
5910 
5911 	D_MAC80211("leave\n");
5912 }
5913 
5914 int
5915 il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5916 		   struct ieee80211_vif *vif, struct ieee80211_sta *sta,
5917 		   struct ieee80211_key_conf *key)
5918 {
5919 	struct il_priv *il = hw->priv;
5920 	int ret;
5921 	u8 sta_id;
5922 	bool is_default_wep_key = false;
5923 
5924 	D_MAC80211("enter\n");
5925 
5926 	if (il->cfg->mod_params->sw_crypto) {
5927 		D_MAC80211("leave - hwcrypto disabled\n");
5928 		return -EOPNOTSUPP;
5929 	}
5930 
5931 	/*
5932 	 * To support IBSS RSN, don't program group keys in IBSS, the
5933 	 * hardware will then not attempt to decrypt the frames.
5934 	 */
5935 	if (vif->type == NL80211_IFTYPE_ADHOC &&
5936 	    !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
5937 		D_MAC80211("leave - ad-hoc group key\n");
5938 		return -EOPNOTSUPP;
5939 	}
5940 
5941 	sta_id = il_sta_id_or_broadcast(il, sta);
5942 	if (sta_id == IL_INVALID_STATION)
5943 		return -EINVAL;
5944 
5945 	mutex_lock(&il->mutex);
5946 	il_scan_cancel_timeout(il, 100);
5947 
5948 	/*
5949 	 * If we are getting WEP group key and we didn't receive any key mapping
5950 	 * so far, we are in legacy wep mode (group key only), otherwise we are
5951 	 * in 1X mode.
5952 	 * In legacy wep mode, we use another host command to the uCode.
5953 	 */
5954 	if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
5955 	     key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) {
5956 		if (cmd == SET_KEY)
5957 			is_default_wep_key = !il->_4965.key_mapping_keys;
5958 		else
5959 			is_default_wep_key =
5960 			    (key->hw_key_idx == HW_KEY_DEFAULT);
5961 	}
5962 
5963 	switch (cmd) {
5964 	case SET_KEY:
5965 		if (is_default_wep_key)
5966 			ret = il4965_set_default_wep_key(il, key);
5967 		else
5968 			ret = il4965_set_dynamic_key(il, key, sta_id);
5969 
5970 		D_MAC80211("enable hwcrypto key\n");
5971 		break;
5972 	case DISABLE_KEY:
5973 		if (is_default_wep_key)
5974 			ret = il4965_remove_default_wep_key(il, key);
5975 		else
5976 			ret = il4965_remove_dynamic_key(il, key, sta_id);
5977 
5978 		D_MAC80211("disable hwcrypto key\n");
5979 		break;
5980 	default:
5981 		ret = -EINVAL;
5982 	}
5983 
5984 	mutex_unlock(&il->mutex);
5985 	D_MAC80211("leave\n");
5986 
5987 	return ret;
5988 }
5989 
5990 int
5991 il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5992 			struct ieee80211_ampdu_params *params)
5993 {
5994 	struct il_priv *il = hw->priv;
5995 	int ret = -EINVAL;
5996 	struct ieee80211_sta *sta = params->sta;
5997 	enum ieee80211_ampdu_mlme_action action = params->action;
5998 	u16 tid = params->tid;
5999 	u16 *ssn = &params->ssn;
6000 
6001 	D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid);
6002 
6003 	if (!(il->cfg->sku & IL_SKU_N))
6004 		return -EACCES;
6005 
6006 	mutex_lock(&il->mutex);
6007 
6008 	switch (action) {
6009 	case IEEE80211_AMPDU_RX_START:
6010 		D_HT("start Rx\n");
6011 		ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn);
6012 		break;
6013 	case IEEE80211_AMPDU_RX_STOP:
6014 		D_HT("stop Rx\n");
6015 		ret = il4965_sta_rx_agg_stop(il, sta, tid);
6016 		if (test_bit(S_EXIT_PENDING, &il->status))
6017 			ret = 0;
6018 		break;
6019 	case IEEE80211_AMPDU_TX_START:
6020 		D_HT("start Tx\n");
6021 		ret = il4965_tx_agg_start(il, vif, sta, tid, ssn);
6022 		break;
6023 	case IEEE80211_AMPDU_TX_STOP_CONT:
6024 	case IEEE80211_AMPDU_TX_STOP_FLUSH:
6025 	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6026 		D_HT("stop Tx\n");
6027 		ret = il4965_tx_agg_stop(il, vif, sta, tid);
6028 		if (test_bit(S_EXIT_PENDING, &il->status))
6029 			ret = 0;
6030 		break;
6031 	case IEEE80211_AMPDU_TX_OPERATIONAL:
6032 		ret = 0;
6033 		break;
6034 	}
6035 	mutex_unlock(&il->mutex);
6036 
6037 	return ret;
6038 }
6039 
6040 int
6041 il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6042 		   struct ieee80211_sta *sta)
6043 {
6044 	struct il_priv *il = hw->priv;
6045 	struct il_station_priv *sta_priv = (void *)sta->drv_priv;
6046 	bool is_ap = vif->type == NL80211_IFTYPE_STATION;
6047 	int ret;
6048 	u8 sta_id;
6049 
6050 	D_INFO("received request to add station %pM\n", sta->addr);
6051 	mutex_lock(&il->mutex);
6052 	D_INFO("proceeding to add station %pM\n", sta->addr);
6053 	sta_priv->common.sta_id = IL_INVALID_STATION;
6054 
6055 	atomic_set(&sta_priv->pending_frames, 0);
6056 
6057 	ret =
6058 	    il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
6059 	if (ret) {
6060 		IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
6061 		/* Should we return success if return code is EEXIST ? */
6062 		mutex_unlock(&il->mutex);
6063 		return ret;
6064 	}
6065 
6066 	sta_priv->common.sta_id = sta_id;
6067 
6068 	/* Initialize rate scaling */
6069 	D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
6070 	il4965_rs_rate_init(il, sta, sta_id);
6071 	mutex_unlock(&il->mutex);
6072 
6073 	return 0;
6074 }
6075 
6076 void
6077 il4965_mac_channel_switch(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6078 			  struct ieee80211_channel_switch *ch_switch)
6079 {
6080 	struct il_priv *il = hw->priv;
6081 	const struct il_channel_info *ch_info;
6082 	struct ieee80211_conf *conf = &hw->conf;
6083 	struct ieee80211_channel *channel = ch_switch->chandef.chan;
6084 	struct il_ht_config *ht_conf = &il->current_ht_config;
6085 	u16 ch;
6086 
6087 	D_MAC80211("enter\n");
6088 
6089 	mutex_lock(&il->mutex);
6090 
6091 	if (il_is_rfkill(il))
6092 		goto out;
6093 
6094 	if (test_bit(S_EXIT_PENDING, &il->status) ||
6095 	    test_bit(S_SCANNING, &il->status) ||
6096 	    test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
6097 		goto out;
6098 
6099 	if (!il_is_associated(il))
6100 		goto out;
6101 
6102 	if (!il->ops->set_channel_switch)
6103 		goto out;
6104 
6105 	ch = channel->hw_value;
6106 	if (le16_to_cpu(il->active.channel) == ch)
6107 		goto out;
6108 
6109 	ch_info = il_get_channel_info(il, channel->band, ch);
6110 	if (!il_is_channel_valid(ch_info)) {
6111 		D_MAC80211("invalid channel\n");
6112 		goto out;
6113 	}
6114 
6115 	spin_lock_irq(&il->lock);
6116 
6117 	il->current_ht_config.smps = conf->smps_mode;
6118 
6119 	/* Configure HT40 channels */
6120 	switch (cfg80211_get_chandef_type(&ch_switch->chandef)) {
6121 	case NL80211_CHAN_NO_HT:
6122 	case NL80211_CHAN_HT20:
6123 		il->ht.is_40mhz = false;
6124 		il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_NONE;
6125 		break;
6126 	case NL80211_CHAN_HT40MINUS:
6127 		il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_BELOW;
6128 		il->ht.is_40mhz = true;
6129 		break;
6130 	case NL80211_CHAN_HT40PLUS:
6131 		il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
6132 		il->ht.is_40mhz = true;
6133 		break;
6134 	}
6135 
6136 	if ((le16_to_cpu(il->staging.channel) != ch))
6137 		il->staging.flags = 0;
6138 
6139 	il_set_rxon_channel(il, channel);
6140 	il_set_rxon_ht(il, ht_conf);
6141 	il_set_flags_for_band(il, channel->band, il->vif);
6142 
6143 	spin_unlock_irq(&il->lock);
6144 
6145 	il_set_rate(il);
6146 	/*
6147 	 * at this point, staging_rxon has the
6148 	 * configuration for channel switch
6149 	 */
6150 	set_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
6151 	il->switch_channel = cpu_to_le16(ch);
6152 	if (il->ops->set_channel_switch(il, ch_switch)) {
6153 		clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
6154 		il->switch_channel = 0;
6155 		ieee80211_chswitch_done(il->vif, false);
6156 	}
6157 
6158 out:
6159 	mutex_unlock(&il->mutex);
6160 	D_MAC80211("leave\n");
6161 }
6162 
6163 void
6164 il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
6165 			unsigned int *total_flags, u64 multicast)
6166 {
6167 	struct il_priv *il = hw->priv;
6168 	__le32 filter_or = 0, filter_nand = 0;
6169 
6170 #define CHK(test, flag)	do { \
6171 	if (*total_flags & (test))		\
6172 		filter_or |= (flag);		\
6173 	else					\
6174 		filter_nand |= (flag);		\
6175 	} while (0)
6176 
6177 	D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
6178 		   *total_flags);
6179 
6180 	CHK(FIF_OTHER_BSS, RXON_FILTER_PROMISC_MSK);
6181 	/* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
6182 	CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
6183 	CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
6184 
6185 #undef CHK
6186 
6187 	mutex_lock(&il->mutex);
6188 
6189 	il->staging.filter_flags &= ~filter_nand;
6190 	il->staging.filter_flags |= filter_or;
6191 
6192 	/*
6193 	 * Not committing directly because hardware can perform a scan,
6194 	 * but we'll eventually commit the filter flags change anyway.
6195 	 */
6196 
6197 	mutex_unlock(&il->mutex);
6198 
6199 	/*
6200 	 * Receiving all multicast frames is always enabled by the
6201 	 * default flags setup in il_connection_init_rx_config()
6202 	 * since we currently do not support programming multicast
6203 	 * filters into the device.
6204 	 */
6205 	*total_flags &=
6206 	    FIF_OTHER_BSS | FIF_ALLMULTI |
6207 	    FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
6208 }
6209 
6210 /*****************************************************************************
6211  *
6212  * driver setup and teardown
6213  *
6214  *****************************************************************************/
6215 
6216 static void
6217 il4965_bg_txpower_work(struct work_struct *work)
6218 {
6219 	struct il_priv *il = container_of(work, struct il_priv,
6220 					  txpower_work);
6221 
6222 	mutex_lock(&il->mutex);
6223 
6224 	/* If a scan happened to start before we got here
6225 	 * then just return; the stats notification will
6226 	 * kick off another scheduled work to compensate for
6227 	 * any temperature delta we missed here. */
6228 	if (test_bit(S_EXIT_PENDING, &il->status) ||
6229 	    test_bit(S_SCANNING, &il->status))
6230 		goto out;
6231 
6232 	/* Regardless of if we are associated, we must reconfigure the
6233 	 * TX power since frames can be sent on non-radar channels while
6234 	 * not associated */
6235 	il->ops->send_tx_power(il);
6236 
6237 	/* Update last_temperature to keep is_calib_needed from running
6238 	 * when it isn't needed... */
6239 	il->last_temperature = il->temperature;
6240 out:
6241 	mutex_unlock(&il->mutex);
6242 }
6243 
6244 static void
6245 il4965_setup_deferred_work(struct il_priv *il)
6246 {
6247 	il->workqueue = create_singlethread_workqueue(DRV_NAME);
6248 
6249 	init_waitqueue_head(&il->wait_command_queue);
6250 
6251 	INIT_WORK(&il->restart, il4965_bg_restart);
6252 	INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish);
6253 	INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work);
6254 	INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start);
6255 	INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start);
6256 
6257 	il_setup_scan_deferred_work(il);
6258 
6259 	INIT_WORK(&il->txpower_work, il4965_bg_txpower_work);
6260 
6261 	setup_timer(&il->stats_periodic, il4965_bg_stats_periodic,
6262 		    (unsigned long)il);
6263 
6264 	setup_timer(&il->watchdog, il_bg_watchdog, (unsigned long)il);
6265 
6266 	tasklet_init(&il->irq_tasklet,
6267 		     (void (*)(unsigned long))il4965_irq_tasklet,
6268 		     (unsigned long)il);
6269 }
6270 
6271 static void
6272 il4965_cancel_deferred_work(struct il_priv *il)
6273 {
6274 	cancel_work_sync(&il->txpower_work);
6275 	cancel_delayed_work_sync(&il->init_alive_start);
6276 	cancel_delayed_work(&il->alive_start);
6277 	cancel_work_sync(&il->run_time_calib_work);
6278 
6279 	il_cancel_scan_deferred_work(il);
6280 
6281 	del_timer_sync(&il->stats_periodic);
6282 }
6283 
6284 static void
6285 il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
6286 {
6287 	int i;
6288 
6289 	for (i = 0; i < RATE_COUNT_LEGACY; i++) {
6290 		rates[i].bitrate = il_rates[i].ieee * 5;
6291 		rates[i].hw_value = i;	/* Rate scaling will work on idxes */
6292 		rates[i].hw_value_short = i;
6293 		rates[i].flags = 0;
6294 		if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) {
6295 			/*
6296 			 * If CCK != 1M then set short preamble rate flag.
6297 			 */
6298 			rates[i].flags |=
6299 			    (il_rates[i].plcp ==
6300 			     RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
6301 		}
6302 	}
6303 }
6304 
6305 /*
6306  * Acquire il->lock before calling this function !
6307  */
6308 void
6309 il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
6310 {
6311 	il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));
6312 	il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
6313 }
6314 
6315 void
6316 il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
6317 			   int tx_fifo_id, int scd_retry)
6318 {
6319 	int txq_id = txq->q.id;
6320 
6321 	/* Find out whether to activate Tx queue */
6322 	int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
6323 
6324 	/* Set up and activate */
6325 	il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
6326 		   (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
6327 		   (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) |
6328 		   (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) |
6329 		   (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
6330 		   IL49_SCD_QUEUE_STTS_REG_MSK);
6331 
6332 	txq->sched_retry = scd_retry;
6333 
6334 	D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate",
6335 	       scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
6336 }
6337 
6338 static const struct ieee80211_ops il4965_mac_ops = {
6339 	.tx = il4965_mac_tx,
6340 	.start = il4965_mac_start,
6341 	.stop = il4965_mac_stop,
6342 	.add_interface = il_mac_add_interface,
6343 	.remove_interface = il_mac_remove_interface,
6344 	.change_interface = il_mac_change_interface,
6345 	.config = il_mac_config,
6346 	.configure_filter = il4965_configure_filter,
6347 	.set_key = il4965_mac_set_key,
6348 	.update_tkip_key = il4965_mac_update_tkip_key,
6349 	.conf_tx = il_mac_conf_tx,
6350 	.reset_tsf = il_mac_reset_tsf,
6351 	.bss_info_changed = il_mac_bss_info_changed,
6352 	.ampdu_action = il4965_mac_ampdu_action,
6353 	.hw_scan = il_mac_hw_scan,
6354 	.sta_add = il4965_mac_sta_add,
6355 	.sta_remove = il_mac_sta_remove,
6356 	.channel_switch = il4965_mac_channel_switch,
6357 	.tx_last_beacon = il_mac_tx_last_beacon,
6358 	.flush = il_mac_flush,
6359 };
6360 
6361 static int
6362 il4965_init_drv(struct il_priv *il)
6363 {
6364 	int ret;
6365 
6366 	spin_lock_init(&il->sta_lock);
6367 	spin_lock_init(&il->hcmd_lock);
6368 
6369 	INIT_LIST_HEAD(&il->free_frames);
6370 
6371 	mutex_init(&il->mutex);
6372 
6373 	il->ieee_channels = NULL;
6374 	il->ieee_rates = NULL;
6375 	il->band = NL80211_BAND_2GHZ;
6376 
6377 	il->iw_mode = NL80211_IFTYPE_STATION;
6378 	il->current_ht_config.smps = IEEE80211_SMPS_STATIC;
6379 	il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
6380 
6381 	/* initialize force reset */
6382 	il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
6383 
6384 	/* Choose which receivers/antennas to use */
6385 	if (il->ops->set_rxon_chain)
6386 		il->ops->set_rxon_chain(il);
6387 
6388 	il_init_scan_params(il);
6389 
6390 	ret = il_init_channel_map(il);
6391 	if (ret) {
6392 		IL_ERR("initializing regulatory failed: %d\n", ret);
6393 		goto err;
6394 	}
6395 
6396 	ret = il_init_geos(il);
6397 	if (ret) {
6398 		IL_ERR("initializing geos failed: %d\n", ret);
6399 		goto err_free_channel_map;
6400 	}
6401 	il4965_init_hw_rates(il, il->ieee_rates);
6402 
6403 	return 0;
6404 
6405 err_free_channel_map:
6406 	il_free_channel_map(il);
6407 err:
6408 	return ret;
6409 }
6410 
6411 static void
6412 il4965_uninit_drv(struct il_priv *il)
6413 {
6414 	il_free_geos(il);
6415 	il_free_channel_map(il);
6416 	kfree(il->scan_cmd);
6417 }
6418 
6419 static void
6420 il4965_hw_detect(struct il_priv *il)
6421 {
6422 	il->hw_rev = _il_rd(il, CSR_HW_REV);
6423 	il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
6424 	il->rev_id = il->pci_dev->revision;
6425 	D_INFO("HW Revision ID = 0x%X\n", il->rev_id);
6426 }
6427 
6428 static const struct il_sensitivity_ranges il4965_sensitivity = {
6429 	.min_nrg_cck = 97,
6430 	.max_nrg_cck = 0,	/* not used, set to 0 */
6431 
6432 	.auto_corr_min_ofdm = 85,
6433 	.auto_corr_min_ofdm_mrc = 170,
6434 	.auto_corr_min_ofdm_x1 = 105,
6435 	.auto_corr_min_ofdm_mrc_x1 = 220,
6436 
6437 	.auto_corr_max_ofdm = 120,
6438 	.auto_corr_max_ofdm_mrc = 210,
6439 	.auto_corr_max_ofdm_x1 = 140,
6440 	.auto_corr_max_ofdm_mrc_x1 = 270,
6441 
6442 	.auto_corr_min_cck = 125,
6443 	.auto_corr_max_cck = 200,
6444 	.auto_corr_min_cck_mrc = 200,
6445 	.auto_corr_max_cck_mrc = 400,
6446 
6447 	.nrg_th_cck = 100,
6448 	.nrg_th_ofdm = 100,
6449 
6450 	.barker_corr_th_min = 190,
6451 	.barker_corr_th_min_mrc = 390,
6452 	.nrg_th_cca = 62,
6453 };
6454 
6455 static void
6456 il4965_set_hw_params(struct il_priv *il)
6457 {
6458 	il->hw_params.bcast_id = IL4965_BROADCAST_ID;
6459 	il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
6460 	il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
6461 	if (il->cfg->mod_params->amsdu_size_8K)
6462 		il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K);
6463 	else
6464 		il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K);
6465 
6466 	il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL;
6467 
6468 	if (il->cfg->mod_params->disable_11n)
6469 		il->cfg->sku &= ~IL_SKU_N;
6470 
6471 	if (il->cfg->mod_params->num_of_queues >= IL_MIN_NUM_QUEUES &&
6472 	    il->cfg->mod_params->num_of_queues <= IL49_NUM_QUEUES)
6473 		il->cfg->num_of_queues =
6474 		    il->cfg->mod_params->num_of_queues;
6475 
6476 	il->hw_params.max_txq_num = il->cfg->num_of_queues;
6477 	il->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
6478 	il->hw_params.scd_bc_tbls_size =
6479 	    il->cfg->num_of_queues *
6480 	    sizeof(struct il4965_scd_bc_tbl);
6481 
6482 	il->hw_params.tfd_size = sizeof(struct il_tfd);
6483 	il->hw_params.max_stations = IL4965_STATION_COUNT;
6484 	il->hw_params.max_data_size = IL49_RTC_DATA_SIZE;
6485 	il->hw_params.max_inst_size = IL49_RTC_INST_SIZE;
6486 	il->hw_params.max_bsm_size = BSM_SRAM_SIZE;
6487 	il->hw_params.ht40_channel = BIT(NL80211_BAND_5GHZ);
6488 
6489 	il->hw_params.rx_wrt_ptr_reg = FH49_RSCSR_CHNL0_WPTR;
6490 
6491 	il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant);
6492 	il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant);
6493 	il->hw_params.valid_tx_ant = il->cfg->valid_tx_ant;
6494 	il->hw_params.valid_rx_ant = il->cfg->valid_rx_ant;
6495 
6496 	il->hw_params.ct_kill_threshold =
6497 	   CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
6498 
6499 	il->hw_params.sens = &il4965_sensitivity;
6500 	il->hw_params.beacon_time_tsf_bits = IL4965_EXT_BEACON_TIME_POS;
6501 }
6502 
6503 static int
6504 il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
6505 {
6506 	int err = 0;
6507 	struct il_priv *il;
6508 	struct ieee80211_hw *hw;
6509 	struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
6510 	unsigned long flags;
6511 	u16 pci_cmd;
6512 
6513 	/************************
6514 	 * 1. Allocating HW data
6515 	 ************************/
6516 
6517 	hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il4965_mac_ops);
6518 	if (!hw) {
6519 		err = -ENOMEM;
6520 		goto out;
6521 	}
6522 	il = hw->priv;
6523 	il->hw = hw;
6524 	SET_IEEE80211_DEV(hw, &pdev->dev);
6525 
6526 	D_INFO("*** LOAD DRIVER ***\n");
6527 	il->cfg = cfg;
6528 	il->ops = &il4965_ops;
6529 #ifdef CONFIG_IWLEGACY_DEBUGFS
6530 	il->debugfs_ops = &il4965_debugfs_ops;
6531 #endif
6532 	il->pci_dev = pdev;
6533 	il->inta_mask = CSR_INI_SET_MASK;
6534 
6535 	/**************************
6536 	 * 2. Initializing PCI bus
6537 	 **************************/
6538 	pci_disable_link_state(pdev,
6539 			       PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6540 			       PCIE_LINK_STATE_CLKPM);
6541 
6542 	if (pci_enable_device(pdev)) {
6543 		err = -ENODEV;
6544 		goto out_ieee80211_free_hw;
6545 	}
6546 
6547 	pci_set_master(pdev);
6548 
6549 	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
6550 	if (!err)
6551 		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
6552 	if (err) {
6553 		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6554 		if (!err)
6555 			err =
6556 			    pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6557 		/* both attempts failed: */
6558 		if (err) {
6559 			IL_WARN("No suitable DMA available.\n");
6560 			goto out_pci_disable_device;
6561 		}
6562 	}
6563 
6564 	err = pci_request_regions(pdev, DRV_NAME);
6565 	if (err)
6566 		goto out_pci_disable_device;
6567 
6568 	pci_set_drvdata(pdev, il);
6569 
6570 	/***********************
6571 	 * 3. Read REV register
6572 	 ***********************/
6573 	il->hw_base = pci_ioremap_bar(pdev, 0);
6574 	if (!il->hw_base) {
6575 		err = -ENODEV;
6576 		goto out_pci_release_regions;
6577 	}
6578 
6579 	D_INFO("pci_resource_len = 0x%08llx\n",
6580 	       (unsigned long long)pci_resource_len(pdev, 0));
6581 	D_INFO("pci_resource_base = %p\n", il->hw_base);
6582 
6583 	/* these spin locks will be used in apm_ops.init and EEPROM access
6584 	 * we should init now
6585 	 */
6586 	spin_lock_init(&il->reg_lock);
6587 	spin_lock_init(&il->lock);
6588 
6589 	/*
6590 	 * stop and reset the on-board processor just in case it is in a
6591 	 * strange state ... like being left stranded by a primary kernel
6592 	 * and this is now the kdump kernel trying to start up
6593 	 */
6594 	_il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
6595 
6596 	il4965_hw_detect(il);
6597 	IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev);
6598 
6599 	/* We disable the RETRY_TIMEOUT register (0x41) to keep
6600 	 * PCI Tx retries from interfering with C3 CPU state */
6601 	pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
6602 
6603 	il4965_prepare_card_hw(il);
6604 	if (!il->hw_ready) {
6605 		IL_WARN("Failed, HW not ready\n");
6606 		err = -EIO;
6607 		goto out_iounmap;
6608 	}
6609 
6610 	/*****************
6611 	 * 4. Read EEPROM
6612 	 *****************/
6613 	/* Read the EEPROM */
6614 	err = il_eeprom_init(il);
6615 	if (err) {
6616 		IL_ERR("Unable to init EEPROM\n");
6617 		goto out_iounmap;
6618 	}
6619 	err = il4965_eeprom_check_version(il);
6620 	if (err)
6621 		goto out_free_eeprom;
6622 
6623 	/* extract MAC Address */
6624 	il4965_eeprom_get_mac(il, il->addresses[0].addr);
6625 	D_INFO("MAC address: %pM\n", il->addresses[0].addr);
6626 	il->hw->wiphy->addresses = il->addresses;
6627 	il->hw->wiphy->n_addresses = 1;
6628 
6629 	/************************
6630 	 * 5. Setup HW constants
6631 	 ************************/
6632 	il4965_set_hw_params(il);
6633 
6634 	/*******************
6635 	 * 6. Setup il
6636 	 *******************/
6637 
6638 	err = il4965_init_drv(il);
6639 	if (err)
6640 		goto out_free_eeprom;
6641 	/* At this point both hw and il are initialized. */
6642 
6643 	/********************
6644 	 * 7. Setup services
6645 	 ********************/
6646 	spin_lock_irqsave(&il->lock, flags);
6647 	il_disable_interrupts(il);
6648 	spin_unlock_irqrestore(&il->lock, flags);
6649 
6650 	pci_enable_msi(il->pci_dev);
6651 
6652 	err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
6653 	if (err) {
6654 		IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
6655 		goto out_disable_msi;
6656 	}
6657 
6658 	il4965_setup_deferred_work(il);
6659 	il4965_setup_handlers(il);
6660 
6661 	/*********************************************
6662 	 * 8. Enable interrupts and read RFKILL state
6663 	 *********************************************/
6664 
6665 	/* enable rfkill interrupt: hw bug w/a */
6666 	pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd);
6667 	if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
6668 		pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
6669 		pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd);
6670 	}
6671 
6672 	il_enable_rfkill_int(il);
6673 
6674 	/* If platform's RF_KILL switch is NOT set to KILL */
6675 	if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6676 		clear_bit(S_RFKILL, &il->status);
6677 	else
6678 		set_bit(S_RFKILL, &il->status);
6679 
6680 	wiphy_rfkill_set_hw_state(il->hw->wiphy,
6681 				  test_bit(S_RFKILL, &il->status));
6682 
6683 	il_power_initialize(il);
6684 
6685 	init_completion(&il->_4965.firmware_loading_complete);
6686 
6687 	err = il4965_request_firmware(il, true);
6688 	if (err)
6689 		goto out_destroy_workqueue;
6690 
6691 	return 0;
6692 
6693 out_destroy_workqueue:
6694 	destroy_workqueue(il->workqueue);
6695 	il->workqueue = NULL;
6696 	free_irq(il->pci_dev->irq, il);
6697 out_disable_msi:
6698 	pci_disable_msi(il->pci_dev);
6699 	il4965_uninit_drv(il);
6700 out_free_eeprom:
6701 	il_eeprom_free(il);
6702 out_iounmap:
6703 	iounmap(il->hw_base);
6704 out_pci_release_regions:
6705 	pci_release_regions(pdev);
6706 out_pci_disable_device:
6707 	pci_disable_device(pdev);
6708 out_ieee80211_free_hw:
6709 	ieee80211_free_hw(il->hw);
6710 out:
6711 	return err;
6712 }
6713 
6714 static void
6715 il4965_pci_remove(struct pci_dev *pdev)
6716 {
6717 	struct il_priv *il = pci_get_drvdata(pdev);
6718 	unsigned long flags;
6719 
6720 	if (!il)
6721 		return;
6722 
6723 	wait_for_completion(&il->_4965.firmware_loading_complete);
6724 
6725 	D_INFO("*** UNLOAD DRIVER ***\n");
6726 
6727 	il_dbgfs_unregister(il);
6728 	sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group);
6729 
6730 	/* ieee80211_unregister_hw call wil cause il_mac_stop to
6731 	 * to be called and il4965_down since we are removing the device
6732 	 * we need to set S_EXIT_PENDING bit.
6733 	 */
6734 	set_bit(S_EXIT_PENDING, &il->status);
6735 
6736 	il_leds_exit(il);
6737 
6738 	if (il->mac80211_registered) {
6739 		ieee80211_unregister_hw(il->hw);
6740 		il->mac80211_registered = 0;
6741 	} else {
6742 		il4965_down(il);
6743 	}
6744 
6745 	/*
6746 	 * Make sure device is reset to low power before unloading driver.
6747 	 * This may be redundant with il4965_down(), but there are paths to
6748 	 * run il4965_down() without calling apm_ops.stop(), and there are
6749 	 * paths to avoid running il4965_down() at all before leaving driver.
6750 	 * This (inexpensive) call *makes sure* device is reset.
6751 	 */
6752 	il_apm_stop(il);
6753 
6754 	/* make sure we flush any pending irq or
6755 	 * tasklet for the driver
6756 	 */
6757 	spin_lock_irqsave(&il->lock, flags);
6758 	il_disable_interrupts(il);
6759 	spin_unlock_irqrestore(&il->lock, flags);
6760 
6761 	il4965_synchronize_irq(il);
6762 
6763 	il4965_dealloc_ucode_pci(il);
6764 
6765 	if (il->rxq.bd)
6766 		il4965_rx_queue_free(il, &il->rxq);
6767 	il4965_hw_txq_ctx_free(il);
6768 
6769 	il_eeprom_free(il);
6770 
6771 	/*netif_stop_queue(dev); */
6772 	flush_workqueue(il->workqueue);
6773 
6774 	/* ieee80211_unregister_hw calls il_mac_stop, which flushes
6775 	 * il->workqueue... so we can't take down the workqueue
6776 	 * until now... */
6777 	destroy_workqueue(il->workqueue);
6778 	il->workqueue = NULL;
6779 
6780 	free_irq(il->pci_dev->irq, il);
6781 	pci_disable_msi(il->pci_dev);
6782 	iounmap(il->hw_base);
6783 	pci_release_regions(pdev);
6784 	pci_disable_device(pdev);
6785 
6786 	il4965_uninit_drv(il);
6787 
6788 	dev_kfree_skb(il->beacon_skb);
6789 
6790 	ieee80211_free_hw(il->hw);
6791 }
6792 
6793 /*
6794  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
6795  * must be called under il->lock and mac access
6796  */
6797 void
6798 il4965_txq_set_sched(struct il_priv *il, u32 mask)
6799 {
6800 	il_wr_prph(il, IL49_SCD_TXFACT, mask);
6801 }
6802 
6803 /*****************************************************************************
6804  *
6805  * driver and module entry point
6806  *
6807  *****************************************************************************/
6808 
6809 /* Hardware specific file defines the PCI IDs table for that hardware module */
6810 static const struct pci_device_id il4965_hw_card_ids[] = {
6811 	{IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
6812 	{IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
6813 	{0}
6814 };
6815 MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids);
6816 
6817 static struct pci_driver il4965_driver = {
6818 	.name = DRV_NAME,
6819 	.id_table = il4965_hw_card_ids,
6820 	.probe = il4965_pci_probe,
6821 	.remove = il4965_pci_remove,
6822 	.driver.pm = IL_LEGACY_PM_OPS,
6823 };
6824 
6825 static int __init
6826 il4965_init(void)
6827 {
6828 
6829 	int ret;
6830 	pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
6831 	pr_info(DRV_COPYRIGHT "\n");
6832 
6833 	ret = il4965_rate_control_register();
6834 	if (ret) {
6835 		pr_err("Unable to register rate control algorithm: %d\n", ret);
6836 		return ret;
6837 	}
6838 
6839 	ret = pci_register_driver(&il4965_driver);
6840 	if (ret) {
6841 		pr_err("Unable to initialize PCI module\n");
6842 		goto error_register;
6843 	}
6844 
6845 	return ret;
6846 
6847 error_register:
6848 	il4965_rate_control_unregister();
6849 	return ret;
6850 }
6851 
6852 static void __exit
6853 il4965_exit(void)
6854 {
6855 	pci_unregister_driver(&il4965_driver);
6856 	il4965_rate_control_unregister();
6857 }
6858 
6859 module_exit(il4965_exit);
6860 module_init(il4965_init);
6861 
6862 #ifdef CONFIG_IWLEGACY_DEBUG
6863 module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
6864 MODULE_PARM_DESC(debug, "debug output mask");
6865 #endif
6866 
6867 module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO);
6868 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
6869 module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO);
6870 MODULE_PARM_DESC(queues_num, "number of hw queues.");
6871 module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO);
6872 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
6873 module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int,
6874 		   S_IRUGO);
6875 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size (default 0 [disabled])");
6876 module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO);
6877 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
6878