1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  *  Intel Linux Wireless <ilw@linux.intel.com>
23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24  *
25  *****************************************************************************/
26 
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/slab.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/sched.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39 #include <net/mac80211.h>
40 
41 #include "common.h"
42 #include "3945.h"
43 
44 /* Send led command */
45 static int
46 il3945_send_led_cmd(struct il_priv *il, struct il_led_cmd *led_cmd)
47 {
48 	struct il_host_cmd cmd = {
49 		.id = C_LEDS,
50 		.len = sizeof(struct il_led_cmd),
51 		.data = led_cmd,
52 		.flags = CMD_ASYNC,
53 		.callback = NULL,
54 	};
55 
56 	return il_send_cmd(il, &cmd);
57 }
58 
59 #define IL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
60 	[RATE_##r##M_IDX] = { RATE_##r##M_PLCP,   \
61 				    RATE_##r##M_IEEE,   \
62 				    RATE_##ip##M_IDX, \
63 				    RATE_##in##M_IDX, \
64 				    RATE_##rp##M_IDX, \
65 				    RATE_##rn##M_IDX, \
66 				    RATE_##pp##M_IDX, \
67 				    RATE_##np##M_IDX, \
68 				    RATE_##r##M_IDX_TBL, \
69 				    RATE_##ip##M_IDX_TBL }
70 
71 /*
72  * Parameter order:
73  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
74  *
75  * If there isn't a valid next or previous rate then INV is used which
76  * maps to RATE_INVALID
77  *
78  */
79 const struct il3945_rate_info il3945_rates[RATE_COUNT_3945] = {
80 	IL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),	/*  1mbps */
81 	IL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),	/*  2mbps */
82 	IL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),	/*5.5mbps */
83 	IL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),	/* 11mbps */
84 	IL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),	/*  6mbps */
85 	IL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),	/*  9mbps */
86 	IL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),	/* 12mbps */
87 	IL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),	/* 18mbps */
88 	IL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),	/* 24mbps */
89 	IL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),	/* 36mbps */
90 	IL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),	/* 48mbps */
91 	IL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),	/* 54mbps */
92 };
93 
94 static inline u8
95 il3945_get_prev_ieee_rate(u8 rate_idx)
96 {
97 	u8 rate = il3945_rates[rate_idx].prev_ieee;
98 
99 	if (rate == RATE_INVALID)
100 		rate = rate_idx;
101 	return rate;
102 }
103 
104 /* 1 = enable the il3945_disable_events() function */
105 #define IL_EVT_DISABLE (0)
106 #define IL_EVT_DISABLE_SIZE (1532/32)
107 
108 /**
109  * il3945_disable_events - Disable selected events in uCode event log
110  *
111  * Disable an event by writing "1"s into "disable"
112  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
113  *   Default values of 0 enable uCode events to be logged.
114  * Use for only special debugging.  This function is just a placeholder as-is,
115  *   you'll need to provide the special bits! ...
116  *   ... and set IL_EVT_DISABLE to 1. */
117 void
118 il3945_disable_events(struct il_priv *il)
119 {
120 	int i;
121 	u32 base;		/* SRAM address of event log header */
122 	u32 disable_ptr;	/* SRAM address of event-disable bitmap array */
123 	u32 array_size;		/* # of u32 entries in array */
124 	static const u32 evt_disable[IL_EVT_DISABLE_SIZE] = {
125 		0x00000000,	/*   31 -    0  Event id numbers */
126 		0x00000000,	/*   63 -   32 */
127 		0x00000000,	/*   95 -   64 */
128 		0x00000000,	/*  127 -   96 */
129 		0x00000000,	/*  159 -  128 */
130 		0x00000000,	/*  191 -  160 */
131 		0x00000000,	/*  223 -  192 */
132 		0x00000000,	/*  255 -  224 */
133 		0x00000000,	/*  287 -  256 */
134 		0x00000000,	/*  319 -  288 */
135 		0x00000000,	/*  351 -  320 */
136 		0x00000000,	/*  383 -  352 */
137 		0x00000000,	/*  415 -  384 */
138 		0x00000000,	/*  447 -  416 */
139 		0x00000000,	/*  479 -  448 */
140 		0x00000000,	/*  511 -  480 */
141 		0x00000000,	/*  543 -  512 */
142 		0x00000000,	/*  575 -  544 */
143 		0x00000000,	/*  607 -  576 */
144 		0x00000000,	/*  639 -  608 */
145 		0x00000000,	/*  671 -  640 */
146 		0x00000000,	/*  703 -  672 */
147 		0x00000000,	/*  735 -  704 */
148 		0x00000000,	/*  767 -  736 */
149 		0x00000000,	/*  799 -  768 */
150 		0x00000000,	/*  831 -  800 */
151 		0x00000000,	/*  863 -  832 */
152 		0x00000000,	/*  895 -  864 */
153 		0x00000000,	/*  927 -  896 */
154 		0x00000000,	/*  959 -  928 */
155 		0x00000000,	/*  991 -  960 */
156 		0x00000000,	/* 1023 -  992 */
157 		0x00000000,	/* 1055 - 1024 */
158 		0x00000000,	/* 1087 - 1056 */
159 		0x00000000,	/* 1119 - 1088 */
160 		0x00000000,	/* 1151 - 1120 */
161 		0x00000000,	/* 1183 - 1152 */
162 		0x00000000,	/* 1215 - 1184 */
163 		0x00000000,	/* 1247 - 1216 */
164 		0x00000000,	/* 1279 - 1248 */
165 		0x00000000,	/* 1311 - 1280 */
166 		0x00000000,	/* 1343 - 1312 */
167 		0x00000000,	/* 1375 - 1344 */
168 		0x00000000,	/* 1407 - 1376 */
169 		0x00000000,	/* 1439 - 1408 */
170 		0x00000000,	/* 1471 - 1440 */
171 		0x00000000,	/* 1503 - 1472 */
172 	};
173 
174 	base = le32_to_cpu(il->card_alive.log_event_table_ptr);
175 	if (!il3945_hw_valid_rtc_data_addr(base)) {
176 		IL_ERR("Invalid event log pointer 0x%08X\n", base);
177 		return;
178 	}
179 
180 	disable_ptr = il_read_targ_mem(il, base + (4 * sizeof(u32)));
181 	array_size = il_read_targ_mem(il, base + (5 * sizeof(u32)));
182 
183 	if (IL_EVT_DISABLE && array_size == IL_EVT_DISABLE_SIZE) {
184 		D_INFO("Disabling selected uCode log events at 0x%x\n",
185 		       disable_ptr);
186 		for (i = 0; i < IL_EVT_DISABLE_SIZE; i++)
187 			il_write_targ_mem(il, disable_ptr + (i * sizeof(u32)),
188 					  evt_disable[i]);
189 
190 	} else {
191 		D_INFO("Selected uCode log events may be disabled\n");
192 		D_INFO("  by writing \"1\"s into disable bitmap\n");
193 		D_INFO("  in SRAM at 0x%x, size %d u32s\n", disable_ptr,
194 		       array_size);
195 	}
196 
197 }
198 
199 static int
200 il3945_hwrate_to_plcp_idx(u8 plcp)
201 {
202 	int idx;
203 
204 	for (idx = 0; idx < RATE_COUNT_3945; idx++)
205 		if (il3945_rates[idx].plcp == plcp)
206 			return idx;
207 	return -1;
208 }
209 
210 #ifdef CONFIG_IWLEGACY_DEBUG
211 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
212 
213 static const char *
214 il3945_get_tx_fail_reason(u32 status)
215 {
216 	switch (status & TX_STATUS_MSK) {
217 	case TX_3945_STATUS_SUCCESS:
218 		return "SUCCESS";
219 		TX_STATUS_ENTRY(SHORT_LIMIT);
220 		TX_STATUS_ENTRY(LONG_LIMIT);
221 		TX_STATUS_ENTRY(FIFO_UNDERRUN);
222 		TX_STATUS_ENTRY(MGMNT_ABORT);
223 		TX_STATUS_ENTRY(NEXT_FRAG);
224 		TX_STATUS_ENTRY(LIFE_EXPIRE);
225 		TX_STATUS_ENTRY(DEST_PS);
226 		TX_STATUS_ENTRY(ABORTED);
227 		TX_STATUS_ENTRY(BT_RETRY);
228 		TX_STATUS_ENTRY(STA_INVALID);
229 		TX_STATUS_ENTRY(FRAG_DROPPED);
230 		TX_STATUS_ENTRY(TID_DISABLE);
231 		TX_STATUS_ENTRY(FRAME_FLUSHED);
232 		TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
233 		TX_STATUS_ENTRY(TX_LOCKED);
234 		TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
235 	}
236 
237 	return "UNKNOWN";
238 }
239 #else
240 static inline const char *
241 il3945_get_tx_fail_reason(u32 status)
242 {
243 	return "";
244 }
245 #endif
246 
247 /*
248  * get ieee prev rate from rate scale table.
249  * for A and B mode we need to overright prev
250  * value
251  */
252 int
253 il3945_rs_next_rate(struct il_priv *il, int rate)
254 {
255 	int next_rate = il3945_get_prev_ieee_rate(rate);
256 
257 	switch (il->band) {
258 	case NL80211_BAND_5GHZ:
259 		if (rate == RATE_12M_IDX)
260 			next_rate = RATE_9M_IDX;
261 		else if (rate == RATE_6M_IDX)
262 			next_rate = RATE_6M_IDX;
263 		break;
264 	case NL80211_BAND_2GHZ:
265 		if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
266 		    il_is_associated(il)) {
267 			if (rate == RATE_11M_IDX)
268 				next_rate = RATE_5M_IDX;
269 		}
270 		break;
271 
272 	default:
273 		break;
274 	}
275 
276 	return next_rate;
277 }
278 
279 /**
280  * il3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
281  *
282  * When FW advances 'R' idx, all entries between old and new 'R' idx
283  * need to be reclaimed. As result, some free space forms. If there is
284  * enough free space (> low mark), wake the stack that feeds us.
285  */
286 static void
287 il3945_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
288 {
289 	struct il_tx_queue *txq = &il->txq[txq_id];
290 	struct il_queue *q = &txq->q;
291 	struct sk_buff *skb;
292 
293 	BUG_ON(txq_id == IL39_CMD_QUEUE_NUM);
294 
295 	for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
296 	     q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
297 
298 		skb = txq->skbs[txq->q.read_ptr];
299 		ieee80211_tx_status_irqsafe(il->hw, skb);
300 		txq->skbs[txq->q.read_ptr] = NULL;
301 		il->ops->txq_free_tfd(il, txq);
302 	}
303 
304 	if (il_queue_space(q) > q->low_mark && txq_id >= 0 &&
305 	    txq_id != IL39_CMD_QUEUE_NUM && il->mac80211_registered)
306 		il_wake_queue(il, txq);
307 }
308 
309 /**
310  * il3945_hdl_tx - Handle Tx response
311  */
312 static void
313 il3945_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
314 {
315 	struct il_rx_pkt *pkt = rxb_addr(rxb);
316 	u16 sequence = le16_to_cpu(pkt->hdr.sequence);
317 	int txq_id = SEQ_TO_QUEUE(sequence);
318 	int idx = SEQ_TO_IDX(sequence);
319 	struct il_tx_queue *txq = &il->txq[txq_id];
320 	struct ieee80211_tx_info *info;
321 	struct il3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
322 	u32 status = le32_to_cpu(tx_resp->status);
323 	int rate_idx;
324 	int fail;
325 
326 	if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
327 		IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
328 		       "is out of range [0-%d] %d %d\n", txq_id, idx,
329 		       txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr);
330 		return;
331 	}
332 
333 	/*
334 	 * Firmware will not transmit frame on passive channel, if it not yet
335 	 * received some valid frame on that channel. When this error happen
336 	 * we have to wait until firmware will unblock itself i.e. when we
337 	 * note received beacon or other frame. We unblock queues in
338 	 * il3945_pass_packet_to_mac80211 or in il_mac_bss_info_changed.
339 	 */
340 	if (unlikely((status & TX_STATUS_MSK) == TX_STATUS_FAIL_PASSIVE_NO_RX) &&
341 	    il->iw_mode == NL80211_IFTYPE_STATION) {
342 		il_stop_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
343 		D_INFO("Stopped queues - RX waiting on passive channel\n");
344 	}
345 
346 	txq->time_stamp = jiffies;
347 	info = IEEE80211_SKB_CB(txq->skbs[txq->q.read_ptr]);
348 	ieee80211_tx_info_clear_status(info);
349 
350 	/* Fill the MRR chain with some info about on-chip retransmissions */
351 	rate_idx = il3945_hwrate_to_plcp_idx(tx_resp->rate);
352 	if (info->band == NL80211_BAND_5GHZ)
353 		rate_idx -= IL_FIRST_OFDM_RATE;
354 
355 	fail = tx_resp->failure_frame;
356 
357 	info->status.rates[0].idx = rate_idx;
358 	info->status.rates[0].count = fail + 1;	/* add final attempt */
359 
360 	/* tx_status->rts_retry_count = tx_resp->failure_rts; */
361 	info->flags |=
362 	    ((status & TX_STATUS_MSK) ==
363 	     TX_STATUS_SUCCESS) ? IEEE80211_TX_STAT_ACK : 0;
364 
365 	D_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n", txq_id,
366 	     il3945_get_tx_fail_reason(status), status, tx_resp->rate,
367 	     tx_resp->failure_frame);
368 
369 	D_TX_REPLY("Tx queue reclaim %d\n", idx);
370 	il3945_tx_queue_reclaim(il, txq_id, idx);
371 
372 	if (status & TX_ABORT_REQUIRED_MSK)
373 		IL_ERR("TODO:  Implement Tx ABORT REQUIRED!!!\n");
374 }
375 
376 /*****************************************************************************
377  *
378  * Intel PRO/Wireless 3945ABG/BG Network Connection
379  *
380  *  RX handler implementations
381  *
382  *****************************************************************************/
383 #ifdef CONFIG_IWLEGACY_DEBUGFS
384 static void
385 il3945_accumulative_stats(struct il_priv *il, __le32 * stats)
386 {
387 	int i;
388 	__le32 *prev_stats;
389 	u32 *accum_stats;
390 	u32 *delta, *max_delta;
391 
392 	prev_stats = (__le32 *) &il->_3945.stats;
393 	accum_stats = (u32 *) &il->_3945.accum_stats;
394 	delta = (u32 *) &il->_3945.delta_stats;
395 	max_delta = (u32 *) &il->_3945.max_delta;
396 
397 	for (i = sizeof(__le32); i < sizeof(struct il3945_notif_stats);
398 	     i +=
399 	     sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
400 	     accum_stats++) {
401 		if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
402 			*delta =
403 			    (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
404 			*accum_stats += *delta;
405 			if (*delta > *max_delta)
406 				*max_delta = *delta;
407 		}
408 	}
409 
410 	/* reset accumulative stats for "no-counter" type stats */
411 	il->_3945.accum_stats.general.temperature =
412 	    il->_3945.stats.general.temperature;
413 	il->_3945.accum_stats.general.ttl_timestamp =
414 	    il->_3945.stats.general.ttl_timestamp;
415 }
416 #endif
417 
418 void
419 il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
420 {
421 	struct il_rx_pkt *pkt = rxb_addr(rxb);
422 
423 	D_RX("Statistics notification received (%d vs %d).\n",
424 	     (int)sizeof(struct il3945_notif_stats),
425 	     le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
426 #ifdef CONFIG_IWLEGACY_DEBUGFS
427 	il3945_accumulative_stats(il, (__le32 *) &pkt->u.raw);
428 #endif
429 
430 	memcpy(&il->_3945.stats, pkt->u.raw, sizeof(il->_3945.stats));
431 }
432 
433 void
434 il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
435 {
436 	struct il_rx_pkt *pkt = rxb_addr(rxb);
437 	__le32 *flag = (__le32 *) &pkt->u.raw;
438 
439 	if (le32_to_cpu(*flag) & UCODE_STATS_CLEAR_MSK) {
440 #ifdef CONFIG_IWLEGACY_DEBUGFS
441 		memset(&il->_3945.accum_stats, 0,
442 		       sizeof(struct il3945_notif_stats));
443 		memset(&il->_3945.delta_stats, 0,
444 		       sizeof(struct il3945_notif_stats));
445 		memset(&il->_3945.max_delta, 0,
446 		       sizeof(struct il3945_notif_stats));
447 #endif
448 		D_RX("Statistics have been cleared\n");
449 	}
450 	il3945_hdl_stats(il, rxb);
451 }
452 
453 /******************************************************************************
454  *
455  * Misc. internal state and helper functions
456  *
457  ******************************************************************************/
458 
459 /* This is necessary only for a number of stats, see the caller. */
460 static int
461 il3945_is_network_packet(struct il_priv *il, struct ieee80211_hdr *header)
462 {
463 	/* Filter incoming packets to determine if they are targeted toward
464 	 * this network, discarding packets coming from ourselves */
465 	switch (il->iw_mode) {
466 	case NL80211_IFTYPE_ADHOC:	/* Header: Dest. | Source    | BSSID */
467 		/* packets to our IBSS update information */
468 		return ether_addr_equal_64bits(header->addr3, il->bssid);
469 	case NL80211_IFTYPE_STATION:	/* Header: Dest. | AP{BSSID} | Source */
470 		/* packets to our IBSS update information */
471 		return ether_addr_equal_64bits(header->addr2, il->bssid);
472 	default:
473 		return 1;
474 	}
475 }
476 
477 #define SMALL_PACKET_SIZE 256
478 
479 static void
480 il3945_pass_packet_to_mac80211(struct il_priv *il, struct il_rx_buf *rxb,
481 			       struct ieee80211_rx_status *stats)
482 {
483 	struct il_rx_pkt *pkt = rxb_addr(rxb);
484 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IL_RX_DATA(pkt);
485 	struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt);
486 	struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt);
487 	u32 len = le16_to_cpu(rx_hdr->len);
488 	struct sk_buff *skb;
489 	__le16 fc = hdr->frame_control;
490 	u32 fraglen = PAGE_SIZE << il->hw_params.rx_page_order;
491 
492 	/* We received data from the HW, so stop the watchdog */
493 	if (unlikely(len + IL39_RX_FRAME_SIZE > fraglen)) {
494 		D_DROP("Corruption detected!\n");
495 		return;
496 	}
497 
498 	/* We only process data packets if the interface is open */
499 	if (unlikely(!il->is_open)) {
500 		D_DROP("Dropping packet while interface is not open.\n");
501 		return;
502 	}
503 
504 	if (unlikely(test_bit(IL_STOP_REASON_PASSIVE, &il->stop_reason))) {
505 		il_wake_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
506 		D_INFO("Woke queues - frame received on passive channel\n");
507 	}
508 
509 	skb = dev_alloc_skb(SMALL_PACKET_SIZE);
510 	if (!skb) {
511 		IL_ERR("dev_alloc_skb failed\n");
512 		return;
513 	}
514 
515 	if (!il3945_mod_params.sw_crypto)
516 		il_set_decrypted_flag(il, (struct ieee80211_hdr *)pkt,
517 				      le32_to_cpu(rx_end->status), stats);
518 
519 	/* If frame is small enough to fit into skb->head, copy it
520 	 * and do not consume a full page
521 	 */
522 	if (len <= SMALL_PACKET_SIZE) {
523 		memcpy(skb_put(skb, len), rx_hdr->payload, len);
524 	} else {
525 		skb_add_rx_frag(skb, 0, rxb->page,
526 				(void *)rx_hdr->payload - (void *)pkt, len,
527 				fraglen);
528 		il->alloc_rxb_page--;
529 		rxb->page = NULL;
530 	}
531 	il_update_stats(il, false, fc, len);
532 	memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
533 
534 	ieee80211_rx(il->hw, skb);
535 }
536 
537 #define IL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
538 
539 static void
540 il3945_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
541 {
542 	struct ieee80211_hdr *header;
543 	struct ieee80211_rx_status rx_status = {};
544 	struct il_rx_pkt *pkt = rxb_addr(rxb);
545 	struct il3945_rx_frame_stats *rx_stats = IL_RX_STATS(pkt);
546 	struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt);
547 	struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt);
548 	u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
549 	u16 rx_stats_noise_diff __maybe_unused =
550 	    le16_to_cpu(rx_stats->noise_diff);
551 	u8 network_packet;
552 
553 	rx_status.flag = 0;
554 	rx_status.mactime = le64_to_cpu(rx_end->timestamp);
555 	rx_status.band =
556 	    (rx_hdr->
557 	     phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? NL80211_BAND_2GHZ :
558 	    NL80211_BAND_5GHZ;
559 	rx_status.freq =
560 	    ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel),
561 					   rx_status.band);
562 
563 	rx_status.rate_idx = il3945_hwrate_to_plcp_idx(rx_hdr->rate);
564 	if (rx_status.band == NL80211_BAND_5GHZ)
565 		rx_status.rate_idx -= IL_FIRST_OFDM_RATE;
566 
567 	rx_status.antenna =
568 	    (le16_to_cpu(rx_hdr->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
569 	    4;
570 
571 	/* set the preamble flag if appropriate */
572 	if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
573 		rx_status.flag |= RX_FLAG_SHORTPRE;
574 
575 	if ((unlikely(rx_stats->phy_count > 20))) {
576 		D_DROP("dsp size out of range [0,20]: %d\n",
577 		       rx_stats->phy_count);
578 		return;
579 	}
580 
581 	if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR) ||
582 	    !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
583 		D_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
584 		return;
585 	}
586 
587 	/* Convert 3945's rssi indicator to dBm */
588 	rx_status.signal = rx_stats->rssi - IL39_RSSI_OFFSET;
589 
590 	D_STATS("Rssi %d sig_avg %d noise_diff %d\n", rx_status.signal,
591 		rx_stats_sig_avg, rx_stats_noise_diff);
592 
593 	header = (struct ieee80211_hdr *)IL_RX_DATA(pkt);
594 
595 	network_packet = il3945_is_network_packet(il, header);
596 
597 	D_STATS("[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
598 		network_packet ? '*' : ' ', le16_to_cpu(rx_hdr->channel),
599 		rx_status.signal, rx_status.signal, rx_status.rate_idx);
600 
601 	if (network_packet) {
602 		il->_3945.last_beacon_time =
603 		    le32_to_cpu(rx_end->beacon_timestamp);
604 		il->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
605 		il->_3945.last_rx_rssi = rx_status.signal;
606 	}
607 
608 	il3945_pass_packet_to_mac80211(il, rxb, &rx_status);
609 }
610 
611 int
612 il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
613 				dma_addr_t addr, u16 len, u8 reset, u8 pad)
614 {
615 	int count;
616 	struct il_queue *q;
617 	struct il3945_tfd *tfd, *tfd_tmp;
618 
619 	q = &txq->q;
620 	tfd_tmp = (struct il3945_tfd *)txq->tfds;
621 	tfd = &tfd_tmp[q->write_ptr];
622 
623 	if (reset)
624 		memset(tfd, 0, sizeof(*tfd));
625 
626 	count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
627 
628 	if (count >= NUM_TFD_CHUNKS || count < 0) {
629 		IL_ERR("Error can not send more than %d chunks\n",
630 		       NUM_TFD_CHUNKS);
631 		return -EINVAL;
632 	}
633 
634 	tfd->tbs[count].addr = cpu_to_le32(addr);
635 	tfd->tbs[count].len = cpu_to_le32(len);
636 
637 	count++;
638 
639 	tfd->control_flags =
640 	    cpu_to_le32(TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad));
641 
642 	return 0;
643 }
644 
645 /**
646  * il3945_hw_txq_free_tfd - Free one TFD, those at idx [txq->q.read_ptr]
647  *
648  * Does NOT advance any idxes
649  */
650 void
651 il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
652 {
653 	struct il3945_tfd *tfd_tmp = (struct il3945_tfd *)txq->tfds;
654 	int idx = txq->q.read_ptr;
655 	struct il3945_tfd *tfd = &tfd_tmp[idx];
656 	struct pci_dev *dev = il->pci_dev;
657 	int i;
658 	int counter;
659 
660 	/* sanity check */
661 	counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
662 	if (counter > NUM_TFD_CHUNKS) {
663 		IL_ERR("Too many chunks: %i\n", counter);
664 		/* @todo issue fatal error, it is quite serious situation */
665 		return;
666 	}
667 
668 	/* Unmap tx_cmd */
669 	if (counter)
670 		pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
671 				 dma_unmap_len(&txq->meta[idx], len),
672 				 PCI_DMA_TODEVICE);
673 
674 	/* unmap chunks if any */
675 
676 	for (i = 1; i < counter; i++)
677 		pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
678 				 le32_to_cpu(tfd->tbs[i].len),
679 				 PCI_DMA_TODEVICE);
680 
681 	/* free SKB */
682 	if (txq->skbs) {
683 		struct sk_buff *skb = txq->skbs[txq->q.read_ptr];
684 
685 		/* can be called from irqs-disabled context */
686 		if (skb) {
687 			dev_kfree_skb_any(skb);
688 			txq->skbs[txq->q.read_ptr] = NULL;
689 		}
690 	}
691 }
692 
693 /**
694  * il3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
695  *
696 */
697 void
698 il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd,
699 			    struct ieee80211_tx_info *info,
700 			    struct ieee80211_hdr *hdr, int sta_id)
701 {
702 	u16 hw_value = ieee80211_get_tx_rate(il->hw, info)->hw_value;
703 	u16 rate_idx = min(hw_value & 0xffff, RATE_COUNT_3945 - 1);
704 	u16 rate_mask;
705 	int rate;
706 	const u8 rts_retry_limit = 7;
707 	u8 data_retry_limit;
708 	__le32 tx_flags;
709 	__le16 fc = hdr->frame_control;
710 	struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
711 
712 	rate = il3945_rates[rate_idx].plcp;
713 	tx_flags = tx_cmd->tx_flags;
714 
715 	/* We need to figure out how to get the sta->supp_rates while
716 	 * in this running context */
717 	rate_mask = RATES_MASK_3945;
718 
719 	/* Set retry limit on DATA packets and Probe Responses */
720 	if (ieee80211_is_probe_resp(fc))
721 		data_retry_limit = 3;
722 	else
723 		data_retry_limit = IL_DEFAULT_TX_RETRY;
724 	tx_cmd->data_retry_limit = data_retry_limit;
725 	/* Set retry limit on RTS packets */
726 	tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
727 
728 	tx_cmd->rate = rate;
729 	tx_cmd->tx_flags = tx_flags;
730 
731 	/* OFDM */
732 	tx_cmd->supp_rates[0] =
733 	    ((rate_mask & IL_OFDM_RATES_MASK) >> IL_FIRST_OFDM_RATE) & 0xFF;
734 
735 	/* CCK */
736 	tx_cmd->supp_rates[1] = (rate_mask & 0xF);
737 
738 	D_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
739 	       "cck/ofdm mask: 0x%x/0x%x\n", sta_id, tx_cmd->rate,
740 	       le32_to_cpu(tx_cmd->tx_flags), tx_cmd->supp_rates[1],
741 	       tx_cmd->supp_rates[0]);
742 }
743 
744 static u8
745 il3945_sync_sta(struct il_priv *il, int sta_id, u16 tx_rate)
746 {
747 	unsigned long flags_spin;
748 	struct il_station_entry *station;
749 
750 	if (sta_id == IL_INVALID_STATION)
751 		return IL_INVALID_STATION;
752 
753 	spin_lock_irqsave(&il->sta_lock, flags_spin);
754 	station = &il->stations[sta_id];
755 
756 	station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
757 	station->sta.rate_n_flags = cpu_to_le16(tx_rate);
758 	station->sta.mode = STA_CONTROL_MODIFY_MSK;
759 	il_send_add_sta(il, &station->sta, CMD_ASYNC);
760 	spin_unlock_irqrestore(&il->sta_lock, flags_spin);
761 
762 	D_RATE("SCALE sync station %d to rate %d\n", sta_id, tx_rate);
763 	return sta_id;
764 }
765 
766 static void
767 il3945_set_pwr_vmain(struct il_priv *il)
768 {
769 /*
770  * (for documentation purposes)
771  * to set power to V_AUX, do
772 
773 		if (pci_pme_capable(il->pci_dev, PCI_D3cold)) {
774 			il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
775 					APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
776 					~APMG_PS_CTRL_MSK_PWR_SRC);
777 
778 			_il_poll_bit(il, CSR_GPIO_IN,
779 				     CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
780 				     CSR_GPIO_IN_BIT_AUX_POWER, 5000);
781 		}
782  */
783 
784 	il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
785 			      APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
786 			      ~APMG_PS_CTRL_MSK_PWR_SRC);
787 
788 	_il_poll_bit(il, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
789 		     CSR_GPIO_IN_BIT_AUX_POWER, 5000);
790 }
791 
792 static int
793 il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
794 {
795 	il_wr(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
796 	il_wr(il, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
797 	il_wr(il, FH39_RCSR_WPTR(0), 0);
798 	il_wr(il, FH39_RCSR_CONFIG(0),
799 	      FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
800 	      FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
801 	      FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
802 	      FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 | (RX_QUEUE_SIZE_LOG
803 							       <<
804 							       FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE)
805 	      | FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST | (1 <<
806 								 FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH)
807 	      | FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
808 
809 	/* fake read to flush all prev I/O */
810 	il_rd(il, FH39_RSSR_CTRL);
811 
812 	return 0;
813 }
814 
815 static int
816 il3945_tx_reset(struct il_priv *il)
817 {
818 	/* bypass mode */
819 	il_wr_prph(il, ALM_SCD_MODE_REG, 0x2);
820 
821 	/* RA 0 is active */
822 	il_wr_prph(il, ALM_SCD_ARASTAT_REG, 0x01);
823 
824 	/* all 6 fifo are active */
825 	il_wr_prph(il, ALM_SCD_TXFACT_REG, 0x3f);
826 
827 	il_wr_prph(il, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
828 	il_wr_prph(il, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
829 	il_wr_prph(il, ALM_SCD_TXF4MF_REG, 0x000004);
830 	il_wr_prph(il, ALM_SCD_TXF5MF_REG, 0x000005);
831 
832 	il_wr(il, FH39_TSSR_CBB_BASE, il->_3945.shared_phys);
833 
834 	il_wr(il, FH39_TSSR_MSG_CONFIG,
835 	      FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
836 	      FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
837 	      FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
838 	      FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
839 	      FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
840 	      FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
841 	      FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
842 
843 	return 0;
844 }
845 
846 /**
847  * il3945_txq_ctx_reset - Reset TX queue context
848  *
849  * Destroys all DMA structures and initialize them again
850  */
851 static int
852 il3945_txq_ctx_reset(struct il_priv *il)
853 {
854 	int rc, txq_id;
855 
856 	il3945_hw_txq_ctx_free(il);
857 
858 	/* allocate tx queue structure */
859 	rc = il_alloc_txq_mem(il);
860 	if (rc)
861 		return rc;
862 
863 	/* Tx CMD queue */
864 	rc = il3945_tx_reset(il);
865 	if (rc)
866 		goto error;
867 
868 	/* Tx queue(s) */
869 	for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
870 		rc = il_tx_queue_init(il, txq_id);
871 		if (rc) {
872 			IL_ERR("Tx %d queue init failed\n", txq_id);
873 			goto error;
874 		}
875 	}
876 
877 	return rc;
878 
879 error:
880 	il3945_hw_txq_ctx_free(il);
881 	return rc;
882 }
883 
884 /*
885  * Start up 3945's basic functionality after it has been reset
886  * (e.g. after platform boot, or shutdown via il_apm_stop())
887  * NOTE:  This does not load uCode nor start the embedded processor
888  */
889 static int
890 il3945_apm_init(struct il_priv *il)
891 {
892 	int ret = il_apm_init(il);
893 
894 	/* Clear APMG (NIC's internal power management) interrupts */
895 	il_wr_prph(il, APMG_RTC_INT_MSK_REG, 0x0);
896 	il_wr_prph(il, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
897 
898 	/* Reset radio chip */
899 	il_set_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
900 	udelay(5);
901 	il_clear_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
902 
903 	return ret;
904 }
905 
906 static void
907 il3945_nic_config(struct il_priv *il)
908 {
909 	struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
910 	unsigned long flags;
911 	u8 rev_id = il->pci_dev->revision;
912 
913 	spin_lock_irqsave(&il->lock, flags);
914 
915 	/* Determine HW type */
916 	D_INFO("HW Revision ID = 0x%X\n", rev_id);
917 
918 	if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
919 		D_INFO("RTP type\n");
920 	else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
921 		D_INFO("3945 RADIO-MB type\n");
922 		il_set_bit(il, CSR_HW_IF_CONFIG_REG,
923 			   CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
924 	} else {
925 		D_INFO("3945 RADIO-MM type\n");
926 		il_set_bit(il, CSR_HW_IF_CONFIG_REG,
927 			   CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
928 	}
929 
930 	if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
931 		D_INFO("SKU OP mode is mrc\n");
932 		il_set_bit(il, CSR_HW_IF_CONFIG_REG,
933 			   CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
934 	} else
935 		D_INFO("SKU OP mode is basic\n");
936 
937 	if ((eeprom->board_revision & 0xF0) == 0xD0) {
938 		D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision);
939 		il_set_bit(il, CSR_HW_IF_CONFIG_REG,
940 			   CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
941 	} else {
942 		D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision);
943 		il_clear_bit(il, CSR_HW_IF_CONFIG_REG,
944 			     CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
945 	}
946 
947 	if (eeprom->almgor_m_version <= 1) {
948 		il_set_bit(il, CSR_HW_IF_CONFIG_REG,
949 			   CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
950 		D_INFO("Card M type A version is 0x%X\n",
951 		       eeprom->almgor_m_version);
952 	} else {
953 		D_INFO("Card M type B version is 0x%X\n",
954 		       eeprom->almgor_m_version);
955 		il_set_bit(il, CSR_HW_IF_CONFIG_REG,
956 			   CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
957 	}
958 	spin_unlock_irqrestore(&il->lock, flags);
959 
960 	if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
961 		D_RF_KILL("SW RF KILL supported in EEPROM.\n");
962 
963 	if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
964 		D_RF_KILL("HW RF KILL supported in EEPROM.\n");
965 }
966 
967 int
968 il3945_hw_nic_init(struct il_priv *il)
969 {
970 	int rc;
971 	unsigned long flags;
972 	struct il_rx_queue *rxq = &il->rxq;
973 
974 	spin_lock_irqsave(&il->lock, flags);
975 	il3945_apm_init(il);
976 	spin_unlock_irqrestore(&il->lock, flags);
977 
978 	il3945_set_pwr_vmain(il);
979 	il3945_nic_config(il);
980 
981 	/* Allocate the RX queue, or reset if it is already allocated */
982 	if (!rxq->bd) {
983 		rc = il_rx_queue_alloc(il);
984 		if (rc) {
985 			IL_ERR("Unable to initialize Rx queue\n");
986 			return -ENOMEM;
987 		}
988 	} else
989 		il3945_rx_queue_reset(il, rxq);
990 
991 	il3945_rx_replenish(il);
992 
993 	il3945_rx_init(il, rxq);
994 
995 	/* Look at using this instead:
996 	   rxq->need_update = 1;
997 	   il_rx_queue_update_write_ptr(il, rxq);
998 	 */
999 
1000 	il_wr(il, FH39_RCSR_WPTR(0), rxq->write & ~7);
1001 
1002 	rc = il3945_txq_ctx_reset(il);
1003 	if (rc)
1004 		return rc;
1005 
1006 	set_bit(S_INIT, &il->status);
1007 
1008 	return 0;
1009 }
1010 
1011 /**
1012  * il3945_hw_txq_ctx_free - Free TXQ Context
1013  *
1014  * Destroy all TX DMA queues and structures
1015  */
1016 void
1017 il3945_hw_txq_ctx_free(struct il_priv *il)
1018 {
1019 	int txq_id;
1020 
1021 	/* Tx queues */
1022 	if (il->txq) {
1023 		for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1024 			if (txq_id == IL39_CMD_QUEUE_NUM)
1025 				il_cmd_queue_free(il);
1026 			else
1027 				il_tx_queue_free(il, txq_id);
1028 	}
1029 
1030 	/* free tx queue structure */
1031 	il_free_txq_mem(il);
1032 }
1033 
1034 void
1035 il3945_hw_txq_ctx_stop(struct il_priv *il)
1036 {
1037 	int txq_id;
1038 
1039 	/* stop SCD */
1040 	_il_wr_prph(il, ALM_SCD_MODE_REG, 0);
1041 	_il_wr_prph(il, ALM_SCD_TXFACT_REG, 0);
1042 
1043 	/* reset TFD queues */
1044 	for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
1045 		_il_wr(il, FH39_TCSR_CONFIG(txq_id), 0x0);
1046 		_il_poll_bit(il, FH39_TSSR_TX_STATUS,
1047 			     FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1048 			     FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1049 			     1000);
1050 	}
1051 }
1052 
1053 /**
1054  * il3945_hw_reg_adjust_power_by_temp
1055  * return idx delta into power gain settings table
1056 */
1057 static int
1058 il3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1059 {
1060 	return (new_reading - old_reading) * (-11) / 100;
1061 }
1062 
1063 /**
1064  * il3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1065  */
1066 static inline int
1067 il3945_hw_reg_temp_out_of_range(int temperature)
1068 {
1069 	return (temperature < -260 || temperature > 25) ? 1 : 0;
1070 }
1071 
1072 int
1073 il3945_hw_get_temperature(struct il_priv *il)
1074 {
1075 	return _il_rd(il, CSR_UCODE_DRV_GP2);
1076 }
1077 
1078 /**
1079  * il3945_hw_reg_txpower_get_temperature
1080  * get the current temperature by reading from NIC
1081 */
1082 static int
1083 il3945_hw_reg_txpower_get_temperature(struct il_priv *il)
1084 {
1085 	struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1086 	int temperature;
1087 
1088 	temperature = il3945_hw_get_temperature(il);
1089 
1090 	/* driver's okay range is -260 to +25.
1091 	 *   human readable okay range is 0 to +285 */
1092 	D_INFO("Temperature: %d\n", temperature + IL_TEMP_CONVERT);
1093 
1094 	/* handle insane temp reading */
1095 	if (il3945_hw_reg_temp_out_of_range(temperature)) {
1096 		IL_ERR("Error bad temperature value  %d\n", temperature);
1097 
1098 		/* if really really hot(?),
1099 		 *   substitute the 3rd band/group's temp measured at factory */
1100 		if (il->last_temperature > 100)
1101 			temperature = eeprom->groups[2].temperature;
1102 		else		/* else use most recent "sane" value from driver */
1103 			temperature = il->last_temperature;
1104 	}
1105 
1106 	return temperature;	/* raw, not "human readable" */
1107 }
1108 
1109 /* Adjust Txpower only if temperature variance is greater than threshold.
1110  *
1111  * Both are lower than older versions' 9 degrees */
1112 #define IL_TEMPERATURE_LIMIT_TIMER   6
1113 
1114 /**
1115  * il3945_is_temp_calib_needed - determines if new calibration is needed
1116  *
1117  * records new temperature in tx_mgr->temperature.
1118  * replaces tx_mgr->last_temperature *only* if calib needed
1119  *    (assumes caller will actually do the calibration!). */
1120 static int
1121 il3945_is_temp_calib_needed(struct il_priv *il)
1122 {
1123 	int temp_diff;
1124 
1125 	il->temperature = il3945_hw_reg_txpower_get_temperature(il);
1126 	temp_diff = il->temperature - il->last_temperature;
1127 
1128 	/* get absolute value */
1129 	if (temp_diff < 0) {
1130 		D_POWER("Getting cooler, delta %d,\n", temp_diff);
1131 		temp_diff = -temp_diff;
1132 	} else if (temp_diff == 0)
1133 		D_POWER("Same temp,\n");
1134 	else
1135 		D_POWER("Getting warmer, delta %d,\n", temp_diff);
1136 
1137 	/* if we don't need calibration, *don't* update last_temperature */
1138 	if (temp_diff < IL_TEMPERATURE_LIMIT_TIMER) {
1139 		D_POWER("Timed thermal calib not needed\n");
1140 		return 0;
1141 	}
1142 
1143 	D_POWER("Timed thermal calib needed\n");
1144 
1145 	/* assume that caller will actually do calib ...
1146 	 *   update the "last temperature" value */
1147 	il->last_temperature = il->temperature;
1148 	return 1;
1149 }
1150 
1151 #define IL_MAX_GAIN_ENTRIES 78
1152 #define IL_CCK_FROM_OFDM_POWER_DIFF  -5
1153 #define IL_CCK_FROM_OFDM_IDX_DIFF (10)
1154 
1155 /* radio and DSP power table, each step is 1/2 dB.
1156  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1157 static struct il3945_tx_power power_gain_table[2][IL_MAX_GAIN_ENTRIES] = {
1158 	{
1159 	 {251, 127},		/* 2.4 GHz, highest power */
1160 	 {251, 127},
1161 	 {251, 127},
1162 	 {251, 127},
1163 	 {251, 125},
1164 	 {251, 110},
1165 	 {251, 105},
1166 	 {251, 98},
1167 	 {187, 125},
1168 	 {187, 115},
1169 	 {187, 108},
1170 	 {187, 99},
1171 	 {243, 119},
1172 	 {243, 111},
1173 	 {243, 105},
1174 	 {243, 97},
1175 	 {243, 92},
1176 	 {211, 106},
1177 	 {211, 100},
1178 	 {179, 120},
1179 	 {179, 113},
1180 	 {179, 107},
1181 	 {147, 125},
1182 	 {147, 119},
1183 	 {147, 112},
1184 	 {147, 106},
1185 	 {147, 101},
1186 	 {147, 97},
1187 	 {147, 91},
1188 	 {115, 107},
1189 	 {235, 121},
1190 	 {235, 115},
1191 	 {235, 109},
1192 	 {203, 127},
1193 	 {203, 121},
1194 	 {203, 115},
1195 	 {203, 108},
1196 	 {203, 102},
1197 	 {203, 96},
1198 	 {203, 92},
1199 	 {171, 110},
1200 	 {171, 104},
1201 	 {171, 98},
1202 	 {139, 116},
1203 	 {227, 125},
1204 	 {227, 119},
1205 	 {227, 113},
1206 	 {227, 107},
1207 	 {227, 101},
1208 	 {227, 96},
1209 	 {195, 113},
1210 	 {195, 106},
1211 	 {195, 102},
1212 	 {195, 95},
1213 	 {163, 113},
1214 	 {163, 106},
1215 	 {163, 102},
1216 	 {163, 95},
1217 	 {131, 113},
1218 	 {131, 106},
1219 	 {131, 102},
1220 	 {131, 95},
1221 	 {99, 113},
1222 	 {99, 106},
1223 	 {99, 102},
1224 	 {99, 95},
1225 	 {67, 113},
1226 	 {67, 106},
1227 	 {67, 102},
1228 	 {67, 95},
1229 	 {35, 113},
1230 	 {35, 106},
1231 	 {35, 102},
1232 	 {35, 95},
1233 	 {3, 113},
1234 	 {3, 106},
1235 	 {3, 102},
1236 	 {3, 95}		/* 2.4 GHz, lowest power */
1237 	},
1238 	{
1239 	 {251, 127},		/* 5.x GHz, highest power */
1240 	 {251, 120},
1241 	 {251, 114},
1242 	 {219, 119},
1243 	 {219, 101},
1244 	 {187, 113},
1245 	 {187, 102},
1246 	 {155, 114},
1247 	 {155, 103},
1248 	 {123, 117},
1249 	 {123, 107},
1250 	 {123, 99},
1251 	 {123, 92},
1252 	 {91, 108},
1253 	 {59, 125},
1254 	 {59, 118},
1255 	 {59, 109},
1256 	 {59, 102},
1257 	 {59, 96},
1258 	 {59, 90},
1259 	 {27, 104},
1260 	 {27, 98},
1261 	 {27, 92},
1262 	 {115, 118},
1263 	 {115, 111},
1264 	 {115, 104},
1265 	 {83, 126},
1266 	 {83, 121},
1267 	 {83, 113},
1268 	 {83, 105},
1269 	 {83, 99},
1270 	 {51, 118},
1271 	 {51, 111},
1272 	 {51, 104},
1273 	 {51, 98},
1274 	 {19, 116},
1275 	 {19, 109},
1276 	 {19, 102},
1277 	 {19, 98},
1278 	 {19, 93},
1279 	 {171, 113},
1280 	 {171, 107},
1281 	 {171, 99},
1282 	 {139, 120},
1283 	 {139, 113},
1284 	 {139, 107},
1285 	 {139, 99},
1286 	 {107, 120},
1287 	 {107, 113},
1288 	 {107, 107},
1289 	 {107, 99},
1290 	 {75, 120},
1291 	 {75, 113},
1292 	 {75, 107},
1293 	 {75, 99},
1294 	 {43, 120},
1295 	 {43, 113},
1296 	 {43, 107},
1297 	 {43, 99},
1298 	 {11, 120},
1299 	 {11, 113},
1300 	 {11, 107},
1301 	 {11, 99},
1302 	 {131, 107},
1303 	 {131, 99},
1304 	 {99, 120},
1305 	 {99, 113},
1306 	 {99, 107},
1307 	 {99, 99},
1308 	 {67, 120},
1309 	 {67, 113},
1310 	 {67, 107},
1311 	 {67, 99},
1312 	 {35, 120},
1313 	 {35, 113},
1314 	 {35, 107},
1315 	 {35, 99},
1316 	 {3, 120}		/* 5.x GHz, lowest power */
1317 	}
1318 };
1319 
1320 static inline u8
1321 il3945_hw_reg_fix_power_idx(int idx)
1322 {
1323 	if (idx < 0)
1324 		return 0;
1325 	if (idx >= IL_MAX_GAIN_ENTRIES)
1326 		return IL_MAX_GAIN_ENTRIES - 1;
1327 	return (u8) idx;
1328 }
1329 
1330 /* Kick off thermal recalibration check every 60 seconds */
1331 #define REG_RECALIB_PERIOD (60)
1332 
1333 /**
1334  * il3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1335  *
1336  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1337  * or 6 Mbit (OFDM) rates.
1338  */
1339 static void
1340 il3945_hw_reg_set_scan_power(struct il_priv *il, u32 scan_tbl_idx, s32 rate_idx,
1341 			     const s8 *clip_pwrs,
1342 			     struct il_channel_info *ch_info, int band_idx)
1343 {
1344 	struct il3945_scan_power_info *scan_power_info;
1345 	s8 power;
1346 	u8 power_idx;
1347 
1348 	scan_power_info = &ch_info->scan_pwr_info[scan_tbl_idx];
1349 
1350 	/* use this channel group's 6Mbit clipping/saturation pwr,
1351 	 *   but cap at regulatory scan power restriction (set during init
1352 	 *   based on eeprom channel data) for this channel.  */
1353 	power = min(ch_info->scan_power, clip_pwrs[RATE_6M_IDX_TBL]);
1354 
1355 	power = min(power, il->tx_power_user_lmt);
1356 	scan_power_info->requested_power = power;
1357 
1358 	/* find difference between new scan *power* and current "normal"
1359 	 *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1360 	 *   current "normal" temperature-compensated Tx power *idx* for
1361 	 *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1362 	 *   *idx*. */
1363 	power_idx =
1364 	    ch_info->power_info[rate_idx].power_table_idx - (power -
1365 							     ch_info->
1366 							     power_info
1367 							     [RATE_6M_IDX_TBL].
1368 							     requested_power) *
1369 	    2;
1370 
1371 	/* store reference idx that we use when adjusting *all* scan
1372 	 *   powers.  So we can accommodate user (all channel) or spectrum
1373 	 *   management (single channel) power changes "between" temperature
1374 	 *   feedback compensation procedures.
1375 	 * don't force fit this reference idx into gain table; it may be a
1376 	 *   negative number.  This will help avoid errors when we're at
1377 	 *   the lower bounds (highest gains, for warmest temperatures)
1378 	 *   of the table. */
1379 
1380 	/* don't exceed table bounds for "real" setting */
1381 	power_idx = il3945_hw_reg_fix_power_idx(power_idx);
1382 
1383 	scan_power_info->power_table_idx = power_idx;
1384 	scan_power_info->tpc.tx_gain =
1385 	    power_gain_table[band_idx][power_idx].tx_gain;
1386 	scan_power_info->tpc.dsp_atten =
1387 	    power_gain_table[band_idx][power_idx].dsp_atten;
1388 }
1389 
1390 /**
1391  * il3945_send_tx_power - fill in Tx Power command with gain settings
1392  *
1393  * Configures power settings for all rates for the current channel,
1394  * using values from channel info struct, and send to NIC
1395  */
1396 static int
1397 il3945_send_tx_power(struct il_priv *il)
1398 {
1399 	int rate_idx, i;
1400 	const struct il_channel_info *ch_info = NULL;
1401 	struct il3945_txpowertable_cmd txpower = {
1402 		.channel = il->active.channel,
1403 	};
1404 	u16 chan;
1405 
1406 	if (WARN_ONCE
1407 	    (test_bit(S_SCAN_HW, &il->status),
1408 	     "TX Power requested while scanning!\n"))
1409 		return -EAGAIN;
1410 
1411 	chan = le16_to_cpu(il->active.channel);
1412 
1413 	txpower.band = (il->band == NL80211_BAND_5GHZ) ? 0 : 1;
1414 	ch_info = il_get_channel_info(il, il->band, chan);
1415 	if (!ch_info) {
1416 		IL_ERR("Failed to get channel info for channel %d [%d]\n", chan,
1417 		       il->band);
1418 		return -EINVAL;
1419 	}
1420 
1421 	if (!il_is_channel_valid(ch_info)) {
1422 		D_POWER("Not calling TX_PWR_TBL_CMD on " "non-Tx channel.\n");
1423 		return 0;
1424 	}
1425 
1426 	/* fill cmd with power settings for all rates for current channel */
1427 	/* Fill OFDM rate */
1428 	for (rate_idx = IL_FIRST_OFDM_RATE, i = 0;
1429 	     rate_idx <= IL39_LAST_OFDM_RATE; rate_idx++, i++) {
1430 
1431 		txpower.power[i].tpc = ch_info->power_info[i].tpc;
1432 		txpower.power[i].rate = il3945_rates[rate_idx].plcp;
1433 
1434 		D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1435 			le16_to_cpu(txpower.channel), txpower.band,
1436 			txpower.power[i].tpc.tx_gain,
1437 			txpower.power[i].tpc.dsp_atten, txpower.power[i].rate);
1438 	}
1439 	/* Fill CCK rates */
1440 	for (rate_idx = IL_FIRST_CCK_RATE; rate_idx <= IL_LAST_CCK_RATE;
1441 	     rate_idx++, i++) {
1442 		txpower.power[i].tpc = ch_info->power_info[i].tpc;
1443 		txpower.power[i].rate = il3945_rates[rate_idx].plcp;
1444 
1445 		D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1446 			le16_to_cpu(txpower.channel), txpower.band,
1447 			txpower.power[i].tpc.tx_gain,
1448 			txpower.power[i].tpc.dsp_atten, txpower.power[i].rate);
1449 	}
1450 
1451 	return il_send_cmd_pdu(il, C_TX_PWR_TBL,
1452 			       sizeof(struct il3945_txpowertable_cmd),
1453 			       &txpower);
1454 
1455 }
1456 
1457 /**
1458  * il3945_hw_reg_set_new_power - Configures power tables at new levels
1459  * @ch_info: Channel to update.  Uses power_info.requested_power.
1460  *
1461  * Replace requested_power and base_power_idx ch_info fields for
1462  * one channel.
1463  *
1464  * Called if user or spectrum management changes power preferences.
1465  * Takes into account h/w and modulation limitations (clip power).
1466  *
1467  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1468  *
1469  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1470  *	 properly fill out the scan powers, and actual h/w gain settings,
1471  *	 and send changes to NIC
1472  */
1473 static int
1474 il3945_hw_reg_set_new_power(struct il_priv *il, struct il_channel_info *ch_info)
1475 {
1476 	struct il3945_channel_power_info *power_info;
1477 	int power_changed = 0;
1478 	int i;
1479 	const s8 *clip_pwrs;
1480 	int power;
1481 
1482 	/* Get this chnlgrp's rate-to-max/clip-powers table */
1483 	clip_pwrs = il->_3945.clip_groups[ch_info->group_idx].clip_powers;
1484 
1485 	/* Get this channel's rate-to-current-power settings table */
1486 	power_info = ch_info->power_info;
1487 
1488 	/* update OFDM Txpower settings */
1489 	for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++, ++power_info) {
1490 		int delta_idx;
1491 
1492 		/* limit new power to be no more than h/w capability */
1493 		power = min(ch_info->curr_txpow, clip_pwrs[i]);
1494 		if (power == power_info->requested_power)
1495 			continue;
1496 
1497 		/* find difference between old and new requested powers,
1498 		 *    update base (non-temp-compensated) power idx */
1499 		delta_idx = (power - power_info->requested_power) * 2;
1500 		power_info->base_power_idx -= delta_idx;
1501 
1502 		/* save new requested power value */
1503 		power_info->requested_power = power;
1504 
1505 		power_changed = 1;
1506 	}
1507 
1508 	/* update CCK Txpower settings, based on OFDM 12M setting ...
1509 	 *    ... all CCK power settings for a given channel are the *same*. */
1510 	if (power_changed) {
1511 		power =
1512 		    ch_info->power_info[RATE_12M_IDX_TBL].requested_power +
1513 		    IL_CCK_FROM_OFDM_POWER_DIFF;
1514 
1515 		/* do all CCK rates' il3945_channel_power_info structures */
1516 		for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++) {
1517 			power_info->requested_power = power;
1518 			power_info->base_power_idx =
1519 			    ch_info->power_info[RATE_12M_IDX_TBL].
1520 			    base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
1521 			++power_info;
1522 		}
1523 	}
1524 
1525 	return 0;
1526 }
1527 
1528 /**
1529  * il3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1530  *
1531  * NOTE: Returned power limit may be less (but not more) than requested,
1532  *	 based strictly on regulatory (eeprom and spectrum mgt) limitations
1533  *	 (no consideration for h/w clipping limitations).
1534  */
1535 static int
1536 il3945_hw_reg_get_ch_txpower_limit(struct il_channel_info *ch_info)
1537 {
1538 	s8 max_power;
1539 
1540 #if 0
1541 	/* if we're using TGd limits, use lower of TGd or EEPROM */
1542 	if (ch_info->tgd_data.max_power != 0)
1543 		max_power =
1544 		    min(ch_info->tgd_data.max_power,
1545 			ch_info->eeprom.max_power_avg);
1546 
1547 	/* else just use EEPROM limits */
1548 	else
1549 #endif
1550 		max_power = ch_info->eeprom.max_power_avg;
1551 
1552 	return min(max_power, ch_info->max_power_avg);
1553 }
1554 
1555 /**
1556  * il3945_hw_reg_comp_txpower_temp - Compensate for temperature
1557  *
1558  * Compensate txpower settings of *all* channels for temperature.
1559  * This only accounts for the difference between current temperature
1560  *   and the factory calibration temperatures, and bases the new settings
1561  *   on the channel's base_power_idx.
1562  *
1563  * If RxOn is "associated", this sends the new Txpower to NIC!
1564  */
1565 static int
1566 il3945_hw_reg_comp_txpower_temp(struct il_priv *il)
1567 {
1568 	struct il_channel_info *ch_info = NULL;
1569 	struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1570 	int delta_idx;
1571 	const s8 *clip_pwrs;	/* array of h/w max power levels for each rate */
1572 	u8 a_band;
1573 	u8 rate_idx;
1574 	u8 scan_tbl_idx;
1575 	u8 i;
1576 	int ref_temp;
1577 	int temperature = il->temperature;
1578 
1579 	if (il->disable_tx_power_cal || test_bit(S_SCANNING, &il->status)) {
1580 		/* do not perform tx power calibration */
1581 		return 0;
1582 	}
1583 	/* set up new Tx power info for each and every channel, 2.4 and 5.x */
1584 	for (i = 0; i < il->channel_count; i++) {
1585 		ch_info = &il->channel_info[i];
1586 		a_band = il_is_channel_a_band(ch_info);
1587 
1588 		/* Get this chnlgrp's factory calibration temperature */
1589 		ref_temp = (s16) eeprom->groups[ch_info->group_idx].temperature;
1590 
1591 		/* get power idx adjustment based on current and factory
1592 		 * temps */
1593 		delta_idx =
1594 		    il3945_hw_reg_adjust_power_by_temp(temperature, ref_temp);
1595 
1596 		/* set tx power value for all rates, OFDM and CCK */
1597 		for (rate_idx = 0; rate_idx < RATE_COUNT_3945; rate_idx++) {
1598 			int power_idx =
1599 			    ch_info->power_info[rate_idx].base_power_idx;
1600 
1601 			/* temperature compensate */
1602 			power_idx += delta_idx;
1603 
1604 			/* stay within table range */
1605 			power_idx = il3945_hw_reg_fix_power_idx(power_idx);
1606 			ch_info->power_info[rate_idx].power_table_idx =
1607 			    (u8) power_idx;
1608 			ch_info->power_info[rate_idx].tpc =
1609 			    power_gain_table[a_band][power_idx];
1610 		}
1611 
1612 		/* Get this chnlgrp's rate-to-max/clip-powers table */
1613 		clip_pwrs =
1614 		    il->_3945.clip_groups[ch_info->group_idx].clip_powers;
1615 
1616 		/* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1617 		for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES;
1618 		     scan_tbl_idx++) {
1619 			s32 actual_idx =
1620 			    (scan_tbl_idx ==
1621 			     0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL;
1622 			il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
1623 						     actual_idx, clip_pwrs,
1624 						     ch_info, a_band);
1625 		}
1626 	}
1627 
1628 	/* send Txpower command for current channel to ucode */
1629 	return il->ops->send_tx_power(il);
1630 }
1631 
1632 int
1633 il3945_hw_reg_set_txpower(struct il_priv *il, s8 power)
1634 {
1635 	struct il_channel_info *ch_info;
1636 	s8 max_power;
1637 	u8 a_band;
1638 	u8 i;
1639 
1640 	if (il->tx_power_user_lmt == power) {
1641 		D_POWER("Requested Tx power same as current " "limit: %ddBm.\n",
1642 			power);
1643 		return 0;
1644 	}
1645 
1646 	D_POWER("Setting upper limit clamp to %ddBm.\n", power);
1647 	il->tx_power_user_lmt = power;
1648 
1649 	/* set up new Tx powers for each and every channel, 2.4 and 5.x */
1650 
1651 	for (i = 0; i < il->channel_count; i++) {
1652 		ch_info = &il->channel_info[i];
1653 		a_band = il_is_channel_a_band(ch_info);
1654 
1655 		/* find minimum power of all user and regulatory constraints
1656 		 *    (does not consider h/w clipping limitations) */
1657 		max_power = il3945_hw_reg_get_ch_txpower_limit(ch_info);
1658 		max_power = min(power, max_power);
1659 		if (max_power != ch_info->curr_txpow) {
1660 			ch_info->curr_txpow = max_power;
1661 
1662 			/* this considers the h/w clipping limitations */
1663 			il3945_hw_reg_set_new_power(il, ch_info);
1664 		}
1665 	}
1666 
1667 	/* update txpower settings for all channels,
1668 	 *   send to NIC if associated. */
1669 	il3945_is_temp_calib_needed(il);
1670 	il3945_hw_reg_comp_txpower_temp(il);
1671 
1672 	return 0;
1673 }
1674 
1675 static int
1676 il3945_send_rxon_assoc(struct il_priv *il)
1677 {
1678 	int rc = 0;
1679 	struct il_rx_pkt *pkt;
1680 	struct il3945_rxon_assoc_cmd rxon_assoc;
1681 	struct il_host_cmd cmd = {
1682 		.id = C_RXON_ASSOC,
1683 		.len = sizeof(rxon_assoc),
1684 		.flags = CMD_WANT_SKB,
1685 		.data = &rxon_assoc,
1686 	};
1687 	const struct il_rxon_cmd *rxon1 = &il->staging;
1688 	const struct il_rxon_cmd *rxon2 = &il->active;
1689 
1690 	if (rxon1->flags == rxon2->flags &&
1691 	    rxon1->filter_flags == rxon2->filter_flags &&
1692 	    rxon1->cck_basic_rates == rxon2->cck_basic_rates &&
1693 	    rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates) {
1694 		D_INFO("Using current RXON_ASSOC.  Not resending.\n");
1695 		return 0;
1696 	}
1697 
1698 	rxon_assoc.flags = il->staging.flags;
1699 	rxon_assoc.filter_flags = il->staging.filter_flags;
1700 	rxon_assoc.ofdm_basic_rates = il->staging.ofdm_basic_rates;
1701 	rxon_assoc.cck_basic_rates = il->staging.cck_basic_rates;
1702 	rxon_assoc.reserved = 0;
1703 
1704 	rc = il_send_cmd_sync(il, &cmd);
1705 	if (rc)
1706 		return rc;
1707 
1708 	pkt = (struct il_rx_pkt *)cmd.reply_page;
1709 	if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
1710 		IL_ERR("Bad return from C_RXON_ASSOC command\n");
1711 		rc = -EIO;
1712 	}
1713 
1714 	il_free_pages(il, cmd.reply_page);
1715 
1716 	return rc;
1717 }
1718 
1719 /**
1720  * il3945_commit_rxon - commit staging_rxon to hardware
1721  *
1722  * The RXON command in staging_rxon is committed to the hardware and
1723  * the active_rxon structure is updated with the new data.  This
1724  * function correctly transitions out of the RXON_ASSOC_MSK state if
1725  * a HW tune is required based on the RXON structure changes.
1726  */
1727 int
1728 il3945_commit_rxon(struct il_priv *il)
1729 {
1730 	/* cast away the const for active_rxon in this function */
1731 	struct il3945_rxon_cmd *active_rxon = (void *)&il->active;
1732 	struct il3945_rxon_cmd *staging_rxon = (void *)&il->staging;
1733 	int rc = 0;
1734 	bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
1735 
1736 	if (test_bit(S_EXIT_PENDING, &il->status))
1737 		return -EINVAL;
1738 
1739 	if (!il_is_alive(il))
1740 		return -1;
1741 
1742 	/* always get timestamp with Rx frame */
1743 	staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1744 
1745 	/* select antenna */
1746 	staging_rxon->flags &= ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1747 	staging_rxon->flags |= il3945_get_antenna_flags(il);
1748 
1749 	rc = il_check_rxon_cmd(il);
1750 	if (rc) {
1751 		IL_ERR("Invalid RXON configuration.  Not committing.\n");
1752 		return -EINVAL;
1753 	}
1754 
1755 	/* If we don't need to send a full RXON, we can use
1756 	 * il3945_rxon_assoc_cmd which is used to reconfigure filter
1757 	 * and other flags for the current radio configuration. */
1758 	if (!il_full_rxon_required(il)) {
1759 		rc = il_send_rxon_assoc(il);
1760 		if (rc) {
1761 			IL_ERR("Error setting RXON_ASSOC "
1762 			       "configuration (%d).\n", rc);
1763 			return rc;
1764 		}
1765 
1766 		memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1767 		/*
1768 		 * We do not commit tx power settings while channel changing,
1769 		 * do it now if tx power changed.
1770 		 */
1771 		il_set_tx_power(il, il->tx_power_next, false);
1772 		return 0;
1773 	}
1774 
1775 	/* If we are currently associated and the new config requires
1776 	 * an RXON_ASSOC and the new config wants the associated mask enabled,
1777 	 * we must clear the associated from the active configuration
1778 	 * before we apply the new config */
1779 	if (il_is_associated(il) && new_assoc) {
1780 		D_INFO("Toggling associated bit on current RXON\n");
1781 		active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1782 
1783 		/*
1784 		 * reserved4 and 5 could have been filled by the iwlcore code.
1785 		 * Let's clear them before pushing to the 3945.
1786 		 */
1787 		active_rxon->reserved4 = 0;
1788 		active_rxon->reserved5 = 0;
1789 		rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd),
1790 				     &il->active);
1791 
1792 		/* If the mask clearing failed then we set
1793 		 * active_rxon back to what it was previously */
1794 		if (rc) {
1795 			active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1796 			IL_ERR("Error clearing ASSOC_MSK on current "
1797 			       "configuration (%d).\n", rc);
1798 			return rc;
1799 		}
1800 		il_clear_ucode_stations(il);
1801 		il_restore_stations(il);
1802 	}
1803 
1804 	D_INFO("Sending RXON\n" "* with%s RXON_FILTER_ASSOC_MSK\n"
1805 	       "* channel = %d\n" "* bssid = %pM\n", (new_assoc ? "" : "out"),
1806 	       le16_to_cpu(staging_rxon->channel), staging_rxon->bssid_addr);
1807 
1808 	/*
1809 	 * reserved4 and 5 could have been filled by the iwlcore code.
1810 	 * Let's clear them before pushing to the 3945.
1811 	 */
1812 	staging_rxon->reserved4 = 0;
1813 	staging_rxon->reserved5 = 0;
1814 
1815 	il_set_rxon_hwcrypto(il, !il3945_mod_params.sw_crypto);
1816 
1817 	/* Apply the new configuration */
1818 	rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd),
1819 			     staging_rxon);
1820 	if (rc) {
1821 		IL_ERR("Error setting new configuration (%d).\n", rc);
1822 		return rc;
1823 	}
1824 
1825 	memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1826 
1827 	if (!new_assoc) {
1828 		il_clear_ucode_stations(il);
1829 		il_restore_stations(il);
1830 	}
1831 
1832 	/* If we issue a new RXON command which required a tune then we must
1833 	 * send a new TXPOWER command or we won't be able to Tx any frames */
1834 	rc = il_set_tx_power(il, il->tx_power_next, true);
1835 	if (rc) {
1836 		IL_ERR("Error setting Tx power (%d).\n", rc);
1837 		return rc;
1838 	}
1839 
1840 	/* Init the hardware's rate fallback order based on the band */
1841 	rc = il3945_init_hw_rate_table(il);
1842 	if (rc) {
1843 		IL_ERR("Error setting HW rate table: %02X\n", rc);
1844 		return -EIO;
1845 	}
1846 
1847 	return 0;
1848 }
1849 
1850 /**
1851  * il3945_reg_txpower_periodic -  called when time to check our temperature.
1852  *
1853  * -- reset periodic timer
1854  * -- see if temp has changed enough to warrant re-calibration ... if so:
1855  *     -- correct coeffs for temp (can reset temp timer)
1856  *     -- save this temp as "last",
1857  *     -- send new set of gain settings to NIC
1858  * NOTE:  This should continue working, even when we're not associated,
1859  *   so we can keep our internal table of scan powers current. */
1860 void
1861 il3945_reg_txpower_periodic(struct il_priv *il)
1862 {
1863 	/* This will kick in the "brute force"
1864 	 * il3945_hw_reg_comp_txpower_temp() below */
1865 	if (!il3945_is_temp_calib_needed(il))
1866 		goto reschedule;
1867 
1868 	/* Set up a new set of temp-adjusted TxPowers, send to NIC.
1869 	 * This is based *only* on current temperature,
1870 	 * ignoring any previous power measurements */
1871 	il3945_hw_reg_comp_txpower_temp(il);
1872 
1873 reschedule:
1874 	queue_delayed_work(il->workqueue, &il->_3945.thermal_periodic,
1875 			   REG_RECALIB_PERIOD * HZ);
1876 }
1877 
1878 static void
1879 il3945_bg_reg_txpower_periodic(struct work_struct *work)
1880 {
1881 	struct il_priv *il = container_of(work, struct il_priv,
1882 					  _3945.thermal_periodic.work);
1883 
1884 	mutex_lock(&il->mutex);
1885 	if (test_bit(S_EXIT_PENDING, &il->status) || il->txq == NULL)
1886 		goto out;
1887 
1888 	il3945_reg_txpower_periodic(il);
1889 out:
1890 	mutex_unlock(&il->mutex);
1891 }
1892 
1893 /**
1894  * il3945_hw_reg_get_ch_grp_idx - find the channel-group idx (0-4) for channel.
1895  *
1896  * This function is used when initializing channel-info structs.
1897  *
1898  * NOTE: These channel groups do *NOT* match the bands above!
1899  *	 These channel groups are based on factory-tested channels;
1900  *	 on A-band, EEPROM's "group frequency" entries represent the top
1901  *	 channel in each group 1-4.  Group 5 All B/G channels are in group 0.
1902  */
1903 static u16
1904 il3945_hw_reg_get_ch_grp_idx(struct il_priv *il,
1905 			     const struct il_channel_info *ch_info)
1906 {
1907 	struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1908 	struct il3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1909 	u8 group;
1910 	u16 group_idx = 0;	/* based on factory calib frequencies */
1911 	u8 grp_channel;
1912 
1913 	/* Find the group idx for the channel ... don't use idx 1(?) */
1914 	if (il_is_channel_a_band(ch_info)) {
1915 		for (group = 1; group < 5; group++) {
1916 			grp_channel = ch_grp[group].group_channel;
1917 			if (ch_info->channel <= grp_channel) {
1918 				group_idx = group;
1919 				break;
1920 			}
1921 		}
1922 		/* group 4 has a few channels *above* its factory cal freq */
1923 		if (group == 5)
1924 			group_idx = 4;
1925 	} else
1926 		group_idx = 0;	/* 2.4 GHz, group 0 */
1927 
1928 	D_POWER("Chnl %d mapped to grp %d\n", ch_info->channel, group_idx);
1929 	return group_idx;
1930 }
1931 
1932 /**
1933  * il3945_hw_reg_get_matched_power_idx - Interpolate to get nominal idx
1934  *
1935  * Interpolate to get nominal (i.e. at factory calibration temperature) idx
1936  *   into radio/DSP gain settings table for requested power.
1937  */
1938 static int
1939 il3945_hw_reg_get_matched_power_idx(struct il_priv *il, s8 requested_power,
1940 				    s32 setting_idx, s32 *new_idx)
1941 {
1942 	const struct il3945_eeprom_txpower_group *chnl_grp = NULL;
1943 	struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1944 	s32 idx0, idx1;
1945 	s32 power = 2 * requested_power;
1946 	s32 i;
1947 	const struct il3945_eeprom_txpower_sample *samples;
1948 	s32 gains0, gains1;
1949 	s32 res;
1950 	s32 denominator;
1951 
1952 	chnl_grp = &eeprom->groups[setting_idx];
1953 	samples = chnl_grp->samples;
1954 	for (i = 0; i < 5; i++) {
1955 		if (power == samples[i].power) {
1956 			*new_idx = samples[i].gain_idx;
1957 			return 0;
1958 		}
1959 	}
1960 
1961 	if (power > samples[1].power) {
1962 		idx0 = 0;
1963 		idx1 = 1;
1964 	} else if (power > samples[2].power) {
1965 		idx0 = 1;
1966 		idx1 = 2;
1967 	} else if (power > samples[3].power) {
1968 		idx0 = 2;
1969 		idx1 = 3;
1970 	} else {
1971 		idx0 = 3;
1972 		idx1 = 4;
1973 	}
1974 
1975 	denominator = (s32) samples[idx1].power - (s32) samples[idx0].power;
1976 	if (denominator == 0)
1977 		return -EINVAL;
1978 	gains0 = (s32) samples[idx0].gain_idx * (1 << 19);
1979 	gains1 = (s32) samples[idx1].gain_idx * (1 << 19);
1980 	res =
1981 	    gains0 + (gains1 - gains0) * ((s32) power -
1982 					  (s32) samples[idx0].power) /
1983 	    denominator + (1 << 18);
1984 	*new_idx = res >> 19;
1985 	return 0;
1986 }
1987 
1988 static void
1989 il3945_hw_reg_init_channel_groups(struct il_priv *il)
1990 {
1991 	u32 i;
1992 	s32 rate_idx;
1993 	struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1994 	const struct il3945_eeprom_txpower_group *group;
1995 
1996 	D_POWER("Initializing factory calib info from EEPROM\n");
1997 
1998 	for (i = 0; i < IL_NUM_TX_CALIB_GROUPS; i++) {
1999 		s8 *clip_pwrs;	/* table of power levels for each rate */
2000 		s8 satur_pwr;	/* saturation power for each chnl group */
2001 		group = &eeprom->groups[i];
2002 
2003 		/* sanity check on factory saturation power value */
2004 		if (group->saturation_power < 40) {
2005 			IL_WARN("Error: saturation power is %d, "
2006 				"less than minimum expected 40\n",
2007 				group->saturation_power);
2008 			return;
2009 		}
2010 
2011 		/*
2012 		 * Derive requested power levels for each rate, based on
2013 		 *   hardware capabilities (saturation power for band).
2014 		 * Basic value is 3dB down from saturation, with further
2015 		 *   power reductions for highest 3 data rates.  These
2016 		 *   backoffs provide headroom for high rate modulation
2017 		 *   power peaks, without too much distortion (clipping).
2018 		 */
2019 		/* we'll fill in this array with h/w max power levels */
2020 		clip_pwrs = (s8 *) il->_3945.clip_groups[i].clip_powers;
2021 
2022 		/* divide factory saturation power by 2 to find -3dB level */
2023 		satur_pwr = (s8) (group->saturation_power >> 1);
2024 
2025 		/* fill in channel group's nominal powers for each rate */
2026 		for (rate_idx = 0; rate_idx < RATE_COUNT_3945;
2027 		     rate_idx++, clip_pwrs++) {
2028 			switch (rate_idx) {
2029 			case RATE_36M_IDX_TBL:
2030 				if (i == 0)	/* B/G */
2031 					*clip_pwrs = satur_pwr;
2032 				else	/* A */
2033 					*clip_pwrs = satur_pwr - 5;
2034 				break;
2035 			case RATE_48M_IDX_TBL:
2036 				if (i == 0)
2037 					*clip_pwrs = satur_pwr - 7;
2038 				else
2039 					*clip_pwrs = satur_pwr - 10;
2040 				break;
2041 			case RATE_54M_IDX_TBL:
2042 				if (i == 0)
2043 					*clip_pwrs = satur_pwr - 9;
2044 				else
2045 					*clip_pwrs = satur_pwr - 12;
2046 				break;
2047 			default:
2048 				*clip_pwrs = satur_pwr;
2049 				break;
2050 			}
2051 		}
2052 	}
2053 }
2054 
2055 /**
2056  * il3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2057  *
2058  * Second pass (during init) to set up il->channel_info
2059  *
2060  * Set up Tx-power settings in our channel info database for each VALID
2061  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2062  * and current temperature.
2063  *
2064  * Since this is based on current temperature (at init time), these values may
2065  * not be valid for very long, but it gives us a starting/default point,
2066  * and allows us to active (i.e. using Tx) scan.
2067  *
2068  * This does *not* write values to NIC, just sets up our internal table.
2069  */
2070 int
2071 il3945_txpower_set_from_eeprom(struct il_priv *il)
2072 {
2073 	struct il_channel_info *ch_info = NULL;
2074 	struct il3945_channel_power_info *pwr_info;
2075 	struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
2076 	int delta_idx;
2077 	u8 rate_idx;
2078 	u8 scan_tbl_idx;
2079 	const s8 *clip_pwrs;	/* array of power levels for each rate */
2080 	u8 gain, dsp_atten;
2081 	s8 power;
2082 	u8 pwr_idx, base_pwr_idx, a_band;
2083 	u8 i;
2084 	int temperature;
2085 
2086 	/* save temperature reference,
2087 	 *   so we can determine next time to calibrate */
2088 	temperature = il3945_hw_reg_txpower_get_temperature(il);
2089 	il->last_temperature = temperature;
2090 
2091 	il3945_hw_reg_init_channel_groups(il);
2092 
2093 	/* initialize Tx power info for each and every channel, 2.4 and 5.x */
2094 	for (i = 0, ch_info = il->channel_info; i < il->channel_count;
2095 	     i++, ch_info++) {
2096 		a_band = il_is_channel_a_band(ch_info);
2097 		if (!il_is_channel_valid(ch_info))
2098 			continue;
2099 
2100 		/* find this channel's channel group (*not* "band") idx */
2101 		ch_info->group_idx = il3945_hw_reg_get_ch_grp_idx(il, ch_info);
2102 
2103 		/* Get this chnlgrp's rate->max/clip-powers table */
2104 		clip_pwrs =
2105 		    il->_3945.clip_groups[ch_info->group_idx].clip_powers;
2106 
2107 		/* calculate power idx *adjustment* value according to
2108 		 *  diff between current temperature and factory temperature */
2109 		delta_idx =
2110 		    il3945_hw_reg_adjust_power_by_temp(temperature,
2111 						       eeprom->groups[ch_info->
2112 								      group_idx].
2113 						       temperature);
2114 
2115 		D_POWER("Delta idx for channel %d: %d [%d]\n", ch_info->channel,
2116 			delta_idx, temperature + IL_TEMP_CONVERT);
2117 
2118 		/* set tx power value for all OFDM rates */
2119 		for (rate_idx = 0; rate_idx < IL_OFDM_RATES; rate_idx++) {
2120 			s32 uninitialized_var(power_idx);
2121 			int rc;
2122 
2123 			/* use channel group's clip-power table,
2124 			 *   but don't exceed channel's max power */
2125 			s8 pwr = min(ch_info->max_power_avg,
2126 				     clip_pwrs[rate_idx]);
2127 
2128 			pwr_info = &ch_info->power_info[rate_idx];
2129 
2130 			/* get base (i.e. at factory-measured temperature)
2131 			 *    power table idx for this rate's power */
2132 			rc = il3945_hw_reg_get_matched_power_idx(il, pwr,
2133 								 ch_info->
2134 								 group_idx,
2135 								 &power_idx);
2136 			if (rc) {
2137 				IL_ERR("Invalid power idx\n");
2138 				return rc;
2139 			}
2140 			pwr_info->base_power_idx = (u8) power_idx;
2141 
2142 			/* temperature compensate */
2143 			power_idx += delta_idx;
2144 
2145 			/* stay within range of gain table */
2146 			power_idx = il3945_hw_reg_fix_power_idx(power_idx);
2147 
2148 			/* fill 1 OFDM rate's il3945_channel_power_info struct */
2149 			pwr_info->requested_power = pwr;
2150 			pwr_info->power_table_idx = (u8) power_idx;
2151 			pwr_info->tpc.tx_gain =
2152 			    power_gain_table[a_band][power_idx].tx_gain;
2153 			pwr_info->tpc.dsp_atten =
2154 			    power_gain_table[a_band][power_idx].dsp_atten;
2155 		}
2156 
2157 		/* set tx power for CCK rates, based on OFDM 12 Mbit settings */
2158 		pwr_info = &ch_info->power_info[RATE_12M_IDX_TBL];
2159 		power = pwr_info->requested_power + IL_CCK_FROM_OFDM_POWER_DIFF;
2160 		pwr_idx = pwr_info->power_table_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
2161 		base_pwr_idx =
2162 		    pwr_info->base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
2163 
2164 		/* stay within table range */
2165 		pwr_idx = il3945_hw_reg_fix_power_idx(pwr_idx);
2166 		gain = power_gain_table[a_band][pwr_idx].tx_gain;
2167 		dsp_atten = power_gain_table[a_band][pwr_idx].dsp_atten;
2168 
2169 		/* fill each CCK rate's il3945_channel_power_info structure
2170 		 * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2171 		 * NOTE:  CCK rates start at end of OFDM rates! */
2172 		for (rate_idx = 0; rate_idx < IL_CCK_RATES; rate_idx++) {
2173 			pwr_info =
2174 			    &ch_info->power_info[rate_idx + IL_OFDM_RATES];
2175 			pwr_info->requested_power = power;
2176 			pwr_info->power_table_idx = pwr_idx;
2177 			pwr_info->base_power_idx = base_pwr_idx;
2178 			pwr_info->tpc.tx_gain = gain;
2179 			pwr_info->tpc.dsp_atten = dsp_atten;
2180 		}
2181 
2182 		/* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2183 		for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES;
2184 		     scan_tbl_idx++) {
2185 			s32 actual_idx =
2186 			    (scan_tbl_idx ==
2187 			     0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL;
2188 			il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
2189 						     actual_idx, clip_pwrs,
2190 						     ch_info, a_band);
2191 		}
2192 	}
2193 
2194 	return 0;
2195 }
2196 
2197 int
2198 il3945_hw_rxq_stop(struct il_priv *il)
2199 {
2200 	int ret;
2201 
2202 	_il_wr(il, FH39_RCSR_CONFIG(0), 0);
2203 	ret = _il_poll_bit(il, FH39_RSSR_STATUS,
2204 			   FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
2205 			   FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
2206 			   1000);
2207 	if (ret < 0)
2208 		IL_ERR("Can't stop Rx DMA.\n");
2209 
2210 	return 0;
2211 }
2212 
2213 int
2214 il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
2215 {
2216 	int txq_id = txq->q.id;
2217 
2218 	struct il3945_shared *shared_data = il->_3945.shared_virt;
2219 
2220 	shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32) txq->q.dma_addr);
2221 
2222 	il_wr(il, FH39_CBCC_CTRL(txq_id), 0);
2223 	il_wr(il, FH39_CBCC_BASE(txq_id), 0);
2224 
2225 	il_wr(il, FH39_TCSR_CONFIG(txq_id),
2226 	      FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2227 	      FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2228 	      FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2229 	      FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2230 	      FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2231 
2232 	/* fake read to flush all prev. writes */
2233 	_il_rd(il, FH39_TSSR_CBB_BASE);
2234 
2235 	return 0;
2236 }
2237 
2238 /*
2239  * HCMD utils
2240  */
2241 static u16
2242 il3945_get_hcmd_size(u8 cmd_id, u16 len)
2243 {
2244 	switch (cmd_id) {
2245 	case C_RXON:
2246 		return sizeof(struct il3945_rxon_cmd);
2247 	case C_POWER_TBL:
2248 		return sizeof(struct il3945_powertable_cmd);
2249 	default:
2250 		return len;
2251 	}
2252 }
2253 
2254 static u16
2255 il3945_build_addsta_hcmd(const struct il_addsta_cmd *cmd, u8 * data)
2256 {
2257 	struct il3945_addsta_cmd *addsta = (struct il3945_addsta_cmd *)data;
2258 	addsta->mode = cmd->mode;
2259 	memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2260 	memcpy(&addsta->key, &cmd->key, sizeof(struct il4965_keyinfo));
2261 	addsta->station_flags = cmd->station_flags;
2262 	addsta->station_flags_msk = cmd->station_flags_msk;
2263 	addsta->tid_disable_tx = cpu_to_le16(0);
2264 	addsta->rate_n_flags = cmd->rate_n_flags;
2265 	addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2266 	addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2267 	addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2268 
2269 	return (u16) sizeof(struct il3945_addsta_cmd);
2270 }
2271 
2272 static int
2273 il3945_add_bssid_station(struct il_priv *il, const u8 * addr, u8 * sta_id_r)
2274 {
2275 	int ret;
2276 	u8 sta_id;
2277 	unsigned long flags;
2278 
2279 	if (sta_id_r)
2280 		*sta_id_r = IL_INVALID_STATION;
2281 
2282 	ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
2283 	if (ret) {
2284 		IL_ERR("Unable to add station %pM\n", addr);
2285 		return ret;
2286 	}
2287 
2288 	if (sta_id_r)
2289 		*sta_id_r = sta_id;
2290 
2291 	spin_lock_irqsave(&il->sta_lock, flags);
2292 	il->stations[sta_id].used |= IL_STA_LOCAL;
2293 	spin_unlock_irqrestore(&il->sta_lock, flags);
2294 
2295 	return 0;
2296 }
2297 
2298 static int
2299 il3945_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
2300 			   bool add)
2301 {
2302 	struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
2303 	int ret;
2304 
2305 	if (add) {
2306 		ret =
2307 		    il3945_add_bssid_station(il, vif->bss_conf.bssid,
2308 					     &vif_priv->ibss_bssid_sta_id);
2309 		if (ret)
2310 			return ret;
2311 
2312 		il3945_sync_sta(il, vif_priv->ibss_bssid_sta_id,
2313 				(il->band ==
2314 				 NL80211_BAND_5GHZ) ? RATE_6M_PLCP :
2315 				RATE_1M_PLCP);
2316 		il3945_rate_scale_init(il->hw, vif_priv->ibss_bssid_sta_id);
2317 
2318 		return 0;
2319 	}
2320 
2321 	return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
2322 				 vif->bss_conf.bssid);
2323 }
2324 
2325 /**
2326  * il3945_init_hw_rate_table - Initialize the hardware rate fallback table
2327  */
2328 int
2329 il3945_init_hw_rate_table(struct il_priv *il)
2330 {
2331 	int rc, i, idx, prev_idx;
2332 	struct il3945_rate_scaling_cmd rate_cmd = {
2333 		.reserved = {0, 0, 0},
2334 	};
2335 	struct il3945_rate_scaling_info *table = rate_cmd.table;
2336 
2337 	for (i = 0; i < ARRAY_SIZE(il3945_rates); i++) {
2338 		idx = il3945_rates[i].table_rs_idx;
2339 
2340 		table[idx].rate_n_flags = cpu_to_le16(il3945_rates[i].plcp);
2341 		table[idx].try_cnt = il->retry_rate;
2342 		prev_idx = il3945_get_prev_ieee_rate(i);
2343 		table[idx].next_rate_idx = il3945_rates[prev_idx].table_rs_idx;
2344 	}
2345 
2346 	switch (il->band) {
2347 	case NL80211_BAND_5GHZ:
2348 		D_RATE("Select A mode rate scale\n");
2349 		/* If one of the following CCK rates is used,
2350 		 * have it fall back to the 6M OFDM rate */
2351 		for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++)
2352 			table[i].next_rate_idx =
2353 			    il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx;
2354 
2355 		/* Don't fall back to CCK rates */
2356 		table[RATE_12M_IDX_TBL].next_rate_idx = RATE_9M_IDX_TBL;
2357 
2358 		/* Don't drop out of OFDM rates */
2359 		table[RATE_6M_IDX_TBL].next_rate_idx =
2360 		    il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx;
2361 		break;
2362 
2363 	case NL80211_BAND_2GHZ:
2364 		D_RATE("Select B/G mode rate scale\n");
2365 		/* If an OFDM rate is used, have it fall back to the
2366 		 * 1M CCK rates */
2367 
2368 		if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
2369 		    il_is_associated(il)) {
2370 
2371 			idx = IL_FIRST_CCK_RATE;
2372 			for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++)
2373 				table[i].next_rate_idx =
2374 				    il3945_rates[idx].table_rs_idx;
2375 
2376 			idx = RATE_11M_IDX_TBL;
2377 			/* CCK shouldn't fall back to OFDM... */
2378 			table[idx].next_rate_idx = RATE_5M_IDX_TBL;
2379 		}
2380 		break;
2381 
2382 	default:
2383 		WARN_ON(1);
2384 		break;
2385 	}
2386 
2387 	/* Update the rate scaling for control frame Tx */
2388 	rate_cmd.table_id = 0;
2389 	rc = il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd);
2390 	if (rc)
2391 		return rc;
2392 
2393 	/* Update the rate scaling for data frame Tx */
2394 	rate_cmd.table_id = 1;
2395 	return il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd);
2396 }
2397 
2398 /* Called when initializing driver */
2399 int
2400 il3945_hw_set_hw_params(struct il_priv *il)
2401 {
2402 	memset((void *)&il->hw_params, 0, sizeof(struct il_hw_params));
2403 
2404 	il->_3945.shared_virt =
2405 	    dma_alloc_coherent(&il->pci_dev->dev, sizeof(struct il3945_shared),
2406 			       &il->_3945.shared_phys, GFP_KERNEL);
2407 	if (!il->_3945.shared_virt)
2408 		return -ENOMEM;
2409 
2410 	il->hw_params.bcast_id = IL3945_BROADCAST_ID;
2411 
2412 	/* Assign number of Usable TX queues */
2413 	il->hw_params.max_txq_num = il->cfg->num_of_queues;
2414 
2415 	il->hw_params.tfd_size = sizeof(struct il3945_tfd);
2416 	il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_3K);
2417 	il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2418 	il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2419 	il->hw_params.max_stations = IL3945_STATION_COUNT;
2420 
2421 	il->sta_key_max_num = STA_KEY_MAX_NUM;
2422 
2423 	il->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2424 	il->hw_params.max_beacon_itrvl = IL39_MAX_UCODE_BEACON_INTERVAL;
2425 	il->hw_params.beacon_time_tsf_bits = IL3945_EXT_BEACON_TIME_POS;
2426 
2427 	return 0;
2428 }
2429 
2430 unsigned int
2431 il3945_hw_get_beacon_cmd(struct il_priv *il, struct il3945_frame *frame,
2432 			 u8 rate)
2433 {
2434 	struct il3945_tx_beacon_cmd *tx_beacon_cmd;
2435 	unsigned int frame_size;
2436 
2437 	tx_beacon_cmd = (struct il3945_tx_beacon_cmd *)&frame->u;
2438 	memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2439 
2440 	tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
2441 	tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2442 
2443 	frame_size =
2444 	    il3945_fill_beacon_frame(il, tx_beacon_cmd->frame,
2445 				     sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2446 
2447 	BUG_ON(frame_size > MAX_MPDU_SIZE);
2448 	tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
2449 
2450 	tx_beacon_cmd->tx.rate = rate;
2451 	tx_beacon_cmd->tx.tx_flags =
2452 	    (TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK);
2453 
2454 	/* supp_rates[0] == OFDM start at IL_FIRST_OFDM_RATE */
2455 	tx_beacon_cmd->tx.supp_rates[0] =
2456 	    (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
2457 
2458 	tx_beacon_cmd->tx.supp_rates[1] = (IL_CCK_BASIC_RATES_MASK & 0xF);
2459 
2460 	return sizeof(struct il3945_tx_beacon_cmd) + frame_size;
2461 }
2462 
2463 void
2464 il3945_hw_handler_setup(struct il_priv *il)
2465 {
2466 	il->handlers[C_TX] = il3945_hdl_tx;
2467 	il->handlers[N_3945_RX] = il3945_hdl_rx;
2468 }
2469 
2470 void
2471 il3945_hw_setup_deferred_work(struct il_priv *il)
2472 {
2473 	INIT_DELAYED_WORK(&il->_3945.thermal_periodic,
2474 			  il3945_bg_reg_txpower_periodic);
2475 }
2476 
2477 void
2478 il3945_hw_cancel_deferred_work(struct il_priv *il)
2479 {
2480 	cancel_delayed_work(&il->_3945.thermal_periodic);
2481 }
2482 
2483 /* check contents of special bootstrap uCode SRAM */
2484 static int
2485 il3945_verify_bsm(struct il_priv *il)
2486 {
2487 	__le32 *image = il->ucode_boot.v_addr;
2488 	u32 len = il->ucode_boot.len;
2489 	u32 reg;
2490 	u32 val;
2491 
2492 	D_INFO("Begin verify bsm\n");
2493 
2494 	/* verify BSM SRAM contents */
2495 	val = il_rd_prph(il, BSM_WR_DWCOUNT_REG);
2496 	for (reg = BSM_SRAM_LOWER_BOUND; reg < BSM_SRAM_LOWER_BOUND + len;
2497 	     reg += sizeof(u32), image++) {
2498 		val = il_rd_prph(il, reg);
2499 		if (val != le32_to_cpu(*image)) {
2500 			IL_ERR("BSM uCode verification failed at "
2501 			       "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2502 			       BSM_SRAM_LOWER_BOUND, reg - BSM_SRAM_LOWER_BOUND,
2503 			       len, val, le32_to_cpu(*image));
2504 			return -EIO;
2505 		}
2506 	}
2507 
2508 	D_INFO("BSM bootstrap uCode image OK\n");
2509 
2510 	return 0;
2511 }
2512 
2513 /******************************************************************************
2514  *
2515  * EEPROM related functions
2516  *
2517  ******************************************************************************/
2518 
2519 /*
2520  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2521  * embedded controller) as EEPROM reader; each read is a series of pulses
2522  * to/from the EEPROM chip, not a single event, so even reads could conflict
2523  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2524  * simply claims ownership, which should be safe when this function is called
2525  * (i.e. before loading uCode!).
2526  */
2527 static int
2528 il3945_eeprom_acquire_semaphore(struct il_priv *il)
2529 {
2530 	_il_clear_bit(il, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2531 	return 0;
2532 }
2533 
2534 static void
2535 il3945_eeprom_release_semaphore(struct il_priv *il)
2536 {
2537 	return;
2538 }
2539 
2540  /**
2541   * il3945_load_bsm - Load bootstrap instructions
2542   *
2543   * BSM operation:
2544   *
2545   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2546   * in special SRAM that does not power down during RFKILL.  When powering back
2547   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2548   * the bootstrap program into the on-board processor, and starts it.
2549   *
2550   * The bootstrap program loads (via DMA) instructions and data for a new
2551   * program from host DRAM locations indicated by the host driver in the
2552   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2553   * automatically.
2554   *
2555   * When initializing the NIC, the host driver points the BSM to the
2556   * "initialize" uCode image.  This uCode sets up some internal data, then
2557   * notifies host via "initialize alive" that it is complete.
2558   *
2559   * The host then replaces the BSM_DRAM_* pointer values to point to the
2560   * normal runtime uCode instructions and a backup uCode data cache buffer
2561   * (filled initially with starting data values for the on-board processor),
2562   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2563   * which begins normal operation.
2564   *
2565   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2566   * the backup data cache in DRAM before SRAM is powered down.
2567   *
2568   * When powering back up, the BSM loads the bootstrap program.  This reloads
2569   * the runtime uCode instructions and the backup data cache into SRAM,
2570   * and re-launches the runtime uCode from where it left off.
2571   */
2572 static int
2573 il3945_load_bsm(struct il_priv *il)
2574 {
2575 	__le32 *image = il->ucode_boot.v_addr;
2576 	u32 len = il->ucode_boot.len;
2577 	dma_addr_t pinst;
2578 	dma_addr_t pdata;
2579 	u32 inst_len;
2580 	u32 data_len;
2581 	int rc;
2582 	int i;
2583 	u32 done;
2584 	u32 reg_offset;
2585 
2586 	D_INFO("Begin load bsm\n");
2587 
2588 	/* make sure bootstrap program is no larger than BSM's SRAM size */
2589 	if (len > IL39_MAX_BSM_SIZE)
2590 		return -EINVAL;
2591 
2592 	/* Tell bootstrap uCode where to find the "Initialize" uCode
2593 	 *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2594 	 * NOTE:  il3945_initialize_alive_start() will replace these values,
2595 	 *        after the "initialize" uCode has run, to point to
2596 	 *        runtime/protocol instructions and backup data cache. */
2597 	pinst = il->ucode_init.p_addr;
2598 	pdata = il->ucode_init_data.p_addr;
2599 	inst_len = il->ucode_init.len;
2600 	data_len = il->ucode_init_data.len;
2601 
2602 	il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2603 	il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2604 	il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2605 	il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2606 
2607 	/* Fill BSM memory with bootstrap instructions */
2608 	for (reg_offset = BSM_SRAM_LOWER_BOUND;
2609 	     reg_offset < BSM_SRAM_LOWER_BOUND + len;
2610 	     reg_offset += sizeof(u32), image++)
2611 		_il_wr_prph(il, reg_offset, le32_to_cpu(*image));
2612 
2613 	rc = il3945_verify_bsm(il);
2614 	if (rc)
2615 		return rc;
2616 
2617 	/* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2618 	il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
2619 	il_wr_prph(il, BSM_WR_MEM_DST_REG, IL39_RTC_INST_LOWER_BOUND);
2620 	il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2621 
2622 	/* Load bootstrap code into instruction SRAM now,
2623 	 *   to prepare to load "initialize" uCode */
2624 	il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
2625 
2626 	/* Wait for load of bootstrap uCode to finish */
2627 	for (i = 0; i < 100; i++) {
2628 		done = il_rd_prph(il, BSM_WR_CTRL_REG);
2629 		if (!(done & BSM_WR_CTRL_REG_BIT_START))
2630 			break;
2631 		udelay(10);
2632 	}
2633 	if (i < 100)
2634 		D_INFO("BSM write complete, poll %d iterations\n", i);
2635 	else {
2636 		IL_ERR("BSM write did not complete!\n");
2637 		return -EIO;
2638 	}
2639 
2640 	/* Enable future boot loads whenever power management unit triggers it
2641 	 *   (e.g. when powering back up after power-save shutdown) */
2642 	il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
2643 
2644 	return 0;
2645 }
2646 
2647 const struct il_ops il3945_ops = {
2648 	.txq_attach_buf_to_tfd = il3945_hw_txq_attach_buf_to_tfd,
2649 	.txq_free_tfd = il3945_hw_txq_free_tfd,
2650 	.txq_init = il3945_hw_tx_queue_init,
2651 	.load_ucode = il3945_load_bsm,
2652 	.dump_nic_error_log = il3945_dump_nic_error_log,
2653 	.apm_init = il3945_apm_init,
2654 	.send_tx_power = il3945_send_tx_power,
2655 	.is_valid_rtc_data_addr = il3945_hw_valid_rtc_data_addr,
2656 	.eeprom_acquire_semaphore = il3945_eeprom_acquire_semaphore,
2657 	.eeprom_release_semaphore = il3945_eeprom_release_semaphore,
2658 
2659 	.rxon_assoc = il3945_send_rxon_assoc,
2660 	.commit_rxon = il3945_commit_rxon,
2661 
2662 	.get_hcmd_size = il3945_get_hcmd_size,
2663 	.build_addsta_hcmd = il3945_build_addsta_hcmd,
2664 	.request_scan = il3945_request_scan,
2665 	.post_scan = il3945_post_scan,
2666 
2667 	.post_associate = il3945_post_associate,
2668 	.config_ap = il3945_config_ap,
2669 	.manage_ibss_station = il3945_manage_ibss_station,
2670 
2671 	.send_led_cmd = il3945_send_led_cmd,
2672 };
2673 
2674 static const struct il_cfg il3945_bg_cfg = {
2675 	.name = "3945BG",
2676 	.fw_name_pre = IL3945_FW_PRE,
2677 	.ucode_api_max = IL3945_UCODE_API_MAX,
2678 	.ucode_api_min = IL3945_UCODE_API_MIN,
2679 	.sku = IL_SKU_G,
2680 	.eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2681 	.mod_params = &il3945_mod_params,
2682 	.led_mode = IL_LED_BLINK,
2683 
2684 	.eeprom_size = IL3945_EEPROM_IMG_SIZE,
2685 	.num_of_queues = IL39_NUM_QUEUES,
2686 	.pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2687 	.set_l0s = false,
2688 	.use_bsm = true,
2689 	.led_compensation = 64,
2690 	.wd_timeout = IL_DEF_WD_TIMEOUT,
2691 
2692 	.regulatory_bands = {
2693 		EEPROM_REGULATORY_BAND_1_CHANNELS,
2694 		EEPROM_REGULATORY_BAND_2_CHANNELS,
2695 		EEPROM_REGULATORY_BAND_3_CHANNELS,
2696 		EEPROM_REGULATORY_BAND_4_CHANNELS,
2697 		EEPROM_REGULATORY_BAND_5_CHANNELS,
2698 		EEPROM_REGULATORY_BAND_NO_HT40,
2699 		EEPROM_REGULATORY_BAND_NO_HT40,
2700 	},
2701 };
2702 
2703 static const struct il_cfg il3945_abg_cfg = {
2704 	.name = "3945ABG",
2705 	.fw_name_pre = IL3945_FW_PRE,
2706 	.ucode_api_max = IL3945_UCODE_API_MAX,
2707 	.ucode_api_min = IL3945_UCODE_API_MIN,
2708 	.sku = IL_SKU_A | IL_SKU_G,
2709 	.eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2710 	.mod_params = &il3945_mod_params,
2711 	.led_mode = IL_LED_BLINK,
2712 
2713 	.eeprom_size = IL3945_EEPROM_IMG_SIZE,
2714 	.num_of_queues = IL39_NUM_QUEUES,
2715 	.pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2716 	.set_l0s = false,
2717 	.use_bsm = true,
2718 	.led_compensation = 64,
2719 	.wd_timeout = IL_DEF_WD_TIMEOUT,
2720 
2721 	.regulatory_bands = {
2722 		EEPROM_REGULATORY_BAND_1_CHANNELS,
2723 		EEPROM_REGULATORY_BAND_2_CHANNELS,
2724 		EEPROM_REGULATORY_BAND_3_CHANNELS,
2725 		EEPROM_REGULATORY_BAND_4_CHANNELS,
2726 		EEPROM_REGULATORY_BAND_5_CHANNELS,
2727 		EEPROM_REGULATORY_BAND_NO_HT40,
2728 		EEPROM_REGULATORY_BAND_NO_HT40,
2729 	},
2730 };
2731 
2732 const struct pci_device_id il3945_hw_card_ids[] = {
2733 	{IL_PCI_DEVICE(0x4222, 0x1005, il3945_bg_cfg)},
2734 	{IL_PCI_DEVICE(0x4222, 0x1034, il3945_bg_cfg)},
2735 	{IL_PCI_DEVICE(0x4222, 0x1044, il3945_bg_cfg)},
2736 	{IL_PCI_DEVICE(0x4227, 0x1014, il3945_bg_cfg)},
2737 	{IL_PCI_DEVICE(0x4222, PCI_ANY_ID, il3945_abg_cfg)},
2738 	{IL_PCI_DEVICE(0x4227, PCI_ANY_ID, il3945_abg_cfg)},
2739 	{0}
2740 };
2741 
2742 MODULE_DEVICE_TABLE(pci, il3945_hw_card_ids);
2743