1 /****************************************************************************** 2 3 Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved. 4 5 This program is free software; you can redistribute it and/or modify it 6 under the terms of version 2 of the GNU General Public License as 7 published by the Free Software Foundation. 8 9 This program is distributed in the hope that it will be useful, but WITHOUT 10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 more details. 13 14 You should have received a copy of the GNU General Public License along with 15 this program; if not, write to the Free Software Foundation, Inc., 59 16 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 18 The full GNU General Public License is included in this distribution in the 19 file called LICENSE. 20 21 Contact Information: 22 Intel Linux Wireless <ilw@linux.intel.com> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25 ******************************************************************************/ 26 27 #ifndef __ipw2200_h__ 28 #define __ipw2200_h__ 29 30 #include <linux/module.h> 31 #include <linux/moduleparam.h> 32 #include <linux/interrupt.h> 33 #include <linux/mutex.h> 34 35 #include <linux/pci.h> 36 #include <linux/netdevice.h> 37 #include <linux/ethtool.h> 38 #include <linux/skbuff.h> 39 #include <linux/etherdevice.h> 40 #include <linux/delay.h> 41 #include <linux/random.h> 42 #include <linux/dma-mapping.h> 43 44 #include <linux/firmware.h> 45 #include <linux/wireless.h> 46 #include <linux/jiffies.h> 47 #include <asm/io.h> 48 49 #include <net/lib80211.h> 50 #include <net/ieee80211_radiotap.h> 51 52 #define DRV_NAME "ipw2200" 53 54 #include <linux/workqueue.h> 55 56 #include "libipw.h" 57 58 /* Authentication and Association States */ 59 enum connection_manager_assoc_states { 60 CMAS_INIT = 0, 61 CMAS_TX_AUTH_SEQ_1, 62 CMAS_RX_AUTH_SEQ_2, 63 CMAS_AUTH_SEQ_1_PASS, 64 CMAS_AUTH_SEQ_1_FAIL, 65 CMAS_TX_AUTH_SEQ_3, 66 CMAS_RX_AUTH_SEQ_4, 67 CMAS_AUTH_SEQ_2_PASS, 68 CMAS_AUTH_SEQ_2_FAIL, 69 CMAS_AUTHENTICATED, 70 CMAS_TX_ASSOC, 71 CMAS_RX_ASSOC_RESP, 72 CMAS_ASSOCIATED, 73 CMAS_LAST 74 }; 75 76 #define IPW_WAIT (1<<0) 77 #define IPW_QUIET (1<<1) 78 #define IPW_ROAMING (1<<2) 79 80 #define IPW_POWER_MODE_CAM 0x00 //(always on) 81 #define IPW_POWER_INDEX_1 0x01 82 #define IPW_POWER_INDEX_2 0x02 83 #define IPW_POWER_INDEX_3 0x03 84 #define IPW_POWER_INDEX_4 0x04 85 #define IPW_POWER_INDEX_5 0x05 86 #define IPW_POWER_AC 0x06 87 #define IPW_POWER_BATTERY 0x07 88 #define IPW_POWER_LIMIT 0x07 89 #define IPW_POWER_MASK 0x0F 90 #define IPW_POWER_ENABLED 0x10 91 #define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK) 92 93 #define IPW_CMD_HOST_COMPLETE 2 94 #define IPW_CMD_POWER_DOWN 4 95 #define IPW_CMD_SYSTEM_CONFIG 6 96 #define IPW_CMD_MULTICAST_ADDRESS 7 97 #define IPW_CMD_SSID 8 98 #define IPW_CMD_ADAPTER_ADDRESS 11 99 #define IPW_CMD_PORT_TYPE 12 100 #define IPW_CMD_RTS_THRESHOLD 15 101 #define IPW_CMD_FRAG_THRESHOLD 16 102 #define IPW_CMD_POWER_MODE 17 103 #define IPW_CMD_WEP_KEY 18 104 #define IPW_CMD_TGI_TX_KEY 19 105 #define IPW_CMD_SCAN_REQUEST 20 106 #define IPW_CMD_ASSOCIATE 21 107 #define IPW_CMD_SUPPORTED_RATES 22 108 #define IPW_CMD_SCAN_ABORT 23 109 #define IPW_CMD_TX_FLUSH 24 110 #define IPW_CMD_QOS_PARAMETERS 25 111 #define IPW_CMD_SCAN_REQUEST_EXT 26 112 #define IPW_CMD_DINO_CONFIG 30 113 #define IPW_CMD_RSN_CAPABILITIES 31 114 #define IPW_CMD_RX_KEY 32 115 #define IPW_CMD_CARD_DISABLE 33 116 #define IPW_CMD_SEED_NUMBER 34 117 #define IPW_CMD_TX_POWER 35 118 #define IPW_CMD_COUNTRY_INFO 36 119 #define IPW_CMD_AIRONET_INFO 37 120 #define IPW_CMD_AP_TX_POWER 38 121 #define IPW_CMD_CCKM_INFO 39 122 #define IPW_CMD_CCX_VER_INFO 40 123 #define IPW_CMD_SET_CALIBRATION 41 124 #define IPW_CMD_SENSITIVITY_CALIB 42 125 #define IPW_CMD_RETRY_LIMIT 51 126 #define IPW_CMD_IPW_PRE_POWER_DOWN 58 127 #define IPW_CMD_VAP_BEACON_TEMPLATE 60 128 #define IPW_CMD_VAP_DTIM_PERIOD 61 129 #define IPW_CMD_EXT_SUPPORTED_RATES 62 130 #define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63 131 #define IPW_CMD_VAP_QUIET_INTERVALS 64 132 #define IPW_CMD_VAP_CHANNEL_SWITCH 65 133 #define IPW_CMD_VAP_MANDATORY_CHANNELS 66 134 #define IPW_CMD_VAP_CELL_PWR_LIMIT 67 135 #define IPW_CMD_VAP_CF_PARAM_SET 68 136 #define IPW_CMD_VAP_SET_BEACONING_STATE 69 137 #define IPW_CMD_MEASUREMENT 80 138 #define IPW_CMD_POWER_CAPABILITY 81 139 #define IPW_CMD_SUPPORTED_CHANNELS 82 140 #define IPW_CMD_TPC_REPORT 83 141 #define IPW_CMD_WME_INFO 84 142 #define IPW_CMD_PRODUCTION_COMMAND 85 143 #define IPW_CMD_LINKSYS_EOU_INFO 90 144 145 #define RFD_SIZE 4 146 #define NUM_TFD_CHUNKS 6 147 148 #define TX_QUEUE_SIZE 32 149 #define RX_QUEUE_SIZE 32 150 151 #define DINO_CMD_WEP_KEY 0x08 152 #define DINO_CMD_TX 0x0B 153 #define DCT_ANTENNA_A 0x01 154 #define DCT_ANTENNA_B 0x02 155 156 #define IPW_A_MODE 0 157 #define IPW_B_MODE 1 158 #define IPW_G_MODE 2 159 160 /* 161 * TX Queue Flag Definitions 162 */ 163 164 /* tx wep key definition */ 165 #define DCT_WEP_KEY_NOT_IMMIDIATE 0x00 166 #define DCT_WEP_KEY_64Bit 0x40 167 #define DCT_WEP_KEY_128Bit 0x80 168 #define DCT_WEP_KEY_128bitIV 0xC0 169 #define DCT_WEP_KEY_SIZE_MASK 0xC0 170 171 #define DCT_WEP_KEY_INDEX_MASK 0x0F 172 #define DCT_WEP_INDEX_USE_IMMEDIATE 0x20 173 174 /* abort attempt if mgmt frame is rx'd */ 175 #define DCT_FLAG_ABORT_MGMT 0x01 176 177 /* require CTS */ 178 #define DCT_FLAG_CTS_REQUIRED 0x02 179 180 /* use short preamble */ 181 #define DCT_FLAG_LONG_PREAMBLE 0x00 182 #define DCT_FLAG_SHORT_PREAMBLE 0x04 183 184 /* RTS/CTS first */ 185 #define DCT_FLAG_RTS_REQD 0x08 186 187 /* dont calculate duration field */ 188 #define DCT_FLAG_DUR_SET 0x10 189 190 /* even if MAC WEP set (allows pre-encrypt) */ 191 #define DCT_FLAG_NO_WEP 0x20 192 193 /* overwrite TSF field */ 194 #define DCT_FLAG_TSF_REQD 0x40 195 196 /* ACK rx is expected to follow */ 197 #define DCT_FLAG_ACK_REQD 0x80 198 199 /* TX flags extension */ 200 #define DCT_FLAG_EXT_MODE_CCK 0x01 201 #define DCT_FLAG_EXT_MODE_OFDM 0x00 202 203 #define DCT_FLAG_EXT_SECURITY_WEP 0x00 204 #define DCT_FLAG_EXT_SECURITY_NO DCT_FLAG_EXT_SECURITY_WEP 205 #define DCT_FLAG_EXT_SECURITY_CKIP 0x04 206 #define DCT_FLAG_EXT_SECURITY_CCM 0x08 207 #define DCT_FLAG_EXT_SECURITY_TKIP 0x0C 208 #define DCT_FLAG_EXT_SECURITY_MASK 0x0C 209 210 #define DCT_FLAG_EXT_QOS_ENABLED 0x10 211 212 #define DCT_FLAG_EXT_HC_NO_SIFS_PIFS 0x00 213 #define DCT_FLAG_EXT_HC_SIFS 0x20 214 #define DCT_FLAG_EXT_HC_PIFS 0x40 215 216 #define TX_RX_TYPE_MASK 0xFF 217 #define TX_FRAME_TYPE 0x00 218 #define TX_HOST_COMMAND_TYPE 0x01 219 #define RX_FRAME_TYPE 0x09 220 #define RX_HOST_NOTIFICATION_TYPE 0x03 221 #define RX_HOST_CMD_RESPONSE_TYPE 0x04 222 #define RX_TX_FRAME_RESPONSE_TYPE 0x05 223 #define TFD_NEED_IRQ_MASK 0x04 224 225 #define HOST_CMD_DINO_CONFIG 30 226 227 #define HOST_NOTIFICATION_STATUS_ASSOCIATED 10 228 #define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11 229 #define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12 230 #define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13 231 #define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14 232 #define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15 233 #define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16 234 #define HOST_NOTIFICATION_STATUS_BEACON_STATE 17 235 #define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18 236 #define HOST_NOTIFICATION_TX_STATUS 19 237 #define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20 238 #define HOST_NOTIFICATION_MEASUREMENT_STARTED 21 239 #define HOST_NOTIFICATION_MEASUREMENT_ENDED 22 240 #define HOST_NOTIFICATION_CHANNEL_SWITCHED 23 241 #define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24 242 #define HOST_NOTIFICATION_NOISE_STATS 25 243 #define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30 244 #define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31 245 246 #define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1 247 #define IPW_MB_SCAN_CANCEL_THRESHOLD 3 248 #define IPW_MB_ROAMING_THRESHOLD_MIN 1 249 #define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8 250 #define IPW_MB_ROAMING_THRESHOLD_MAX 30 251 #define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 3*IPW_MB_ROAMING_THRESHOLD_DEFAULT 252 #define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300 253 254 #define MACADRR_BYTE_LEN 6 255 256 #define DCR_TYPE_AP 0x01 257 #define DCR_TYPE_WLAP 0x02 258 #define DCR_TYPE_MU_ESS 0x03 259 #define DCR_TYPE_MU_IBSS 0x04 260 #define DCR_TYPE_MU_PIBSS 0x05 261 #define DCR_TYPE_SNIFFER 0x06 262 #define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS 263 264 /* QoS definitions */ 265 266 #define CW_MIN_OFDM 15 267 #define CW_MAX_OFDM 1023 268 #define CW_MIN_CCK 31 269 #define CW_MAX_CCK 1023 270 271 #define QOS_TX0_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM) 272 #define QOS_TX1_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM) 273 #define QOS_TX2_CW_MIN_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/2 - 1) 274 #define QOS_TX3_CW_MIN_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/4 - 1) 275 276 #define QOS_TX0_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK) 277 #define QOS_TX1_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK) 278 #define QOS_TX2_CW_MIN_CCK cpu_to_le16((CW_MIN_CCK + 1)/2 - 1) 279 #define QOS_TX3_CW_MIN_CCK cpu_to_le16((CW_MIN_CCK + 1)/4 - 1) 280 281 #define QOS_TX0_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM) 282 #define QOS_TX1_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM) 283 #define QOS_TX2_CW_MAX_OFDM cpu_to_le16(CW_MIN_OFDM) 284 #define QOS_TX3_CW_MAX_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/2 - 1) 285 286 #define QOS_TX0_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK) 287 #define QOS_TX1_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK) 288 #define QOS_TX2_CW_MAX_CCK cpu_to_le16(CW_MIN_CCK) 289 #define QOS_TX3_CW_MAX_CCK cpu_to_le16((CW_MIN_CCK + 1)/2 - 1) 290 291 #define QOS_TX0_AIFS (3 - QOS_AIFSN_MIN_VALUE) 292 #define QOS_TX1_AIFS (7 - QOS_AIFSN_MIN_VALUE) 293 #define QOS_TX2_AIFS (2 - QOS_AIFSN_MIN_VALUE) 294 #define QOS_TX3_AIFS (2 - QOS_AIFSN_MIN_VALUE) 295 296 #define QOS_TX0_ACM 0 297 #define QOS_TX1_ACM 0 298 #define QOS_TX2_ACM 0 299 #define QOS_TX3_ACM 0 300 301 #define QOS_TX0_TXOP_LIMIT_CCK 0 302 #define QOS_TX1_TXOP_LIMIT_CCK 0 303 #define QOS_TX2_TXOP_LIMIT_CCK cpu_to_le16(6016) 304 #define QOS_TX3_TXOP_LIMIT_CCK cpu_to_le16(3264) 305 306 #define QOS_TX0_TXOP_LIMIT_OFDM 0 307 #define QOS_TX1_TXOP_LIMIT_OFDM 0 308 #define QOS_TX2_TXOP_LIMIT_OFDM cpu_to_le16(3008) 309 #define QOS_TX3_TXOP_LIMIT_OFDM cpu_to_le16(1504) 310 311 #define DEF_TX0_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM) 312 #define DEF_TX1_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM) 313 #define DEF_TX2_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM) 314 #define DEF_TX3_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM) 315 316 #define DEF_TX0_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK) 317 #define DEF_TX1_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK) 318 #define DEF_TX2_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK) 319 #define DEF_TX3_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK) 320 321 #define DEF_TX0_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM) 322 #define DEF_TX1_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM) 323 #define DEF_TX2_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM) 324 #define DEF_TX3_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM) 325 326 #define DEF_TX0_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK) 327 #define DEF_TX1_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK) 328 #define DEF_TX2_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK) 329 #define DEF_TX3_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK) 330 331 #define DEF_TX0_AIFS 0 332 #define DEF_TX1_AIFS 0 333 #define DEF_TX2_AIFS 0 334 #define DEF_TX3_AIFS 0 335 336 #define DEF_TX0_ACM 0 337 #define DEF_TX1_ACM 0 338 #define DEF_TX2_ACM 0 339 #define DEF_TX3_ACM 0 340 341 #define DEF_TX0_TXOP_LIMIT_CCK 0 342 #define DEF_TX1_TXOP_LIMIT_CCK 0 343 #define DEF_TX2_TXOP_LIMIT_CCK 0 344 #define DEF_TX3_TXOP_LIMIT_CCK 0 345 346 #define DEF_TX0_TXOP_LIMIT_OFDM 0 347 #define DEF_TX1_TXOP_LIMIT_OFDM 0 348 #define DEF_TX2_TXOP_LIMIT_OFDM 0 349 #define DEF_TX3_TXOP_LIMIT_OFDM 0 350 351 #define QOS_QOS_SETS 3 352 #define QOS_PARAM_SET_ACTIVE 0 353 #define QOS_PARAM_SET_DEF_CCK 1 354 #define QOS_PARAM_SET_DEF_OFDM 2 355 356 #define CTRL_QOS_NO_ACK (0x0020) 357 358 #define IPW_TX_QUEUE_1 1 359 #define IPW_TX_QUEUE_2 2 360 #define IPW_TX_QUEUE_3 3 361 #define IPW_TX_QUEUE_4 4 362 363 /* QoS sturctures */ 364 struct ipw_qos_info { 365 int qos_enable; 366 struct libipw_qos_parameters *def_qos_parm_OFDM; 367 struct libipw_qos_parameters *def_qos_parm_CCK; 368 u32 burst_duration_CCK; 369 u32 burst_duration_OFDM; 370 u16 qos_no_ack_mask; 371 int burst_enable; 372 }; 373 374 /**************************************************************/ 375 /** 376 * Generic queue structure 377 * 378 * Contains common data for Rx and Tx queues 379 */ 380 struct clx2_queue { 381 int n_bd; /**< number of BDs in this queue */ 382 int first_empty; /**< 1-st empty entry (index) */ 383 int last_used; /**< last used entry (index) */ 384 u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */ 385 u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */ 386 dma_addr_t dma_addr; /**< physical addr for BD's */ 387 int low_mark; /**< low watermark, resume queue if free space more than this */ 388 int high_mark; /**< high watermark, stop queue if free space less than this */ 389 } __packed; /* XXX */ 390 391 struct machdr32 { 392 __le16 frame_ctl; 393 __le16 duration; // watch out for endians! 394 u8 addr1[MACADRR_BYTE_LEN]; 395 u8 addr2[MACADRR_BYTE_LEN]; 396 u8 addr3[MACADRR_BYTE_LEN]; 397 __le16 seq_ctrl; // more endians! 398 u8 addr4[MACADRR_BYTE_LEN]; 399 __le16 qos_ctrl; 400 } __packed; 401 402 struct machdr30 { 403 __le16 frame_ctl; 404 __le16 duration; // watch out for endians! 405 u8 addr1[MACADRR_BYTE_LEN]; 406 u8 addr2[MACADRR_BYTE_LEN]; 407 u8 addr3[MACADRR_BYTE_LEN]; 408 __le16 seq_ctrl; // more endians! 409 u8 addr4[MACADRR_BYTE_LEN]; 410 } __packed; 411 412 struct machdr26 { 413 __le16 frame_ctl; 414 __le16 duration; // watch out for endians! 415 u8 addr1[MACADRR_BYTE_LEN]; 416 u8 addr2[MACADRR_BYTE_LEN]; 417 u8 addr3[MACADRR_BYTE_LEN]; 418 __le16 seq_ctrl; // more endians! 419 __le16 qos_ctrl; 420 } __packed; 421 422 struct machdr24 { 423 __le16 frame_ctl; 424 __le16 duration; // watch out for endians! 425 u8 addr1[MACADRR_BYTE_LEN]; 426 u8 addr2[MACADRR_BYTE_LEN]; 427 u8 addr3[MACADRR_BYTE_LEN]; 428 __le16 seq_ctrl; // more endians! 429 } __packed; 430 431 // TX TFD with 32 byte MAC Header 432 struct tx_tfd_32 { 433 struct machdr32 mchdr; // 32 434 __le32 uivplaceholder[2]; // 8 435 } __packed; 436 437 // TX TFD with 30 byte MAC Header 438 struct tx_tfd_30 { 439 struct machdr30 mchdr; // 30 440 u8 reserved[2]; // 2 441 __le32 uivplaceholder[2]; // 8 442 } __packed; 443 444 // tx tfd with 26 byte mac header 445 struct tx_tfd_26 { 446 struct machdr26 mchdr; // 26 447 u8 reserved1[2]; // 2 448 __le32 uivplaceholder[2]; // 8 449 u8 reserved2[4]; // 4 450 } __packed; 451 452 // tx tfd with 24 byte mac header 453 struct tx_tfd_24 { 454 struct machdr24 mchdr; // 24 455 __le32 uivplaceholder[2]; // 8 456 u8 reserved[8]; // 8 457 } __packed; 458 459 #define DCT_WEP_KEY_FIELD_LENGTH 16 460 461 struct tfd_command { 462 u8 index; 463 u8 length; 464 __le16 reserved; 465 u8 payload[0]; 466 } __packed; 467 468 struct tfd_data { 469 /* Header */ 470 __le32 work_area_ptr; 471 u8 station_number; /* 0 for BSS */ 472 u8 reserved1; 473 __le16 reserved2; 474 475 /* Tx Parameters */ 476 u8 cmd_id; 477 u8 seq_num; 478 __le16 len; 479 u8 priority; 480 u8 tx_flags; 481 u8 tx_flags_ext; 482 u8 key_index; 483 u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH]; 484 u8 rate; 485 u8 antenna; 486 __le16 next_packet_duration; 487 __le16 next_frag_len; 488 __le16 back_off_counter; //////txop; 489 u8 retrylimit; 490 __le16 cwcurrent; 491 u8 reserved3; 492 493 /* 802.11 MAC Header */ 494 union { 495 struct tx_tfd_24 tfd_24; 496 struct tx_tfd_26 tfd_26; 497 struct tx_tfd_30 tfd_30; 498 struct tx_tfd_32 tfd_32; 499 } tfd; 500 501 /* Payload DMA info */ 502 __le32 num_chunks; 503 __le32 chunk_ptr[NUM_TFD_CHUNKS]; 504 __le16 chunk_len[NUM_TFD_CHUNKS]; 505 } __packed; 506 507 struct txrx_control_flags { 508 u8 message_type; 509 u8 rx_seq_num; 510 u8 control_bits; 511 u8 reserved; 512 } __packed; 513 514 #define TFD_SIZE 128 515 #define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags)) 516 517 struct tfd_frame { 518 struct txrx_control_flags control_flags; 519 union { 520 struct tfd_data data; 521 struct tfd_command cmd; 522 u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH]; 523 } u; 524 } __packed; 525 526 typedef void destructor_func(const void *); 527 528 /** 529 * Tx Queue for DMA. Queue consists of circular buffer of 530 * BD's and required locking structures. 531 */ 532 struct clx2_tx_queue { 533 struct clx2_queue q; 534 struct tfd_frame *bd; 535 struct libipw_txb **txb; 536 }; 537 538 /* 539 * RX related structures and functions 540 */ 541 #define RX_FREE_BUFFERS 32 542 #define RX_LOW_WATERMARK 8 543 544 #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 545 #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 546 #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 547 548 // Used for passing to driver number of successes and failures per rate 549 struct rate_histogram { 550 union { 551 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS]; 552 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS]; 553 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS]; 554 } success; 555 union { 556 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS]; 557 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS]; 558 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS]; 559 } failed; 560 } __packed; 561 562 /* statistics command response */ 563 struct ipw_cmd_stats { 564 u8 cmd_id; 565 u8 seq_num; 566 __le16 good_sfd; 567 __le16 bad_plcp; 568 __le16 wrong_bssid; 569 __le16 valid_mpdu; 570 __le16 bad_mac_header; 571 __le16 reserved_frame_types; 572 __le16 rx_ina; 573 __le16 bad_crc32; 574 __le16 invalid_cts; 575 __le16 invalid_acks; 576 __le16 long_distance_ina_fina; 577 __le16 dsp_silence_unreachable; 578 __le16 accumulated_rssi; 579 __le16 rx_ovfl_frame_tossed; 580 __le16 rssi_silence_threshold; 581 __le16 rx_ovfl_frame_supplied; 582 __le16 last_rx_frame_signal; 583 __le16 last_rx_frame_noise; 584 __le16 rx_autodetec_no_ofdm; 585 __le16 rx_autodetec_no_barker; 586 __le16 reserved; 587 } __packed; 588 589 struct notif_channel_result { 590 u8 channel_num; 591 struct ipw_cmd_stats stats; 592 u8 uReserved; 593 } __packed; 594 595 #define SCAN_COMPLETED_STATUS_COMPLETE 1 596 #define SCAN_COMPLETED_STATUS_ABORTED 2 597 598 struct notif_scan_complete { 599 u8 scan_type; 600 u8 num_channels; 601 u8 status; 602 u8 reserved; 603 } __packed; 604 605 struct notif_frag_length { 606 __le16 frag_length; 607 __le16 reserved; 608 } __packed; 609 610 struct notif_beacon_state { 611 __le32 state; 612 __le32 number; 613 } __packed; 614 615 struct notif_tgi_tx_key { 616 u8 key_state; 617 u8 security_type; 618 u8 station_index; 619 u8 reserved; 620 } __packed; 621 622 #define SILENCE_OVER_THRESH (1) 623 #define SILENCE_UNDER_THRESH (2) 624 625 struct notif_link_deterioration { 626 struct ipw_cmd_stats stats; 627 u8 rate; 628 u8 modulation; 629 struct rate_histogram histogram; 630 u8 silence_notification_type; /* SILENCE_OVER/UNDER_THRESH */ 631 __le16 silence_count; 632 } __packed; 633 634 struct notif_association { 635 u8 state; 636 } __packed; 637 638 struct notif_authenticate { 639 u8 state; 640 struct machdr24 addr; 641 __le16 status; 642 } __packed; 643 644 struct notif_calibration { 645 u8 data[104]; 646 } __packed; 647 648 struct notif_noise { 649 __le32 value; 650 } __packed; 651 652 struct ipw_rx_notification { 653 u8 reserved[8]; 654 u8 subtype; 655 u8 flags; 656 __le16 size; 657 union { 658 struct notif_association assoc; 659 struct notif_authenticate auth; 660 struct notif_channel_result channel_result; 661 struct notif_scan_complete scan_complete; 662 struct notif_frag_length frag_len; 663 struct notif_beacon_state beacon_state; 664 struct notif_tgi_tx_key tgi_tx_key; 665 struct notif_link_deterioration link_deterioration; 666 struct notif_calibration calibration; 667 struct notif_noise noise; 668 u8 raw[0]; 669 } u; 670 } __packed; 671 672 struct ipw_rx_frame { 673 __le32 reserved1; 674 u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER 675 u8 received_channel; // The channel that this frame was received on. 676 // Note that for .11b this does not have to be 677 // the same as the channel that it was sent. 678 // Filled by LMAC 679 u8 frameStatus; 680 u8 rate; 681 u8 rssi; 682 u8 agc; 683 u8 rssi_dbm; 684 __le16 signal; 685 __le16 noise; 686 u8 antennaAndPhy; 687 u8 control; // control bit should be on in bg 688 u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate 689 // is identical) 690 u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen 691 __le16 length; 692 u8 data[0]; 693 } __packed; 694 695 struct ipw_rx_header { 696 u8 message_type; 697 u8 rx_seq_num; 698 u8 control_bits; 699 u8 reserved; 700 } __packed; 701 702 struct ipw_rx_packet { 703 struct ipw_rx_header header; 704 union { 705 struct ipw_rx_frame frame; 706 struct ipw_rx_notification notification; 707 } u; 708 } __packed; 709 710 #define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12 711 #define IPW_RX_FRAME_SIZE (unsigned int)(sizeof(struct ipw_rx_header) + \ 712 sizeof(struct ipw_rx_frame)) 713 714 struct ipw_rx_mem_buffer { 715 dma_addr_t dma_addr; 716 struct sk_buff *skb; 717 struct list_head list; 718 }; /* Not transferred over network, so not __packed */ 719 720 struct ipw_rx_queue { 721 struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; 722 struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 723 u32 processed; /* Internal index to last handled Rx packet */ 724 u32 read; /* Shared index to newest available Rx buffer */ 725 u32 write; /* Shared index to oldest written Rx packet */ 726 u32 free_count; /* Number of pre-allocated buffers in rx_free */ 727 /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */ 728 struct list_head rx_free; /* Own an SKBs */ 729 struct list_head rx_used; /* No SKB allocated */ 730 spinlock_t lock; 731 }; /* Not transferred over network, so not __packed */ 732 733 struct alive_command_responce { 734 u8 alive_command; 735 u8 sequence_number; 736 __le16 software_revision; 737 u8 device_identifier; 738 u8 reserved1[5]; 739 __le16 reserved2; 740 __le16 reserved3; 741 __le16 clock_settle_time; 742 __le16 powerup_settle_time; 743 __le16 reserved4; 744 u8 time_stamp[5]; /* month, day, year, hours, minutes */ 745 u8 ucode_valid; 746 } __packed; 747 748 #define IPW_MAX_RATES 12 749 750 struct ipw_rates { 751 u8 num_rates; 752 u8 rates[IPW_MAX_RATES]; 753 } __packed; 754 755 struct command_block { 756 unsigned int control; 757 u32 source_addr; 758 u32 dest_addr; 759 unsigned int status; 760 } __packed; 761 762 #define CB_NUMBER_OF_ELEMENTS_SMALL 64 763 struct fw_image_desc { 764 unsigned long last_cb_index; 765 unsigned long current_cb_index; 766 struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL]; 767 void *v_addr; 768 unsigned long p_addr; 769 unsigned long len; 770 }; 771 772 struct ipw_sys_config { 773 u8 bt_coexistence; 774 u8 reserved1; 775 u8 answer_broadcast_ssid_probe; 776 u8 accept_all_data_frames; 777 u8 accept_non_directed_frames; 778 u8 exclude_unicast_unencrypted; 779 u8 disable_unicast_decryption; 780 u8 exclude_multicast_unencrypted; 781 u8 disable_multicast_decryption; 782 u8 antenna_diversity; 783 u8 pass_crc_to_host; 784 u8 dot11g_auto_detection; 785 u8 enable_cts_to_self; 786 u8 enable_multicast_filtering; 787 u8 bt_coexist_collision_thr; 788 u8 silence_threshold; 789 u8 accept_all_mgmt_bcpr; 790 u8 accept_all_mgmt_frames; 791 u8 pass_noise_stats_to_host; 792 u8 reserved3; 793 } __packed; 794 795 struct ipw_multicast_addr { 796 u8 num_of_multicast_addresses; 797 u8 reserved[3]; 798 u8 mac1[6]; 799 u8 mac2[6]; 800 u8 mac3[6]; 801 u8 mac4[6]; 802 } __packed; 803 804 #define DCW_WEP_KEY_INDEX_MASK 0x03 /* bits [0:1] */ 805 #define DCW_WEP_KEY_SEC_TYPE_MASK 0x30 /* bits [4:5] */ 806 807 #define DCW_WEP_KEY_SEC_TYPE_WEP 0x00 808 #define DCW_WEP_KEY_SEC_TYPE_CCM 0x20 809 #define DCW_WEP_KEY_SEC_TYPE_TKIP 0x30 810 811 #define DCW_WEP_KEY_INVALID_SIZE 0x00 /* 0 = Invalid key */ 812 #define DCW_WEP_KEY64Bit_SIZE 0x05 /* 64-bit encryption */ 813 #define DCW_WEP_KEY128Bit_SIZE 0x0D /* 128-bit encryption */ 814 #define DCW_CCM_KEY128Bit_SIZE 0x10 /* 128-bit key */ 815 //#define DCW_WEP_KEY128BitIV_SIZE 0x10 /* 128-bit key and 128-bit IV */ 816 817 struct ipw_wep_key { 818 u8 cmd_id; 819 u8 seq_num; 820 u8 key_index; 821 u8 key_size; 822 u8 key[16]; 823 } __packed; 824 825 struct ipw_tgi_tx_key { 826 u8 key_id; 827 u8 security_type; 828 u8 station_index; 829 u8 flags; 830 u8 key[16]; 831 __le32 tx_counter[2]; 832 } __packed; 833 834 #define IPW_SCAN_CHANNELS 54 835 836 struct ipw_scan_request { 837 u8 scan_type; 838 __le16 dwell_time; 839 u8 channels_list[IPW_SCAN_CHANNELS]; 840 u8 channels_reserved[3]; 841 } __packed; 842 843 enum { 844 IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0, 845 IPW_SCAN_PASSIVE_FULL_DWELL_SCAN, 846 IPW_SCAN_ACTIVE_DIRECT_SCAN, 847 IPW_SCAN_ACTIVE_BROADCAST_SCAN, 848 IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN, 849 IPW_SCAN_TYPES 850 }; 851 852 struct ipw_scan_request_ext { 853 __le32 full_scan_index; 854 u8 channels_list[IPW_SCAN_CHANNELS]; 855 u8 scan_type[IPW_SCAN_CHANNELS / 2]; 856 u8 reserved; 857 __le16 dwell_time[IPW_SCAN_TYPES]; 858 } __packed; 859 860 static inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index) 861 { 862 if (index % 2) 863 return scan->scan_type[index / 2] & 0x0F; 864 else 865 return (scan->scan_type[index / 2] & 0xF0) >> 4; 866 } 867 868 static inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan, 869 u8 index, u8 scan_type) 870 { 871 if (index % 2) 872 scan->scan_type[index / 2] = 873 (scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F); 874 else 875 scan->scan_type[index / 2] = 876 (scan->scan_type[index / 2] & 0x0F) | 877 ((scan_type & 0x0F) << 4); 878 } 879 880 struct ipw_associate { 881 u8 channel; 882 #ifdef __LITTLE_ENDIAN_BITFIELD 883 u8 auth_type:4, auth_key:4; 884 #else 885 u8 auth_key:4, auth_type:4; 886 #endif 887 u8 assoc_type; 888 u8 reserved; 889 __le16 policy_support; 890 u8 preamble_length; 891 u8 ieee_mode; 892 u8 bssid[ETH_ALEN]; 893 __le32 assoc_tsf_msw; 894 __le32 assoc_tsf_lsw; 895 __le16 capability; 896 __le16 listen_interval; 897 __le16 beacon_interval; 898 u8 dest[ETH_ALEN]; 899 __le16 atim_window; 900 u8 smr; 901 u8 reserved1; 902 __le16 reserved2; 903 } __packed; 904 905 struct ipw_supported_rates { 906 u8 ieee_mode; 907 u8 num_rates; 908 u8 purpose; 909 u8 reserved; 910 u8 supported_rates[IPW_MAX_RATES]; 911 } __packed; 912 913 struct ipw_rts_threshold { 914 __le16 rts_threshold; 915 __le16 reserved; 916 } __packed; 917 918 struct ipw_frag_threshold { 919 __le16 frag_threshold; 920 __le16 reserved; 921 } __packed; 922 923 struct ipw_retry_limit { 924 u8 short_retry_limit; 925 u8 long_retry_limit; 926 __le16 reserved; 927 } __packed; 928 929 struct ipw_dino_config { 930 __le32 dino_config_addr; 931 __le16 dino_config_size; 932 u8 dino_response; 933 u8 reserved; 934 } __packed; 935 936 struct ipw_aironet_info { 937 u8 id; 938 u8 length; 939 __le16 reserved; 940 } __packed; 941 942 struct ipw_rx_key { 943 u8 station_index; 944 u8 key_type; 945 u8 key_id; 946 u8 key_flag; 947 u8 key[16]; 948 u8 station_address[6]; 949 u8 key_index; 950 u8 reserved; 951 } __packed; 952 953 struct ipw_country_channel_info { 954 u8 first_channel; 955 u8 no_channels; 956 s8 max_tx_power; 957 } __packed; 958 959 struct ipw_country_info { 960 u8 id; 961 u8 length; 962 u8 country_str[IEEE80211_COUNTRY_STRING_LEN]; 963 struct ipw_country_channel_info groups[7]; 964 } __packed; 965 966 struct ipw_channel_tx_power { 967 u8 channel_number; 968 s8 tx_power; 969 } __packed; 970 971 #define SCAN_ASSOCIATED_INTERVAL (HZ) 972 #define SCAN_INTERVAL (HZ / 10) 973 #define MAX_A_CHANNELS 37 974 #define MAX_B_CHANNELS 14 975 976 struct ipw_tx_power { 977 u8 num_channels; 978 u8 ieee_mode; 979 struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS]; 980 } __packed; 981 982 struct ipw_rsn_capabilities { 983 u8 id; 984 u8 length; 985 __le16 version; 986 } __packed; 987 988 struct ipw_sensitivity_calib { 989 __le16 beacon_rssi_raw; 990 __le16 reserved; 991 } __packed; 992 993 /** 994 * Host command structure. 995 * 996 * On input, the following fields should be filled: 997 * - cmd 998 * - len 999 * - status_len 1000 * - param (if needed) 1001 * 1002 * On output, 1003 * - \a status contains status; 1004 * - \a param filled with status parameters. 1005 */ 1006 struct ipw_cmd { /* XXX */ 1007 u32 cmd; /**< Host command */ 1008 u32 status;/**< Status */ 1009 u32 status_len; 1010 /**< How many 32 bit parameters in the status */ 1011 u32 len; /**< incoming parameters length, bytes */ 1012 /** 1013 * command parameters. 1014 * There should be enough space for incoming and 1015 * outcoming parameters. 1016 * Incoming parameters listed 1-st, followed by outcoming params. 1017 * nParams=(len+3)/4+status_len 1018 */ 1019 u32 param[0]; 1020 } __packed; 1021 1022 #define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */ 1023 1024 #define STATUS_INT_ENABLED (1<<1) 1025 #define STATUS_RF_KILL_HW (1<<2) 1026 #define STATUS_RF_KILL_SW (1<<3) 1027 #define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW) 1028 1029 #define STATUS_INIT (1<<5) 1030 #define STATUS_AUTH (1<<6) 1031 #define STATUS_ASSOCIATED (1<<7) 1032 #define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED) 1033 1034 #define STATUS_ASSOCIATING (1<<8) 1035 #define STATUS_DISASSOCIATING (1<<9) 1036 #define STATUS_ROAMING (1<<10) 1037 #define STATUS_EXIT_PENDING (1<<11) 1038 #define STATUS_DISASSOC_PENDING (1<<12) 1039 #define STATUS_STATE_PENDING (1<<13) 1040 1041 #define STATUS_DIRECT_SCAN_PENDING (1<<19) 1042 #define STATUS_SCAN_PENDING (1<<20) 1043 #define STATUS_SCANNING (1<<21) 1044 #define STATUS_SCAN_ABORTING (1<<22) 1045 #define STATUS_SCAN_FORCED (1<<23) 1046 1047 #define STATUS_LED_LINK_ON (1<<24) 1048 #define STATUS_LED_ACT_ON (1<<25) 1049 1050 #define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */ 1051 #define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */ 1052 #define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */ 1053 1054 #define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */ 1055 1056 #define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */ 1057 #define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */ 1058 #define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */ 1059 #define CFG_CUSTOM_MAC (1<<3) 1060 #define CFG_PREAMBLE_LONG (1<<4) 1061 #define CFG_ADHOC_PERSIST (1<<5) 1062 #define CFG_ASSOCIATE (1<<6) 1063 #define CFG_FIXED_RATE (1<<7) 1064 #define CFG_ADHOC_CREATE (1<<8) 1065 #define CFG_NO_LED (1<<9) 1066 #define CFG_BACKGROUND_SCAN (1<<10) 1067 #define CFG_SPEED_SCAN (1<<11) 1068 #define CFG_NET_STATS (1<<12) 1069 1070 #define CAP_SHARED_KEY (1<<0) /* Off = OPEN */ 1071 #define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */ 1072 1073 #define MAX_STATIONS 32 1074 #define IPW_INVALID_STATION (0xff) 1075 1076 struct ipw_station_entry { 1077 u8 mac_addr[ETH_ALEN]; 1078 u8 reserved; 1079 u8 support_mode; 1080 }; 1081 1082 #define AVG_ENTRIES 8 1083 struct average { 1084 s16 entries[AVG_ENTRIES]; 1085 u8 pos; 1086 u8 init; 1087 s32 sum; 1088 }; 1089 1090 #define MAX_SPEED_SCAN 100 1091 #define IPW_IBSS_MAC_HASH_SIZE 31 1092 1093 struct ipw_ibss_seq { 1094 u8 mac[ETH_ALEN]; 1095 u16 seq_num; 1096 u16 frag_num; 1097 unsigned long packet_time; 1098 struct list_head list; 1099 }; 1100 1101 struct ipw_error_elem { /* XXX */ 1102 u32 desc; 1103 u32 time; 1104 u32 blink1; 1105 u32 blink2; 1106 u32 link1; 1107 u32 link2; 1108 u32 data; 1109 }; 1110 1111 struct ipw_event { /* XXX */ 1112 u32 event; 1113 u32 time; 1114 u32 data; 1115 } __packed; 1116 1117 struct ipw_fw_error { /* XXX */ 1118 unsigned long jiffies; 1119 u32 status; 1120 u32 config; 1121 u32 elem_len; 1122 u32 log_len; 1123 struct ipw_error_elem *elem; 1124 struct ipw_event *log; 1125 u8 payload[0]; 1126 } __packed; 1127 1128 #ifdef CONFIG_IPW2200_PROMISCUOUS 1129 1130 enum ipw_prom_filter { 1131 IPW_PROM_CTL_HEADER_ONLY = (1 << 0), 1132 IPW_PROM_MGMT_HEADER_ONLY = (1 << 1), 1133 IPW_PROM_DATA_HEADER_ONLY = (1 << 2), 1134 IPW_PROM_ALL_HEADER_ONLY = 0xf, /* bits 0..3 */ 1135 IPW_PROM_NO_TX = (1 << 4), 1136 IPW_PROM_NO_RX = (1 << 5), 1137 IPW_PROM_NO_CTL = (1 << 6), 1138 IPW_PROM_NO_MGMT = (1 << 7), 1139 IPW_PROM_NO_DATA = (1 << 8), 1140 }; 1141 1142 struct ipw_priv; 1143 struct ipw_prom_priv { 1144 struct ipw_priv *priv; 1145 struct libipw_device *ieee; 1146 enum ipw_prom_filter filter; 1147 int tx_packets; 1148 int rx_packets; 1149 }; 1150 #endif 1151 1152 #if defined(CONFIG_IPW2200_RADIOTAP) || defined(CONFIG_IPW2200_PROMISCUOUS) 1153 /* Magic struct that slots into the radiotap header -- no reason 1154 * to build this manually element by element, we can write it much 1155 * more efficiently than we can parse it. ORDER MATTERS HERE 1156 * 1157 * When sent to us via the simulated Rx interface in sysfs, the entire 1158 * structure is provided regardless of any bits unset. 1159 */ 1160 struct ipw_rt_hdr { 1161 struct ieee80211_radiotap_header rt_hdr; 1162 u64 rt_tsf; /* TSF */ /* XXX */ 1163 u8 rt_flags; /* radiotap packet flags */ 1164 u8 rt_rate; /* rate in 500kb/s */ 1165 __le16 rt_channel; /* channel in mhz */ 1166 __le16 rt_chbitmask; /* channel bitfield */ 1167 s8 rt_dbmsignal; /* signal in dbM, kluged to signed */ 1168 s8 rt_dbmnoise; 1169 u8 rt_antenna; /* antenna number */ 1170 u8 payload[0]; /* payload... */ 1171 } __packed; 1172 #endif 1173 1174 struct ipw_priv { 1175 /* ieee device used by generic ieee processing code */ 1176 struct libipw_device *ieee; 1177 1178 spinlock_t lock; 1179 spinlock_t irq_lock; 1180 struct mutex mutex; 1181 1182 /* basic pci-network driver stuff */ 1183 struct pci_dev *pci_dev; 1184 struct net_device *net_dev; 1185 1186 #ifdef CONFIG_IPW2200_PROMISCUOUS 1187 /* Promiscuous mode */ 1188 struct ipw_prom_priv *prom_priv; 1189 struct net_device *prom_net_dev; 1190 #endif 1191 1192 /* pci hardware address support */ 1193 void __iomem *hw_base; 1194 unsigned long hw_len; 1195 1196 struct fw_image_desc sram_desc; 1197 1198 /* result of ucode download */ 1199 struct alive_command_responce dino_alive; 1200 1201 wait_queue_head_t wait_command_queue; 1202 wait_queue_head_t wait_state; 1203 1204 /* Rx and Tx DMA processing queues */ 1205 struct ipw_rx_queue *rxq; 1206 struct clx2_tx_queue txq_cmd; 1207 struct clx2_tx_queue txq[4]; 1208 u32 status; 1209 u32 config; 1210 u32 capability; 1211 1212 struct average average_missed_beacons; 1213 s16 exp_avg_rssi; 1214 s16 exp_avg_noise; 1215 u32 port_type; 1216 int rx_bufs_min; /**< minimum number of bufs in Rx queue */ 1217 int rx_pend_max; /**< maximum pending buffers for one IRQ */ 1218 u32 hcmd_seq; /**< sequence number for hcmd */ 1219 u32 disassociate_threshold; 1220 u32 roaming_threshold; 1221 1222 struct ipw_associate assoc_request; 1223 struct libipw_network *assoc_network; 1224 1225 unsigned long ts_scan_abort; 1226 struct ipw_supported_rates rates; 1227 struct ipw_rates phy[3]; /**< PHY restrictions, per band */ 1228 struct ipw_rates supp; /**< software defined */ 1229 struct ipw_rates extended; /**< use for corresp. IE, AP only */ 1230 1231 struct notif_link_deterioration last_link_deterioration; /** for statistics */ 1232 struct ipw_cmd *hcmd; /**< host command currently executed */ 1233 1234 wait_queue_head_t hcmd_wq; /**< host command waits for execution */ 1235 u32 tsf_bcn[2]; /**< TSF from latest beacon */ 1236 1237 struct notif_calibration calib; /**< last calibration */ 1238 1239 /* ordinal interface with firmware */ 1240 u32 table0_addr; 1241 u32 table0_len; 1242 u32 table1_addr; 1243 u32 table1_len; 1244 u32 table2_addr; 1245 u32 table2_len; 1246 1247 /* context information */ 1248 u8 essid[IW_ESSID_MAX_SIZE]; 1249 u8 essid_len; 1250 u8 nick[IW_ESSID_MAX_SIZE]; 1251 u16 rates_mask; 1252 u8 channel; 1253 struct ipw_sys_config sys_config; 1254 u32 power_mode; 1255 u8 bssid[ETH_ALEN]; 1256 u16 rts_threshold; 1257 u8 mac_addr[ETH_ALEN]; 1258 u8 num_stations; 1259 u8 stations[MAX_STATIONS][ETH_ALEN]; 1260 u8 short_retry_limit; 1261 u8 long_retry_limit; 1262 1263 u32 notif_missed_beacons; 1264 1265 /* Statistics and counters normalized with each association */ 1266 u32 last_missed_beacons; 1267 u32 last_tx_packets; 1268 u32 last_rx_packets; 1269 u32 last_tx_failures; 1270 u32 last_rx_err; 1271 u32 last_rate; 1272 1273 u32 missed_adhoc_beacons; 1274 u32 missed_beacons; 1275 u32 rx_packets; 1276 u32 tx_packets; 1277 u32 quality; 1278 1279 u8 speed_scan[MAX_SPEED_SCAN]; 1280 u8 speed_scan_pos; 1281 1282 u16 last_seq_num; 1283 u16 last_frag_num; 1284 unsigned long last_packet_time; 1285 struct list_head ibss_mac_hash[IPW_IBSS_MAC_HASH_SIZE]; 1286 1287 /* eeprom */ 1288 u8 eeprom[0x100]; /* 256 bytes of eeprom */ 1289 u8 country[4]; 1290 int eeprom_delay; 1291 1292 struct iw_statistics wstats; 1293 1294 struct iw_public_data wireless_data; 1295 1296 int user_requested_scan; 1297 u8 direct_scan_ssid[IW_ESSID_MAX_SIZE]; 1298 u8 direct_scan_ssid_len; 1299 1300 struct delayed_work adhoc_check; 1301 struct work_struct associate; 1302 struct work_struct disassociate; 1303 struct work_struct system_config; 1304 struct work_struct rx_replenish; 1305 struct delayed_work request_scan; 1306 struct delayed_work request_direct_scan; 1307 struct delayed_work request_passive_scan; 1308 struct delayed_work scan_event; 1309 struct work_struct adapter_restart; 1310 struct delayed_work rf_kill; 1311 struct work_struct up; 1312 struct work_struct down; 1313 struct delayed_work gather_stats; 1314 struct work_struct abort_scan; 1315 struct work_struct roam; 1316 struct delayed_work scan_check; 1317 struct work_struct link_up; 1318 struct work_struct link_down; 1319 1320 struct tasklet_struct irq_tasklet; 1321 1322 /* LED related variables and work_struct */ 1323 u8 nic_type; 1324 u32 led_activity_on; 1325 u32 led_activity_off; 1326 u32 led_association_on; 1327 u32 led_association_off; 1328 u32 led_ofdm_on; 1329 u32 led_ofdm_off; 1330 1331 struct delayed_work led_link_on; 1332 struct delayed_work led_link_off; 1333 struct delayed_work led_act_off; 1334 struct work_struct merge_networks; 1335 1336 struct ipw_cmd_log *cmdlog; 1337 int cmdlog_len; 1338 int cmdlog_pos; 1339 1340 #define IPW_2200BG 1 1341 #define IPW_2915ABG 2 1342 u8 adapter; 1343 1344 s8 tx_power; 1345 1346 /* Track time in suspend */ 1347 unsigned long suspend_at; 1348 unsigned long suspend_time; 1349 1350 #ifdef CONFIG_PM 1351 u32 pm_state[16]; 1352 #endif 1353 1354 struct ipw_fw_error *error; 1355 1356 /* network state */ 1357 1358 /* Used to pass the current INTA value from ISR to Tasklet */ 1359 u32 isr_inta; 1360 1361 /* QoS */ 1362 struct ipw_qos_info qos_data; 1363 struct work_struct qos_activate; 1364 /*********************************/ 1365 1366 /* debugging info */ 1367 u32 indirect_dword; 1368 u32 direct_dword; 1369 u32 indirect_byte; 1370 }; /*ipw_priv */ 1371 1372 /* debug macros */ 1373 1374 /* Debug and printf string expansion helpers for printing bitfields */ 1375 #define BIT_FMT8 "%c%c%c%c-%c%c%c%c" 1376 #define BIT_FMT16 BIT_FMT8 ":" BIT_FMT8 1377 #define BIT_FMT32 BIT_FMT16 " " BIT_FMT16 1378 1379 #define BITC(x,y) (((x>>y)&1)?'1':'0') 1380 #define BIT_ARG8(x) \ 1381 BITC(x,7),BITC(x,6),BITC(x,5),BITC(x,4),\ 1382 BITC(x,3),BITC(x,2),BITC(x,1),BITC(x,0) 1383 1384 #define BIT_ARG16(x) \ 1385 BITC(x,15),BITC(x,14),BITC(x,13),BITC(x,12),\ 1386 BITC(x,11),BITC(x,10),BITC(x,9),BITC(x,8),\ 1387 BIT_ARG8(x) 1388 1389 #define BIT_ARG32(x) \ 1390 BITC(x,31),BITC(x,30),BITC(x,29),BITC(x,28),\ 1391 BITC(x,27),BITC(x,26),BITC(x,25),BITC(x,24),\ 1392 BITC(x,23),BITC(x,22),BITC(x,21),BITC(x,20),\ 1393 BITC(x,19),BITC(x,18),BITC(x,17),BITC(x,16),\ 1394 BIT_ARG16(x) 1395 1396 1397 #define IPW_DEBUG(level, fmt, args...) \ 1398 do { if (ipw_debug_level & (level)) \ 1399 printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \ 1400 in_interrupt() ? 'I' : 'U', __func__ , ## args); } while (0) 1401 1402 #ifdef CONFIG_IPW2200_DEBUG 1403 #define IPW_LL_DEBUG(level, fmt, args...) \ 1404 do { if (ipw_debug_level & (level)) \ 1405 printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \ 1406 in_interrupt() ? 'I' : 'U', __func__ , ## args); } while (0) 1407 #else 1408 #define IPW_LL_DEBUG(level, fmt, args...) do {} while (0) 1409 #endif /* CONFIG_IPW2200_DEBUG */ 1410 1411 /* 1412 * To use the debug system; 1413 * 1414 * If you are defining a new debug classification, simply add it to the #define 1415 * list here in the form of: 1416 * 1417 * #define IPW_DL_xxxx VALUE 1418 * 1419 * shifting value to the left one bit from the previous entry. xxxx should be 1420 * the name of the classification (for example, WEP) 1421 * 1422 * You then need to either add a IPW_xxxx_DEBUG() macro definition for your 1423 * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want 1424 * to send output to that classification. 1425 * 1426 * To add your debug level to the list of levels seen when you perform 1427 * 1428 * % cat /proc/net/ipw/debug_level 1429 * 1430 * you simply need to add your entry to the ipw_debug_levels array. 1431 * 1432 * If you do not see debug_level in /proc/net/ipw then you do not have 1433 * CONFIG_IPW2200_DEBUG defined in your kernel configuration 1434 * 1435 */ 1436 1437 #define IPW_DL_ERROR (1<<0) 1438 #define IPW_DL_WARNING (1<<1) 1439 #define IPW_DL_INFO (1<<2) 1440 #define IPW_DL_WX (1<<3) 1441 #define IPW_DL_HOST_COMMAND (1<<5) 1442 #define IPW_DL_STATE (1<<6) 1443 1444 #define IPW_DL_NOTIF (1<<10) 1445 #define IPW_DL_SCAN (1<<11) 1446 #define IPW_DL_ASSOC (1<<12) 1447 #define IPW_DL_DROP (1<<13) 1448 #define IPW_DL_IOCTL (1<<14) 1449 1450 #define IPW_DL_MANAGE (1<<15) 1451 #define IPW_DL_FW (1<<16) 1452 #define IPW_DL_RF_KILL (1<<17) 1453 #define IPW_DL_FW_ERRORS (1<<18) 1454 1455 #define IPW_DL_LED (1<<19) 1456 1457 #define IPW_DL_ORD (1<<20) 1458 1459 #define IPW_DL_FRAG (1<<21) 1460 #define IPW_DL_WEP (1<<22) 1461 #define IPW_DL_TX (1<<23) 1462 #define IPW_DL_RX (1<<24) 1463 #define IPW_DL_ISR (1<<25) 1464 #define IPW_DL_FW_INFO (1<<26) 1465 #define IPW_DL_IO (1<<27) 1466 #define IPW_DL_TRACE (1<<28) 1467 1468 #define IPW_DL_STATS (1<<29) 1469 #define IPW_DL_MERGE (1<<30) 1470 #define IPW_DL_QOS (1<<31) 1471 1472 #define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a) 1473 #define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a) 1474 #define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a) 1475 1476 #define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a) 1477 #define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a) 1478 #define IPW_DEBUG_TRACE(f, a...) IPW_LL_DEBUG(IPW_DL_TRACE, f, ## a) 1479 #define IPW_DEBUG_RX(f, a...) IPW_LL_DEBUG(IPW_DL_RX, f, ## a) 1480 #define IPW_DEBUG_TX(f, a...) IPW_LL_DEBUG(IPW_DL_TX, f, ## a) 1481 #define IPW_DEBUG_ISR(f, a...) IPW_LL_DEBUG(IPW_DL_ISR, f, ## a) 1482 #define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a) 1483 #define IPW_DEBUG_LED(f, a...) IPW_LL_DEBUG(IPW_DL_LED, f, ## a) 1484 #define IPW_DEBUG_WEP(f, a...) IPW_LL_DEBUG(IPW_DL_WEP, f, ## a) 1485 #define IPW_DEBUG_HC(f, a...) IPW_LL_DEBUG(IPW_DL_HOST_COMMAND, f, ## a) 1486 #define IPW_DEBUG_FRAG(f, a...) IPW_LL_DEBUG(IPW_DL_FRAG, f, ## a) 1487 #define IPW_DEBUG_FW(f, a...) IPW_LL_DEBUG(IPW_DL_FW, f, ## a) 1488 #define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a) 1489 #define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a) 1490 #define IPW_DEBUG_IO(f, a...) IPW_LL_DEBUG(IPW_DL_IO, f, ## a) 1491 #define IPW_DEBUG_ORD(f, a...) IPW_LL_DEBUG(IPW_DL_ORD, f, ## a) 1492 #define IPW_DEBUG_FW_INFO(f, a...) IPW_LL_DEBUG(IPW_DL_FW_INFO, f, ## a) 1493 #define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a) 1494 #define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a) 1495 #define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a) 1496 #define IPW_DEBUG_STATS(f, a...) IPW_LL_DEBUG(IPW_DL_STATS, f, ## a) 1497 #define IPW_DEBUG_MERGE(f, a...) IPW_LL_DEBUG(IPW_DL_MERGE, f, ## a) 1498 #define IPW_DEBUG_QOS(f, a...) IPW_LL_DEBUG(IPW_DL_QOS, f, ## a) 1499 1500 #include <linux/ctype.h> 1501 1502 /* 1503 * Register bit definitions 1504 */ 1505 1506 #define IPW_INTA_RW 0x00000008 1507 #define IPW_INTA_MASK_R 0x0000000C 1508 #define IPW_INDIRECT_ADDR 0x00000010 1509 #define IPW_INDIRECT_DATA 0x00000014 1510 #define IPW_AUTOINC_ADDR 0x00000018 1511 #define IPW_AUTOINC_DATA 0x0000001C 1512 #define IPW_RESET_REG 0x00000020 1513 #define IPW_GP_CNTRL_RW 0x00000024 1514 1515 #define IPW_READ_INT_REGISTER 0xFF4 1516 1517 #define IPW_GP_CNTRL_BIT_INIT_DONE 0x00000004 1518 1519 #define IPW_REGISTER_DOMAIN1_END 0x00001000 1520 #define IPW_SRAM_READ_INT_REGISTER 0x00000ff4 1521 1522 #define IPW_SHARED_LOWER_BOUND 0x00000200 1523 #define IPW_INTERRUPT_AREA_LOWER_BOUND 0x00000f80 1524 1525 #define IPW_NIC_SRAM_LOWER_BOUND 0x00000000 1526 #define IPW_NIC_SRAM_UPPER_BOUND 0x00030000 1527 1528 #define IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29) 1529 #define IPW_GP_CNTRL_BIT_CLOCK_READY 0x00000001 1530 #define IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002 1531 1532 /* 1533 * RESET Register Bit Indexes 1534 */ 1535 #define CBD_RESET_REG_PRINCETON_RESET (1<<0) 1536 #define IPW_START_STANDBY (1<<2) 1537 #define IPW_ACTIVITY_LED (1<<4) 1538 #define IPW_ASSOCIATED_LED (1<<5) 1539 #define IPW_OFDM_LED (1<<6) 1540 #define IPW_RESET_REG_SW_RESET (1<<7) 1541 #define IPW_RESET_REG_MASTER_DISABLED (1<<8) 1542 #define IPW_RESET_REG_STOP_MASTER (1<<9) 1543 #define IPW_GATE_ODMA (1<<25) 1544 #define IPW_GATE_IDMA (1<<26) 1545 #define IPW_ARC_KESHET_CONFIG (1<<27) 1546 #define IPW_GATE_ADMA (1<<29) 1547 1548 #define IPW_CSR_CIS_UPPER_BOUND 0x00000200 1549 #define IPW_DOMAIN_0_END 0x1000 1550 #define CLX_MEM_BAR_SIZE 0x1000 1551 1552 /* Dino/baseband control registers bits */ 1553 1554 #define DINO_ENABLE_SYSTEM 0x80 /* 1 = baseband processor on, 0 = reset */ 1555 #define DINO_ENABLE_CS 0x40 /* 1 = enable ucode load */ 1556 #define DINO_RXFIFO_DATA 0x01 /* 1 = data available */ 1557 #define IPW_BASEBAND_CONTROL_STATUS 0X00200000 1558 #define IPW_BASEBAND_TX_FIFO_WRITE 0X00200004 1559 #define IPW_BASEBAND_RX_FIFO_READ 0X00200004 1560 #define IPW_BASEBAND_CONTROL_STORE 0X00200010 1561 1562 #define IPW_INTERNAL_CMD_EVENT 0X00300004 1563 #define IPW_BASEBAND_POWER_DOWN 0x00000001 1564 1565 #define IPW_MEM_HALT_AND_RESET 0x003000e0 1566 1567 /* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */ 1568 #define IPW_BIT_HALT_RESET_ON 0x80000000 1569 #define IPW_BIT_HALT_RESET_OFF 0x00000000 1570 1571 #define CB_LAST_VALID 0x20000000 1572 #define CB_INT_ENABLED 0x40000000 1573 #define CB_VALID 0x80000000 1574 #define CB_SRC_LE 0x08000000 1575 #define CB_DEST_LE 0x04000000 1576 #define CB_SRC_AUTOINC 0x00800000 1577 #define CB_SRC_IO_GATED 0x00400000 1578 #define CB_DEST_AUTOINC 0x00080000 1579 #define CB_SRC_SIZE_LONG 0x00200000 1580 #define CB_DEST_SIZE_LONG 0x00020000 1581 1582 /* DMA DEFINES */ 1583 1584 #define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000 1585 #define DMA_CB_STOP_AND_ABORT 0x00000C00 1586 #define DMA_CB_START 0x00000100 1587 1588 #define IPW_SHARED_SRAM_SIZE 0x00030000 1589 #define IPW_SHARED_SRAM_DMA_CONTROL 0x00027000 1590 #define CB_MAX_LENGTH 0x1FFF 1591 1592 #define IPW_HOST_EEPROM_DATA_SRAM_SIZE 0xA18 1593 #define IPW_EEPROM_IMAGE_SIZE 0x100 1594 1595 /* DMA defs */ 1596 #define IPW_DMA_I_CURRENT_CB 0x003000D0 1597 #define IPW_DMA_O_CURRENT_CB 0x003000D4 1598 #define IPW_DMA_I_DMA_CONTROL 0x003000A4 1599 #define IPW_DMA_I_CB_BASE 0x003000A0 1600 1601 #define IPW_TX_CMD_QUEUE_BD_BASE 0x00000200 1602 #define IPW_TX_CMD_QUEUE_BD_SIZE 0x00000204 1603 #define IPW_TX_QUEUE_0_BD_BASE 0x00000208 1604 #define IPW_TX_QUEUE_0_BD_SIZE (0x0000020C) 1605 #define IPW_TX_QUEUE_1_BD_BASE 0x00000210 1606 #define IPW_TX_QUEUE_1_BD_SIZE 0x00000214 1607 #define IPW_TX_QUEUE_2_BD_BASE 0x00000218 1608 #define IPW_TX_QUEUE_2_BD_SIZE (0x0000021C) 1609 #define IPW_TX_QUEUE_3_BD_BASE 0x00000220 1610 #define IPW_TX_QUEUE_3_BD_SIZE 0x00000224 1611 #define IPW_RX_BD_BASE 0x00000240 1612 #define IPW_RX_BD_SIZE 0x00000244 1613 #define IPW_RFDS_TABLE_LOWER 0x00000500 1614 1615 #define IPW_TX_CMD_QUEUE_READ_INDEX 0x00000280 1616 #define IPW_TX_QUEUE_0_READ_INDEX 0x00000284 1617 #define IPW_TX_QUEUE_1_READ_INDEX 0x00000288 1618 #define IPW_TX_QUEUE_2_READ_INDEX (0x0000028C) 1619 #define IPW_TX_QUEUE_3_READ_INDEX 0x00000290 1620 #define IPW_RX_READ_INDEX (0x000002A0) 1621 1622 #define IPW_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80) 1623 #define IPW_TX_QUEUE_0_WRITE_INDEX (0x00000F84) 1624 #define IPW_TX_QUEUE_1_WRITE_INDEX (0x00000F88) 1625 #define IPW_TX_QUEUE_2_WRITE_INDEX (0x00000F8C) 1626 #define IPW_TX_QUEUE_3_WRITE_INDEX (0x00000F90) 1627 #define IPW_RX_WRITE_INDEX (0x00000FA0) 1628 1629 /* 1630 * EEPROM Related Definitions 1631 */ 1632 1633 #define IPW_EEPROM_DATA_SRAM_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x814) 1634 #define IPW_EEPROM_DATA_SRAM_SIZE (IPW_SHARED_LOWER_BOUND + 0x818) 1635 #define IPW_EEPROM_LOAD_DISABLE (IPW_SHARED_LOWER_BOUND + 0x81C) 1636 #define IPW_EEPROM_DATA (IPW_SHARED_LOWER_BOUND + 0x820) 1637 #define IPW_EEPROM_UPPER_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x9E0) 1638 1639 #define IPW_STATION_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0xA0C) 1640 #define IPW_STATION_TABLE_UPPER (IPW_SHARED_LOWER_BOUND + 0xB0C) 1641 #define IPW_REQUEST_ATIM (IPW_SHARED_LOWER_BOUND + 0xB0C) 1642 #define IPW_ATIM_SENT (IPW_SHARED_LOWER_BOUND + 0xB10) 1643 #define IPW_WHO_IS_AWAKE (IPW_SHARED_LOWER_BOUND + 0xB14) 1644 #define IPW_DURING_ATIM_WINDOW (IPW_SHARED_LOWER_BOUND + 0xB18) 1645 1646 #define MSB 1 1647 #define LSB 0 1648 #define WORD_TO_BYTE(_word) ((_word) * sizeof(u16)) 1649 1650 #define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \ 1651 ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) ) 1652 1653 /* EEPROM access by BYTE */ 1654 #define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */ 1655 #define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */ 1656 #define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */ 1657 #define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */ 1658 #define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */ 1659 #define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */ 1660 #define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */ 1661 #define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */ 1662 #define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */ 1663 #define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */ 1664 1665 /* NIC type as found in the one byte EEPROM_NIC_TYPE offset */ 1666 #define EEPROM_NIC_TYPE_0 0 1667 #define EEPROM_NIC_TYPE_1 1 1668 #define EEPROM_NIC_TYPE_2 2 1669 #define EEPROM_NIC_TYPE_3 3 1670 #define EEPROM_NIC_TYPE_4 4 1671 1672 /* Bluetooth Coexistence capabilities as found in EEPROM_SKU_CAPABILITY */ 1673 #define EEPROM_SKU_CAP_BT_CHANNEL_SIG 0x01 /* we can tell BT our channel # */ 1674 #define EEPROM_SKU_CAP_BT_PRIORITY 0x02 /* BT can take priority over us */ 1675 #define EEPROM_SKU_CAP_BT_OOB 0x04 /* we can signal BT out-of-band */ 1676 1677 #define FW_MEM_REG_LOWER_BOUND 0x00300000 1678 #define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40) 1679 #define IPW_EVENT_REG (FW_MEM_REG_LOWER_BOUND + 0x04) 1680 #define EEPROM_BIT_SK (1<<0) 1681 #define EEPROM_BIT_CS (1<<1) 1682 #define EEPROM_BIT_DI (1<<2) 1683 #define EEPROM_BIT_DO (1<<4) 1684 1685 #define EEPROM_CMD_READ 0x2 1686 1687 /* Interrupts masks */ 1688 #define IPW_INTA_NONE 0x00000000 1689 1690 #define IPW_INTA_BIT_RX_TRANSFER 0x00000002 1691 #define IPW_INTA_BIT_STATUS_CHANGE 0x00000010 1692 #define IPW_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020 1693 1694 //Inta Bits for CF 1695 #define IPW_INTA_BIT_TX_CMD_QUEUE 0x00000800 1696 #define IPW_INTA_BIT_TX_QUEUE_1 0x00001000 1697 #define IPW_INTA_BIT_TX_QUEUE_2 0x00002000 1698 #define IPW_INTA_BIT_TX_QUEUE_3 0x00004000 1699 #define IPW_INTA_BIT_TX_QUEUE_4 0x00008000 1700 1701 #define IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000 1702 1703 #define IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000 1704 #define IPW_INTA_BIT_POWER_DOWN 0x00200000 1705 1706 #define IPW_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000 1707 #define IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000 1708 #define IPW_INTA_BIT_RF_KILL_DONE 0x04000000 1709 #define IPW_INTA_BIT_FATAL_ERROR 0x40000000 1710 #define IPW_INTA_BIT_PARITY_ERROR 0x80000000 1711 1712 /* Interrupts enabled at init time. */ 1713 #define IPW_INTA_MASK_ALL \ 1714 (IPW_INTA_BIT_TX_QUEUE_1 | \ 1715 IPW_INTA_BIT_TX_QUEUE_2 | \ 1716 IPW_INTA_BIT_TX_QUEUE_3 | \ 1717 IPW_INTA_BIT_TX_QUEUE_4 | \ 1718 IPW_INTA_BIT_TX_CMD_QUEUE | \ 1719 IPW_INTA_BIT_RX_TRANSFER | \ 1720 IPW_INTA_BIT_FATAL_ERROR | \ 1721 IPW_INTA_BIT_PARITY_ERROR | \ 1722 IPW_INTA_BIT_STATUS_CHANGE | \ 1723 IPW_INTA_BIT_FW_INITIALIZATION_DONE | \ 1724 IPW_INTA_BIT_BEACON_PERIOD_EXPIRED | \ 1725 IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \ 1726 IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN | \ 1727 IPW_INTA_BIT_POWER_DOWN | \ 1728 IPW_INTA_BIT_RF_KILL_DONE ) 1729 1730 /* FW event log definitions */ 1731 #define EVENT_ELEM_SIZE (3 * sizeof(u32)) 1732 #define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16)) 1733 1734 /* FW error log definitions */ 1735 #define ERROR_ELEM_SIZE (7 * sizeof(u32)) 1736 #define ERROR_START_OFFSET (1 * sizeof(u32)) 1737 1738 /* TX power level (dbm) */ 1739 #define IPW_TX_POWER_MIN -12 1740 #define IPW_TX_POWER_MAX 20 1741 #define IPW_TX_POWER_DEFAULT IPW_TX_POWER_MAX 1742 1743 enum { 1744 IPW_FW_ERROR_OK = 0, 1745 IPW_FW_ERROR_FAIL, 1746 IPW_FW_ERROR_MEMORY_UNDERFLOW, 1747 IPW_FW_ERROR_MEMORY_OVERFLOW, 1748 IPW_FW_ERROR_BAD_PARAM, 1749 IPW_FW_ERROR_BAD_CHECKSUM, 1750 IPW_FW_ERROR_NMI_INTERRUPT, 1751 IPW_FW_ERROR_BAD_DATABASE, 1752 IPW_FW_ERROR_ALLOC_FAIL, 1753 IPW_FW_ERROR_DMA_UNDERRUN, 1754 IPW_FW_ERROR_DMA_STATUS, 1755 IPW_FW_ERROR_DINO_ERROR, 1756 IPW_FW_ERROR_EEPROM_ERROR, 1757 IPW_FW_ERROR_SYSASSERT, 1758 IPW_FW_ERROR_FATAL_ERROR 1759 }; 1760 1761 #define AUTH_OPEN 0 1762 #define AUTH_SHARED_KEY 1 1763 #define AUTH_LEAP 2 1764 #define AUTH_IGNORE 3 1765 1766 #define HC_ASSOCIATE 0 1767 #define HC_REASSOCIATE 1 1768 #define HC_DISASSOCIATE 2 1769 #define HC_IBSS_START 3 1770 #define HC_IBSS_RECONF 4 1771 #define HC_DISASSOC_QUIET 5 1772 1773 #define HC_QOS_SUPPORT_ASSOC cpu_to_le16(0x01) 1774 1775 #define IPW_RATE_CAPABILITIES 1 1776 #define IPW_RATE_CONNECT 0 1777 1778 /* 1779 * Rate values and masks 1780 */ 1781 #define IPW_TX_RATE_1MB 0x0A 1782 #define IPW_TX_RATE_2MB 0x14 1783 #define IPW_TX_RATE_5MB 0x37 1784 #define IPW_TX_RATE_6MB 0x0D 1785 #define IPW_TX_RATE_9MB 0x0F 1786 #define IPW_TX_RATE_11MB 0x6E 1787 #define IPW_TX_RATE_12MB 0x05 1788 #define IPW_TX_RATE_18MB 0x07 1789 #define IPW_TX_RATE_24MB 0x09 1790 #define IPW_TX_RATE_36MB 0x0B 1791 #define IPW_TX_RATE_48MB 0x01 1792 #define IPW_TX_RATE_54MB 0x03 1793 1794 #define IPW_ORD_TABLE_ID_MASK 0x0000FF00 1795 #define IPW_ORD_TABLE_VALUE_MASK 0x000000FF 1796 1797 #define IPW_ORD_TABLE_0_MASK 0x0000F000 1798 #define IPW_ORD_TABLE_1_MASK 0x0000F100 1799 #define IPW_ORD_TABLE_2_MASK 0x0000F200 1800 #define IPW_ORD_TABLE_3_MASK 0x0000F300 1801 #define IPW_ORD_TABLE_4_MASK 0x0000F400 1802 #define IPW_ORD_TABLE_5_MASK 0x0000F500 1803 #define IPW_ORD_TABLE_6_MASK 0x0000F600 1804 #define IPW_ORD_TABLE_7_MASK 0x0000F700 1805 1806 /* 1807 * Table 0 Entries (all entries are 32 bits) 1808 */ 1809 enum { 1810 IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1, 1811 IPW_ORD_STAT_FRAG_TRESHOLD, 1812 IPW_ORD_STAT_RTS_THRESHOLD, 1813 IPW_ORD_STAT_TX_HOST_REQUESTS, 1814 IPW_ORD_STAT_TX_HOST_COMPLETE, 1815 IPW_ORD_STAT_TX_DIR_DATA, 1816 IPW_ORD_STAT_TX_DIR_DATA_B_1, 1817 IPW_ORD_STAT_TX_DIR_DATA_B_2, 1818 IPW_ORD_STAT_TX_DIR_DATA_B_5_5, 1819 IPW_ORD_STAT_TX_DIR_DATA_B_11, 1820 /* Hole */ 1821 1822 IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19, 1823 IPW_ORD_STAT_TX_DIR_DATA_G_2, 1824 IPW_ORD_STAT_TX_DIR_DATA_G_5_5, 1825 IPW_ORD_STAT_TX_DIR_DATA_G_6, 1826 IPW_ORD_STAT_TX_DIR_DATA_G_9, 1827 IPW_ORD_STAT_TX_DIR_DATA_G_11, 1828 IPW_ORD_STAT_TX_DIR_DATA_G_12, 1829 IPW_ORD_STAT_TX_DIR_DATA_G_18, 1830 IPW_ORD_STAT_TX_DIR_DATA_G_24, 1831 IPW_ORD_STAT_TX_DIR_DATA_G_36, 1832 IPW_ORD_STAT_TX_DIR_DATA_G_48, 1833 IPW_ORD_STAT_TX_DIR_DATA_G_54, 1834 IPW_ORD_STAT_TX_NON_DIR_DATA, 1835 IPW_ORD_STAT_TX_NON_DIR_DATA_B_1, 1836 IPW_ORD_STAT_TX_NON_DIR_DATA_B_2, 1837 IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5, 1838 IPW_ORD_STAT_TX_NON_DIR_DATA_B_11, 1839 /* Hole */ 1840 1841 IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44, 1842 IPW_ORD_STAT_TX_NON_DIR_DATA_G_2, 1843 IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5, 1844 IPW_ORD_STAT_TX_NON_DIR_DATA_G_6, 1845 IPW_ORD_STAT_TX_NON_DIR_DATA_G_9, 1846 IPW_ORD_STAT_TX_NON_DIR_DATA_G_11, 1847 IPW_ORD_STAT_TX_NON_DIR_DATA_G_12, 1848 IPW_ORD_STAT_TX_NON_DIR_DATA_G_18, 1849 IPW_ORD_STAT_TX_NON_DIR_DATA_G_24, 1850 IPW_ORD_STAT_TX_NON_DIR_DATA_G_36, 1851 IPW_ORD_STAT_TX_NON_DIR_DATA_G_48, 1852 IPW_ORD_STAT_TX_NON_DIR_DATA_G_54, 1853 IPW_ORD_STAT_TX_RETRY, 1854 IPW_ORD_STAT_TX_FAILURE, 1855 IPW_ORD_STAT_RX_ERR_CRC, 1856 IPW_ORD_STAT_RX_ERR_ICV, 1857 IPW_ORD_STAT_RX_NO_BUFFER, 1858 IPW_ORD_STAT_FULL_SCANS, 1859 IPW_ORD_STAT_PARTIAL_SCANS, 1860 IPW_ORD_STAT_TGH_ABORTED_SCANS, 1861 IPW_ORD_STAT_TX_TOTAL_BYTES, 1862 IPW_ORD_STAT_CURR_RSSI_RAW, 1863 IPW_ORD_STAT_RX_BEACON, 1864 IPW_ORD_STAT_MISSED_BEACONS, 1865 IPW_ORD_TABLE_0_LAST 1866 }; 1867 1868 #define IPW_RSSI_TO_DBM 112 1869 1870 /* Table 1 Entries 1871 */ 1872 enum { 1873 IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1, 1874 }; 1875 1876 /* 1877 * Table 2 Entries 1878 * 1879 * FW_VERSION: 16 byte string 1880 * FW_DATE: 16 byte string (only 14 bytes used) 1881 * UCODE_VERSION: 4 byte version code 1882 * UCODE_DATE: 5 bytes code code 1883 * ADDAPTER_MAC: 6 byte MAC address 1884 * RTC: 4 byte clock 1885 */ 1886 enum { 1887 IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1, 1888 IPW_ORD_STAT_FW_DATE, 1889 IPW_ORD_STAT_UCODE_VERSION, 1890 IPW_ORD_STAT_UCODE_DATE, 1891 IPW_ORD_STAT_ADAPTER_MAC, 1892 IPW_ORD_STAT_RTC, 1893 IPW_ORD_TABLE_2_LAST 1894 }; 1895 1896 /* Table 3 */ 1897 enum { 1898 IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0, 1899 IPW_ORD_STAT_TX_PACKET_FAILURE, 1900 IPW_ORD_STAT_TX_PACKET_SUCCESS, 1901 IPW_ORD_STAT_TX_PACKET_ABORTED, 1902 IPW_ORD_TABLE_3_LAST 1903 }; 1904 1905 /* Table 4 */ 1906 enum { 1907 IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK 1908 }; 1909 1910 /* Table 5 */ 1911 enum { 1912 IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK, 1913 IPW_ORD_STAT_AP_ASSNS, 1914 IPW_ORD_STAT_ROAM, 1915 IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS, 1916 IPW_ORD_STAT_ROAM_CAUSE_UNASSOC, 1917 IPW_ORD_STAT_ROAM_CAUSE_RSSI, 1918 IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY, 1919 IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE, 1920 IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX, 1921 IPW_ORD_STAT_LINK_UP, 1922 IPW_ORD_STAT_LINK_DOWN, 1923 IPW_ORD_ANTENNA_DIVERSITY, 1924 IPW_ORD_CURR_FREQ, 1925 IPW_ORD_TABLE_5_LAST 1926 }; 1927 1928 /* Table 6 */ 1929 enum { 1930 IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK, 1931 IPW_ORD_CURR_BSSID, 1932 IPW_ORD_CURR_SSID, 1933 IPW_ORD_TABLE_6_LAST 1934 }; 1935 1936 /* Table 7 */ 1937 enum { 1938 IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK, 1939 IPW_ORD_STAT_PERCENT_TX_RETRIES, 1940 IPW_ORD_STAT_PERCENT_LINK_QUALITY, 1941 IPW_ORD_STAT_CURR_RSSI_DBM, 1942 IPW_ORD_TABLE_7_LAST 1943 }; 1944 1945 #define IPW_ERROR_LOG (IPW_SHARED_LOWER_BOUND + 0x410) 1946 #define IPW_EVENT_LOG (IPW_SHARED_LOWER_BOUND + 0x414) 1947 #define IPW_ORDINALS_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0x500) 1948 #define IPW_ORDINALS_TABLE_0 (IPW_SHARED_LOWER_BOUND + 0x180) 1949 #define IPW_ORDINALS_TABLE_1 (IPW_SHARED_LOWER_BOUND + 0x184) 1950 #define IPW_ORDINALS_TABLE_2 (IPW_SHARED_LOWER_BOUND + 0x188) 1951 #define IPW_MEM_FIXED_OVERRIDE (IPW_SHARED_LOWER_BOUND + 0x41C) 1952 1953 struct ipw_fixed_rate { 1954 __le16 tx_rates; 1955 __le16 reserved; 1956 } __packed; 1957 1958 #define IPW_INDIRECT_ADDR_MASK (~0x3ul) 1959 1960 struct host_cmd { 1961 u8 cmd; 1962 u8 len; 1963 u16 reserved; 1964 u32 *param; 1965 } __packed; /* XXX */ 1966 1967 struct cmdlog_host_cmd { 1968 u8 cmd; 1969 u8 len; 1970 __le16 reserved; 1971 char param[124]; 1972 } __packed; 1973 1974 struct ipw_cmd_log { 1975 unsigned long jiffies; 1976 int retcode; 1977 struct cmdlog_host_cmd cmd; 1978 }; 1979 1980 /* SysConfig command parameters ... */ 1981 /* bt_coexistence param */ 1982 #define CFG_BT_COEXISTENCE_SIGNAL_CHNL 0x01 /* tell BT our chnl # */ 1983 #define CFG_BT_COEXISTENCE_DEFER 0x02 /* defer our Tx if BT traffic */ 1984 #define CFG_BT_COEXISTENCE_KILL 0x04 /* kill our Tx if BT traffic */ 1985 #define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08 /* multimedia extensions */ 1986 #define CFG_BT_COEXISTENCE_OOB 0x10 /* signal BT via out-of-band */ 1987 1988 /* clear-to-send to self param */ 1989 #define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x00 1990 #define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x01 1991 #define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN 1992 1993 /* Antenna diversity param (h/w can select best antenna, based on signal) */ 1994 #define CFG_SYS_ANTENNA_BOTH 0x00 /* NIC selects best antenna */ 1995 #define CFG_SYS_ANTENNA_A 0x01 /* force antenna A */ 1996 #define CFG_SYS_ANTENNA_B 0x03 /* force antenna B */ 1997 #define CFG_SYS_ANTENNA_SLOW_DIV 0x02 /* consider background noise */ 1998 1999 #define IPW_MAX_CONFIG_RETRIES 10 2000 2001 #endif /* __ipw2200_h__ */ 2002