1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _BRCM_PHY_INT_H_ 18 #define _BRCM_PHY_INT_H_ 19 20 #include <types.h> 21 #include <brcmu_utils.h> 22 #include <brcmu_wifi.h> 23 24 #define PHY_VERSION { 1, 82, 8, 0 } 25 26 #define LCNXN_BASEREV 16 27 28 struct phy_shim_info; 29 30 struct brcms_phy_srom_fem { 31 /* TSSI positive slope, 1: positive, 0: negative */ 32 u8 tssipos; 33 /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */ 34 u8 extpagain; 35 /* support 32 combinations of different Pdet dynamic ranges */ 36 u8 pdetrange; 37 /* TR switch isolation */ 38 u8 triso; 39 /* antswctrl lookup table configuration: 32 possible choices */ 40 u8 antswctrllut; 41 }; 42 43 #define ISNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N) 44 #define ISLCNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN) 45 46 #define PHY_GET_RFATTN(rfgain) ((rfgain) & 0x0f) 47 #define PHY_GET_PADMIX(rfgain) (((rfgain) & 0x10) >> 4) 48 #define PHY_GET_RFGAINID(rfattn, padmix, width) ((rfattn) + ((padmix)*(width))) 49 #define PHY_SAT(x, n) ((x) > ((1<<((n)-1))-1) ? ((1<<((n)-1))-1) : \ 50 ((x) < -(1<<((n)-1)) ? -(1<<((n)-1)) : (x))) 51 #define PHY_SHIFT_ROUND(x, n) ((x) >= 0 ? ((x)+(1<<((n)-1)))>>(n) : (x)>>(n)) 52 #define PHY_HW_ROUND(x, s) ((x >> s) + ((x >> (s-1)) & (s != 0))) 53 54 #define CH_5G_GROUP 3 55 #define A_LOW_CHANS 0 56 #define A_MID_CHANS 1 57 #define A_HIGH_CHANS 2 58 #define CH_2G_GROUP 1 59 #define G_ALL_CHANS 0 60 61 #define FIRST_REF5_CHANNUM 149 62 #define LAST_REF5_CHANNUM 165 63 #define FIRST_5G_CHAN 14 64 #define LAST_5G_CHAN 50 65 #define FIRST_MID_5G_CHAN 14 66 #define LAST_MID_5G_CHAN 35 67 #define FIRST_HIGH_5G_CHAN 36 68 #define LAST_HIGH_5G_CHAN 41 69 #define FIRST_LOW_5G_CHAN 42 70 #define LAST_LOW_5G_CHAN 50 71 72 #define BASE_LOW_5G_CHAN 4900 73 #define BASE_MID_5G_CHAN 5100 74 #define BASE_HIGH_5G_CHAN 5500 75 76 #define CHAN5G_FREQ(chan) (5000 + chan*5) 77 #define CHAN2G_FREQ(chan) (2407 + chan*5) 78 79 #define TXP_FIRST_CCK 0 80 #define TXP_LAST_CCK 3 81 #define TXP_FIRST_OFDM 4 82 #define TXP_LAST_OFDM 11 83 #define TXP_FIRST_OFDM_20_CDD 12 84 #define TXP_LAST_OFDM_20_CDD 19 85 #define TXP_FIRST_MCS_20_SISO 20 86 #define TXP_LAST_MCS_20_SISO 27 87 #define TXP_FIRST_MCS_20_CDD 28 88 #define TXP_LAST_MCS_20_CDD 35 89 #define TXP_FIRST_MCS_20_STBC 36 90 #define TXP_LAST_MCS_20_STBC 43 91 #define TXP_FIRST_MCS_20_SDM 44 92 #define TXP_LAST_MCS_20_SDM 51 93 #define TXP_FIRST_OFDM_40_SISO 52 94 #define TXP_LAST_OFDM_40_SISO 59 95 #define TXP_FIRST_OFDM_40_CDD 60 96 #define TXP_LAST_OFDM_40_CDD 67 97 #define TXP_FIRST_MCS_40_SISO 68 98 #define TXP_LAST_MCS_40_SISO 75 99 #define TXP_FIRST_MCS_40_CDD 76 100 #define TXP_LAST_MCS_40_CDD 83 101 #define TXP_FIRST_MCS_40_STBC 84 102 #define TXP_LAST_MCS_40_STBC 91 103 #define TXP_FIRST_MCS_40_SDM 92 104 #define TXP_LAST_MCS_40_SDM 99 105 #define TXP_MCS_32 100 106 #define TXP_NUM_RATES 101 107 #define ADJ_PWR_TBL_LEN 84 108 109 #define TXP_FIRST_SISO_MCS_20 20 110 #define TXP_LAST_SISO_MCS_20 27 111 112 #define PHY_CORE_NUM_1 1 113 #define PHY_CORE_NUM_2 2 114 #define PHY_CORE_NUM_3 3 115 #define PHY_CORE_NUM_4 4 116 #define PHY_CORE_MAX PHY_CORE_NUM_4 117 #define PHY_CORE_0 0 118 #define PHY_CORE_1 1 119 #define PHY_CORE_2 2 120 #define PHY_CORE_3 3 121 122 #define MA_WINDOW_SZ 8 123 124 #define PHY_NOISE_SAMPLE_MON 1 125 #define PHY_NOISE_SAMPLE_EXTERNAL 2 126 #define PHY_NOISE_WINDOW_SZ 16 127 #define PHY_NOISE_GLITCH_INIT_MA 10 128 #define PHY_NOISE_GLITCH_INIT_MA_BADPlCP 10 129 #define PHY_NOISE_STATE_MON 0x1 130 #define PHY_NOISE_STATE_EXTERNAL 0x2 131 #define PHY_NOISE_SAMPLE_LOG_NUM_NPHY 10 132 #define PHY_NOISE_SAMPLE_LOG_NUM_UCODE 9 133 134 #define PHY_NOISE_OFFSETFACT_4322 (-103) 135 #define PHY_NOISE_MA_WINDOW_SZ 2 136 137 #define PHY_RSSI_TABLE_SIZE 64 138 #define RSSI_ANT_MERGE_MAX 0 139 #define RSSI_ANT_MERGE_MIN 1 140 #define RSSI_ANT_MERGE_AVG 2 141 142 #define PHY_TSSI_TABLE_SIZE 64 143 #define APHY_TSSI_TABLE_SIZE 256 144 #define TX_GAIN_TABLE_LENGTH 64 145 #define DEFAULT_11A_TXP_IDX 24 146 #define NUM_TSSI_FRAMES 4 147 #define NULL_TSSI 0x7f 148 #define NULL_TSSI_W 0x7f7f 149 150 #define PHY_PAPD_EPS_TBL_SIZE_LCNPHY 64 151 152 #define LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL 9 153 154 #define PHY_TXPWR_MIN 10 155 #define PHY_TXPWR_MIN_NPHY 8 156 #define RADIOPWR_OVERRIDE_DEF (-1) 157 158 #define PWRTBL_NUM_COEFF 3 159 160 #define SPURAVOID_DISABLE 0 161 #define SPURAVOID_AUTO 1 162 #define SPURAVOID_FORCEON 2 163 #define SPURAVOID_FORCEON2 3 164 165 #define PHY_SW_TIMER_FAST 15 166 #define PHY_SW_TIMER_SLOW 60 167 #define PHY_SW_TIMER_GLACIAL 120 168 169 #define PHY_PERICAL_AUTO 0 170 #define PHY_PERICAL_FULL 1 171 #define PHY_PERICAL_PARTIAL 2 172 173 #define PHY_PERICAL_NODELAY 0 174 #define PHY_PERICAL_INIT_DELAY 5 175 #define PHY_PERICAL_ASSOC_DELAY 5 176 #define PHY_PERICAL_WDOG_DELAY 5 177 178 #define MPHASE_TXCAL_NUMCMDS 2 179 180 #define PHY_PERICAL_MPHASE_PENDING(pi) \ 181 (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE) 182 183 enum { 184 MPHASE_CAL_STATE_IDLE = 0, 185 MPHASE_CAL_STATE_INIT = 1, 186 MPHASE_CAL_STATE_TXPHASE0, 187 MPHASE_CAL_STATE_TXPHASE1, 188 MPHASE_CAL_STATE_TXPHASE2, 189 MPHASE_CAL_STATE_TXPHASE3, 190 MPHASE_CAL_STATE_TXPHASE4, 191 MPHASE_CAL_STATE_TXPHASE5, 192 MPHASE_CAL_STATE_PAPDCAL, 193 MPHASE_CAL_STATE_RXCAL, 194 MPHASE_CAL_STATE_RSSICAL, 195 MPHASE_CAL_STATE_IDLETSSI 196 }; 197 198 enum phy_cal_mode { 199 CAL_FULL, 200 CAL_RECAL, 201 CAL_CURRECAL, 202 CAL_DIGCAL, 203 CAL_GCTRL, 204 CAL_SOFT, 205 CAL_DIGLO 206 }; 207 208 #define RDR_NTIERS 1 209 #define RDR_TIER_SIZE 64 210 #define RDR_LIST_SIZE (512/3) 211 #define RDR_EPOCH_SIZE 40 212 #define RDR_NANTENNAS 2 213 #define RDR_NTIER_SIZE RDR_LIST_SIZE 214 #define RDR_LP_BUFFER_SIZE 64 215 #define LP_LEN_HIS_SIZE 10 216 217 #define STATIC_NUM_RF 32 218 #define STATIC_NUM_BB 9 219 220 #define BB_MULT_MASK 0x0000ffff 221 #define BB_MULT_VALID_MASK 0x80000000 222 223 #define PHY_CHAIN_TX_DISABLE_TEMP 115 224 #define PHY_HYSTERESIS_DELTATEMP 5 225 226 #define SCAN_INPROG_PHY(pi) \ 227 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN)) 228 229 #define PLT_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT)) 230 231 #define ASSOC_INPROG_PHY(pi) \ 232 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC)) 233 234 #define SCAN_RM_IN_PROGRESS(pi) \ 235 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN | PHY_HOLD_FOR_RM)) 236 237 #define PHY_MUTED(pi) \ 238 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_MUTE)) 239 240 #define PUB_NOT_ASSOC(pi) \ 241 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_NOT_ASSOC)) 242 243 struct phy_table_info { 244 uint table; 245 int q; 246 uint max; 247 }; 248 249 struct phytbl_info { 250 const void *tbl_ptr; 251 u32 tbl_len; 252 u32 tbl_id; 253 u32 tbl_offset; 254 u32 tbl_width; 255 }; 256 257 struct interference_info { 258 u8 curr_home_channel; 259 u16 crsminpwrthld_40_stored; 260 u16 crsminpwrthld_20L_stored; 261 u16 crsminpwrthld_20U_stored; 262 u16 init_gain_code_core1_stored; 263 u16 init_gain_code_core2_stored; 264 u16 init_gain_codeb_core1_stored; 265 u16 init_gain_codeb_core2_stored; 266 u16 init_gain_table_stored[4]; 267 268 u16 clip1_hi_gain_code_core1_stored; 269 u16 clip1_hi_gain_code_core2_stored; 270 u16 clip1_hi_gain_codeb_core1_stored; 271 u16 clip1_hi_gain_codeb_core2_stored; 272 u16 nb_clip_thresh_core1_stored; 273 u16 nb_clip_thresh_core2_stored; 274 u16 init_ofdmlna2gainchange_stored[4]; 275 u16 init_ccklna2gainchange_stored[4]; 276 u16 clip1_lo_gain_code_core1_stored; 277 u16 clip1_lo_gain_code_core2_stored; 278 u16 clip1_lo_gain_codeb_core1_stored; 279 u16 clip1_lo_gain_codeb_core2_stored; 280 u16 w1_clip_thresh_core1_stored; 281 u16 w1_clip_thresh_core2_stored; 282 u16 radio_2056_core1_rssi_gain_stored; 283 u16 radio_2056_core2_rssi_gain_stored; 284 u16 energy_drop_timeout_len_stored; 285 286 u16 ed_crs40_assertthld0_stored; 287 u16 ed_crs40_assertthld1_stored; 288 u16 ed_crs40_deassertthld0_stored; 289 u16 ed_crs40_deassertthld1_stored; 290 u16 ed_crs20L_assertthld0_stored; 291 u16 ed_crs20L_assertthld1_stored; 292 u16 ed_crs20L_deassertthld0_stored; 293 u16 ed_crs20L_deassertthld1_stored; 294 u16 ed_crs20U_assertthld0_stored; 295 u16 ed_crs20U_assertthld1_stored; 296 u16 ed_crs20U_deassertthld0_stored; 297 u16 ed_crs20U_deassertthld1_stored; 298 299 u16 badplcp_ma; 300 u16 badplcp_ma_previous; 301 u16 badplcp_ma_total; 302 u16 badplcp_ma_list[MA_WINDOW_SZ]; 303 int badplcp_ma_index; 304 s16 pre_badplcp_cnt; 305 s16 bphy_pre_badplcp_cnt; 306 307 u16 init_gain_core1; 308 u16 init_gain_core2; 309 u16 init_gainb_core1; 310 u16 init_gainb_core2; 311 u16 init_gain_rfseq[4]; 312 313 u16 crsminpwr0; 314 u16 crsminpwrl0; 315 u16 crsminpwru0; 316 317 s16 crsminpwr_index; 318 319 u16 radio_2057_core1_rssi_wb1a_gc_stored; 320 u16 radio_2057_core2_rssi_wb1a_gc_stored; 321 u16 radio_2057_core1_rssi_wb1g_gc_stored; 322 u16 radio_2057_core2_rssi_wb1g_gc_stored; 323 u16 radio_2057_core1_rssi_wb2_gc_stored; 324 u16 radio_2057_core2_rssi_wb2_gc_stored; 325 u16 radio_2057_core1_rssi_nb_gc_stored; 326 u16 radio_2057_core2_rssi_nb_gc_stored; 327 }; 328 329 struct aci_save_gphy { 330 u16 rc_cal_ovr; 331 u16 phycrsth1; 332 u16 phycrsth2; 333 u16 init_n1p1_gain; 334 u16 p1_p2_gain; 335 u16 n1_n2_gain; 336 u16 n1_p1_gain; 337 u16 div_search_gain; 338 u16 div_p1_p2_gain; 339 u16 div_search_gn_change; 340 u16 table_7_2; 341 u16 table_7_3; 342 u16 cckshbits_gnref; 343 u16 clip_thresh; 344 u16 clip2_thresh; 345 u16 clip3_thresh; 346 u16 clip_p2_thresh; 347 u16 clip_pwdn_thresh; 348 u16 clip_n1p1_thresh; 349 u16 clip_n1_pwdn_thresh; 350 u16 bbconfig; 351 u16 cthr_sthr_shdin; 352 u16 energy; 353 u16 clip_p1_p2_thresh; 354 u16 threshold; 355 u16 reg15; 356 u16 reg16; 357 u16 reg17; 358 u16 div_srch_idx; 359 u16 div_srch_p1_p2; 360 u16 div_srch_gn_back; 361 u16 ant_dwell; 362 u16 ant_wr_settle; 363 }; 364 365 struct lo_complex_abgphy_info { 366 s8 i; 367 s8 q; 368 }; 369 370 struct nphy_iq_comp { 371 s16 a0; 372 s16 b0; 373 s16 a1; 374 s16 b1; 375 }; 376 377 struct nphy_txpwrindex { 378 s8 index; 379 s8 index_internal; 380 s8 index_internal_save; 381 u16 AfectrlOverride; 382 u16 AfeCtrlDacGain; 383 u16 rad_gain; 384 u8 bbmult; 385 u16 iqcomp_a; 386 u16 iqcomp_b; 387 u16 locomp; 388 }; 389 390 struct txiqcal_cache { 391 392 u16 txcal_coeffs_2G[8]; 393 u16 txcal_radio_regs_2G[8]; 394 struct nphy_iq_comp rxcal_coeffs_2G; 395 396 u16 txcal_coeffs_5G[8]; 397 u16 txcal_radio_regs_5G[8]; 398 struct nphy_iq_comp rxcal_coeffs_5G; 399 }; 400 401 struct nphy_pwrctrl { 402 s8 max_pwr_2g; 403 s8 idle_targ_2g; 404 s16 pwrdet_2g_a1; 405 s16 pwrdet_2g_b0; 406 s16 pwrdet_2g_b1; 407 s8 max_pwr_5gm; 408 s8 idle_targ_5gm; 409 s8 max_pwr_5gh; 410 s8 max_pwr_5gl; 411 s16 pwrdet_5gm_a1; 412 s16 pwrdet_5gm_b0; 413 s16 pwrdet_5gm_b1; 414 s16 pwrdet_5gl_a1; 415 s16 pwrdet_5gl_b0; 416 s16 pwrdet_5gl_b1; 417 s16 pwrdet_5gh_a1; 418 s16 pwrdet_5gh_b0; 419 s16 pwrdet_5gh_b1; 420 s8 idle_targ_5gl; 421 s8 idle_targ_5gh; 422 s8 idle_tssi_2g; 423 s8 idle_tssi_5g; 424 s8 idle_tssi; 425 s16 a1; 426 s16 b0; 427 s16 b1; 428 }; 429 430 struct nphy_txgains { 431 u16 txlpf[2]; 432 u16 txgm[2]; 433 u16 pga[2]; 434 u16 pad[2]; 435 u16 ipa[2]; 436 }; 437 438 #define PHY_NOISEVAR_BUFSIZE 10 439 440 struct nphy_noisevar_buf { 441 int bufcount; 442 int tone_id[PHY_NOISEVAR_BUFSIZE]; 443 u32 noise_vars[PHY_NOISEVAR_BUFSIZE]; 444 u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE]; 445 }; 446 447 struct rssical_cache { 448 u16 rssical_radio_regs_2G[2]; 449 u16 rssical_phyregs_2G[12]; 450 451 u16 rssical_radio_regs_5G[2]; 452 u16 rssical_phyregs_5G[12]; 453 }; 454 455 struct lcnphy_cal_results { 456 457 u16 txiqlocal_a; 458 u16 txiqlocal_b; 459 u16 txiqlocal_didq; 460 u8 txiqlocal_ei0; 461 u8 txiqlocal_eq0; 462 u8 txiqlocal_fi0; 463 u8 txiqlocal_fq0; 464 465 u16 txiqlocal_bestcoeffs[11]; 466 u16 txiqlocal_bestcoeffs_valid; 467 468 u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY]; 469 u16 analog_gain_ref; 470 u16 lut_begin; 471 u16 lut_end; 472 u16 lut_step; 473 u16 rxcompdbm; 474 u16 papdctrl; 475 u16 sslpnCalibClkEnCtrl; 476 477 u16 rxiqcal_coeff_a0; 478 u16 rxiqcal_coeff_b0; 479 }; 480 481 struct shared_phy { 482 struct brcms_phy *phy_head; 483 uint unit; 484 struct phy_shim_info *physhim; 485 uint corerev; 486 u32 machwcap; 487 bool up; 488 bool clk; 489 uint now; 490 u16 vid; 491 u16 did; 492 uint chip; 493 uint chiprev; 494 uint chippkg; 495 uint sromrev; 496 uint boardtype; 497 uint boardrev; 498 u32 boardflags; 499 u32 boardflags2; 500 uint fast_timer; 501 uint slow_timer; 502 uint glacial_timer; 503 u8 rx_antdiv; 504 s8 phy_noise_window[MA_WINDOW_SZ]; 505 uint phy_noise_index; 506 u8 hw_phytxchain; 507 u8 hw_phyrxchain; 508 u8 phytxchain; 509 u8 phyrxchain; 510 u8 rssi_mode; 511 bool _rifs_phy; 512 }; 513 514 struct brcms_phy_pub { 515 uint phy_type; 516 uint phy_rev; 517 u8 phy_corenum; 518 u16 radioid; 519 u8 radiorev; 520 u8 radiover; 521 522 uint coreflags; 523 uint ana_rev; 524 bool abgphy_encore; 525 }; 526 527 struct phy_func_ptr { 528 void (*init)(struct brcms_phy *); 529 void (*calinit)(struct brcms_phy *); 530 void (*chanset)(struct brcms_phy *, u16 chanspec); 531 void (*txpwrrecalc)(struct brcms_phy *); 532 int (*longtrn)(struct brcms_phy *, int); 533 void (*txiqccget)(struct brcms_phy *, u16 *, u16 *); 534 void (*txiqccset)(struct brcms_phy *, u16, u16); 535 u16 (*txloccget)(struct brcms_phy *); 536 void (*radioloftget)(struct brcms_phy *, u8 *, u8 *, u8 *, u8 *); 537 void (*carrsuppr)(struct brcms_phy *); 538 s32 (*rxsigpwr)(struct brcms_phy *, s32); 539 void (*detach)(struct brcms_phy *); 540 }; 541 542 struct brcms_phy { 543 struct brcms_phy_pub pubpi_ro; 544 struct shared_phy *sh; 545 struct phy_func_ptr pi_fptr; 546 547 union { 548 struct brcms_phy_lcnphy *pi_lcnphy; 549 } u; 550 bool user_txpwr_at_rfport; 551 552 struct bcma_device *d11core; 553 struct brcms_phy *next; 554 struct brcms_phy_pub pubpi; 555 556 bool do_initcal; 557 bool phytest_on; 558 bool ofdm_rateset_war; 559 bool bf_preempt_4306; 560 u16 radio_chanspec; 561 u8 antsel_type; 562 u16 bw; 563 u8 txpwr_percent; 564 bool phy_init_por; 565 566 bool init_in_progress; 567 bool initialized; 568 bool sbtml_gm; 569 uint refcnt; 570 bool watchdog_override; 571 u8 phynoise_state; 572 uint phynoise_now; 573 int phynoise_chan_watchdog; 574 bool phynoise_polling; 575 bool disable_percal; 576 u32 measure_hold; 577 578 s16 txpa_2g[PWRTBL_NUM_COEFF]; 579 s16 txpa_2g_low_temp[PWRTBL_NUM_COEFF]; 580 s16 txpa_2g_high_temp[PWRTBL_NUM_COEFF]; 581 s16 txpa_5g_low[PWRTBL_NUM_COEFF]; 582 s16 txpa_5g_mid[PWRTBL_NUM_COEFF]; 583 s16 txpa_5g_hi[PWRTBL_NUM_COEFF]; 584 585 u8 tx_srom_max_2g; 586 u8 tx_srom_max_5g_low; 587 u8 tx_srom_max_5g_mid; 588 u8 tx_srom_max_5g_hi; 589 u8 tx_srom_max_rate_2g[TXP_NUM_RATES]; 590 u8 tx_srom_max_rate_5g_low[TXP_NUM_RATES]; 591 u8 tx_srom_max_rate_5g_mid[TXP_NUM_RATES]; 592 u8 tx_srom_max_rate_5g_hi[TXP_NUM_RATES]; 593 u8 tx_user_target[TXP_NUM_RATES]; 594 s8 tx_power_offset[TXP_NUM_RATES]; 595 u8 tx_power_target[TXP_NUM_RATES]; 596 597 struct brcms_phy_srom_fem srom_fem2g; 598 struct brcms_phy_srom_fem srom_fem5g; 599 600 u8 tx_power_max; 601 u8 tx_power_max_rate_ind; 602 bool hwpwrctrl; 603 u8 nphy_txpwrctrl; 604 s8 nphy_txrx_chain; 605 bool phy_5g_pwrgain; 606 607 u16 phy_wreg; 608 u16 phy_wreg_limit; 609 610 s8 n_preamble_override; 611 u8 antswitch; 612 u8 aa2g, aa5g; 613 614 s8 idle_tssi[CH_5G_GROUP]; 615 s8 target_idle_tssi; 616 s8 txpwr_est_Pout; 617 u8 tx_power_min; 618 u8 txpwr_limit[TXP_NUM_RATES]; 619 u8 txpwr_env_limit[TXP_NUM_RATES]; 620 u8 adj_pwr_tbl_nphy[ADJ_PWR_TBL_LEN]; 621 622 bool channel_14_wide_filter; 623 624 bool txpwroverride; 625 bool txpwridx_override_aphy; 626 s16 radiopwr_override; 627 u16 hwpwr_txcur; 628 u8 saved_txpwr_idx; 629 630 bool edcrs_threshold_lock; 631 632 u32 tr_R_gain_val; 633 u32 tr_T_gain_val; 634 635 s16 ofdm_analog_filt_bw_override; 636 s16 cck_analog_filt_bw_override; 637 s16 ofdm_rccal_override; 638 s16 cck_rccal_override; 639 u16 extlna_type; 640 641 uint interference_mode_crs_time; 642 u16 crsglitch_prev; 643 bool interference_mode_crs; 644 645 u32 phy_tx_tone_freq; 646 uint phy_lastcal; 647 bool phy_forcecal; 648 bool phy_fixed_noise; 649 u32 xtalfreq; 650 u8 pdiv; 651 s8 carrier_suppr_disable; 652 653 bool phy_bphy_evm; 654 bool phy_bphy_rfcs; 655 s8 phy_scraminit; 656 u8 phy_gpiosel; 657 658 s16 phy_txcore_disable_temp; 659 s16 phy_txcore_enable_temp; 660 s8 phy_tempsense_offset; 661 bool phy_txcore_heatedup; 662 663 u16 radiopwr; 664 u16 bb_atten; 665 u16 txctl1; 666 667 u16 mintxbias; 668 u16 mintxmag; 669 struct lo_complex_abgphy_info gphy_locomp_iq 670 [STATIC_NUM_RF][STATIC_NUM_BB]; 671 s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB]; 672 u16 gain_table[TX_GAIN_TABLE_LENGTH]; 673 bool loopback_gain; 674 s16 max_lpback_gain_hdB; 675 s16 trsw_rx_gain_hdB; 676 u8 power_vec[8]; 677 678 u16 rc_cal; 679 int nrssi_table_delta; 680 int nrssi_slope_scale; 681 int nrssi_slope_offset; 682 int min_rssi; 683 int max_rssi; 684 685 s8 txpwridx; 686 u8 min_txpower; 687 688 u8 a_band_high_disable; 689 690 u16 tx_vos; 691 u16 global_tx_bb_dc_bias_loft; 692 693 int rf_max; 694 int bb_max; 695 int rf_list_size; 696 int bb_list_size; 697 u16 *rf_attn_list; 698 u16 *bb_attn_list; 699 u16 padmix_mask; 700 u16 padmix_reg; 701 u16 *txmag_list; 702 uint txmag_len; 703 bool txmag_enable; 704 705 s8 *a_tssi_to_dbm; 706 s8 *m_tssi_to_dbm; 707 s8 *l_tssi_to_dbm; 708 s8 *h_tssi_to_dbm; 709 u8 *hwtxpwr; 710 711 u16 freqtrack_saved_regs[2]; 712 int cur_interference_mode; 713 bool hwpwrctrl_capable; 714 bool temppwrctrl_capable; 715 716 uint phycal_nslope; 717 uint phycal_noffset; 718 uint phycal_mlo; 719 uint phycal_txpower; 720 721 u8 phy_aa2g; 722 723 bool nphy_tableloaded; 724 s8 nphy_rssisel; 725 u32 nphy_bb_mult_save; 726 u16 nphy_txiqlocal_bestc[11]; 727 bool nphy_txiqlocal_coeffsvalid; 728 struct nphy_txpwrindex nphy_txpwrindex[PHY_CORE_NUM_2]; 729 struct nphy_pwrctrl nphy_pwrctrl_info[PHY_CORE_NUM_2]; 730 u16 cck2gpo; 731 u32 ofdm2gpo; 732 u32 ofdm5gpo; 733 u32 ofdm5glpo; 734 u32 ofdm5ghpo; 735 u8 bw402gpo; 736 u8 bw405gpo; 737 u8 bw405glpo; 738 u8 bw405ghpo; 739 u8 cdd2gpo; 740 u8 cdd5gpo; 741 u8 cdd5glpo; 742 u8 cdd5ghpo; 743 u8 stbc2gpo; 744 u8 stbc5gpo; 745 u8 stbc5glpo; 746 u8 stbc5ghpo; 747 u8 bwdup2gpo; 748 u8 bwdup5gpo; 749 u8 bwdup5glpo; 750 u8 bwdup5ghpo; 751 u16 mcs2gpo[8]; 752 u16 mcs5gpo[8]; 753 u16 mcs5glpo[8]; 754 u16 mcs5ghpo[8]; 755 u32 nphy_rxcalparams; 756 757 u8 phy_spuravoid; 758 bool phy_isspuravoid; 759 760 u8 phy_pabias; 761 u8 nphy_papd_skip; 762 u8 nphy_tssi_slope; 763 764 s16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ]; 765 u8 nphy_noise_index; 766 767 bool nphy_gain_boost; 768 bool nphy_elna_gain_config; 769 u16 old_bphy_test; 770 u16 old_bphy_testcontrol; 771 772 bool phyhang_avoid; 773 774 bool rssical_nphy; 775 u8 nphy_perical; 776 uint nphy_perical_last; 777 u8 cal_type_override; 778 u8 mphase_cal_phase_id; 779 u8 mphase_txcal_cmdidx; 780 u8 mphase_txcal_numcmds; 781 u16 mphase_txcal_bestcoeffs[11]; 782 u16 nphy_txiqlocal_chanspec; 783 u16 nphy_iqcal_chanspec_2G; 784 u16 nphy_iqcal_chanspec_5G; 785 u16 nphy_rssical_chanspec_2G; 786 u16 nphy_rssical_chanspec_5G; 787 struct wlapi_timer *phycal_timer; 788 bool use_int_tx_iqlo_cal_nphy; 789 bool internal_tx_iqlo_cal_tapoff_intpa_nphy; 790 s16 nphy_lastcal_temp; 791 792 struct txiqcal_cache calibration_cache; 793 struct rssical_cache rssical_cache; 794 795 u8 nphy_txpwr_idx[2]; 796 u8 nphy_papd_cal_type; 797 uint nphy_papd_last_cal; 798 u16 nphy_papd_tx_gain_at_last_cal[2]; 799 u8 nphy_papd_cal_gain_index[2]; 800 s16 nphy_papd_epsilon_offset[2]; 801 bool nphy_papd_recal_enable; 802 u32 nphy_papd_recal_counter; 803 bool nphy_force_papd_cal; 804 bool nphy_papdcomp; 805 bool ipa2g_on; 806 bool ipa5g_on; 807 808 u16 classifier_state; 809 u16 clip_state[2]; 810 uint nphy_deaf_count; 811 u8 rxiq_samps; 812 u8 rxiq_antsel; 813 814 u16 rfctrlIntc1_save; 815 u16 rfctrlIntc2_save; 816 bool first_cal_after_assoc; 817 u16 tx_rx_cal_radio_saveregs[22]; 818 u16 tx_rx_cal_phy_saveregs[15]; 819 820 u8 nphy_cal_orig_pwr_idx[2]; 821 u8 nphy_txcal_pwr_idx[2]; 822 u8 nphy_rxcal_pwr_idx[2]; 823 u16 nphy_cal_orig_tx_gain[2]; 824 struct nphy_txgains nphy_cal_target_gain; 825 u16 nphy_txcal_bbmult; 826 u16 nphy_gmval; 827 828 u16 nphy_saved_bbconf; 829 830 bool nphy_gband_spurwar_en; 831 bool nphy_gband_spurwar2_en; 832 bool nphy_aband_spurwar_en; 833 u16 nphy_rccal_value; 834 u16 nphy_crsminpwr[3]; 835 struct nphy_noisevar_buf nphy_saved_noisevars; 836 bool nphy_anarxlpf_adjusted; 837 bool nphy_crsminpwr_adjusted; 838 bool nphy_noisevars_adjusted; 839 840 bool nphy_rxcal_active; 841 u16 radar_percal_mask; 842 bool dfs_lp_buffer_nphy; 843 844 u16 nphy_fineclockgatecontrol; 845 846 s8 rx2tx_biasentry; 847 848 u16 crsminpwr0; 849 u16 crsminpwrl0; 850 u16 crsminpwru0; 851 s16 noise_crsminpwr_index; 852 u16 init_gain_core1; 853 u16 init_gain_core2; 854 u16 init_gainb_core1; 855 u16 init_gainb_core2; 856 u8 aci_noise_curr_channel; 857 u16 init_gain_rfseq[4]; 858 859 bool radio_is_on; 860 861 bool nphy_sample_play_lpf_bw_ctl_ovr; 862 863 u16 tbl_data_hi; 864 u16 tbl_data_lo; 865 u16 tbl_addr; 866 867 uint tbl_save_id; 868 uint tbl_save_offset; 869 870 u8 txpwrctrl; 871 s8 txpwrindex[PHY_CORE_MAX]; 872 873 u8 phycal_tempdelta; 874 u32 mcs20_po; 875 u32 mcs40_po; 876 struct wiphy *wiphy; 877 }; 878 879 struct cs32 { 880 s32 q; 881 s32 i; 882 }; 883 884 struct radio_regs { 885 u16 address; 886 u32 init_a; 887 u32 init_g; 888 u8 do_init_a; 889 u8 do_init_g; 890 }; 891 892 struct radio_20xx_regs { 893 u16 address; 894 u8 init; 895 u8 do_init; 896 }; 897 898 struct lcnphy_radio_regs { 899 u16 address; 900 u8 init_a; 901 u8 init_g; 902 u8 do_init_a; 903 u8 do_init_g; 904 }; 905 906 u16 read_phy_reg(struct brcms_phy *pi, u16 addr); 907 void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val); 908 void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val); 909 void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val); 910 void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val); 911 912 u16 read_radio_reg(struct brcms_phy *pi, u16 addr); 913 void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val); 914 void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val); 915 void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val); 916 void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask); 917 918 void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val); 919 920 void wlc_phyreg_enter(struct brcms_phy_pub *pih); 921 void wlc_phyreg_exit(struct brcms_phy_pub *pih); 922 void wlc_radioreg_enter(struct brcms_phy_pub *pih); 923 void wlc_radioreg_exit(struct brcms_phy_pub *pih); 924 925 void wlc_phy_read_table(struct brcms_phy *pi, 926 const struct phytbl_info *ptbl_info, 927 u16 tblAddr, u16 tblDataHi, u16 tblDatalo); 928 void wlc_phy_write_table(struct brcms_phy *pi, 929 const struct phytbl_info *ptbl_info, 930 u16 tblAddr, u16 tblDataHi, u16 tblDatalo); 931 void wlc_phy_table_addr(struct brcms_phy *pi, uint tbl_id, uint tbl_offset, 932 u16 tblAddr, u16 tblDataHi, u16 tblDataLo); 933 void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val); 934 935 void write_phy_channel_reg(struct brcms_phy *pi, uint val); 936 void wlc_phy_txpower_update_shm(struct brcms_phy *pi); 937 938 u8 wlc_phy_nbits(s32 value); 939 void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core); 940 941 uint wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi, 942 struct radio_20xx_regs *radioregs); 943 uint wlc_phy_init_radio_regs(struct brcms_phy *pi, 944 const struct radio_regs *radioregs, 945 u16 core_offset); 946 947 void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi); 948 949 void wlc_phy_do_dummy_tx(struct brcms_phy *pi, bool ofdm, bool pa_on); 950 void wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real, s32 *eps_imag); 951 952 void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi); 953 void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi); 954 955 bool wlc_phy_attach_nphy(struct brcms_phy *pi); 956 bool wlc_phy_attach_lcnphy(struct brcms_phy *pi); 957 958 void wlc_phy_detach_lcnphy(struct brcms_phy *pi); 959 960 void wlc_phy_init_nphy(struct brcms_phy *pi); 961 void wlc_phy_init_lcnphy(struct brcms_phy *pi); 962 963 void wlc_phy_cal_init_nphy(struct brcms_phy *pi); 964 void wlc_phy_cal_init_lcnphy(struct brcms_phy *pi); 965 966 void wlc_phy_chanspec_set_nphy(struct brcms_phy *pi, u16 chanspec); 967 void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi, u16 chanspec); 968 void wlc_phy_chanspec_set_fixup_lcnphy(struct brcms_phy *pi, u16 chanspec); 969 int wlc_phy_channel2freq(uint channel); 970 int wlc_phy_chanspec_freq2bandrange_lpssn(uint); 971 int wlc_phy_chanspec_bandrange_get(struct brcms_phy *, u16 chanspec); 972 973 void wlc_lcnphy_set_tx_pwr_ctrl(struct brcms_phy *pi, u16 mode); 974 s8 wlc_lcnphy_get_current_tx_pwr_idx(struct brcms_phy *pi); 975 976 void wlc_phy_txpower_recalc_target_nphy(struct brcms_phy *pi); 977 void wlc_lcnphy_txpower_recalc_target(struct brcms_phy *pi); 978 void wlc_phy_txpower_recalc_target_lcnphy(struct brcms_phy *pi); 979 980 void wlc_lcnphy_set_tx_pwr_by_index(struct brcms_phy *pi, int index); 981 void wlc_lcnphy_tx_pu(struct brcms_phy *pi, bool bEnable); 982 void wlc_lcnphy_stop_tx_tone(struct brcms_phy *pi); 983 void wlc_lcnphy_start_tx_tone(struct brcms_phy *pi, s32 f_kHz, u16 max_val, 984 bool iqcalmode); 985 986 void wlc_phy_txpower_sromlimit_get_nphy(struct brcms_phy *pi, uint chan, 987 u8 *max_pwr, u8 rate_id); 988 void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start, 989 u8 rate_mcs_end, u8 rate_ofdm_start); 990 void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power, u8 rate_ofdm_start, 991 u8 rate_ofdm_end, u8 rate_mcs_start); 992 993 u16 wlc_lcnphy_tempsense(struct brcms_phy *pi, bool mode); 994 s16 wlc_lcnphy_tempsense_new(struct brcms_phy *pi, bool mode); 995 s8 wlc_lcnphy_tempsense_degree(struct brcms_phy *pi, bool mode); 996 s8 wlc_lcnphy_vbatsense(struct brcms_phy *pi, bool mode); 997 void wlc_phy_carrier_suppress_lcnphy(struct brcms_phy *pi); 998 void wlc_lcnphy_crsuprs(struct brcms_phy *pi, int channel); 999 void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode); 1000 void wlc_2064_vco_cal(struct brcms_phy *pi); 1001 1002 void wlc_phy_txpower_recalc_target(struct brcms_phy *pi); 1003 1004 #define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18 1005 #define LCNPHY_TX_POWER_TABLE_SIZE 128 1006 #define LCNPHY_MAX_TX_POWER_INDEX (LCNPHY_TX_POWER_TABLE_SIZE - 1) 1007 #define LCNPHY_TBL_ID_TXPWRCTL 0x07 1008 #define LCNPHY_TX_PWR_CTRL_OFF 0 1009 #define LCNPHY_TX_PWR_CTRL_SW (0x1 << 15) 1010 #define LCNPHY_TX_PWR_CTRL_HW ((0x1 << 15) | \ 1011 (0x1 << 14) | \ 1012 (0x1 << 13)) 1013 1014 #define LCNPHY_TX_PWR_CTRL_TEMPBASED 0xE001 1015 1016 void wlc_lcnphy_write_table(struct brcms_phy *pi, 1017 const struct phytbl_info *pti); 1018 void wlc_lcnphy_read_table(struct brcms_phy *pi, struct phytbl_info *pti); 1019 void wlc_lcnphy_set_tx_iqcc(struct brcms_phy *pi, u16 a, u16 b); 1020 void wlc_lcnphy_set_tx_locc(struct brcms_phy *pi, u16 didq); 1021 void wlc_lcnphy_get_tx_iqcc(struct brcms_phy *pi, u16 *a, u16 *b); 1022 u16 wlc_lcnphy_get_tx_locc(struct brcms_phy *pi); 1023 void wlc_lcnphy_get_radio_loft(struct brcms_phy *pi, u8 *ei0, u8 *eq0, u8 *fi0, 1024 u8 *fq0); 1025 void wlc_lcnphy_calib_modes(struct brcms_phy *pi, uint mode); 1026 void wlc_lcnphy_deaf_mode(struct brcms_phy *pi, bool mode); 1027 bool wlc_phy_tpc_isenabled_lcnphy(struct brcms_phy *pi); 1028 void wlc_lcnphy_tx_pwr_update_npt(struct brcms_phy *pi); 1029 s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1); 1030 void wlc_lcnphy_get_tssi(struct brcms_phy *pi, s8 *ofdm_pwr, s8 *cck_pwr); 1031 void wlc_lcnphy_tx_power_adjustment(struct brcms_phy_pub *ppi); 1032 1033 s32 wlc_lcnphy_rx_signal_power(struct brcms_phy *pi, s32 gain_index); 1034 1035 #define NPHY_MAX_HPVGA1_INDEX 10 1036 #define NPHY_DEF_HPVGA1_INDEXLIMIT 7 1037 1038 struct phy_iq_est { 1039 s32 iq_prod; 1040 u32 i_pwr; 1041 u32 q_pwr; 1042 }; 1043 1044 void wlc_phy_stay_in_carriersearch_nphy(struct brcms_phy *pi, bool enable); 1045 void wlc_nphy_deaf_mode(struct brcms_phy *pi, bool mode); 1046 1047 #define wlc_phy_write_table_nphy(pi, pti) \ 1048 wlc_phy_write_table(pi, pti, 0x72, 0x74, 0x73) 1049 1050 #define wlc_phy_read_table_nphy(pi, pti) \ 1051 wlc_phy_read_table(pi, pti, 0x72, 0x74, 0x73) 1052 1053 #define wlc_nphy_table_addr(pi, id, off) \ 1054 wlc_phy_table_addr((pi), (id), (off), 0x72, 0x74, 0x73) 1055 1056 #define wlc_nphy_table_data_write(pi, w, v) \ 1057 wlc_phy_table_data_write((pi), (w), (v)) 1058 1059 void wlc_phy_table_read_nphy(struct brcms_phy *pi, u32, u32 l, u32 o, u32 w, 1060 void *d); 1061 void wlc_phy_table_write_nphy(struct brcms_phy *pi, u32, u32, u32, u32, 1062 const void *); 1063 1064 #define PHY_IPA(pi) \ 1065 ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \ 1066 (pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec))) 1067 1068 #define BRCMS_PHY_WAR_PR51571(pi) \ 1069 if (NREV_LT((pi)->pubpi.phy_rev, 3)) \ 1070 (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) 1071 1072 void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi, u8 caltype); 1073 void wlc_phy_aci_reset_nphy(struct brcms_phy *pi); 1074 void wlc_phy_pa_override_nphy(struct brcms_phy *pi, bool en); 1075 1076 u8 wlc_phy_get_chan_freq_range_nphy(struct brcms_phy *pi, uint chan); 1077 void wlc_phy_switch_radio_nphy(struct brcms_phy *pi, bool on); 1078 1079 void wlc_phy_stf_chain_upd_nphy(struct brcms_phy *pi); 1080 1081 void wlc_phy_force_rfseq_nphy(struct brcms_phy *pi, u8 cmd); 1082 s16 wlc_phy_tempsense_nphy(struct brcms_phy *pi); 1083 1084 u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val); 1085 1086 void wlc_phy_rx_iq_est_nphy(struct brcms_phy *pi, struct phy_iq_est *est, 1087 u16 num_samps, u8 wait_time, u8 wait_for_crs); 1088 1089 void wlc_phy_rx_iq_coeffs_nphy(struct brcms_phy *pi, u8 write, 1090 struct nphy_iq_comp *comp); 1091 void wlc_phy_aci_and_noise_reduction_nphy(struct brcms_phy *pi); 1092 1093 void wlc_phy_rxcore_setstate_nphy(struct brcms_phy_pub *pih, u8 rxcore_bitmask); 1094 u8 wlc_phy_rxcore_getstate_nphy(struct brcms_phy_pub *pih); 1095 1096 void wlc_phy_txpwrctrl_enable_nphy(struct brcms_phy *pi, u8 ctrl_type); 1097 void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi); 1098 void wlc_phy_txpwr_apply_nphy(struct brcms_phy *pi); 1099 void wlc_phy_txpwr_papd_cal_nphy(struct brcms_phy *pi); 1100 u16 wlc_phy_txpwr_idx_get_nphy(struct brcms_phy *pi); 1101 1102 struct nphy_txgains wlc_phy_get_tx_gain_nphy(struct brcms_phy *pi); 1103 int wlc_phy_cal_txiqlo_nphy(struct brcms_phy *pi, 1104 struct nphy_txgains target_gain, bool full, bool m); 1105 int wlc_phy_cal_rxiq_nphy(struct brcms_phy *pi, struct nphy_txgains target_gain, 1106 u8 type, bool d); 1107 void wlc_phy_txpwr_index_nphy(struct brcms_phy *pi, u8 core_mask, 1108 s8 txpwrindex, bool res); 1109 void wlc_phy_rssisel_nphy(struct brcms_phy *pi, u8 core, u8 rssi_type); 1110 int wlc_phy_poll_rssi_nphy(struct brcms_phy *pi, u8 rssi_type, 1111 s32 *rssi_buf, u8 nsamps); 1112 void wlc_phy_rssi_cal_nphy(struct brcms_phy *pi); 1113 int wlc_phy_aci_scan_nphy(struct brcms_phy *pi); 1114 void wlc_phy_cal_txgainctrl_nphy(struct brcms_phy *pi, s32 dBm_targetpower, 1115 bool debug); 1116 int wlc_phy_tx_tone_nphy(struct brcms_phy *pi, u32 f_kHz, u16 max_val, u8 mode, 1117 u8, bool); 1118 void wlc_phy_stopplayback_nphy(struct brcms_phy *pi); 1119 void wlc_phy_est_tonepwr_nphy(struct brcms_phy *pi, s32 *qdBm_pwrbuf, 1120 u8 num_samps); 1121 void wlc_phy_radio205x_vcocal_nphy(struct brcms_phy *pi); 1122 1123 int wlc_phy_rssi_compute_nphy(struct brcms_phy *pi, struct d11rxhdr *rxh); 1124 1125 #define NPHY_TESTPATTERN_BPHY_EVM 0 1126 #define NPHY_TESTPATTERN_BPHY_RFCS 1 1127 1128 void wlc_phy_nphy_tkip_rifs_war(struct brcms_phy *pi, u8 rifs); 1129 1130 void wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi, s8 *cckoffset, 1131 s8 *ofdmoffset); 1132 s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi, s8 rssi, u16 chanspec); 1133 1134 bool wlc_phy_n_txpower_ipa_ison(struct brcms_phy *pih); 1135 #endif /* _BRCM_PHY_INT_H_ */ 1136