1f843863dSArend van Spriel // SPDX-License-Identifier: ISC 205491d2cSKalle Valo /* 305491d2cSKalle Valo * Copyright (c) 2010 Broadcom Corporation 405491d2cSKalle Valo */ 505491d2cSKalle Valo 605491d2cSKalle Valo #ifndef _BRCM_PHY_INT_H_ 705491d2cSKalle Valo #define _BRCM_PHY_INT_H_ 805491d2cSKalle Valo 905491d2cSKalle Valo #include <types.h> 1005491d2cSKalle Valo #include <brcmu_utils.h> 1105491d2cSKalle Valo #include <brcmu_wifi.h> 1205491d2cSKalle Valo 1305491d2cSKalle Valo #define PHY_VERSION { 1, 82, 8, 0 } 1405491d2cSKalle Valo 1505491d2cSKalle Valo #define LCNXN_BASEREV 16 1605491d2cSKalle Valo 1705491d2cSKalle Valo struct phy_shim_info; 1805491d2cSKalle Valo 1905491d2cSKalle Valo struct brcms_phy_srom_fem { 2005491d2cSKalle Valo /* TSSI positive slope, 1: positive, 0: negative */ 2105491d2cSKalle Valo u8 tssipos; 2205491d2cSKalle Valo /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */ 2305491d2cSKalle Valo u8 extpagain; 2405491d2cSKalle Valo /* support 32 combinations of different Pdet dynamic ranges */ 2505491d2cSKalle Valo u8 pdetrange; 2605491d2cSKalle Valo /* TR switch isolation */ 2705491d2cSKalle Valo u8 triso; 2805491d2cSKalle Valo /* antswctrl lookup table configuration: 32 possible choices */ 2905491d2cSKalle Valo u8 antswctrllut; 3005491d2cSKalle Valo }; 3105491d2cSKalle Valo 3205491d2cSKalle Valo #define ISNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N) 3305491d2cSKalle Valo #define ISLCNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN) 3405491d2cSKalle Valo 3505491d2cSKalle Valo #define PHY_GET_RFATTN(rfgain) ((rfgain) & 0x0f) 3605491d2cSKalle Valo #define PHY_GET_PADMIX(rfgain) (((rfgain) & 0x10) >> 4) 3705491d2cSKalle Valo #define PHY_GET_RFGAINID(rfattn, padmix, width) ((rfattn) + ((padmix)*(width))) 3805491d2cSKalle Valo #define PHY_SAT(x, n) ((x) > ((1<<((n)-1))-1) ? ((1<<((n)-1))-1) : \ 3905491d2cSKalle Valo ((x) < -(1<<((n)-1)) ? -(1<<((n)-1)) : (x))) 4005491d2cSKalle Valo #define PHY_SHIFT_ROUND(x, n) ((x) >= 0 ? ((x)+(1<<((n)-1)))>>(n) : (x)>>(n)) 4105491d2cSKalle Valo #define PHY_HW_ROUND(x, s) ((x >> s) + ((x >> (s-1)) & (s != 0))) 4205491d2cSKalle Valo 4305491d2cSKalle Valo #define CH_5G_GROUP 3 4405491d2cSKalle Valo #define A_LOW_CHANS 0 4505491d2cSKalle Valo #define A_MID_CHANS 1 4605491d2cSKalle Valo #define A_HIGH_CHANS 2 4705491d2cSKalle Valo #define CH_2G_GROUP 1 4805491d2cSKalle Valo #define G_ALL_CHANS 0 4905491d2cSKalle Valo 5005491d2cSKalle Valo #define FIRST_REF5_CHANNUM 149 5105491d2cSKalle Valo #define LAST_REF5_CHANNUM 165 5205491d2cSKalle Valo #define FIRST_5G_CHAN 14 5305491d2cSKalle Valo #define LAST_5G_CHAN 50 5405491d2cSKalle Valo #define FIRST_MID_5G_CHAN 14 5505491d2cSKalle Valo #define LAST_MID_5G_CHAN 35 5605491d2cSKalle Valo #define FIRST_HIGH_5G_CHAN 36 5705491d2cSKalle Valo #define LAST_HIGH_5G_CHAN 41 5805491d2cSKalle Valo #define FIRST_LOW_5G_CHAN 42 5905491d2cSKalle Valo #define LAST_LOW_5G_CHAN 50 6005491d2cSKalle Valo 6105491d2cSKalle Valo #define BASE_LOW_5G_CHAN 4900 6205491d2cSKalle Valo #define BASE_MID_5G_CHAN 5100 6305491d2cSKalle Valo #define BASE_HIGH_5G_CHAN 5500 6405491d2cSKalle Valo 6505491d2cSKalle Valo #define CHAN5G_FREQ(chan) (5000 + chan*5) 6605491d2cSKalle Valo #define CHAN2G_FREQ(chan) (2407 + chan*5) 6705491d2cSKalle Valo 6805491d2cSKalle Valo #define TXP_FIRST_CCK 0 6905491d2cSKalle Valo #define TXP_LAST_CCK 3 7005491d2cSKalle Valo #define TXP_FIRST_OFDM 4 7105491d2cSKalle Valo #define TXP_LAST_OFDM 11 7205491d2cSKalle Valo #define TXP_FIRST_OFDM_20_CDD 12 7305491d2cSKalle Valo #define TXP_LAST_OFDM_20_CDD 19 7405491d2cSKalle Valo #define TXP_FIRST_MCS_20_SISO 20 7505491d2cSKalle Valo #define TXP_LAST_MCS_20_SISO 27 7605491d2cSKalle Valo #define TXP_FIRST_MCS_20_CDD 28 7705491d2cSKalle Valo #define TXP_LAST_MCS_20_CDD 35 7805491d2cSKalle Valo #define TXP_FIRST_MCS_20_STBC 36 7905491d2cSKalle Valo #define TXP_LAST_MCS_20_STBC 43 8005491d2cSKalle Valo #define TXP_FIRST_MCS_20_SDM 44 8105491d2cSKalle Valo #define TXP_LAST_MCS_20_SDM 51 8205491d2cSKalle Valo #define TXP_FIRST_OFDM_40_SISO 52 8305491d2cSKalle Valo #define TXP_LAST_OFDM_40_SISO 59 8405491d2cSKalle Valo #define TXP_FIRST_OFDM_40_CDD 60 8505491d2cSKalle Valo #define TXP_LAST_OFDM_40_CDD 67 8605491d2cSKalle Valo #define TXP_FIRST_MCS_40_SISO 68 8705491d2cSKalle Valo #define TXP_LAST_MCS_40_SISO 75 8805491d2cSKalle Valo #define TXP_FIRST_MCS_40_CDD 76 8905491d2cSKalle Valo #define TXP_LAST_MCS_40_CDD 83 9005491d2cSKalle Valo #define TXP_FIRST_MCS_40_STBC 84 9105491d2cSKalle Valo #define TXP_LAST_MCS_40_STBC 91 9205491d2cSKalle Valo #define TXP_FIRST_MCS_40_SDM 92 9305491d2cSKalle Valo #define TXP_LAST_MCS_40_SDM 99 9405491d2cSKalle Valo #define TXP_MCS_32 100 9505491d2cSKalle Valo #define TXP_NUM_RATES 101 9605491d2cSKalle Valo #define ADJ_PWR_TBL_LEN 84 9705491d2cSKalle Valo 9805491d2cSKalle Valo #define TXP_FIRST_SISO_MCS_20 20 9905491d2cSKalle Valo #define TXP_LAST_SISO_MCS_20 27 10005491d2cSKalle Valo 10105491d2cSKalle Valo #define PHY_CORE_NUM_1 1 10205491d2cSKalle Valo #define PHY_CORE_NUM_2 2 10305491d2cSKalle Valo #define PHY_CORE_NUM_3 3 10405491d2cSKalle Valo #define PHY_CORE_NUM_4 4 10505491d2cSKalle Valo #define PHY_CORE_MAX PHY_CORE_NUM_4 10605491d2cSKalle Valo #define PHY_CORE_0 0 10705491d2cSKalle Valo #define PHY_CORE_1 1 10805491d2cSKalle Valo #define PHY_CORE_2 2 10905491d2cSKalle Valo #define PHY_CORE_3 3 11005491d2cSKalle Valo 11105491d2cSKalle Valo #define MA_WINDOW_SZ 8 11205491d2cSKalle Valo 11305491d2cSKalle Valo #define PHY_NOISE_SAMPLE_MON 1 11405491d2cSKalle Valo #define PHY_NOISE_SAMPLE_EXTERNAL 2 11505491d2cSKalle Valo #define PHY_NOISE_WINDOW_SZ 16 11605491d2cSKalle Valo #define PHY_NOISE_GLITCH_INIT_MA 10 11705491d2cSKalle Valo #define PHY_NOISE_GLITCH_INIT_MA_BADPlCP 10 11805491d2cSKalle Valo #define PHY_NOISE_STATE_MON 0x1 11905491d2cSKalle Valo #define PHY_NOISE_STATE_EXTERNAL 0x2 12005491d2cSKalle Valo #define PHY_NOISE_SAMPLE_LOG_NUM_NPHY 10 12105491d2cSKalle Valo #define PHY_NOISE_SAMPLE_LOG_NUM_UCODE 9 12205491d2cSKalle Valo 12305491d2cSKalle Valo #define PHY_NOISE_OFFSETFACT_4322 (-103) 12405491d2cSKalle Valo #define PHY_NOISE_MA_WINDOW_SZ 2 12505491d2cSKalle Valo 12605491d2cSKalle Valo #define PHY_RSSI_TABLE_SIZE 64 12705491d2cSKalle Valo #define RSSI_ANT_MERGE_MAX 0 12805491d2cSKalle Valo #define RSSI_ANT_MERGE_MIN 1 12905491d2cSKalle Valo #define RSSI_ANT_MERGE_AVG 2 13005491d2cSKalle Valo 13105491d2cSKalle Valo #define PHY_TSSI_TABLE_SIZE 64 13205491d2cSKalle Valo #define APHY_TSSI_TABLE_SIZE 256 13305491d2cSKalle Valo #define TX_GAIN_TABLE_LENGTH 64 13405491d2cSKalle Valo #define DEFAULT_11A_TXP_IDX 24 13505491d2cSKalle Valo #define NUM_TSSI_FRAMES 4 13605491d2cSKalle Valo #define NULL_TSSI 0x7f 13705491d2cSKalle Valo #define NULL_TSSI_W 0x7f7f 13805491d2cSKalle Valo 13905491d2cSKalle Valo #define PHY_PAPD_EPS_TBL_SIZE_LCNPHY 64 14005491d2cSKalle Valo 14105491d2cSKalle Valo #define LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL 9 14205491d2cSKalle Valo 14305491d2cSKalle Valo #define PHY_TXPWR_MIN 10 14405491d2cSKalle Valo #define PHY_TXPWR_MIN_NPHY 8 14505491d2cSKalle Valo #define RADIOPWR_OVERRIDE_DEF (-1) 14605491d2cSKalle Valo 14705491d2cSKalle Valo #define PWRTBL_NUM_COEFF 3 14805491d2cSKalle Valo 14905491d2cSKalle Valo #define SPURAVOID_DISABLE 0 15005491d2cSKalle Valo #define SPURAVOID_AUTO 1 15105491d2cSKalle Valo #define SPURAVOID_FORCEON 2 15205491d2cSKalle Valo #define SPURAVOID_FORCEON2 3 15305491d2cSKalle Valo 15405491d2cSKalle Valo #define PHY_SW_TIMER_FAST 15 15505491d2cSKalle Valo #define PHY_SW_TIMER_SLOW 60 15605491d2cSKalle Valo #define PHY_SW_TIMER_GLACIAL 120 15705491d2cSKalle Valo 15805491d2cSKalle Valo #define PHY_PERICAL_AUTO 0 15905491d2cSKalle Valo #define PHY_PERICAL_FULL 1 16005491d2cSKalle Valo #define PHY_PERICAL_PARTIAL 2 16105491d2cSKalle Valo 16205491d2cSKalle Valo #define PHY_PERICAL_NODELAY 0 16305491d2cSKalle Valo #define PHY_PERICAL_INIT_DELAY 5 16405491d2cSKalle Valo #define PHY_PERICAL_ASSOC_DELAY 5 16505491d2cSKalle Valo #define PHY_PERICAL_WDOG_DELAY 5 16605491d2cSKalle Valo 16705491d2cSKalle Valo #define MPHASE_TXCAL_NUMCMDS 2 16805491d2cSKalle Valo 16905491d2cSKalle Valo #define PHY_PERICAL_MPHASE_PENDING(pi) \ 17005491d2cSKalle Valo (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE) 17105491d2cSKalle Valo 17205491d2cSKalle Valo enum { 17305491d2cSKalle Valo MPHASE_CAL_STATE_IDLE = 0, 17405491d2cSKalle Valo MPHASE_CAL_STATE_INIT = 1, 17505491d2cSKalle Valo MPHASE_CAL_STATE_TXPHASE0, 17605491d2cSKalle Valo MPHASE_CAL_STATE_TXPHASE1, 17705491d2cSKalle Valo MPHASE_CAL_STATE_TXPHASE2, 17805491d2cSKalle Valo MPHASE_CAL_STATE_TXPHASE3, 17905491d2cSKalle Valo MPHASE_CAL_STATE_TXPHASE4, 18005491d2cSKalle Valo MPHASE_CAL_STATE_TXPHASE5, 18105491d2cSKalle Valo MPHASE_CAL_STATE_PAPDCAL, 18205491d2cSKalle Valo MPHASE_CAL_STATE_RXCAL, 18305491d2cSKalle Valo MPHASE_CAL_STATE_RSSICAL, 18405491d2cSKalle Valo MPHASE_CAL_STATE_IDLETSSI 18505491d2cSKalle Valo }; 18605491d2cSKalle Valo 18705491d2cSKalle Valo enum phy_cal_mode { 18805491d2cSKalle Valo CAL_FULL, 18905491d2cSKalle Valo CAL_RECAL, 19005491d2cSKalle Valo CAL_CURRECAL, 19105491d2cSKalle Valo CAL_DIGCAL, 19205491d2cSKalle Valo CAL_GCTRL, 19305491d2cSKalle Valo CAL_SOFT, 19405491d2cSKalle Valo CAL_DIGLO 19505491d2cSKalle Valo }; 19605491d2cSKalle Valo 19705491d2cSKalle Valo #define RDR_NTIERS 1 19805491d2cSKalle Valo #define RDR_TIER_SIZE 64 19905491d2cSKalle Valo #define RDR_LIST_SIZE (512/3) 20005491d2cSKalle Valo #define RDR_EPOCH_SIZE 40 20105491d2cSKalle Valo #define RDR_NANTENNAS 2 20205491d2cSKalle Valo #define RDR_NTIER_SIZE RDR_LIST_SIZE 20305491d2cSKalle Valo #define RDR_LP_BUFFER_SIZE 64 20405491d2cSKalle Valo #define LP_LEN_HIS_SIZE 10 20505491d2cSKalle Valo 20605491d2cSKalle Valo #define STATIC_NUM_RF 32 20705491d2cSKalle Valo #define STATIC_NUM_BB 9 20805491d2cSKalle Valo 20905491d2cSKalle Valo #define BB_MULT_MASK 0x0000ffff 21005491d2cSKalle Valo #define BB_MULT_VALID_MASK 0x80000000 21105491d2cSKalle Valo 21205491d2cSKalle Valo #define PHY_CHAIN_TX_DISABLE_TEMP 115 21305491d2cSKalle Valo #define PHY_HYSTERESIS_DELTATEMP 5 21405491d2cSKalle Valo 21505491d2cSKalle Valo #define SCAN_INPROG_PHY(pi) \ 21605491d2cSKalle Valo (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN)) 21705491d2cSKalle Valo 21805491d2cSKalle Valo #define PLT_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT)) 21905491d2cSKalle Valo 22005491d2cSKalle Valo #define ASSOC_INPROG_PHY(pi) \ 22105491d2cSKalle Valo (mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC)) 22205491d2cSKalle Valo 22305491d2cSKalle Valo #define SCAN_RM_IN_PROGRESS(pi) \ 22405491d2cSKalle Valo (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN | PHY_HOLD_FOR_RM)) 22505491d2cSKalle Valo 22605491d2cSKalle Valo #define PHY_MUTED(pi) \ 22705491d2cSKalle Valo (mboolisset(pi->measure_hold, PHY_HOLD_FOR_MUTE)) 22805491d2cSKalle Valo 22905491d2cSKalle Valo #define PUB_NOT_ASSOC(pi) \ 23005491d2cSKalle Valo (mboolisset(pi->measure_hold, PHY_HOLD_FOR_NOT_ASSOC)) 23105491d2cSKalle Valo 23205491d2cSKalle Valo struct phy_table_info { 23305491d2cSKalle Valo uint table; 23405491d2cSKalle Valo int q; 23505491d2cSKalle Valo uint max; 23605491d2cSKalle Valo }; 23705491d2cSKalle Valo 23805491d2cSKalle Valo struct phytbl_info { 23905491d2cSKalle Valo const void *tbl_ptr; 24005491d2cSKalle Valo u32 tbl_len; 24105491d2cSKalle Valo u32 tbl_id; 24205491d2cSKalle Valo u32 tbl_offset; 24305491d2cSKalle Valo u32 tbl_width; 24405491d2cSKalle Valo }; 24505491d2cSKalle Valo 24605491d2cSKalle Valo struct interference_info { 24705491d2cSKalle Valo u8 curr_home_channel; 24805491d2cSKalle Valo u16 crsminpwrthld_40_stored; 24905491d2cSKalle Valo u16 crsminpwrthld_20L_stored; 25005491d2cSKalle Valo u16 crsminpwrthld_20U_stored; 25105491d2cSKalle Valo u16 init_gain_code_core1_stored; 25205491d2cSKalle Valo u16 init_gain_code_core2_stored; 25305491d2cSKalle Valo u16 init_gain_codeb_core1_stored; 25405491d2cSKalle Valo u16 init_gain_codeb_core2_stored; 25505491d2cSKalle Valo u16 init_gain_table_stored[4]; 25605491d2cSKalle Valo 25705491d2cSKalle Valo u16 clip1_hi_gain_code_core1_stored; 25805491d2cSKalle Valo u16 clip1_hi_gain_code_core2_stored; 25905491d2cSKalle Valo u16 clip1_hi_gain_codeb_core1_stored; 26005491d2cSKalle Valo u16 clip1_hi_gain_codeb_core2_stored; 26105491d2cSKalle Valo u16 nb_clip_thresh_core1_stored; 26205491d2cSKalle Valo u16 nb_clip_thresh_core2_stored; 26305491d2cSKalle Valo u16 init_ofdmlna2gainchange_stored[4]; 26405491d2cSKalle Valo u16 init_ccklna2gainchange_stored[4]; 26505491d2cSKalle Valo u16 clip1_lo_gain_code_core1_stored; 26605491d2cSKalle Valo u16 clip1_lo_gain_code_core2_stored; 26705491d2cSKalle Valo u16 clip1_lo_gain_codeb_core1_stored; 26805491d2cSKalle Valo u16 clip1_lo_gain_codeb_core2_stored; 26905491d2cSKalle Valo u16 w1_clip_thresh_core1_stored; 27005491d2cSKalle Valo u16 w1_clip_thresh_core2_stored; 27105491d2cSKalle Valo u16 radio_2056_core1_rssi_gain_stored; 27205491d2cSKalle Valo u16 radio_2056_core2_rssi_gain_stored; 27305491d2cSKalle Valo u16 energy_drop_timeout_len_stored; 27405491d2cSKalle Valo 27505491d2cSKalle Valo u16 ed_crs40_assertthld0_stored; 27605491d2cSKalle Valo u16 ed_crs40_assertthld1_stored; 27705491d2cSKalle Valo u16 ed_crs40_deassertthld0_stored; 27805491d2cSKalle Valo u16 ed_crs40_deassertthld1_stored; 27905491d2cSKalle Valo u16 ed_crs20L_assertthld0_stored; 28005491d2cSKalle Valo u16 ed_crs20L_assertthld1_stored; 28105491d2cSKalle Valo u16 ed_crs20L_deassertthld0_stored; 28205491d2cSKalle Valo u16 ed_crs20L_deassertthld1_stored; 28305491d2cSKalle Valo u16 ed_crs20U_assertthld0_stored; 28405491d2cSKalle Valo u16 ed_crs20U_assertthld1_stored; 28505491d2cSKalle Valo u16 ed_crs20U_deassertthld0_stored; 28605491d2cSKalle Valo u16 ed_crs20U_deassertthld1_stored; 28705491d2cSKalle Valo 28805491d2cSKalle Valo u16 badplcp_ma; 28905491d2cSKalle Valo u16 badplcp_ma_previous; 29005491d2cSKalle Valo u16 badplcp_ma_total; 29105491d2cSKalle Valo u16 badplcp_ma_list[MA_WINDOW_SZ]; 29205491d2cSKalle Valo int badplcp_ma_index; 29305491d2cSKalle Valo s16 pre_badplcp_cnt; 29405491d2cSKalle Valo s16 bphy_pre_badplcp_cnt; 29505491d2cSKalle Valo 29605491d2cSKalle Valo u16 init_gain_core1; 29705491d2cSKalle Valo u16 init_gain_core2; 29805491d2cSKalle Valo u16 init_gainb_core1; 29905491d2cSKalle Valo u16 init_gainb_core2; 30005491d2cSKalle Valo u16 init_gain_rfseq[4]; 30105491d2cSKalle Valo 30205491d2cSKalle Valo u16 crsminpwr0; 30305491d2cSKalle Valo u16 crsminpwrl0; 30405491d2cSKalle Valo u16 crsminpwru0; 30505491d2cSKalle Valo 30605491d2cSKalle Valo s16 crsminpwr_index; 30705491d2cSKalle Valo 30805491d2cSKalle Valo u16 radio_2057_core1_rssi_wb1a_gc_stored; 30905491d2cSKalle Valo u16 radio_2057_core2_rssi_wb1a_gc_stored; 31005491d2cSKalle Valo u16 radio_2057_core1_rssi_wb1g_gc_stored; 31105491d2cSKalle Valo u16 radio_2057_core2_rssi_wb1g_gc_stored; 31205491d2cSKalle Valo u16 radio_2057_core1_rssi_wb2_gc_stored; 31305491d2cSKalle Valo u16 radio_2057_core2_rssi_wb2_gc_stored; 31405491d2cSKalle Valo u16 radio_2057_core1_rssi_nb_gc_stored; 31505491d2cSKalle Valo u16 radio_2057_core2_rssi_nb_gc_stored; 31605491d2cSKalle Valo }; 31705491d2cSKalle Valo 31805491d2cSKalle Valo struct aci_save_gphy { 31905491d2cSKalle Valo u16 rc_cal_ovr; 32005491d2cSKalle Valo u16 phycrsth1; 32105491d2cSKalle Valo u16 phycrsth2; 32205491d2cSKalle Valo u16 init_n1p1_gain; 32305491d2cSKalle Valo u16 p1_p2_gain; 32405491d2cSKalle Valo u16 n1_n2_gain; 32505491d2cSKalle Valo u16 n1_p1_gain; 32605491d2cSKalle Valo u16 div_search_gain; 32705491d2cSKalle Valo u16 div_p1_p2_gain; 32805491d2cSKalle Valo u16 div_search_gn_change; 32905491d2cSKalle Valo u16 table_7_2; 33005491d2cSKalle Valo u16 table_7_3; 33105491d2cSKalle Valo u16 cckshbits_gnref; 33205491d2cSKalle Valo u16 clip_thresh; 33305491d2cSKalle Valo u16 clip2_thresh; 33405491d2cSKalle Valo u16 clip3_thresh; 33505491d2cSKalle Valo u16 clip_p2_thresh; 33605491d2cSKalle Valo u16 clip_pwdn_thresh; 33705491d2cSKalle Valo u16 clip_n1p1_thresh; 33805491d2cSKalle Valo u16 clip_n1_pwdn_thresh; 33905491d2cSKalle Valo u16 bbconfig; 34005491d2cSKalle Valo u16 cthr_sthr_shdin; 34105491d2cSKalle Valo u16 energy; 34205491d2cSKalle Valo u16 clip_p1_p2_thresh; 34305491d2cSKalle Valo u16 threshold; 34405491d2cSKalle Valo u16 reg15; 34505491d2cSKalle Valo u16 reg16; 34605491d2cSKalle Valo u16 reg17; 34705491d2cSKalle Valo u16 div_srch_idx; 34805491d2cSKalle Valo u16 div_srch_p1_p2; 34905491d2cSKalle Valo u16 div_srch_gn_back; 35005491d2cSKalle Valo u16 ant_dwell; 35105491d2cSKalle Valo u16 ant_wr_settle; 35205491d2cSKalle Valo }; 35305491d2cSKalle Valo 35405491d2cSKalle Valo struct lo_complex_abgphy_info { 35505491d2cSKalle Valo s8 i; 35605491d2cSKalle Valo s8 q; 35705491d2cSKalle Valo }; 35805491d2cSKalle Valo 35905491d2cSKalle Valo struct nphy_iq_comp { 36005491d2cSKalle Valo s16 a0; 36105491d2cSKalle Valo s16 b0; 36205491d2cSKalle Valo s16 a1; 36305491d2cSKalle Valo s16 b1; 36405491d2cSKalle Valo }; 36505491d2cSKalle Valo 36605491d2cSKalle Valo struct nphy_txpwrindex { 36705491d2cSKalle Valo s8 index; 36805491d2cSKalle Valo s8 index_internal; 36905491d2cSKalle Valo s8 index_internal_save; 37005491d2cSKalle Valo u16 AfectrlOverride; 37105491d2cSKalle Valo u16 AfeCtrlDacGain; 37205491d2cSKalle Valo u16 rad_gain; 37305491d2cSKalle Valo u8 bbmult; 37405491d2cSKalle Valo u16 iqcomp_a; 37505491d2cSKalle Valo u16 iqcomp_b; 37605491d2cSKalle Valo u16 locomp; 37705491d2cSKalle Valo }; 37805491d2cSKalle Valo 37905491d2cSKalle Valo struct txiqcal_cache { 38005491d2cSKalle Valo 38105491d2cSKalle Valo u16 txcal_coeffs_2G[8]; 38205491d2cSKalle Valo u16 txcal_radio_regs_2G[8]; 38305491d2cSKalle Valo struct nphy_iq_comp rxcal_coeffs_2G; 38405491d2cSKalle Valo 38505491d2cSKalle Valo u16 txcal_coeffs_5G[8]; 38605491d2cSKalle Valo u16 txcal_radio_regs_5G[8]; 38705491d2cSKalle Valo struct nphy_iq_comp rxcal_coeffs_5G; 38805491d2cSKalle Valo }; 38905491d2cSKalle Valo 39005491d2cSKalle Valo struct nphy_pwrctrl { 39105491d2cSKalle Valo s8 max_pwr_2g; 39205491d2cSKalle Valo s8 idle_targ_2g; 39305491d2cSKalle Valo s16 pwrdet_2g_a1; 39405491d2cSKalle Valo s16 pwrdet_2g_b0; 39505491d2cSKalle Valo s16 pwrdet_2g_b1; 39605491d2cSKalle Valo s8 max_pwr_5gm; 39705491d2cSKalle Valo s8 idle_targ_5gm; 39805491d2cSKalle Valo s8 max_pwr_5gh; 39905491d2cSKalle Valo s8 max_pwr_5gl; 40005491d2cSKalle Valo s16 pwrdet_5gm_a1; 40105491d2cSKalle Valo s16 pwrdet_5gm_b0; 40205491d2cSKalle Valo s16 pwrdet_5gm_b1; 40305491d2cSKalle Valo s16 pwrdet_5gl_a1; 40405491d2cSKalle Valo s16 pwrdet_5gl_b0; 40505491d2cSKalle Valo s16 pwrdet_5gl_b1; 40605491d2cSKalle Valo s16 pwrdet_5gh_a1; 40705491d2cSKalle Valo s16 pwrdet_5gh_b0; 40805491d2cSKalle Valo s16 pwrdet_5gh_b1; 40905491d2cSKalle Valo s8 idle_targ_5gl; 41005491d2cSKalle Valo s8 idle_targ_5gh; 41105491d2cSKalle Valo s8 idle_tssi_2g; 41205491d2cSKalle Valo s8 idle_tssi_5g; 41305491d2cSKalle Valo s8 idle_tssi; 41405491d2cSKalle Valo s16 a1; 41505491d2cSKalle Valo s16 b0; 41605491d2cSKalle Valo s16 b1; 41705491d2cSKalle Valo }; 41805491d2cSKalle Valo 41905491d2cSKalle Valo struct nphy_txgains { 42005491d2cSKalle Valo u16 txlpf[2]; 42105491d2cSKalle Valo u16 txgm[2]; 42205491d2cSKalle Valo u16 pga[2]; 42305491d2cSKalle Valo u16 pad[2]; 42405491d2cSKalle Valo u16 ipa[2]; 42505491d2cSKalle Valo }; 42605491d2cSKalle Valo 42705491d2cSKalle Valo #define PHY_NOISEVAR_BUFSIZE 10 42805491d2cSKalle Valo 42905491d2cSKalle Valo struct nphy_noisevar_buf { 43005491d2cSKalle Valo int bufcount; 43105491d2cSKalle Valo int tone_id[PHY_NOISEVAR_BUFSIZE]; 43205491d2cSKalle Valo u32 noise_vars[PHY_NOISEVAR_BUFSIZE]; 43305491d2cSKalle Valo u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE]; 43405491d2cSKalle Valo }; 43505491d2cSKalle Valo 43605491d2cSKalle Valo struct rssical_cache { 43705491d2cSKalle Valo u16 rssical_radio_regs_2G[2]; 43805491d2cSKalle Valo u16 rssical_phyregs_2G[12]; 43905491d2cSKalle Valo 44005491d2cSKalle Valo u16 rssical_radio_regs_5G[2]; 44105491d2cSKalle Valo u16 rssical_phyregs_5G[12]; 44205491d2cSKalle Valo }; 44305491d2cSKalle Valo 44405491d2cSKalle Valo struct lcnphy_cal_results { 44505491d2cSKalle Valo 44605491d2cSKalle Valo u16 txiqlocal_a; 44705491d2cSKalle Valo u16 txiqlocal_b; 44805491d2cSKalle Valo u16 txiqlocal_didq; 44905491d2cSKalle Valo u8 txiqlocal_ei0; 45005491d2cSKalle Valo u8 txiqlocal_eq0; 45105491d2cSKalle Valo u8 txiqlocal_fi0; 45205491d2cSKalle Valo u8 txiqlocal_fq0; 45305491d2cSKalle Valo 45405491d2cSKalle Valo u16 txiqlocal_bestcoeffs[11]; 45505491d2cSKalle Valo u16 txiqlocal_bestcoeffs_valid; 45605491d2cSKalle Valo 45705491d2cSKalle Valo u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY]; 45805491d2cSKalle Valo u16 analog_gain_ref; 45905491d2cSKalle Valo u16 lut_begin; 46005491d2cSKalle Valo u16 lut_end; 46105491d2cSKalle Valo u16 lut_step; 46205491d2cSKalle Valo u16 rxcompdbm; 46305491d2cSKalle Valo u16 papdctrl; 46405491d2cSKalle Valo u16 sslpnCalibClkEnCtrl; 46505491d2cSKalle Valo 46605491d2cSKalle Valo u16 rxiqcal_coeff_a0; 46705491d2cSKalle Valo u16 rxiqcal_coeff_b0; 46805491d2cSKalle Valo }; 46905491d2cSKalle Valo 47005491d2cSKalle Valo struct shared_phy { 47105491d2cSKalle Valo struct brcms_phy *phy_head; 47205491d2cSKalle Valo uint unit; 47305491d2cSKalle Valo struct phy_shim_info *physhim; 47405491d2cSKalle Valo uint corerev; 47505491d2cSKalle Valo u32 machwcap; 47605491d2cSKalle Valo bool up; 47705491d2cSKalle Valo bool clk; 47805491d2cSKalle Valo uint now; 47905491d2cSKalle Valo u16 vid; 48005491d2cSKalle Valo u16 did; 48105491d2cSKalle Valo uint chip; 48205491d2cSKalle Valo uint chiprev; 48305491d2cSKalle Valo uint chippkg; 48405491d2cSKalle Valo uint sromrev; 48505491d2cSKalle Valo uint boardtype; 48605491d2cSKalle Valo uint boardrev; 48705491d2cSKalle Valo u32 boardflags; 48805491d2cSKalle Valo u32 boardflags2; 48905491d2cSKalle Valo uint fast_timer; 49005491d2cSKalle Valo uint slow_timer; 49105491d2cSKalle Valo uint glacial_timer; 49205491d2cSKalle Valo u8 rx_antdiv; 49305491d2cSKalle Valo s8 phy_noise_window[MA_WINDOW_SZ]; 49405491d2cSKalle Valo uint phy_noise_index; 49505491d2cSKalle Valo u8 hw_phytxchain; 49605491d2cSKalle Valo u8 hw_phyrxchain; 49705491d2cSKalle Valo u8 phytxchain; 49805491d2cSKalle Valo u8 phyrxchain; 49905491d2cSKalle Valo u8 rssi_mode; 50005491d2cSKalle Valo bool _rifs_phy; 50105491d2cSKalle Valo }; 50205491d2cSKalle Valo 50305491d2cSKalle Valo struct brcms_phy_pub { 50405491d2cSKalle Valo uint phy_type; 50505491d2cSKalle Valo uint phy_rev; 50605491d2cSKalle Valo u8 phy_corenum; 50705491d2cSKalle Valo u16 radioid; 50805491d2cSKalle Valo u8 radiorev; 50905491d2cSKalle Valo u8 radiover; 51005491d2cSKalle Valo 51105491d2cSKalle Valo uint coreflags; 51205491d2cSKalle Valo uint ana_rev; 51305491d2cSKalle Valo bool abgphy_encore; 51405491d2cSKalle Valo }; 51505491d2cSKalle Valo 51605491d2cSKalle Valo struct phy_func_ptr { 51705491d2cSKalle Valo void (*init)(struct brcms_phy *); 51805491d2cSKalle Valo void (*calinit)(struct brcms_phy *); 51905491d2cSKalle Valo void (*chanset)(struct brcms_phy *, u16 chanspec); 52005491d2cSKalle Valo void (*txpwrrecalc)(struct brcms_phy *); 52105491d2cSKalle Valo int (*longtrn)(struct brcms_phy *, int); 52205491d2cSKalle Valo void (*txiqccget)(struct brcms_phy *, u16 *, u16 *); 52305491d2cSKalle Valo void (*txiqccset)(struct brcms_phy *, u16, u16); 52405491d2cSKalle Valo u16 (*txloccget)(struct brcms_phy *); 52505491d2cSKalle Valo void (*radioloftget)(struct brcms_phy *, u8 *, u8 *, u8 *, u8 *); 52605491d2cSKalle Valo void (*carrsuppr)(struct brcms_phy *); 52705491d2cSKalle Valo s32 (*rxsigpwr)(struct brcms_phy *, s32); 52805491d2cSKalle Valo void (*detach)(struct brcms_phy *); 52905491d2cSKalle Valo }; 53005491d2cSKalle Valo 53105491d2cSKalle Valo struct brcms_phy { 53205491d2cSKalle Valo struct brcms_phy_pub pubpi_ro; 53305491d2cSKalle Valo struct shared_phy *sh; 53405491d2cSKalle Valo struct phy_func_ptr pi_fptr; 53505491d2cSKalle Valo 53605491d2cSKalle Valo union { 53705491d2cSKalle Valo struct brcms_phy_lcnphy *pi_lcnphy; 53805491d2cSKalle Valo } u; 53905491d2cSKalle Valo bool user_txpwr_at_rfport; 54005491d2cSKalle Valo 54105491d2cSKalle Valo struct bcma_device *d11core; 54205491d2cSKalle Valo struct brcms_phy *next; 54305491d2cSKalle Valo struct brcms_phy_pub pubpi; 54405491d2cSKalle Valo 54505491d2cSKalle Valo bool do_initcal; 54605491d2cSKalle Valo bool phytest_on; 54705491d2cSKalle Valo bool ofdm_rateset_war; 54805491d2cSKalle Valo bool bf_preempt_4306; 54905491d2cSKalle Valo u16 radio_chanspec; 55005491d2cSKalle Valo u8 antsel_type; 55105491d2cSKalle Valo u16 bw; 55205491d2cSKalle Valo u8 txpwr_percent; 55305491d2cSKalle Valo bool phy_init_por; 55405491d2cSKalle Valo 55505491d2cSKalle Valo bool init_in_progress; 55605491d2cSKalle Valo bool initialized; 55705491d2cSKalle Valo bool sbtml_gm; 55805491d2cSKalle Valo uint refcnt; 55905491d2cSKalle Valo bool watchdog_override; 56005491d2cSKalle Valo u8 phynoise_state; 56105491d2cSKalle Valo uint phynoise_now; 56205491d2cSKalle Valo int phynoise_chan_watchdog; 56305491d2cSKalle Valo bool phynoise_polling; 56405491d2cSKalle Valo bool disable_percal; 56505491d2cSKalle Valo u32 measure_hold; 56605491d2cSKalle Valo 56705491d2cSKalle Valo s16 txpa_2g[PWRTBL_NUM_COEFF]; 56805491d2cSKalle Valo s16 txpa_2g_low_temp[PWRTBL_NUM_COEFF]; 56905491d2cSKalle Valo s16 txpa_2g_high_temp[PWRTBL_NUM_COEFF]; 57005491d2cSKalle Valo s16 txpa_5g_low[PWRTBL_NUM_COEFF]; 57105491d2cSKalle Valo s16 txpa_5g_mid[PWRTBL_NUM_COEFF]; 57205491d2cSKalle Valo s16 txpa_5g_hi[PWRTBL_NUM_COEFF]; 57305491d2cSKalle Valo 57405491d2cSKalle Valo u8 tx_srom_max_2g; 57505491d2cSKalle Valo u8 tx_srom_max_5g_low; 57605491d2cSKalle Valo u8 tx_srom_max_5g_mid; 57705491d2cSKalle Valo u8 tx_srom_max_5g_hi; 57805491d2cSKalle Valo u8 tx_srom_max_rate_2g[TXP_NUM_RATES]; 57905491d2cSKalle Valo u8 tx_srom_max_rate_5g_low[TXP_NUM_RATES]; 58005491d2cSKalle Valo u8 tx_srom_max_rate_5g_mid[TXP_NUM_RATES]; 58105491d2cSKalle Valo u8 tx_srom_max_rate_5g_hi[TXP_NUM_RATES]; 58205491d2cSKalle Valo u8 tx_user_target[TXP_NUM_RATES]; 58305491d2cSKalle Valo s8 tx_power_offset[TXP_NUM_RATES]; 58405491d2cSKalle Valo u8 tx_power_target[TXP_NUM_RATES]; 58505491d2cSKalle Valo 58605491d2cSKalle Valo struct brcms_phy_srom_fem srom_fem2g; 58705491d2cSKalle Valo struct brcms_phy_srom_fem srom_fem5g; 58805491d2cSKalle Valo 58905491d2cSKalle Valo u8 tx_power_max; 59005491d2cSKalle Valo u8 tx_power_max_rate_ind; 59105491d2cSKalle Valo bool hwpwrctrl; 59205491d2cSKalle Valo u8 nphy_txpwrctrl; 59305491d2cSKalle Valo s8 nphy_txrx_chain; 59405491d2cSKalle Valo bool phy_5g_pwrgain; 59505491d2cSKalle Valo 59605491d2cSKalle Valo u16 phy_wreg; 59705491d2cSKalle Valo u16 phy_wreg_limit; 59805491d2cSKalle Valo 59905491d2cSKalle Valo s8 n_preamble_override; 60005491d2cSKalle Valo u8 antswitch; 60105491d2cSKalle Valo u8 aa2g, aa5g; 60205491d2cSKalle Valo 60305491d2cSKalle Valo s8 idle_tssi[CH_5G_GROUP]; 60405491d2cSKalle Valo s8 target_idle_tssi; 60505491d2cSKalle Valo s8 txpwr_est_Pout; 60605491d2cSKalle Valo u8 tx_power_min; 60705491d2cSKalle Valo u8 txpwr_limit[TXP_NUM_RATES]; 60805491d2cSKalle Valo u8 txpwr_env_limit[TXP_NUM_RATES]; 60905491d2cSKalle Valo u8 adj_pwr_tbl_nphy[ADJ_PWR_TBL_LEN]; 61005491d2cSKalle Valo 61105491d2cSKalle Valo bool channel_14_wide_filter; 61205491d2cSKalle Valo 61305491d2cSKalle Valo bool txpwroverride; 61405491d2cSKalle Valo bool txpwridx_override_aphy; 61505491d2cSKalle Valo s16 radiopwr_override; 61605491d2cSKalle Valo u16 hwpwr_txcur; 61705491d2cSKalle Valo u8 saved_txpwr_idx; 61805491d2cSKalle Valo 61905491d2cSKalle Valo bool edcrs_threshold_lock; 62005491d2cSKalle Valo 62105491d2cSKalle Valo u32 tr_R_gain_val; 62205491d2cSKalle Valo u32 tr_T_gain_val; 62305491d2cSKalle Valo 62405491d2cSKalle Valo s16 ofdm_analog_filt_bw_override; 62505491d2cSKalle Valo s16 cck_analog_filt_bw_override; 62605491d2cSKalle Valo s16 ofdm_rccal_override; 62705491d2cSKalle Valo s16 cck_rccal_override; 62805491d2cSKalle Valo u16 extlna_type; 62905491d2cSKalle Valo 63005491d2cSKalle Valo uint interference_mode_crs_time; 63105491d2cSKalle Valo u16 crsglitch_prev; 63205491d2cSKalle Valo bool interference_mode_crs; 63305491d2cSKalle Valo 63405491d2cSKalle Valo u32 phy_tx_tone_freq; 63505491d2cSKalle Valo uint phy_lastcal; 63605491d2cSKalle Valo bool phy_forcecal; 63705491d2cSKalle Valo bool phy_fixed_noise; 63805491d2cSKalle Valo u32 xtalfreq; 63905491d2cSKalle Valo u8 pdiv; 64005491d2cSKalle Valo s8 carrier_suppr_disable; 64105491d2cSKalle Valo 64205491d2cSKalle Valo bool phy_bphy_evm; 64305491d2cSKalle Valo bool phy_bphy_rfcs; 64405491d2cSKalle Valo s8 phy_scraminit; 64505491d2cSKalle Valo u8 phy_gpiosel; 64605491d2cSKalle Valo 64705491d2cSKalle Valo s16 phy_txcore_disable_temp; 64805491d2cSKalle Valo s16 phy_txcore_enable_temp; 64905491d2cSKalle Valo s8 phy_tempsense_offset; 65005491d2cSKalle Valo bool phy_txcore_heatedup; 65105491d2cSKalle Valo 65205491d2cSKalle Valo u16 radiopwr; 65305491d2cSKalle Valo u16 bb_atten; 65405491d2cSKalle Valo u16 txctl1; 65505491d2cSKalle Valo 65605491d2cSKalle Valo u16 mintxbias; 65705491d2cSKalle Valo u16 mintxmag; 65805491d2cSKalle Valo struct lo_complex_abgphy_info gphy_locomp_iq 65905491d2cSKalle Valo [STATIC_NUM_RF][STATIC_NUM_BB]; 66005491d2cSKalle Valo s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB]; 66105491d2cSKalle Valo u16 gain_table[TX_GAIN_TABLE_LENGTH]; 66205491d2cSKalle Valo bool loopback_gain; 66305491d2cSKalle Valo s16 max_lpback_gain_hdB; 66405491d2cSKalle Valo s16 trsw_rx_gain_hdB; 66505491d2cSKalle Valo u8 power_vec[8]; 66605491d2cSKalle Valo 66705491d2cSKalle Valo u16 rc_cal; 66805491d2cSKalle Valo int nrssi_table_delta; 66905491d2cSKalle Valo int nrssi_slope_scale; 67005491d2cSKalle Valo int nrssi_slope_offset; 67105491d2cSKalle Valo int min_rssi; 67205491d2cSKalle Valo int max_rssi; 67305491d2cSKalle Valo 67405491d2cSKalle Valo s8 txpwridx; 67505491d2cSKalle Valo u8 min_txpower; 67605491d2cSKalle Valo 67705491d2cSKalle Valo u8 a_band_high_disable; 67805491d2cSKalle Valo 67905491d2cSKalle Valo u16 tx_vos; 68005491d2cSKalle Valo u16 global_tx_bb_dc_bias_loft; 68105491d2cSKalle Valo 68205491d2cSKalle Valo int rf_max; 68305491d2cSKalle Valo int bb_max; 68405491d2cSKalle Valo int rf_list_size; 68505491d2cSKalle Valo int bb_list_size; 68605491d2cSKalle Valo u16 *rf_attn_list; 68705491d2cSKalle Valo u16 *bb_attn_list; 68805491d2cSKalle Valo u16 padmix_mask; 68905491d2cSKalle Valo u16 padmix_reg; 69005491d2cSKalle Valo u16 *txmag_list; 69105491d2cSKalle Valo uint txmag_len; 69205491d2cSKalle Valo bool txmag_enable; 69305491d2cSKalle Valo 69405491d2cSKalle Valo s8 *a_tssi_to_dbm; 69505491d2cSKalle Valo s8 *m_tssi_to_dbm; 69605491d2cSKalle Valo s8 *l_tssi_to_dbm; 69705491d2cSKalle Valo s8 *h_tssi_to_dbm; 69805491d2cSKalle Valo u8 *hwtxpwr; 69905491d2cSKalle Valo 70005491d2cSKalle Valo u16 freqtrack_saved_regs[2]; 70105491d2cSKalle Valo int cur_interference_mode; 70205491d2cSKalle Valo bool hwpwrctrl_capable; 70305491d2cSKalle Valo bool temppwrctrl_capable; 70405491d2cSKalle Valo 70505491d2cSKalle Valo uint phycal_nslope; 70605491d2cSKalle Valo uint phycal_noffset; 70705491d2cSKalle Valo uint phycal_mlo; 70805491d2cSKalle Valo uint phycal_txpower; 70905491d2cSKalle Valo 71005491d2cSKalle Valo u8 phy_aa2g; 71105491d2cSKalle Valo 71205491d2cSKalle Valo bool nphy_tableloaded; 71305491d2cSKalle Valo s8 nphy_rssisel; 71405491d2cSKalle Valo u32 nphy_bb_mult_save; 71505491d2cSKalle Valo u16 nphy_txiqlocal_bestc[11]; 71605491d2cSKalle Valo bool nphy_txiqlocal_coeffsvalid; 71705491d2cSKalle Valo struct nphy_txpwrindex nphy_txpwrindex[PHY_CORE_NUM_2]; 71805491d2cSKalle Valo struct nphy_pwrctrl nphy_pwrctrl_info[PHY_CORE_NUM_2]; 71905491d2cSKalle Valo u16 cck2gpo; 72005491d2cSKalle Valo u32 ofdm2gpo; 72105491d2cSKalle Valo u32 ofdm5gpo; 72205491d2cSKalle Valo u32 ofdm5glpo; 72305491d2cSKalle Valo u32 ofdm5ghpo; 72405491d2cSKalle Valo u8 bw402gpo; 72505491d2cSKalle Valo u8 bw405gpo; 72605491d2cSKalle Valo u8 bw405glpo; 72705491d2cSKalle Valo u8 bw405ghpo; 72805491d2cSKalle Valo u8 cdd2gpo; 72905491d2cSKalle Valo u8 cdd5gpo; 73005491d2cSKalle Valo u8 cdd5glpo; 73105491d2cSKalle Valo u8 cdd5ghpo; 73205491d2cSKalle Valo u8 stbc2gpo; 73305491d2cSKalle Valo u8 stbc5gpo; 73405491d2cSKalle Valo u8 stbc5glpo; 73505491d2cSKalle Valo u8 stbc5ghpo; 73605491d2cSKalle Valo u8 bwdup2gpo; 73705491d2cSKalle Valo u8 bwdup5gpo; 73805491d2cSKalle Valo u8 bwdup5glpo; 73905491d2cSKalle Valo u8 bwdup5ghpo; 74005491d2cSKalle Valo u16 mcs2gpo[8]; 74105491d2cSKalle Valo u16 mcs5gpo[8]; 74205491d2cSKalle Valo u16 mcs5glpo[8]; 74305491d2cSKalle Valo u16 mcs5ghpo[8]; 74405491d2cSKalle Valo u32 nphy_rxcalparams; 74505491d2cSKalle Valo 74605491d2cSKalle Valo u8 phy_spuravoid; 74705491d2cSKalle Valo bool phy_isspuravoid; 74805491d2cSKalle Valo 74905491d2cSKalle Valo u8 phy_pabias; 75005491d2cSKalle Valo u8 nphy_papd_skip; 75105491d2cSKalle Valo u8 nphy_tssi_slope; 75205491d2cSKalle Valo 75305491d2cSKalle Valo s16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ]; 75405491d2cSKalle Valo u8 nphy_noise_index; 75505491d2cSKalle Valo 75605491d2cSKalle Valo bool nphy_gain_boost; 75705491d2cSKalle Valo bool nphy_elna_gain_config; 75805491d2cSKalle Valo u16 old_bphy_test; 75905491d2cSKalle Valo u16 old_bphy_testcontrol; 76005491d2cSKalle Valo 76105491d2cSKalle Valo bool phyhang_avoid; 76205491d2cSKalle Valo 76305491d2cSKalle Valo bool rssical_nphy; 76405491d2cSKalle Valo u8 nphy_perical; 76505491d2cSKalle Valo uint nphy_perical_last; 76605491d2cSKalle Valo u8 cal_type_override; 76705491d2cSKalle Valo u8 mphase_cal_phase_id; 76805491d2cSKalle Valo u8 mphase_txcal_cmdidx; 76905491d2cSKalle Valo u8 mphase_txcal_numcmds; 77005491d2cSKalle Valo u16 mphase_txcal_bestcoeffs[11]; 77105491d2cSKalle Valo u16 nphy_txiqlocal_chanspec; 77205491d2cSKalle Valo u16 nphy_iqcal_chanspec_2G; 77305491d2cSKalle Valo u16 nphy_iqcal_chanspec_5G; 77405491d2cSKalle Valo u16 nphy_rssical_chanspec_2G; 77505491d2cSKalle Valo u16 nphy_rssical_chanspec_5G; 77605491d2cSKalle Valo struct wlapi_timer *phycal_timer; 77705491d2cSKalle Valo bool use_int_tx_iqlo_cal_nphy; 77805491d2cSKalle Valo bool internal_tx_iqlo_cal_tapoff_intpa_nphy; 77905491d2cSKalle Valo s16 nphy_lastcal_temp; 78005491d2cSKalle Valo 78105491d2cSKalle Valo struct txiqcal_cache calibration_cache; 78205491d2cSKalle Valo struct rssical_cache rssical_cache; 78305491d2cSKalle Valo 78405491d2cSKalle Valo u8 nphy_txpwr_idx[2]; 78505491d2cSKalle Valo u8 nphy_papd_cal_type; 78605491d2cSKalle Valo uint nphy_papd_last_cal; 78705491d2cSKalle Valo u16 nphy_papd_tx_gain_at_last_cal[2]; 78805491d2cSKalle Valo u8 nphy_papd_cal_gain_index[2]; 78905491d2cSKalle Valo s16 nphy_papd_epsilon_offset[2]; 79005491d2cSKalle Valo bool nphy_papd_recal_enable; 79105491d2cSKalle Valo u32 nphy_papd_recal_counter; 79205491d2cSKalle Valo bool nphy_force_papd_cal; 79305491d2cSKalle Valo bool nphy_papdcomp; 79405491d2cSKalle Valo bool ipa2g_on; 79505491d2cSKalle Valo bool ipa5g_on; 79605491d2cSKalle Valo 79705491d2cSKalle Valo u16 classifier_state; 79805491d2cSKalle Valo u16 clip_state[2]; 79905491d2cSKalle Valo uint nphy_deaf_count; 80005491d2cSKalle Valo u8 rxiq_samps; 80105491d2cSKalle Valo u8 rxiq_antsel; 80205491d2cSKalle Valo 80305491d2cSKalle Valo u16 rfctrlIntc1_save; 80405491d2cSKalle Valo u16 rfctrlIntc2_save; 80505491d2cSKalle Valo bool first_cal_after_assoc; 80605491d2cSKalle Valo u16 tx_rx_cal_radio_saveregs[22]; 80705491d2cSKalle Valo u16 tx_rx_cal_phy_saveregs[15]; 80805491d2cSKalle Valo 80905491d2cSKalle Valo u8 nphy_cal_orig_pwr_idx[2]; 81005491d2cSKalle Valo u8 nphy_txcal_pwr_idx[2]; 81105491d2cSKalle Valo u8 nphy_rxcal_pwr_idx[2]; 81205491d2cSKalle Valo u16 nphy_cal_orig_tx_gain[2]; 81305491d2cSKalle Valo struct nphy_txgains nphy_cal_target_gain; 81405491d2cSKalle Valo u16 nphy_txcal_bbmult; 81505491d2cSKalle Valo u16 nphy_gmval; 81605491d2cSKalle Valo 81705491d2cSKalle Valo u16 nphy_saved_bbconf; 81805491d2cSKalle Valo 81905491d2cSKalle Valo bool nphy_gband_spurwar_en; 82005491d2cSKalle Valo bool nphy_gband_spurwar2_en; 82105491d2cSKalle Valo bool nphy_aband_spurwar_en; 82205491d2cSKalle Valo u16 nphy_rccal_value; 82305491d2cSKalle Valo u16 nphy_crsminpwr[3]; 82405491d2cSKalle Valo struct nphy_noisevar_buf nphy_saved_noisevars; 82505491d2cSKalle Valo bool nphy_anarxlpf_adjusted; 82605491d2cSKalle Valo bool nphy_crsminpwr_adjusted; 82705491d2cSKalle Valo bool nphy_noisevars_adjusted; 82805491d2cSKalle Valo 82905491d2cSKalle Valo bool nphy_rxcal_active; 83005491d2cSKalle Valo u16 radar_percal_mask; 83105491d2cSKalle Valo bool dfs_lp_buffer_nphy; 83205491d2cSKalle Valo 83305491d2cSKalle Valo u16 nphy_fineclockgatecontrol; 83405491d2cSKalle Valo 83505491d2cSKalle Valo s8 rx2tx_biasentry; 83605491d2cSKalle Valo 83705491d2cSKalle Valo u16 crsminpwr0; 83805491d2cSKalle Valo u16 crsminpwrl0; 83905491d2cSKalle Valo u16 crsminpwru0; 84005491d2cSKalle Valo s16 noise_crsminpwr_index; 84105491d2cSKalle Valo u16 init_gain_core1; 84205491d2cSKalle Valo u16 init_gain_core2; 84305491d2cSKalle Valo u16 init_gainb_core1; 84405491d2cSKalle Valo u16 init_gainb_core2; 84505491d2cSKalle Valo u8 aci_noise_curr_channel; 84605491d2cSKalle Valo u16 init_gain_rfseq[4]; 84705491d2cSKalle Valo 84805491d2cSKalle Valo bool radio_is_on; 84905491d2cSKalle Valo 85005491d2cSKalle Valo bool nphy_sample_play_lpf_bw_ctl_ovr; 85105491d2cSKalle Valo 85205491d2cSKalle Valo u16 tbl_data_hi; 85305491d2cSKalle Valo u16 tbl_data_lo; 85405491d2cSKalle Valo u16 tbl_addr; 85505491d2cSKalle Valo 85605491d2cSKalle Valo uint tbl_save_id; 85705491d2cSKalle Valo uint tbl_save_offset; 85805491d2cSKalle Valo 85905491d2cSKalle Valo u8 txpwrctrl; 86005491d2cSKalle Valo s8 txpwrindex[PHY_CORE_MAX]; 86105491d2cSKalle Valo 86205491d2cSKalle Valo u8 phycal_tempdelta; 86305491d2cSKalle Valo u32 mcs20_po; 86405491d2cSKalle Valo u32 mcs40_po; 86505491d2cSKalle Valo struct wiphy *wiphy; 86605491d2cSKalle Valo }; 86705491d2cSKalle Valo 86805491d2cSKalle Valo struct cs32 { 86905491d2cSKalle Valo s32 q; 87005491d2cSKalle Valo s32 i; 87105491d2cSKalle Valo }; 87205491d2cSKalle Valo 87305491d2cSKalle Valo struct radio_regs { 87405491d2cSKalle Valo u16 address; 87505491d2cSKalle Valo u32 init_a; 87605491d2cSKalle Valo u32 init_g; 87705491d2cSKalle Valo u8 do_init_a; 87805491d2cSKalle Valo u8 do_init_g; 87905491d2cSKalle Valo }; 88005491d2cSKalle Valo 88105491d2cSKalle Valo struct radio_20xx_regs { 88205491d2cSKalle Valo u16 address; 88305491d2cSKalle Valo u8 init; 88405491d2cSKalle Valo u8 do_init; 88505491d2cSKalle Valo }; 88605491d2cSKalle Valo 88705491d2cSKalle Valo struct lcnphy_radio_regs { 88805491d2cSKalle Valo u16 address; 88905491d2cSKalle Valo u8 init_a; 89005491d2cSKalle Valo u8 init_g; 89105491d2cSKalle Valo u8 do_init_a; 89205491d2cSKalle Valo u8 do_init_g; 89305491d2cSKalle Valo }; 89405491d2cSKalle Valo 89505491d2cSKalle Valo u16 read_phy_reg(struct brcms_phy *pi, u16 addr); 89605491d2cSKalle Valo void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val); 89705491d2cSKalle Valo void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val); 89805491d2cSKalle Valo void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val); 89905491d2cSKalle Valo void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val); 90005491d2cSKalle Valo 90105491d2cSKalle Valo u16 read_radio_reg(struct brcms_phy *pi, u16 addr); 90205491d2cSKalle Valo void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val); 90305491d2cSKalle Valo void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val); 90405491d2cSKalle Valo void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val); 90505491d2cSKalle Valo void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask); 90605491d2cSKalle Valo 90705491d2cSKalle Valo void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val); 90805491d2cSKalle Valo 90905491d2cSKalle Valo void wlc_phyreg_enter(struct brcms_phy_pub *pih); 91005491d2cSKalle Valo void wlc_phyreg_exit(struct brcms_phy_pub *pih); 91105491d2cSKalle Valo void wlc_radioreg_enter(struct brcms_phy_pub *pih); 91205491d2cSKalle Valo void wlc_radioreg_exit(struct brcms_phy_pub *pih); 91305491d2cSKalle Valo 91405491d2cSKalle Valo void wlc_phy_read_table(struct brcms_phy *pi, 91505491d2cSKalle Valo const struct phytbl_info *ptbl_info, 91605491d2cSKalle Valo u16 tblAddr, u16 tblDataHi, u16 tblDatalo); 91705491d2cSKalle Valo void wlc_phy_write_table(struct brcms_phy *pi, 91805491d2cSKalle Valo const struct phytbl_info *ptbl_info, 91905491d2cSKalle Valo u16 tblAddr, u16 tblDataHi, u16 tblDatalo); 92005491d2cSKalle Valo void wlc_phy_table_addr(struct brcms_phy *pi, uint tbl_id, uint tbl_offset, 92105491d2cSKalle Valo u16 tblAddr, u16 tblDataHi, u16 tblDataLo); 92205491d2cSKalle Valo void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val); 92305491d2cSKalle Valo 92405491d2cSKalle Valo void write_phy_channel_reg(struct brcms_phy *pi, uint val); 92505491d2cSKalle Valo void wlc_phy_txpower_update_shm(struct brcms_phy *pi); 92605491d2cSKalle Valo 92705491d2cSKalle Valo u8 wlc_phy_nbits(s32 value); 92805491d2cSKalle Valo void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core); 92905491d2cSKalle Valo 93005491d2cSKalle Valo uint wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi, 93105491d2cSKalle Valo struct radio_20xx_regs *radioregs); 93205491d2cSKalle Valo uint wlc_phy_init_radio_regs(struct brcms_phy *pi, 93305491d2cSKalle Valo const struct radio_regs *radioregs, 93405491d2cSKalle Valo u16 core_offset); 93505491d2cSKalle Valo 93605491d2cSKalle Valo void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi); 93705491d2cSKalle Valo 93805491d2cSKalle Valo void wlc_phy_do_dummy_tx(struct brcms_phy *pi, bool ofdm, bool pa_on); 93905491d2cSKalle Valo void wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real, s32 *eps_imag); 94005491d2cSKalle Valo 94105491d2cSKalle Valo void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi); 94205491d2cSKalle Valo void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi); 94305491d2cSKalle Valo 94405491d2cSKalle Valo bool wlc_phy_attach_nphy(struct brcms_phy *pi); 94505491d2cSKalle Valo bool wlc_phy_attach_lcnphy(struct brcms_phy *pi); 94605491d2cSKalle Valo 94705491d2cSKalle Valo void wlc_phy_detach_lcnphy(struct brcms_phy *pi); 94805491d2cSKalle Valo 94905491d2cSKalle Valo void wlc_phy_init_nphy(struct brcms_phy *pi); 95005491d2cSKalle Valo void wlc_phy_init_lcnphy(struct brcms_phy *pi); 95105491d2cSKalle Valo 95205491d2cSKalle Valo void wlc_phy_cal_init_nphy(struct brcms_phy *pi); 95305491d2cSKalle Valo void wlc_phy_cal_init_lcnphy(struct brcms_phy *pi); 95405491d2cSKalle Valo 95505491d2cSKalle Valo void wlc_phy_chanspec_set_nphy(struct brcms_phy *pi, u16 chanspec); 95605491d2cSKalle Valo void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi, u16 chanspec); 95705491d2cSKalle Valo void wlc_phy_chanspec_set_fixup_lcnphy(struct brcms_phy *pi, u16 chanspec); 95805491d2cSKalle Valo int wlc_phy_channel2freq(uint channel); 95905491d2cSKalle Valo int wlc_phy_chanspec_freq2bandrange_lpssn(uint); 96005491d2cSKalle Valo int wlc_phy_chanspec_bandrange_get(struct brcms_phy *, u16 chanspec); 96105491d2cSKalle Valo 96205491d2cSKalle Valo void wlc_lcnphy_set_tx_pwr_ctrl(struct brcms_phy *pi, u16 mode); 96305491d2cSKalle Valo s8 wlc_lcnphy_get_current_tx_pwr_idx(struct brcms_phy *pi); 96405491d2cSKalle Valo 96505491d2cSKalle Valo void wlc_phy_txpower_recalc_target_nphy(struct brcms_phy *pi); 96605491d2cSKalle Valo void wlc_lcnphy_txpower_recalc_target(struct brcms_phy *pi); 96705491d2cSKalle Valo void wlc_phy_txpower_recalc_target_lcnphy(struct brcms_phy *pi); 96805491d2cSKalle Valo 96905491d2cSKalle Valo void wlc_lcnphy_set_tx_pwr_by_index(struct brcms_phy *pi, int index); 97005491d2cSKalle Valo void wlc_lcnphy_tx_pu(struct brcms_phy *pi, bool bEnable); 97105491d2cSKalle Valo void wlc_lcnphy_stop_tx_tone(struct brcms_phy *pi); 97205491d2cSKalle Valo void wlc_lcnphy_start_tx_tone(struct brcms_phy *pi, s32 f_kHz, u16 max_val, 97305491d2cSKalle Valo bool iqcalmode); 97405491d2cSKalle Valo 97505491d2cSKalle Valo void wlc_phy_txpower_sromlimit_get_nphy(struct brcms_phy *pi, uint chan, 97605491d2cSKalle Valo u8 *max_pwr, u8 rate_id); 97705491d2cSKalle Valo void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start, 97805491d2cSKalle Valo u8 rate_mcs_end, u8 rate_ofdm_start); 97905491d2cSKalle Valo void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power, u8 rate_ofdm_start, 98005491d2cSKalle Valo u8 rate_ofdm_end, u8 rate_mcs_start); 98105491d2cSKalle Valo 98205491d2cSKalle Valo u16 wlc_lcnphy_tempsense(struct brcms_phy *pi, bool mode); 98305491d2cSKalle Valo s16 wlc_lcnphy_tempsense_new(struct brcms_phy *pi, bool mode); 98405491d2cSKalle Valo s8 wlc_lcnphy_tempsense_degree(struct brcms_phy *pi, bool mode); 98505491d2cSKalle Valo s8 wlc_lcnphy_vbatsense(struct brcms_phy *pi, bool mode); 98605491d2cSKalle Valo void wlc_phy_carrier_suppress_lcnphy(struct brcms_phy *pi); 98705491d2cSKalle Valo void wlc_lcnphy_crsuprs(struct brcms_phy *pi, int channel); 98805491d2cSKalle Valo void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode); 98905491d2cSKalle Valo void wlc_2064_vco_cal(struct brcms_phy *pi); 99005491d2cSKalle Valo 99105491d2cSKalle Valo void wlc_phy_txpower_recalc_target(struct brcms_phy *pi); 99205491d2cSKalle Valo 99305491d2cSKalle Valo #define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18 99405491d2cSKalle Valo #define LCNPHY_TX_POWER_TABLE_SIZE 128 99505491d2cSKalle Valo #define LCNPHY_MAX_TX_POWER_INDEX (LCNPHY_TX_POWER_TABLE_SIZE - 1) 99605491d2cSKalle Valo #define LCNPHY_TBL_ID_TXPWRCTL 0x07 99705491d2cSKalle Valo #define LCNPHY_TX_PWR_CTRL_OFF 0 99805491d2cSKalle Valo #define LCNPHY_TX_PWR_CTRL_SW (0x1 << 15) 99905491d2cSKalle Valo #define LCNPHY_TX_PWR_CTRL_HW ((0x1 << 15) | \ 100005491d2cSKalle Valo (0x1 << 14) | \ 100105491d2cSKalle Valo (0x1 << 13)) 100205491d2cSKalle Valo 100305491d2cSKalle Valo #define LCNPHY_TX_PWR_CTRL_TEMPBASED 0xE001 100405491d2cSKalle Valo 100505491d2cSKalle Valo void wlc_lcnphy_write_table(struct brcms_phy *pi, 100605491d2cSKalle Valo const struct phytbl_info *pti); 100705491d2cSKalle Valo void wlc_lcnphy_read_table(struct brcms_phy *pi, struct phytbl_info *pti); 100805491d2cSKalle Valo void wlc_lcnphy_set_tx_iqcc(struct brcms_phy *pi, u16 a, u16 b); 100905491d2cSKalle Valo void wlc_lcnphy_set_tx_locc(struct brcms_phy *pi, u16 didq); 101005491d2cSKalle Valo void wlc_lcnphy_get_tx_iqcc(struct brcms_phy *pi, u16 *a, u16 *b); 101105491d2cSKalle Valo u16 wlc_lcnphy_get_tx_locc(struct brcms_phy *pi); 101205491d2cSKalle Valo void wlc_lcnphy_get_radio_loft(struct brcms_phy *pi, u8 *ei0, u8 *eq0, u8 *fi0, 101305491d2cSKalle Valo u8 *fq0); 101405491d2cSKalle Valo void wlc_lcnphy_calib_modes(struct brcms_phy *pi, uint mode); 101505491d2cSKalle Valo void wlc_lcnphy_deaf_mode(struct brcms_phy *pi, bool mode); 101605491d2cSKalle Valo bool wlc_phy_tpc_isenabled_lcnphy(struct brcms_phy *pi); 101705491d2cSKalle Valo void wlc_lcnphy_tx_pwr_update_npt(struct brcms_phy *pi); 101805491d2cSKalle Valo s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1); 101905491d2cSKalle Valo void wlc_lcnphy_get_tssi(struct brcms_phy *pi, s8 *ofdm_pwr, s8 *cck_pwr); 102005491d2cSKalle Valo void wlc_lcnphy_tx_power_adjustment(struct brcms_phy_pub *ppi); 102105491d2cSKalle Valo 102205491d2cSKalle Valo s32 wlc_lcnphy_rx_signal_power(struct brcms_phy *pi, s32 gain_index); 102305491d2cSKalle Valo 102405491d2cSKalle Valo #define NPHY_MAX_HPVGA1_INDEX 10 102505491d2cSKalle Valo #define NPHY_DEF_HPVGA1_INDEXLIMIT 7 102605491d2cSKalle Valo 102705491d2cSKalle Valo struct phy_iq_est { 102805491d2cSKalle Valo s32 iq_prod; 102905491d2cSKalle Valo u32 i_pwr; 103005491d2cSKalle Valo u32 q_pwr; 103105491d2cSKalle Valo }; 103205491d2cSKalle Valo 103305491d2cSKalle Valo void wlc_phy_stay_in_carriersearch_nphy(struct brcms_phy *pi, bool enable); 103405491d2cSKalle Valo void wlc_nphy_deaf_mode(struct brcms_phy *pi, bool mode); 103505491d2cSKalle Valo 103605491d2cSKalle Valo #define wlc_phy_write_table_nphy(pi, pti) \ 103705491d2cSKalle Valo wlc_phy_write_table(pi, pti, 0x72, 0x74, 0x73) 103805491d2cSKalle Valo 103905491d2cSKalle Valo #define wlc_phy_read_table_nphy(pi, pti) \ 104005491d2cSKalle Valo wlc_phy_read_table(pi, pti, 0x72, 0x74, 0x73) 104105491d2cSKalle Valo 104205491d2cSKalle Valo #define wlc_nphy_table_addr(pi, id, off) \ 104305491d2cSKalle Valo wlc_phy_table_addr((pi), (id), (off), 0x72, 0x74, 0x73) 104405491d2cSKalle Valo 104505491d2cSKalle Valo #define wlc_nphy_table_data_write(pi, w, v) \ 104605491d2cSKalle Valo wlc_phy_table_data_write((pi), (w), (v)) 104705491d2cSKalle Valo 104805491d2cSKalle Valo void wlc_phy_table_read_nphy(struct brcms_phy *pi, u32, u32 l, u32 o, u32 w, 104905491d2cSKalle Valo void *d); 105005491d2cSKalle Valo void wlc_phy_table_write_nphy(struct brcms_phy *pi, u32, u32, u32, u32, 105105491d2cSKalle Valo const void *); 105205491d2cSKalle Valo 105305491d2cSKalle Valo #define PHY_IPA(pi) \ 105405491d2cSKalle Valo ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \ 105505491d2cSKalle Valo (pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec))) 105605491d2cSKalle Valo 105705491d2cSKalle Valo #define BRCMS_PHY_WAR_PR51571(pi) \ 105805491d2cSKalle Valo if (NREV_LT((pi)->pubpi.phy_rev, 3)) \ 105905491d2cSKalle Valo (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) 106005491d2cSKalle Valo 106105491d2cSKalle Valo void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi, u8 caltype); 106205491d2cSKalle Valo void wlc_phy_aci_reset_nphy(struct brcms_phy *pi); 106305491d2cSKalle Valo void wlc_phy_pa_override_nphy(struct brcms_phy *pi, bool en); 106405491d2cSKalle Valo 106505491d2cSKalle Valo u8 wlc_phy_get_chan_freq_range_nphy(struct brcms_phy *pi, uint chan); 106605491d2cSKalle Valo void wlc_phy_switch_radio_nphy(struct brcms_phy *pi, bool on); 106705491d2cSKalle Valo 106805491d2cSKalle Valo void wlc_phy_stf_chain_upd_nphy(struct brcms_phy *pi); 106905491d2cSKalle Valo 107005491d2cSKalle Valo void wlc_phy_force_rfseq_nphy(struct brcms_phy *pi, u8 cmd); 107105491d2cSKalle Valo s16 wlc_phy_tempsense_nphy(struct brcms_phy *pi); 107205491d2cSKalle Valo 107305491d2cSKalle Valo u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val); 107405491d2cSKalle Valo 107505491d2cSKalle Valo void wlc_phy_rx_iq_est_nphy(struct brcms_phy *pi, struct phy_iq_est *est, 107605491d2cSKalle Valo u16 num_samps, u8 wait_time, u8 wait_for_crs); 107705491d2cSKalle Valo 107805491d2cSKalle Valo void wlc_phy_rx_iq_coeffs_nphy(struct brcms_phy *pi, u8 write, 107905491d2cSKalle Valo struct nphy_iq_comp *comp); 108005491d2cSKalle Valo void wlc_phy_aci_and_noise_reduction_nphy(struct brcms_phy *pi); 108105491d2cSKalle Valo 108205491d2cSKalle Valo void wlc_phy_rxcore_setstate_nphy(struct brcms_phy_pub *pih, u8 rxcore_bitmask); 108305491d2cSKalle Valo u8 wlc_phy_rxcore_getstate_nphy(struct brcms_phy_pub *pih); 108405491d2cSKalle Valo 108505491d2cSKalle Valo void wlc_phy_txpwrctrl_enable_nphy(struct brcms_phy *pi, u8 ctrl_type); 108605491d2cSKalle Valo void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi); 108705491d2cSKalle Valo void wlc_phy_txpwr_apply_nphy(struct brcms_phy *pi); 108805491d2cSKalle Valo void wlc_phy_txpwr_papd_cal_nphy(struct brcms_phy *pi); 108905491d2cSKalle Valo u16 wlc_phy_txpwr_idx_get_nphy(struct brcms_phy *pi); 109005491d2cSKalle Valo 109105491d2cSKalle Valo struct nphy_txgains wlc_phy_get_tx_gain_nphy(struct brcms_phy *pi); 109205491d2cSKalle Valo int wlc_phy_cal_txiqlo_nphy(struct brcms_phy *pi, 109305491d2cSKalle Valo struct nphy_txgains target_gain, bool full, bool m); 109405491d2cSKalle Valo int wlc_phy_cal_rxiq_nphy(struct brcms_phy *pi, struct nphy_txgains target_gain, 109505491d2cSKalle Valo u8 type, bool d); 109605491d2cSKalle Valo void wlc_phy_txpwr_index_nphy(struct brcms_phy *pi, u8 core_mask, 109705491d2cSKalle Valo s8 txpwrindex, bool res); 109805491d2cSKalle Valo void wlc_phy_rssisel_nphy(struct brcms_phy *pi, u8 core, u8 rssi_type); 109905491d2cSKalle Valo int wlc_phy_poll_rssi_nphy(struct brcms_phy *pi, u8 rssi_type, 110005491d2cSKalle Valo s32 *rssi_buf, u8 nsamps); 110105491d2cSKalle Valo void wlc_phy_rssi_cal_nphy(struct brcms_phy *pi); 110205491d2cSKalle Valo int wlc_phy_aci_scan_nphy(struct brcms_phy *pi); 110305491d2cSKalle Valo void wlc_phy_cal_txgainctrl_nphy(struct brcms_phy *pi, s32 dBm_targetpower, 110405491d2cSKalle Valo bool debug); 110505491d2cSKalle Valo int wlc_phy_tx_tone_nphy(struct brcms_phy *pi, u32 f_kHz, u16 max_val, u8 mode, 110605491d2cSKalle Valo u8, bool); 110705491d2cSKalle Valo void wlc_phy_stopplayback_nphy(struct brcms_phy *pi); 110805491d2cSKalle Valo void wlc_phy_est_tonepwr_nphy(struct brcms_phy *pi, s32 *qdBm_pwrbuf, 110905491d2cSKalle Valo u8 num_samps); 111005491d2cSKalle Valo void wlc_phy_radio205x_vcocal_nphy(struct brcms_phy *pi); 111105491d2cSKalle Valo 111205491d2cSKalle Valo int wlc_phy_rssi_compute_nphy(struct brcms_phy *pi, struct d11rxhdr *rxh); 111305491d2cSKalle Valo 111405491d2cSKalle Valo #define NPHY_TESTPATTERN_BPHY_EVM 0 111505491d2cSKalle Valo #define NPHY_TESTPATTERN_BPHY_RFCS 1 111605491d2cSKalle Valo 111705491d2cSKalle Valo void wlc_phy_nphy_tkip_rifs_war(struct brcms_phy *pi, u8 rifs); 111805491d2cSKalle Valo 111905491d2cSKalle Valo void wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi, s8 *cckoffset, 112005491d2cSKalle Valo s8 *ofdmoffset); 112105491d2cSKalle Valo s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi, s8 rssi, u16 chanspec); 112205491d2cSKalle Valo 112305491d2cSKalle Valo bool wlc_phy_n_txpower_ipa_ison(struct brcms_phy *pih); 112405491d2cSKalle Valo #endif /* _BRCM_PHY_INT_H_ */ 1125