105491d2cSKalle Valo /*
205491d2cSKalle Valo * Copyright (c) 2010 Broadcom Corporation
305491d2cSKalle Valo *
405491d2cSKalle Valo * Permission to use, copy, modify, and/or distribute this software for any
505491d2cSKalle Valo * purpose with or without fee is hereby granted, provided that the above
605491d2cSKalle Valo * copyright notice and this permission notice appear in all copies.
705491d2cSKalle Valo *
805491d2cSKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
905491d2cSKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
1005491d2cSKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
1105491d2cSKalle Valo * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
1205491d2cSKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
1305491d2cSKalle Valo * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
1405491d2cSKalle Valo * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
1505491d2cSKalle Valo */
1605491d2cSKalle Valo
1705491d2cSKalle Valo #ifndef _BRCM_DMA_H_
1805491d2cSKalle Valo #define _BRCM_DMA_H_
1905491d2cSKalle Valo
2005491d2cSKalle Valo #include <linux/delay.h>
2105491d2cSKalle Valo #include <linux/skbuff.h>
2205491d2cSKalle Valo #include "types.h" /* forward structure declarations */
2305491d2cSKalle Valo
2405491d2cSKalle Valo /* map/unmap direction */
2505491d2cSKalle Valo #define DMA_TX 1 /* TX direction for DMA */
2605491d2cSKalle Valo #define DMA_RX 2 /* RX direction for DMA */
2705491d2cSKalle Valo
2805491d2cSKalle Valo /* DMA structure:
2905491d2cSKalle Valo * support two DMA engines: 32 bits address or 64 bit addressing
3005491d2cSKalle Valo * basic DMA register set is per channel(transmit or receive)
3105491d2cSKalle Valo * a pair of channels is defined for convenience
3205491d2cSKalle Valo */
3305491d2cSKalle Valo
3405491d2cSKalle Valo /* 32 bits addressing */
3505491d2cSKalle Valo
3605491d2cSKalle Valo struct dma32diag { /* diag access */
3705491d2cSKalle Valo u32 fifoaddr; /* diag address */
3805491d2cSKalle Valo u32 fifodatalow; /* low 32bits of data */
3905491d2cSKalle Valo u32 fifodatahigh; /* high 32bits of data */
4005491d2cSKalle Valo u32 pad; /* reserved */
4105491d2cSKalle Valo };
4205491d2cSKalle Valo
4305491d2cSKalle Valo /* 64 bits addressing */
4405491d2cSKalle Valo
4505491d2cSKalle Valo /* dma registers per channel(xmt or rcv) */
4605491d2cSKalle Valo struct dma64regs {
4705491d2cSKalle Valo u32 control; /* enable, et al */
4805491d2cSKalle Valo u32 ptr; /* last descriptor posted to chip */
4905491d2cSKalle Valo u32 addrlow; /* desc ring base address low 32-bits (8K aligned) */
5005491d2cSKalle Valo u32 addrhigh; /* desc ring base address bits 63:32 (8K aligned) */
5105491d2cSKalle Valo u32 status0; /* current descriptor, xmt state */
5205491d2cSKalle Valo u32 status1; /* active descriptor, xmt error */
5305491d2cSKalle Valo };
5405491d2cSKalle Valo
5505491d2cSKalle Valo /* range param for dma_getnexttxp() and dma_txreclaim */
5605491d2cSKalle Valo enum txd_range {
5705491d2cSKalle Valo DMA_RANGE_ALL = 1,
5805491d2cSKalle Valo DMA_RANGE_TRANSMITTED,
5905491d2cSKalle Valo DMA_RANGE_TRANSFERED
6005491d2cSKalle Valo };
6105491d2cSKalle Valo
6205491d2cSKalle Valo /*
6305491d2cSKalle Valo * Exported data structure (read-only)
6405491d2cSKalle Valo */
6505491d2cSKalle Valo /* export structure */
6605491d2cSKalle Valo struct dma_pub {
6705491d2cSKalle Valo uint txavail; /* # free tx descriptors */
6805491d2cSKalle Valo uint dmactrlflags; /* dma control flags */
6905491d2cSKalle Valo
7005491d2cSKalle Valo /* rx error counters */
7105491d2cSKalle Valo uint rxgiants; /* rx giant frames */
7205491d2cSKalle Valo uint rxnobuf; /* rx out of dma descriptors */
7305491d2cSKalle Valo /* tx error counters */
7405491d2cSKalle Valo uint txnobuf; /* tx out of dma descriptors */
7505491d2cSKalle Valo };
7605491d2cSKalle Valo
7705491d2cSKalle Valo extern struct dma_pub *dma_attach(char *name, struct brcms_c_info *wlc,
7805491d2cSKalle Valo uint txregbase, uint rxregbase,
7905491d2cSKalle Valo uint ntxd, uint nrxd,
8005491d2cSKalle Valo uint rxbufsize, int rxextheadroom,
8105491d2cSKalle Valo uint nrxpost, uint rxoffset);
8205491d2cSKalle Valo
8305491d2cSKalle Valo void dma_rxinit(struct dma_pub *pub);
8405491d2cSKalle Valo int dma_rx(struct dma_pub *pub, struct sk_buff_head *skb_list);
8505491d2cSKalle Valo bool dma_rxfill(struct dma_pub *pub);
8605491d2cSKalle Valo bool dma_rxreset(struct dma_pub *pub);
8705491d2cSKalle Valo bool dma_txreset(struct dma_pub *pub);
8805491d2cSKalle Valo void dma_txinit(struct dma_pub *pub);
8905491d2cSKalle Valo int dma_txfast(struct brcms_c_info *wlc, struct dma_pub *pub,
9005491d2cSKalle Valo struct sk_buff *p0);
9105491d2cSKalle Valo void dma_txflush(struct dma_pub *pub);
9205491d2cSKalle Valo int dma_txpending(struct dma_pub *pub);
9305491d2cSKalle Valo void dma_kick_tx(struct dma_pub *pub);
9405491d2cSKalle Valo void dma_txsuspend(struct dma_pub *pub);
9505491d2cSKalle Valo bool dma_txsuspended(struct dma_pub *pub);
9605491d2cSKalle Valo void dma_txresume(struct dma_pub *pub);
9705491d2cSKalle Valo void dma_txreclaim(struct dma_pub *pub, enum txd_range range);
9805491d2cSKalle Valo void dma_rxreclaim(struct dma_pub *pub);
9905491d2cSKalle Valo void dma_detach(struct dma_pub *pub);
10005491d2cSKalle Valo unsigned long dma_getvar(struct dma_pub *pub, const char *name);
10105491d2cSKalle Valo struct sk_buff *dma_getnexttxp(struct dma_pub *pub, enum txd_range range);
10205491d2cSKalle Valo void dma_counterreset(struct dma_pub *pub);
10305491d2cSKalle Valo
10405491d2cSKalle Valo void dma_walk_packets(struct dma_pub *dmah, void (*callback_fnc)
10505491d2cSKalle Valo (void *pkt, void *arg_a), void *arg_a);
10605491d2cSKalle Valo
10705491d2cSKalle Valo /*
10805491d2cSKalle Valo * DMA(Bug) on bcm47xx chips seems to declare that the packet is ready, but
10905491d2cSKalle Valo * the packet length is not updated yet (by DMA) on the expected time.
11005491d2cSKalle Valo * Workaround is to hold processor till DMA updates the length, and stay off
11105491d2cSKalle Valo * the bus to allow DMA update the length in buffer
11205491d2cSKalle Valo */
dma_spin_for_len(uint len,struct sk_buff * head)11305491d2cSKalle Valo static inline void dma_spin_for_len(uint len, struct sk_buff *head)
11405491d2cSKalle Valo {
11505491d2cSKalle Valo #if defined(CONFIG_BCM47XX)
11605491d2cSKalle Valo if (!len) {
11705491d2cSKalle Valo while (!(len = *(u16 *) KSEG1ADDR(head->data)))
11805491d2cSKalle Valo udelay(1);
11905491d2cSKalle Valo
12005491d2cSKalle Valo *(u16 *) (head->data) = cpu_to_le16((u16) len);
12105491d2cSKalle Valo }
12205491d2cSKalle Valo #endif /* defined(CONFIG_BCM47XX) */
12305491d2cSKalle Valo }
12405491d2cSKalle Valo
12505491d2cSKalle Valo #endif /* _BRCM_DMA_H_ */
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