1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef BRCMFMAC_SDIO_H 18 #define BRCMFMAC_SDIO_H 19 20 #include <linux/skbuff.h> 21 #include <linux/firmware.h> 22 #include "firmware.h" 23 24 #define SDIOD_FBR_SIZE 0x100 25 26 /* io_en */ 27 #define SDIO_FUNC_ENABLE_1 0x02 28 #define SDIO_FUNC_ENABLE_2 0x04 29 30 /* io_rdys */ 31 #define SDIO_FUNC_READY_1 0x02 32 #define SDIO_FUNC_READY_2 0x04 33 34 /* intr_status */ 35 #define INTR_STATUS_FUNC1 0x2 36 #define INTR_STATUS_FUNC2 0x4 37 38 /* mask of register map */ 39 #define REG_F0_REG_MASK 0x7FF 40 #define REG_F1_MISC_MASK 0x1FFFF 41 42 /* function 0 vendor specific CCCR registers */ 43 44 #define SDIO_CCCR_BRCM_CARDCAP 0xf0 45 #define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT BIT(1) 46 #define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT BIT(2) 47 #define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC BIT(3) 48 49 /* Interrupt enable bits for each function */ 50 #define SDIO_CCCR_IEN_FUNC0 BIT(0) 51 #define SDIO_CCCR_IEN_FUNC1 BIT(1) 52 #define SDIO_CCCR_IEN_FUNC2 BIT(2) 53 54 #define SDIO_CCCR_BRCM_CARDCTRL 0xf1 55 #define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET BIT(1) 56 57 #define SDIO_CCCR_BRCM_SEPINT 0xf2 58 #define SDIO_CCCR_BRCM_SEPINT_MASK BIT(0) 59 #define SDIO_CCCR_BRCM_SEPINT_OE BIT(1) 60 #define SDIO_CCCR_BRCM_SEPINT_ACT_HI BIT(2) 61 62 /* function 1 miscellaneous registers */ 63 64 /* sprom command and status */ 65 #define SBSDIO_SPROM_CS 0x10000 66 /* sprom info register */ 67 #define SBSDIO_SPROM_INFO 0x10001 68 /* sprom indirect access data byte 0 */ 69 #define SBSDIO_SPROM_DATA_LOW 0x10002 70 /* sprom indirect access data byte 1 */ 71 #define SBSDIO_SPROM_DATA_HIGH 0x10003 72 /* sprom indirect access addr byte 0 */ 73 #define SBSDIO_SPROM_ADDR_LOW 0x10004 74 /* gpio select */ 75 #define SBSDIO_GPIO_SELECT 0x10005 76 /* gpio output */ 77 #define SBSDIO_GPIO_OUT 0x10006 78 /* gpio enable */ 79 #define SBSDIO_GPIO_EN 0x10007 80 /* rev < 7, watermark for sdio device TX path */ 81 #define SBSDIO_WATERMARK 0x10008 82 /* control busy signal generation */ 83 #define SBSDIO_DEVICE_CTL 0x10009 84 85 /* SB Address Window Low (b15) */ 86 #define SBSDIO_FUNC1_SBADDRLOW 0x1000A 87 /* SB Address Window Mid (b23:b16) */ 88 #define SBSDIO_FUNC1_SBADDRMID 0x1000B 89 /* SB Address Window High (b31:b24) */ 90 #define SBSDIO_FUNC1_SBADDRHIGH 0x1000C 91 /* Frame Control (frame term/abort) */ 92 #define SBSDIO_FUNC1_FRAMECTRL 0x1000D 93 /* ChipClockCSR (ALP/HT ctl/status) */ 94 #define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E 95 /* SdioPullUp (on cmd, d0-d2) */ 96 #define SBSDIO_FUNC1_SDIOPULLUP 0x1000F 97 /* Write Frame Byte Count Low */ 98 #define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 99 /* Write Frame Byte Count High */ 100 #define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A 101 /* Read Frame Byte Count Low */ 102 #define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B 103 /* Read Frame Byte Count High */ 104 #define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C 105 /* MesBusyCtl (rev 11) */ 106 #define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D 107 /* Watermark for sdio device RX path */ 108 #define SBSDIO_MESBUSY_RXFIFO_WM_MASK 0x7F 109 #define SBSDIO_MESBUSY_RXFIFO_WM_SHIFT 0 110 /* Enable busy capability for MES access */ 111 #define SBSDIO_MESBUSYCTRL_ENAB 0x80 112 #define SBSDIO_MESBUSYCTRL_ENAB_SHIFT 7 113 114 /* Sdio Core Rev 12 */ 115 #define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E 116 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1 117 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0 118 #define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2 119 #define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1 120 #define SBSDIO_FUNC1_SLEEPCSR 0x1001F 121 #define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1 122 #define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0 123 #define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1 124 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2 125 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1 126 127 #define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */ 128 #define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */ 129 130 /* function 1 OCP space */ 131 132 /* sb offset addr is <= 15 bits, 32k */ 133 #define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF 134 #define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000 135 /* with b15, maps to 32-bit SB access */ 136 #define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 137 138 /* Address bits from SBADDR regs */ 139 #define SBSDIO_SBWINDOW_MASK 0xffff8000 140 141 #define SDIOH_READ 0 /* Read request */ 142 #define SDIOH_WRITE 1 /* Write request */ 143 144 #define SDIOH_DATA_FIX 0 /* Fixed addressing */ 145 #define SDIOH_DATA_INC 1 /* Incremental addressing */ 146 147 /* internal return code */ 148 #define SUCCESS 0 149 #define ERROR 1 150 151 /* Packet alignment for most efficient SDIO (can change based on platform) */ 152 #define BRCMF_SDALIGN (1 << 6) 153 154 /* watchdog polling interval */ 155 #define BRCMF_WD_POLL msecs_to_jiffies(10) 156 157 /** 158 * enum brcmf_sdiod_state - the state of the bus. 159 * 160 * @BRCMF_SDIOD_DOWN: Device can be accessed, no DPC. 161 * @BRCMF_SDIOD_DATA: Ready for data transfers, DPC enabled. 162 * @BRCMF_SDIOD_NOMEDIUM: No medium access to dongle possible. 163 */ 164 enum brcmf_sdiod_state { 165 BRCMF_SDIOD_DOWN, 166 BRCMF_SDIOD_DATA, 167 BRCMF_SDIOD_NOMEDIUM 168 }; 169 170 struct brcmf_sdreg { 171 int func; 172 int offset; 173 int value; 174 }; 175 176 struct brcmf_sdio; 177 struct brcmf_sdiod_freezer; 178 179 struct brcmf_sdio_dev { 180 struct sdio_func *func1; 181 struct sdio_func *func2; 182 u32 sbwad; /* Save backplane window address */ 183 struct brcmf_core *cc_core; /* chipcommon core info struct */ 184 struct brcmf_sdio *bus; 185 struct device *dev; 186 struct brcmf_bus *bus_if; 187 struct brcmf_mp_device *settings; 188 bool oob_irq_requested; 189 bool sd_irq_requested; 190 bool irq_en; /* irq enable flags */ 191 spinlock_t irq_en_lock; 192 bool irq_wake; /* irq wake enable flags */ 193 bool sg_support; 194 uint max_request_size; 195 ushort max_segment_count; 196 uint max_segment_size; 197 uint txglomsz; 198 struct sg_table sgtable; 199 char fw_name[BRCMF_FW_NAME_LEN]; 200 char nvram_name[BRCMF_FW_NAME_LEN]; 201 bool wowl_enabled; 202 enum brcmf_sdiod_state state; 203 struct brcmf_sdiod_freezer *freezer; 204 }; 205 206 /* sdio core registers */ 207 struct sdpcmd_regs { 208 u32 corecontrol; /* 0x00, rev8 */ 209 u32 corestatus; /* rev8 */ 210 u32 PAD[1]; 211 u32 biststatus; /* rev8 */ 212 213 /* PCMCIA access */ 214 u16 pcmciamesportaladdr; /* 0x010, rev8 */ 215 u16 PAD[1]; 216 u16 pcmciamesportalmask; /* rev8 */ 217 u16 PAD[1]; 218 u16 pcmciawrframebc; /* rev8 */ 219 u16 PAD[1]; 220 u16 pcmciaunderflowtimer; /* rev8 */ 221 u16 PAD[1]; 222 223 /* interrupt */ 224 u32 intstatus; /* 0x020, rev8 */ 225 u32 hostintmask; /* rev8 */ 226 u32 intmask; /* rev8 */ 227 u32 sbintstatus; /* rev8 */ 228 u32 sbintmask; /* rev8 */ 229 u32 funcintmask; /* rev4 */ 230 u32 PAD[2]; 231 u32 tosbmailbox; /* 0x040, rev8 */ 232 u32 tohostmailbox; /* rev8 */ 233 u32 tosbmailboxdata; /* rev8 */ 234 u32 tohostmailboxdata; /* rev8 */ 235 236 /* synchronized access to registers in SDIO clock domain */ 237 u32 sdioaccess; /* 0x050, rev8 */ 238 u32 PAD[3]; 239 240 /* PCMCIA frame control */ 241 u8 pcmciaframectrl; /* 0x060, rev8 */ 242 u8 PAD[3]; 243 u8 pcmciawatermark; /* rev8 */ 244 u8 PAD[155]; 245 246 /* interrupt batching control */ 247 u32 intrcvlazy; /* 0x100, rev8 */ 248 u32 PAD[3]; 249 250 /* counters */ 251 u32 cmd52rd; /* 0x110, rev8 */ 252 u32 cmd52wr; /* rev8 */ 253 u32 cmd53rd; /* rev8 */ 254 u32 cmd53wr; /* rev8 */ 255 u32 abort; /* rev8 */ 256 u32 datacrcerror; /* rev8 */ 257 u32 rdoutofsync; /* rev8 */ 258 u32 wroutofsync; /* rev8 */ 259 u32 writebusy; /* rev8 */ 260 u32 readwait; /* rev8 */ 261 u32 readterm; /* rev8 */ 262 u32 writeterm; /* rev8 */ 263 u32 PAD[40]; 264 u32 clockctlstatus; /* rev8 */ 265 u32 PAD[7]; 266 267 u32 PAD[128]; /* DMA engines */ 268 269 /* SDIO/PCMCIA CIS region */ 270 char cis[512]; /* 0x400-0x5ff, rev6 */ 271 272 /* PCMCIA function control registers */ 273 char pcmciafcr[256]; /* 0x600-6ff, rev6 */ 274 u16 PAD[55]; 275 276 /* PCMCIA backplane access */ 277 u16 backplanecsr; /* 0x76E, rev6 */ 278 u16 backplaneaddr0; /* rev6 */ 279 u16 backplaneaddr1; /* rev6 */ 280 u16 backplaneaddr2; /* rev6 */ 281 u16 backplaneaddr3; /* rev6 */ 282 u16 backplanedata0; /* rev6 */ 283 u16 backplanedata1; /* rev6 */ 284 u16 backplanedata2; /* rev6 */ 285 u16 backplanedata3; /* rev6 */ 286 u16 PAD[31]; 287 288 /* sprom "size" & "blank" info */ 289 u16 spromstatus; /* 0x7BE, rev2 */ 290 u32 PAD[464]; 291 292 u16 PAD[0x80]; 293 }; 294 295 /* Register/deregister interrupt handler. */ 296 int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev); 297 void brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev); 298 299 /* SDIO device register access interface */ 300 /* Accessors for SDIO Function 0 */ 301 #define brcmf_sdiod_func0_rb(sdiodev, addr, r) \ 302 sdio_f0_readb((sdiodev)->func1, (addr), (r)) 303 304 #define brcmf_sdiod_func0_wb(sdiodev, addr, v, ret) \ 305 sdio_f0_writeb((sdiodev)->func1, (v), (addr), (ret)) 306 307 /* Accessors for SDIO Function 1 */ 308 #define brcmf_sdiod_readb(sdiodev, addr, r) \ 309 sdio_readb((sdiodev)->func1, (addr), (r)) 310 311 #define brcmf_sdiod_writeb(sdiodev, addr, v, ret) \ 312 sdio_writeb((sdiodev)->func1, (v), (addr), (ret)) 313 314 u32 brcmf_sdiod_readl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret); 315 void brcmf_sdiod_writel(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data, 316 int *ret); 317 318 /* Buffer transfer to/from device (client) core via cmd53. 319 * fn: function number 320 * flags: backplane width, address increment, sync/async 321 * buf: pointer to memory data buffer 322 * nbytes: number of bytes to transfer to/from buf 323 * pkt: pointer to packet associated with buf (if any) 324 * complete: callback function for command completion (async only) 325 * handle: handle for completion callback (first arg in callback) 326 * Returns 0 or error code. 327 * NOTE: Async operation is not currently supported. 328 */ 329 int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev, 330 struct sk_buff_head *pktq); 331 int brcmf_sdiod_send_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes); 332 333 int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev *sdiodev, struct sk_buff *pkt); 334 int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes); 335 int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev, 336 struct sk_buff_head *pktq, uint totlen); 337 338 /* Flags bits */ 339 340 /* Four-byte target (backplane) width (vs. two-byte) */ 341 #define SDIO_REQ_4BYTE 0x1 342 /* Fixed address (FIFO) (vs. incrementing address) */ 343 #define SDIO_REQ_FIXED 0x2 344 345 /* Read/write to memory block (F1, no FIFO) via CMD53 (sync only). 346 * rw: read or write (0/1) 347 * addr: direct SDIO address 348 * buf: pointer to memory data buffer 349 * nbytes: number of bytes to transfer to/from buf 350 * Returns 0 or error code. 351 */ 352 int brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address, 353 u8 *data, uint size); 354 355 /* Issue an abort to the specified function */ 356 int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, struct sdio_func *func); 357 358 void brcmf_sdiod_sgtable_alloc(struct brcmf_sdio_dev *sdiodev); 359 void brcmf_sdiod_change_state(struct brcmf_sdio_dev *sdiodev, 360 enum brcmf_sdiod_state state); 361 #ifdef CONFIG_PM_SLEEP 362 bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev); 363 void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev); 364 void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev); 365 void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev); 366 #else 367 static inline bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev) 368 { 369 return false; 370 } 371 static inline void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev) 372 { 373 } 374 static inline void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev) 375 { 376 } 377 static inline void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev) 378 { 379 } 380 #endif /* CONFIG_PM_SLEEP */ 381 382 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev); 383 void brcmf_sdio_remove(struct brcmf_sdio *bus); 384 void brcmf_sdio_isr(struct brcmf_sdio *bus); 385 386 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active); 387 void brcmf_sdio_wowl_config(struct device *dev, bool enabled); 388 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep); 389 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus); 390 391 #endif /* BRCMFMAC_SDIO_H */ 392