1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/types.h> 18 #include <linux/atomic.h> 19 #include <linux/kernel.h> 20 #include <linux/kthread.h> 21 #include <linux/printk.h> 22 #include <linux/pci_ids.h> 23 #include <linux/netdevice.h> 24 #include <linux/interrupt.h> 25 #include <linux/sched/signal.h> 26 #include <linux/mmc/sdio.h> 27 #include <linux/mmc/sdio_ids.h> 28 #include <linux/mmc/sdio_func.h> 29 #include <linux/mmc/card.h> 30 #include <linux/semaphore.h> 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <linux/bcma/bcma.h> 34 #include <linux/debugfs.h> 35 #include <linux/vmalloc.h> 36 #include <asm/unaligned.h> 37 #include <defs.h> 38 #include <brcmu_wifi.h> 39 #include <brcmu_utils.h> 40 #include <brcm_hw_ids.h> 41 #include <soc.h> 42 #include "sdio.h" 43 #include "chip.h" 44 #include "firmware.h" 45 #include "core.h" 46 #include "common.h" 47 #include "bcdc.h" 48 49 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500) 50 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500) 51 52 /* watermark expressed in number of words */ 53 #define DEFAULT_F2_WATERMARK 0x8 54 #define CY_4373_F2_WATERMARK 0x40 55 #define CY_43012_F2_WATERMARK 0x60 56 57 #ifdef DEBUG 58 59 #define BRCMF_TRAP_INFO_SIZE 80 60 61 #define CBUF_LEN (128) 62 63 /* Device console log buffer state */ 64 #define CONSOLE_BUFFER_MAX 2024 65 66 struct rte_log_le { 67 __le32 buf; /* Can't be pointer on (64-bit) hosts */ 68 __le32 buf_size; 69 __le32 idx; 70 char *_buf_compat; /* Redundant pointer for backward compat. */ 71 }; 72 73 struct rte_console { 74 /* Virtual UART 75 * When there is no UART (e.g. Quickturn), 76 * the host should write a complete 77 * input line directly into cbuf and then write 78 * the length into vcons_in. 79 * This may also be used when there is a real UART 80 * (at risk of conflicting with 81 * the real UART). vcons_out is currently unused. 82 */ 83 uint vcons_in; 84 uint vcons_out; 85 86 /* Output (logging) buffer 87 * Console output is written to a ring buffer log_buf at index log_idx. 88 * The host may read the output when it sees log_idx advance. 89 * Output will be lost if the output wraps around faster than the host 90 * polls. 91 */ 92 struct rte_log_le log_le; 93 94 /* Console input line buffer 95 * Characters are read one at a time into cbuf 96 * until <CR> is received, then 97 * the buffer is processed as a command line. 98 * Also used for virtual UART. 99 */ 100 uint cbuf_idx; 101 char cbuf[CBUF_LEN]; 102 }; 103 104 #endif /* DEBUG */ 105 #include <chipcommon.h> 106 107 #include "bus.h" 108 #include "debug.h" 109 #include "tracepoint.h" 110 111 #define TXQLEN 2048 /* bulk tx queue length */ 112 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ 113 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ 114 #define PRIOMASK 7 115 116 #define TXRETRIES 2 /* # of retries for tx frames */ 117 118 #define BRCMF_RXBOUND 50 /* Default for max rx frames in 119 one scheduling */ 120 121 #define BRCMF_TXBOUND 20 /* Default for max tx frames in 122 one scheduling */ 123 124 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ 125 126 #define MEMBLOCK 2048 /* Block size used for downloading 127 of dongle image */ 128 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold 129 biggest possible glom */ 130 131 #define BRCMF_FIRSTREAD (1 << 6) 132 133 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */ 134 135 /* SBSDIO_DEVICE_CTL */ 136 137 /* 1: device will assert busy signal when receiving CMD53 */ 138 #define SBSDIO_DEVCTL_SETBUSY 0x01 139 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ 140 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 141 /* 1: mask all interrupts to host except the chipActive (rev 8) */ 142 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 143 /* 1: isolate internal sdio signals, put external pads in tri-state; requires 144 * sdio bus power cycle to clear (rev 9) */ 145 #define SBSDIO_DEVCTL_PADS_ISO 0x08 146 /* 1: enable F2 Watermark */ 147 #define SBSDIO_DEVCTL_F2WM_ENAB 0x10 148 /* Force SD->SB reset mapping (rev 11) */ 149 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 150 /* Determined by CoreControl bit */ 151 #define SBSDIO_DEVCTL_RST_CORECTL 0x00 152 /* Force backplane reset */ 153 #define SBSDIO_DEVCTL_RST_BPRESET 0x10 154 /* Force no backplane reset */ 155 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 156 157 /* direct(mapped) cis space */ 158 159 /* MAPPED common CIS address */ 160 #define SBSDIO_CIS_BASE_COMMON 0x1000 161 /* maximum bytes in one CIS */ 162 #define SBSDIO_CIS_SIZE_LIMIT 0x200 163 /* cis offset addr is < 17 bits */ 164 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF 165 166 /* manfid tuple length, include tuple, link bytes */ 167 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 168 169 #define SD_REG(field) \ 170 (offsetof(struct sdpcmd_regs, field)) 171 172 /* SDIO function 1 register CHIPCLKCSR */ 173 /* Force ALP request to backplane */ 174 #define SBSDIO_FORCE_ALP 0x01 175 /* Force HT request to backplane */ 176 #define SBSDIO_FORCE_HT 0x02 177 /* Force ILP request to backplane */ 178 #define SBSDIO_FORCE_ILP 0x04 179 /* Make ALP ready (power up xtal) */ 180 #define SBSDIO_ALP_AVAIL_REQ 0x08 181 /* Make HT ready (power up PLL) */ 182 #define SBSDIO_HT_AVAIL_REQ 0x10 183 /* Squelch clock requests from HW */ 184 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 185 /* Status: ALP is ready */ 186 #define SBSDIO_ALP_AVAIL 0x40 187 /* Status: HT is ready */ 188 #define SBSDIO_HT_AVAIL 0x80 189 #define SBSDIO_CSR_MASK 0x1F 190 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) 191 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) 192 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) 193 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) 194 #define SBSDIO_CLKAV(regval, alponly) \ 195 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) 196 197 /* intstatus */ 198 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ 199 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ 200 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ 201 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ 202 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ 203 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ 204 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ 205 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ 206 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ 207 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ 208 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ 209 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ 210 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ 211 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ 212 #define I_PC (1 << 10) /* descriptor error */ 213 #define I_PD (1 << 11) /* data error */ 214 #define I_DE (1 << 12) /* Descriptor protocol Error */ 215 #define I_RU (1 << 13) /* Receive descriptor Underflow */ 216 #define I_RO (1 << 14) /* Receive fifo Overflow */ 217 #define I_XU (1 << 15) /* Transmit fifo Underflow */ 218 #define I_RI (1 << 16) /* Receive Interrupt */ 219 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ 220 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ 221 #define I_XI (1 << 24) /* Transmit Interrupt */ 222 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ 223 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ 224 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ 225 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ 226 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ 227 #define I_SRESET (1 << 30) /* CCCR RES interrupt */ 228 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ 229 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) 230 #define I_DMA (I_RI | I_XI | I_ERRORS) 231 232 /* corecontrol */ 233 #define CC_CISRDY (1 << 0) /* CIS Ready */ 234 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */ 235 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ 236 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ 237 #define CC_XMTDATAAVAIL_MODE (1 << 4) 238 #define CC_XMTDATAAVAIL_CTRL (1 << 5) 239 240 /* SDA_FRAMECTRL */ 241 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ 242 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ 243 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ 244 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ 245 246 /* 247 * Software allocation of To SB Mailbox resources 248 */ 249 250 /* tosbmailbox bits corresponding to intstatus bits */ 251 #define SMB_NAK (1 << 0) /* Frame NAK */ 252 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ 253 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ 254 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ 255 256 /* tosbmailboxdata */ 257 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ 258 259 /* 260 * Software allocation of To Host Mailbox resources 261 */ 262 263 /* intstatus bits */ 264 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ 265 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ 266 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ 267 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ 268 269 /* tohostmailboxdata */ 270 #define HMB_DATA_NAKHANDLED 0x0001 /* retransmit NAK'd frame */ 271 #define HMB_DATA_DEVREADY 0x0002 /* talk to host after enable */ 272 #define HMB_DATA_FC 0x0004 /* per prio flowcontrol update flag */ 273 #define HMB_DATA_FWREADY 0x0008 /* fw ready for protocol activity */ 274 #define HMB_DATA_FWHALT 0x0010 /* firmware halted */ 275 276 #define HMB_DATA_FCDATA_MASK 0xff000000 277 #define HMB_DATA_FCDATA_SHIFT 24 278 279 #define HMB_DATA_VERSION_MASK 0x00ff0000 280 #define HMB_DATA_VERSION_SHIFT 16 281 282 /* 283 * Software-defined protocol header 284 */ 285 286 /* Current protocol version */ 287 #define SDPCM_PROT_VERSION 4 288 289 /* 290 * Shared structure between dongle and the host. 291 * The structure contains pointers to trap or assert information. 292 */ 293 #define SDPCM_SHARED_VERSION 0x0003 294 #define SDPCM_SHARED_VERSION_MASK 0x00FF 295 #define SDPCM_SHARED_ASSERT_BUILT 0x0100 296 #define SDPCM_SHARED_ASSERT 0x0200 297 #define SDPCM_SHARED_TRAP 0x0400 298 299 /* Space for header read, limit for data packets */ 300 #define MAX_HDR_READ (1 << 6) 301 #define MAX_RX_DATASZ 2048 302 303 /* Bump up limit on waiting for HT to account for first startup; 304 * if the image is doing a CRC calculation before programming the PMU 305 * for HT availability, it could take a couple hundred ms more, so 306 * max out at a 1 second (1000000us). 307 */ 308 #undef PMU_MAX_TRANSITION_DLY 309 #define PMU_MAX_TRANSITION_DLY 1000000 310 311 /* Value for ChipClockCSR during initial setup */ 312 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ 313 SBSDIO_ALP_AVAIL_REQ) 314 315 /* Flags for SDH calls */ 316 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) 317 318 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change 319 * when idle 320 */ 321 #define BRCMF_IDLE_INTERVAL 1 322 323 #define KSO_WAIT_US 50 324 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US) 325 #define BRCMF_SDIO_MAX_ACCESS_ERRORS 5 326 327 /* 328 * Conversion of 802.1D priority to precedence level 329 */ 330 static uint prio2prec(u32 prio) 331 { 332 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ? 333 (prio^2) : prio; 334 } 335 336 #ifdef DEBUG 337 /* Device console log buffer state */ 338 struct brcmf_console { 339 uint count; /* Poll interval msec counter */ 340 uint log_addr; /* Log struct address (fixed) */ 341 struct rte_log_le log_le; /* Log struct (host copy) */ 342 uint bufsize; /* Size of log buffer */ 343 u8 *buf; /* Log buffer (host copy) */ 344 uint last; /* Last buffer read index */ 345 }; 346 347 struct brcmf_trap_info { 348 __le32 type; 349 __le32 epc; 350 __le32 cpsr; 351 __le32 spsr; 352 __le32 r0; /* a1 */ 353 __le32 r1; /* a2 */ 354 __le32 r2; /* a3 */ 355 __le32 r3; /* a4 */ 356 __le32 r4; /* v1 */ 357 __le32 r5; /* v2 */ 358 __le32 r6; /* v3 */ 359 __le32 r7; /* v4 */ 360 __le32 r8; /* v5 */ 361 __le32 r9; /* sb/v6 */ 362 __le32 r10; /* sl/v7 */ 363 __le32 r11; /* fp/v8 */ 364 __le32 r12; /* ip */ 365 __le32 r13; /* sp */ 366 __le32 r14; /* lr */ 367 __le32 pc; /* r15 */ 368 }; 369 #endif /* DEBUG */ 370 371 struct sdpcm_shared { 372 u32 flags; 373 u32 trap_addr; 374 u32 assert_exp_addr; 375 u32 assert_file_addr; 376 u32 assert_line; 377 u32 console_addr; /* Address of struct rte_console */ 378 u32 msgtrace_addr; 379 u8 tag[32]; 380 u32 brpt_addr; 381 }; 382 383 struct sdpcm_shared_le { 384 __le32 flags; 385 __le32 trap_addr; 386 __le32 assert_exp_addr; 387 __le32 assert_file_addr; 388 __le32 assert_line; 389 __le32 console_addr; /* Address of struct rte_console */ 390 __le32 msgtrace_addr; 391 u8 tag[32]; 392 __le32 brpt_addr; 393 }; 394 395 /* dongle SDIO bus specific header info */ 396 struct brcmf_sdio_hdrinfo { 397 u8 seq_num; 398 u8 channel; 399 u16 len; 400 u16 len_left; 401 u16 len_nxtfrm; 402 u8 dat_offset; 403 bool lastfrm; 404 u16 tail_pad; 405 }; 406 407 /* 408 * hold counter variables 409 */ 410 struct brcmf_sdio_count { 411 uint intrcount; /* Count of device interrupt callbacks */ 412 uint lastintrs; /* Count as of last watchdog timer */ 413 uint pollcnt; /* Count of active polls */ 414 uint regfails; /* Count of R_REG failures */ 415 uint tx_sderrs; /* Count of tx attempts with sd errors */ 416 uint fcqueued; /* Tx packets that got queued */ 417 uint rxrtx; /* Count of rtx requests (NAK to dongle) */ 418 uint rx_toolong; /* Receive frames too long to receive */ 419 uint rxc_errors; /* SDIO errors when reading control frames */ 420 uint rx_hdrfail; /* SDIO errors on header reads */ 421 uint rx_badhdr; /* Bad received headers (roosync?) */ 422 uint rx_badseq; /* Mismatched rx sequence number */ 423 uint fc_rcvd; /* Number of flow-control events received */ 424 uint fc_xoff; /* Number which turned on flow-control */ 425 uint fc_xon; /* Number which turned off flow-control */ 426 uint rxglomfail; /* Failed deglom attempts */ 427 uint rxglomframes; /* Number of glom frames (superframes) */ 428 uint rxglompkts; /* Number of packets from glom frames */ 429 uint f2rxhdrs; /* Number of header reads */ 430 uint f2rxdata; /* Number of frame data reads */ 431 uint f2txdata; /* Number of f2 frame writes */ 432 uint f1regdata; /* Number of f1 register accesses */ 433 uint tickcnt; /* Number of watchdog been schedule */ 434 ulong tx_ctlerrs; /* Err of sending ctrl frames */ 435 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */ 436 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */ 437 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */ 438 ulong rx_readahead_cnt; /* packets where header read-ahead was used */ 439 }; 440 441 /* misc chip info needed by some of the routines */ 442 /* Private data for SDIO bus interaction */ 443 struct brcmf_sdio { 444 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ 445 struct brcmf_chip *ci; /* Chip info struct */ 446 struct brcmf_core *sdio_core; /* sdio core info struct */ 447 448 u32 hostintmask; /* Copy of Host Interrupt Mask */ 449 atomic_t intstatus; /* Intstatus bits (events) pending */ 450 atomic_t fcstate; /* State of dongle flow-control */ 451 452 uint blocksize; /* Block size of SDIO transfers */ 453 uint roundup; /* Max roundup limit */ 454 455 struct pktq txq; /* Queue length used for flow-control */ 456 u8 flowcontrol; /* per prio flow control bitmask */ 457 u8 tx_seq; /* Transmit sequence number (next) */ 458 u8 tx_max; /* Maximum transmit sequence allowed */ 459 460 u8 *hdrbuf; /* buffer for handling rx frame */ 461 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ 462 u8 rx_seq; /* Receive sequence number (expected) */ 463 struct brcmf_sdio_hdrinfo cur_read; 464 /* info of current read frame */ 465 bool rxskip; /* Skip receive (awaiting NAK ACK) */ 466 bool rxpending; /* Data frame pending in dongle */ 467 468 uint rxbound; /* Rx frames to read before resched */ 469 uint txbound; /* Tx frames to send before resched */ 470 uint txminmax; 471 472 struct sk_buff *glomd; /* Packet containing glomming descriptor */ 473 struct sk_buff_head glom; /* Packet list for glommed superframe */ 474 475 u8 *rxbuf; /* Buffer for receiving control packets */ 476 uint rxblen; /* Allocated length of rxbuf */ 477 u8 *rxctl; /* Aligned pointer into rxbuf */ 478 u8 *rxctl_orig; /* pointer for freeing rxctl */ 479 uint rxlen; /* Length of valid data in buffer */ 480 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */ 481 482 u8 sdpcm_ver; /* Bus protocol reported by dongle */ 483 484 bool intr; /* Use interrupts */ 485 bool poll; /* Use polling */ 486 atomic_t ipend; /* Device interrupt is pending */ 487 uint spurious; /* Count of spurious interrupts */ 488 uint pollrate; /* Ticks between device polls */ 489 uint polltick; /* Tick counter */ 490 491 #ifdef DEBUG 492 uint console_interval; 493 struct brcmf_console console; /* Console output polling support */ 494 uint console_addr; /* Console address from shared struct */ 495 #endif /* DEBUG */ 496 497 uint clkstate; /* State of sd and backplane clock(s) */ 498 s32 idletime; /* Control for activity timeout */ 499 s32 idlecount; /* Activity timeout counter */ 500 s32 idleclock; /* How to set bus driver when idle */ 501 bool rxflow_mode; /* Rx flow control mode */ 502 bool rxflow; /* Is rx flow control on */ 503 bool alp_only; /* Don't use HT clock (ALP only) */ 504 505 u8 *ctrl_frame_buf; 506 u16 ctrl_frame_len; 507 bool ctrl_frame_stat; 508 int ctrl_frame_err; 509 510 spinlock_t txq_lock; /* protect bus->txq */ 511 wait_queue_head_t ctrl_wait; 512 wait_queue_head_t dcmd_resp_wait; 513 514 struct timer_list timer; 515 struct completion watchdog_wait; 516 struct task_struct *watchdog_tsk; 517 bool wd_active; 518 519 struct workqueue_struct *brcmf_wq; 520 struct work_struct datawork; 521 bool dpc_triggered; 522 bool dpc_running; 523 524 bool txoff; /* Transmit flow-controlled */ 525 struct brcmf_sdio_count sdcnt; 526 bool sr_enabled; /* SaveRestore enabled */ 527 bool sleeping; 528 529 u8 tx_hdrlen; /* sdio bus header length for tx packet */ 530 bool txglom; /* host tx glomming enable flag */ 531 u16 head_align; /* buffer pointer alignment */ 532 u16 sgentry_align; /* scatter-gather buffer alignment */ 533 }; 534 535 /* clkstate */ 536 #define CLK_NONE 0 537 #define CLK_SDONLY 1 538 #define CLK_PENDING 2 539 #define CLK_AVAIL 3 540 541 #ifdef DEBUG 542 static int qcount[NUMPRIO]; 543 #endif /* DEBUG */ 544 545 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */ 546 547 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) 548 549 /* Limit on rounding up frames */ 550 static const uint max_roundup = 512; 551 552 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 553 #define ALIGNMENT 8 554 #else 555 #define ALIGNMENT 4 556 #endif 557 558 enum brcmf_sdio_frmtype { 559 BRCMF_SDIO_FT_NORMAL, 560 BRCMF_SDIO_FT_SUPER, 561 BRCMF_SDIO_FT_SUB, 562 }; 563 564 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) 565 566 /* SDIO Pad drive strength to select value mappings */ 567 struct sdiod_drive_str { 568 u8 strength; /* Pad Drive Strength in mA */ 569 u8 sel; /* Chip-specific select value */ 570 }; 571 572 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */ 573 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = { 574 {32, 0x6}, 575 {26, 0x7}, 576 {22, 0x4}, 577 {16, 0x5}, 578 {12, 0x2}, 579 {8, 0x3}, 580 {4, 0x0}, 581 {0, 0x1} 582 }; 583 584 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */ 585 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = { 586 {6, 0x7}, 587 {5, 0x6}, 588 {4, 0x5}, 589 {3, 0x4}, 590 {2, 0x2}, 591 {1, 0x1}, 592 {0, 0x0} 593 }; 594 595 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */ 596 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = { 597 {3, 0x3}, 598 {2, 0x2}, 599 {1, 0x1}, 600 {0, 0x0} }; 601 602 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */ 603 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = { 604 {16, 0x7}, 605 {12, 0x5}, 606 {8, 0x3}, 607 {4, 0x1} 608 }; 609 610 BRCMF_FW_DEF(43143, "brcmfmac43143-sdio"); 611 BRCMF_FW_DEF(43241B0, "brcmfmac43241b0-sdio"); 612 BRCMF_FW_DEF(43241B4, "brcmfmac43241b4-sdio"); 613 BRCMF_FW_DEF(43241B5, "brcmfmac43241b5-sdio"); 614 BRCMF_FW_DEF(4329, "brcmfmac4329-sdio"); 615 BRCMF_FW_DEF(4330, "brcmfmac4330-sdio"); 616 BRCMF_FW_DEF(4334, "brcmfmac4334-sdio"); 617 BRCMF_FW_DEF(43340, "brcmfmac43340-sdio"); 618 BRCMF_FW_DEF(4335, "brcmfmac4335-sdio"); 619 BRCMF_FW_DEF(43362, "brcmfmac43362-sdio"); 620 BRCMF_FW_DEF(4339, "brcmfmac4339-sdio"); 621 BRCMF_FW_DEF(43430A0, "brcmfmac43430a0-sdio"); 622 /* Note the names are not postfixed with a1 for backward compatibility */ 623 BRCMF_FW_DEF(43430A1, "brcmfmac43430-sdio"); 624 BRCMF_FW_DEF(43455, "brcmfmac43455-sdio"); 625 BRCMF_FW_DEF(43456, "brcmfmac43456-sdio"); 626 BRCMF_FW_DEF(4354, "brcmfmac4354-sdio"); 627 BRCMF_FW_DEF(4356, "brcmfmac4356-sdio"); 628 BRCMF_FW_DEF(4373, "brcmfmac4373-sdio"); 629 BRCMF_FW_DEF(43012, "brcmfmac43012-sdio"); 630 631 static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = { 632 BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143), 633 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0), 634 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4), 635 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5), 636 BRCMF_FW_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329), 637 BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330), 638 BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334), 639 BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340), 640 BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340), 641 BRCMF_FW_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335), 642 BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362), 643 BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339), 644 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0), 645 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFE, 43430A1), 646 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0x00000200, 43456), 647 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFDC0, 43455), 648 BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354), 649 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 650 BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373), 651 BRCMF_FW_ENTRY(CY_CC_43012_CHIP_ID, 0xFFFFFFFF, 43012) 652 }; 653 654 static void pkt_align(struct sk_buff *p, int len, int align) 655 { 656 uint datalign; 657 datalign = (unsigned long)(p->data); 658 datalign = roundup(datalign, (align)) - datalign; 659 if (datalign) 660 skb_pull(p, datalign); 661 __skb_trim(p, len); 662 } 663 664 /* To check if there's window offered */ 665 static bool data_ok(struct brcmf_sdio *bus) 666 { 667 return (u8)(bus->tx_max - bus->tx_seq) != 0 && 668 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0; 669 } 670 671 static int 672 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on) 673 { 674 u8 wr_val = 0, rd_val, cmp_val, bmask; 675 int err = 0; 676 int err_cnt = 0; 677 int try_cnt = 0; 678 679 brcmf_dbg(TRACE, "Enter: on=%d\n", on); 680 681 sdio_retune_crc_disable(bus->sdiodev->func1); 682 683 /* Cannot re-tune if device is asleep; defer till we're awake */ 684 if (on) 685 sdio_retune_hold_now(bus->sdiodev->func1); 686 687 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); 688 /* 1st KSO write goes to AOS wake up core if device is asleep */ 689 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err); 690 691 /* In case of 43012 chip, the chip could go down immediately after 692 * KSO bit is cleared. So the further reads of KSO register could 693 * fail. Thereby just bailing out immediately after clearing KSO 694 * bit, to avoid polling of KSO bit. 695 */ 696 if (!on && bus->ci->chip == CY_CC_43012_CHIP_ID) 697 return err; 698 699 if (on) { 700 /* device WAKEUP through KSO: 701 * write bit 0 & read back until 702 * both bits 0 (kso bit) & 1 (dev on status) are set 703 */ 704 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | 705 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK; 706 bmask = cmp_val; 707 usleep_range(2000, 3000); 708 } else { 709 /* Put device to sleep, turn off KSO */ 710 cmp_val = 0; 711 /* only check for bit0, bit1(dev on status) may not 712 * get cleared right away 713 */ 714 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK; 715 } 716 717 do { 718 /* reliable KSO bit set/clr: 719 * the sdiod sleep write access is synced to PMU 32khz clk 720 * just one write attempt may fail, 721 * read it back until it matches written value 722 */ 723 rd_val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 724 &err); 725 if (!err) { 726 if ((rd_val & bmask) == cmp_val) 727 break; 728 err_cnt = 0; 729 } 730 /* bail out upon subsequent access errors */ 731 if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS)) 732 break; 733 734 udelay(KSO_WAIT_US); 735 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, 736 &err); 737 738 } while (try_cnt++ < MAX_KSO_ATTEMPTS); 739 740 if (try_cnt > 2) 741 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt, 742 rd_val, err); 743 744 if (try_cnt > MAX_KSO_ATTEMPTS) 745 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err); 746 747 if (on) 748 sdio_retune_release(bus->sdiodev->func1); 749 750 sdio_retune_crc_enable(bus->sdiodev->func1); 751 752 return err; 753 } 754 755 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) 756 757 /* Turn backplane clock on or off */ 758 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok) 759 { 760 int err; 761 u8 clkctl, clkreq, devctl; 762 unsigned long timeout; 763 764 brcmf_dbg(SDIO, "Enter\n"); 765 766 clkctl = 0; 767 768 if (bus->sr_enabled) { 769 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY); 770 return 0; 771 } 772 773 if (on) { 774 /* Request HT Avail */ 775 clkreq = 776 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; 777 778 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 779 clkreq, &err); 780 if (err) { 781 brcmf_err("HT Avail request error: %d\n", err); 782 return -EBADE; 783 } 784 785 /* Check current status */ 786 clkctl = brcmf_sdiod_readb(bus->sdiodev, 787 SBSDIO_FUNC1_CHIPCLKCSR, &err); 788 if (err) { 789 brcmf_err("HT Avail read error: %d\n", err); 790 return -EBADE; 791 } 792 793 /* Go to pending and await interrupt if appropriate */ 794 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { 795 /* Allow only clock-available interrupt */ 796 devctl = brcmf_sdiod_readb(bus->sdiodev, 797 SBSDIO_DEVICE_CTL, &err); 798 if (err) { 799 brcmf_err("Devctl error setting CA: %d\n", err); 800 return -EBADE; 801 } 802 803 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; 804 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 805 devctl, &err); 806 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n"); 807 bus->clkstate = CLK_PENDING; 808 809 return 0; 810 } else if (bus->clkstate == CLK_PENDING) { 811 /* Cancel CA-only interrupt filter */ 812 devctl = brcmf_sdiod_readb(bus->sdiodev, 813 SBSDIO_DEVICE_CTL, &err); 814 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 815 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 816 devctl, &err); 817 } 818 819 /* Otherwise, wait here (polling) for HT Avail */ 820 timeout = jiffies + 821 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); 822 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 823 clkctl = brcmf_sdiod_readb(bus->sdiodev, 824 SBSDIO_FUNC1_CHIPCLKCSR, 825 &err); 826 if (time_after(jiffies, timeout)) 827 break; 828 else 829 usleep_range(5000, 10000); 830 } 831 if (err) { 832 brcmf_err("HT Avail request error: %d\n", err); 833 return -EBADE; 834 } 835 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 836 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n", 837 PMU_MAX_TRANSITION_DLY, clkctl); 838 return -EBADE; 839 } 840 841 /* Mark clock available */ 842 bus->clkstate = CLK_AVAIL; 843 brcmf_dbg(SDIO, "CLKCTL: turned ON\n"); 844 845 #if defined(DEBUG) 846 if (!bus->alp_only) { 847 if (SBSDIO_ALPONLY(clkctl)) 848 brcmf_err("HT Clock should be on\n"); 849 } 850 #endif /* defined (DEBUG) */ 851 852 } else { 853 clkreq = 0; 854 855 if (bus->clkstate == CLK_PENDING) { 856 /* Cancel CA-only interrupt filter */ 857 devctl = brcmf_sdiod_readb(bus->sdiodev, 858 SBSDIO_DEVICE_CTL, &err); 859 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 860 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 861 devctl, &err); 862 } 863 864 bus->clkstate = CLK_SDONLY; 865 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 866 clkreq, &err); 867 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n"); 868 if (err) { 869 brcmf_err("Failed access turning clock off: %d\n", 870 err); 871 return -EBADE; 872 } 873 } 874 return 0; 875 } 876 877 /* Change idle/active SD state */ 878 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on) 879 { 880 brcmf_dbg(SDIO, "Enter\n"); 881 882 if (on) 883 bus->clkstate = CLK_SDONLY; 884 else 885 bus->clkstate = CLK_NONE; 886 887 return 0; 888 } 889 890 /* Transition SD and backplane clock readiness */ 891 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) 892 { 893 #ifdef DEBUG 894 uint oldstate = bus->clkstate; 895 #endif /* DEBUG */ 896 897 brcmf_dbg(SDIO, "Enter\n"); 898 899 /* Early exit if we're already there */ 900 if (bus->clkstate == target) 901 return 0; 902 903 switch (target) { 904 case CLK_AVAIL: 905 /* Make sure SD clock is available */ 906 if (bus->clkstate == CLK_NONE) 907 brcmf_sdio_sdclk(bus, true); 908 /* Now request HT Avail on the backplane */ 909 brcmf_sdio_htclk(bus, true, pendok); 910 break; 911 912 case CLK_SDONLY: 913 /* Remove HT request, or bring up SD clock */ 914 if (bus->clkstate == CLK_NONE) 915 brcmf_sdio_sdclk(bus, true); 916 else if (bus->clkstate == CLK_AVAIL) 917 brcmf_sdio_htclk(bus, false, false); 918 else 919 brcmf_err("request for %d -> %d\n", 920 bus->clkstate, target); 921 break; 922 923 case CLK_NONE: 924 /* Make sure to remove HT request */ 925 if (bus->clkstate == CLK_AVAIL) 926 brcmf_sdio_htclk(bus, false, false); 927 /* Now remove the SD clock */ 928 brcmf_sdio_sdclk(bus, false); 929 break; 930 } 931 #ifdef DEBUG 932 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate); 933 #endif /* DEBUG */ 934 935 return 0; 936 } 937 938 static int 939 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok) 940 { 941 int err = 0; 942 u8 clkcsr; 943 944 brcmf_dbg(SDIO, "Enter: request %s currently %s\n", 945 (sleep ? "SLEEP" : "WAKE"), 946 (bus->sleeping ? "SLEEP" : "WAKE")); 947 948 /* If SR is enabled control bus state with KSO */ 949 if (bus->sr_enabled) { 950 /* Done if we're already in the requested state */ 951 if (sleep == bus->sleeping) 952 goto end; 953 954 /* Going to sleep */ 955 if (sleep) { 956 clkcsr = brcmf_sdiod_readb(bus->sdiodev, 957 SBSDIO_FUNC1_CHIPCLKCSR, 958 &err); 959 if ((clkcsr & SBSDIO_CSR_MASK) == 0) { 960 brcmf_dbg(SDIO, "no clock, set ALP\n"); 961 brcmf_sdiod_writeb(bus->sdiodev, 962 SBSDIO_FUNC1_CHIPCLKCSR, 963 SBSDIO_ALP_AVAIL_REQ, &err); 964 } 965 err = brcmf_sdio_kso_control(bus, false); 966 } else { 967 err = brcmf_sdio_kso_control(bus, true); 968 } 969 if (err) { 970 brcmf_err("error while changing bus sleep state %d\n", 971 err); 972 goto done; 973 } 974 } 975 976 end: 977 /* control clocks */ 978 if (sleep) { 979 if (!bus->sr_enabled) 980 brcmf_sdio_clkctl(bus, CLK_NONE, pendok); 981 } else { 982 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok); 983 brcmf_sdio_wd_timer(bus, true); 984 } 985 bus->sleeping = sleep; 986 brcmf_dbg(SDIO, "new state %s\n", 987 (sleep ? "SLEEP" : "WAKE")); 988 done: 989 brcmf_dbg(SDIO, "Exit: err=%d\n", err); 990 return err; 991 992 } 993 994 #ifdef DEBUG 995 static inline bool brcmf_sdio_valid_shared_address(u32 addr) 996 { 997 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)); 998 } 999 1000 static int brcmf_sdio_readshared(struct brcmf_sdio *bus, 1001 struct sdpcm_shared *sh) 1002 { 1003 u32 addr = 0; 1004 int rv; 1005 u32 shaddr = 0; 1006 struct sdpcm_shared_le sh_le; 1007 __le32 addr_le; 1008 1009 sdio_claim_host(bus->sdiodev->func1); 1010 brcmf_sdio_bus_sleep(bus, false, false); 1011 1012 /* 1013 * Read last word in socram to determine 1014 * address of sdpcm_shared structure 1015 */ 1016 shaddr = bus->ci->rambase + bus->ci->ramsize - 4; 1017 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci)) 1018 shaddr -= bus->ci->srsize; 1019 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, 1020 (u8 *)&addr_le, 4); 1021 if (rv < 0) 1022 goto fail; 1023 1024 /* 1025 * Check if addr is valid. 1026 * NVRAM length at the end of memory should have been overwritten. 1027 */ 1028 addr = le32_to_cpu(addr_le); 1029 if (!brcmf_sdio_valid_shared_address(addr)) { 1030 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr); 1031 rv = -EINVAL; 1032 goto fail; 1033 } 1034 1035 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr); 1036 1037 /* Read hndrte_shared structure */ 1038 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le, 1039 sizeof(struct sdpcm_shared_le)); 1040 if (rv < 0) 1041 goto fail; 1042 1043 sdio_release_host(bus->sdiodev->func1); 1044 1045 /* Endianness */ 1046 sh->flags = le32_to_cpu(sh_le.flags); 1047 sh->trap_addr = le32_to_cpu(sh_le.trap_addr); 1048 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr); 1049 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr); 1050 sh->assert_line = le32_to_cpu(sh_le.assert_line); 1051 sh->console_addr = le32_to_cpu(sh_le.console_addr); 1052 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr); 1053 1054 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) { 1055 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n", 1056 SDPCM_SHARED_VERSION, 1057 sh->flags & SDPCM_SHARED_VERSION_MASK); 1058 return -EPROTO; 1059 } 1060 return 0; 1061 1062 fail: 1063 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n", 1064 rv, addr); 1065 sdio_release_host(bus->sdiodev->func1); 1066 return rv; 1067 } 1068 1069 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) 1070 { 1071 struct sdpcm_shared sh; 1072 1073 if (brcmf_sdio_readshared(bus, &sh) == 0) 1074 bus->console_addr = sh.console_addr; 1075 } 1076 #else 1077 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) 1078 { 1079 } 1080 #endif /* DEBUG */ 1081 1082 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus) 1083 { 1084 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 1085 struct brcmf_core *core = bus->sdio_core; 1086 u32 intstatus = 0; 1087 u32 hmb_data; 1088 u8 fcbits; 1089 int ret; 1090 1091 brcmf_dbg(SDIO, "Enter\n"); 1092 1093 /* Read mailbox data and ack that we did so */ 1094 hmb_data = brcmf_sdiod_readl(sdiod, 1095 core->base + SD_REG(tohostmailboxdata), 1096 &ret); 1097 1098 if (!ret) 1099 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox), 1100 SMB_INT_ACK, &ret); 1101 1102 bus->sdcnt.f1regdata += 2; 1103 1104 /* dongle indicates the firmware has halted/crashed */ 1105 if (hmb_data & HMB_DATA_FWHALT) { 1106 brcmf_dbg(SDIO, "mailbox indicates firmware halted\n"); 1107 brcmf_fw_crashed(&sdiod->func1->dev); 1108 } 1109 1110 /* Dongle recomposed rx frames, accept them again */ 1111 if (hmb_data & HMB_DATA_NAKHANDLED) { 1112 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n", 1113 bus->rx_seq); 1114 if (!bus->rxskip) 1115 brcmf_err("unexpected NAKHANDLED!\n"); 1116 1117 bus->rxskip = false; 1118 intstatus |= I_HMB_FRAME_IND; 1119 } 1120 1121 /* 1122 * DEVREADY does not occur with gSPI. 1123 */ 1124 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { 1125 bus->sdpcm_ver = 1126 (hmb_data & HMB_DATA_VERSION_MASK) >> 1127 HMB_DATA_VERSION_SHIFT; 1128 if (bus->sdpcm_ver != SDPCM_PROT_VERSION) 1129 brcmf_err("Version mismatch, dongle reports %d, " 1130 "expecting %d\n", 1131 bus->sdpcm_ver, SDPCM_PROT_VERSION); 1132 else 1133 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n", 1134 bus->sdpcm_ver); 1135 1136 /* 1137 * Retrieve console state address now that firmware should have 1138 * updated it. 1139 */ 1140 brcmf_sdio_get_console_addr(bus); 1141 } 1142 1143 /* 1144 * Flow Control has been moved into the RX headers and this out of band 1145 * method isn't used any more. 1146 * remaining backward compatible with older dongles. 1147 */ 1148 if (hmb_data & HMB_DATA_FC) { 1149 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> 1150 HMB_DATA_FCDATA_SHIFT; 1151 1152 if (fcbits & ~bus->flowcontrol) 1153 bus->sdcnt.fc_xoff++; 1154 1155 if (bus->flowcontrol & ~fcbits) 1156 bus->sdcnt.fc_xon++; 1157 1158 bus->sdcnt.fc_rcvd++; 1159 bus->flowcontrol = fcbits; 1160 } 1161 1162 /* Shouldn't be any others */ 1163 if (hmb_data & ~(HMB_DATA_DEVREADY | 1164 HMB_DATA_NAKHANDLED | 1165 HMB_DATA_FC | 1166 HMB_DATA_FWREADY | 1167 HMB_DATA_FWHALT | 1168 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) 1169 brcmf_err("Unknown mailbox data content: 0x%02x\n", 1170 hmb_data); 1171 1172 return intstatus; 1173 } 1174 1175 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) 1176 { 1177 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 1178 struct brcmf_core *core = bus->sdio_core; 1179 uint retries = 0; 1180 u16 lastrbc; 1181 u8 hi, lo; 1182 int err; 1183 1184 brcmf_err("%sterminate frame%s\n", 1185 abort ? "abort command, " : "", 1186 rtx ? ", send NAK" : ""); 1187 1188 if (abort) 1189 brcmf_sdiod_abort(bus->sdiodev, bus->sdiodev->func2); 1190 1191 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM, 1192 &err); 1193 bus->sdcnt.f1regdata++; 1194 1195 /* Wait until the packet has been flushed (device/FIFO stable) */ 1196 for (lastrbc = retries = 0xffff; retries > 0; retries--) { 1197 hi = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCHI, 1198 &err); 1199 lo = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCLO, 1200 &err); 1201 bus->sdcnt.f1regdata += 2; 1202 1203 if ((hi == 0) && (lo == 0)) 1204 break; 1205 1206 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { 1207 brcmf_err("count growing: last 0x%04x now 0x%04x\n", 1208 lastrbc, (hi << 8) + lo); 1209 } 1210 lastrbc = (hi << 8) + lo; 1211 } 1212 1213 if (!retries) 1214 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc); 1215 else 1216 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries); 1217 1218 if (rtx) { 1219 bus->sdcnt.rxrtx++; 1220 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox), 1221 SMB_NAK, &err); 1222 1223 bus->sdcnt.f1regdata++; 1224 if (err == 0) 1225 bus->rxskip = true; 1226 } 1227 1228 /* Clear partial in any case */ 1229 bus->cur_read.len = 0; 1230 } 1231 1232 static void brcmf_sdio_txfail(struct brcmf_sdio *bus) 1233 { 1234 struct brcmf_sdio_dev *sdiodev = bus->sdiodev; 1235 u8 i, hi, lo; 1236 1237 /* On failure, abort the command and terminate the frame */ 1238 brcmf_err("sdio error, abort command and terminate frame\n"); 1239 bus->sdcnt.tx_sderrs++; 1240 1241 brcmf_sdiod_abort(sdiodev, sdiodev->func2); 1242 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL); 1243 bus->sdcnt.f1regdata++; 1244 1245 for (i = 0; i < 3; i++) { 1246 hi = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL); 1247 lo = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL); 1248 bus->sdcnt.f1regdata += 2; 1249 if ((hi == 0) && (lo == 0)) 1250 break; 1251 } 1252 } 1253 1254 /* return total length of buffer chain */ 1255 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus) 1256 { 1257 struct sk_buff *p; 1258 uint total; 1259 1260 total = 0; 1261 skb_queue_walk(&bus->glom, p) 1262 total += p->len; 1263 return total; 1264 } 1265 1266 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus) 1267 { 1268 struct sk_buff *cur, *next; 1269 1270 skb_queue_walk_safe(&bus->glom, cur, next) { 1271 skb_unlink(cur, &bus->glom); 1272 brcmu_pkt_buf_free_skb(cur); 1273 } 1274 } 1275 1276 /** 1277 * brcmfmac sdio bus specific header 1278 * This is the lowest layer header wrapped on the packets transmitted between 1279 * host and WiFi dongle which contains information needed for SDIO core and 1280 * firmware 1281 * 1282 * It consists of 3 parts: hardware header, hardware extension header and 1283 * software header 1284 * hardware header (frame tag) - 4 bytes 1285 * Byte 0~1: Frame length 1286 * Byte 2~3: Checksum, bit-wise inverse of frame length 1287 * hardware extension header - 8 bytes 1288 * Tx glom mode only, N/A for Rx or normal Tx 1289 * Byte 0~1: Packet length excluding hw frame tag 1290 * Byte 2: Reserved 1291 * Byte 3: Frame flags, bit 0: last frame indication 1292 * Byte 4~5: Reserved 1293 * Byte 6~7: Tail padding length 1294 * software header - 8 bytes 1295 * Byte 0: Rx/Tx sequence number 1296 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag 1297 * Byte 2: Length of next data frame, reserved for Tx 1298 * Byte 3: Data offset 1299 * Byte 4: Flow control bits, reserved for Tx 1300 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet 1301 * Byte 6~7: Reserved 1302 */ 1303 #define SDPCM_HWHDR_LEN 4 1304 #define SDPCM_HWEXT_LEN 8 1305 #define SDPCM_SWHDR_LEN 8 1306 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN) 1307 /* software header */ 1308 #define SDPCM_SEQ_MASK 0x000000ff 1309 #define SDPCM_SEQ_WRAP 256 1310 #define SDPCM_CHANNEL_MASK 0x00000f00 1311 #define SDPCM_CHANNEL_SHIFT 8 1312 #define SDPCM_CONTROL_CHANNEL 0 /* Control */ 1313 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */ 1314 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */ 1315 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */ 1316 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */ 1317 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) 1318 #define SDPCM_NEXTLEN_MASK 0x00ff0000 1319 #define SDPCM_NEXTLEN_SHIFT 16 1320 #define SDPCM_DOFFSET_MASK 0xff000000 1321 #define SDPCM_DOFFSET_SHIFT 24 1322 #define SDPCM_FCMASK_MASK 0x000000ff 1323 #define SDPCM_WINDOW_MASK 0x0000ff00 1324 #define SDPCM_WINDOW_SHIFT 8 1325 1326 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader) 1327 { 1328 u32 hdrvalue; 1329 hdrvalue = *(u32 *)swheader; 1330 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT); 1331 } 1332 1333 static inline bool brcmf_sdio_fromevntchan(u8 *swheader) 1334 { 1335 u32 hdrvalue; 1336 u8 ret; 1337 1338 hdrvalue = *(u32 *)swheader; 1339 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT); 1340 1341 return (ret == SDPCM_EVENT_CHANNEL); 1342 } 1343 1344 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header, 1345 struct brcmf_sdio_hdrinfo *rd, 1346 enum brcmf_sdio_frmtype type) 1347 { 1348 u16 len, checksum; 1349 u8 rx_seq, fc, tx_seq_max; 1350 u32 swheader; 1351 1352 trace_brcmf_sdpcm_hdr(SDPCM_RX, header); 1353 1354 /* hw header */ 1355 len = get_unaligned_le16(header); 1356 checksum = get_unaligned_le16(header + sizeof(u16)); 1357 /* All zero means no more to read */ 1358 if (!(len | checksum)) { 1359 bus->rxpending = false; 1360 return -ENODATA; 1361 } 1362 if ((u16)(~(len ^ checksum))) { 1363 brcmf_err("HW header checksum error\n"); 1364 bus->sdcnt.rx_badhdr++; 1365 brcmf_sdio_rxfail(bus, false, false); 1366 return -EIO; 1367 } 1368 if (len < SDPCM_HDRLEN) { 1369 brcmf_err("HW header length error\n"); 1370 return -EPROTO; 1371 } 1372 if (type == BRCMF_SDIO_FT_SUPER && 1373 (roundup(len, bus->blocksize) != rd->len)) { 1374 brcmf_err("HW superframe header length error\n"); 1375 return -EPROTO; 1376 } 1377 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) { 1378 brcmf_err("HW subframe header length error\n"); 1379 return -EPROTO; 1380 } 1381 rd->len = len; 1382 1383 /* software header */ 1384 header += SDPCM_HWHDR_LEN; 1385 swheader = le32_to_cpu(*(__le32 *)header); 1386 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) { 1387 brcmf_err("Glom descriptor found in superframe head\n"); 1388 rd->len = 0; 1389 return -EINVAL; 1390 } 1391 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK); 1392 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT; 1393 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL && 1394 type != BRCMF_SDIO_FT_SUPER) { 1395 brcmf_err("HW header length too long\n"); 1396 bus->sdcnt.rx_toolong++; 1397 brcmf_sdio_rxfail(bus, false, false); 1398 rd->len = 0; 1399 return -EPROTO; 1400 } 1401 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) { 1402 brcmf_err("Wrong channel for superframe\n"); 1403 rd->len = 0; 1404 return -EINVAL; 1405 } 1406 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL && 1407 rd->channel != SDPCM_EVENT_CHANNEL) { 1408 brcmf_err("Wrong channel for subframe\n"); 1409 rd->len = 0; 1410 return -EINVAL; 1411 } 1412 rd->dat_offset = brcmf_sdio_getdatoffset(header); 1413 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) { 1414 brcmf_err("seq %d: bad data offset\n", rx_seq); 1415 bus->sdcnt.rx_badhdr++; 1416 brcmf_sdio_rxfail(bus, false, false); 1417 rd->len = 0; 1418 return -ENXIO; 1419 } 1420 if (rd->seq_num != rx_seq) { 1421 brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num); 1422 bus->sdcnt.rx_badseq++; 1423 rd->seq_num = rx_seq; 1424 } 1425 /* no need to check the reset for subframe */ 1426 if (type == BRCMF_SDIO_FT_SUB) 1427 return 0; 1428 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT; 1429 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) { 1430 /* only warm for NON glom packet */ 1431 if (rd->channel != SDPCM_GLOM_CHANNEL) 1432 brcmf_err("seq %d: next length error\n", rx_seq); 1433 rd->len_nxtfrm = 0; 1434 } 1435 swheader = le32_to_cpu(*(__le32 *)(header + 4)); 1436 fc = swheader & SDPCM_FCMASK_MASK; 1437 if (bus->flowcontrol != fc) { 1438 if (~bus->flowcontrol & fc) 1439 bus->sdcnt.fc_xoff++; 1440 if (bus->flowcontrol & ~fc) 1441 bus->sdcnt.fc_xon++; 1442 bus->sdcnt.fc_rcvd++; 1443 bus->flowcontrol = fc; 1444 } 1445 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT; 1446 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) { 1447 brcmf_err("seq %d: max tx seq number error\n", rx_seq); 1448 tx_seq_max = bus->tx_seq + 2; 1449 } 1450 bus->tx_max = tx_seq_max; 1451 1452 return 0; 1453 } 1454 1455 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length) 1456 { 1457 *(__le16 *)header = cpu_to_le16(frm_length); 1458 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length); 1459 } 1460 1461 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header, 1462 struct brcmf_sdio_hdrinfo *hd_info) 1463 { 1464 u32 hdrval; 1465 u8 hdr_offset; 1466 1467 brcmf_sdio_update_hwhdr(header, hd_info->len); 1468 hdr_offset = SDPCM_HWHDR_LEN; 1469 1470 if (bus->txglom) { 1471 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24); 1472 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); 1473 hdrval = (u16)hd_info->tail_pad << 16; 1474 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval); 1475 hdr_offset += SDPCM_HWEXT_LEN; 1476 } 1477 1478 hdrval = hd_info->seq_num; 1479 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) & 1480 SDPCM_CHANNEL_MASK; 1481 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) & 1482 SDPCM_DOFFSET_MASK; 1483 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); 1484 *(((__le32 *)(header + hdr_offset)) + 1) = 0; 1485 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header); 1486 } 1487 1488 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq) 1489 { 1490 u16 dlen, totlen; 1491 u8 *dptr, num = 0; 1492 u16 sublen; 1493 struct sk_buff *pfirst, *pnext; 1494 1495 int errcode; 1496 u8 doff; 1497 1498 struct brcmf_sdio_hdrinfo rd_new; 1499 1500 /* If packets, issue read(s) and send up packet chain */ 1501 /* Return sequence numbers consumed? */ 1502 1503 brcmf_dbg(SDIO, "start: glomd %p glom %p\n", 1504 bus->glomd, skb_peek(&bus->glom)); 1505 1506 /* If there's a descriptor, generate the packet chain */ 1507 if (bus->glomd) { 1508 pfirst = pnext = NULL; 1509 dlen = (u16) (bus->glomd->len); 1510 dptr = bus->glomd->data; 1511 if (!dlen || (dlen & 1)) { 1512 brcmf_err("bad glomd len(%d), ignore descriptor\n", 1513 dlen); 1514 dlen = 0; 1515 } 1516 1517 for (totlen = num = 0; dlen; num++) { 1518 /* Get (and move past) next length */ 1519 sublen = get_unaligned_le16(dptr); 1520 dlen -= sizeof(u16); 1521 dptr += sizeof(u16); 1522 if ((sublen < SDPCM_HDRLEN) || 1523 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { 1524 brcmf_err("descriptor len %d bad: %d\n", 1525 num, sublen); 1526 pnext = NULL; 1527 break; 1528 } 1529 if (sublen % bus->sgentry_align) { 1530 brcmf_err("sublen %d not multiple of %d\n", 1531 sublen, bus->sgentry_align); 1532 } 1533 totlen += sublen; 1534 1535 /* For last frame, adjust read len so total 1536 is a block multiple */ 1537 if (!dlen) { 1538 sublen += 1539 (roundup(totlen, bus->blocksize) - totlen); 1540 totlen = roundup(totlen, bus->blocksize); 1541 } 1542 1543 /* Allocate/chain packet for next subframe */ 1544 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align); 1545 if (pnext == NULL) { 1546 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n", 1547 num, sublen); 1548 break; 1549 } 1550 skb_queue_tail(&bus->glom, pnext); 1551 1552 /* Adhere to start alignment requirements */ 1553 pkt_align(pnext, sublen, bus->sgentry_align); 1554 } 1555 1556 /* If all allocations succeeded, save packet chain 1557 in bus structure */ 1558 if (pnext) { 1559 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", 1560 totlen, num); 1561 if (BRCMF_GLOM_ON() && bus->cur_read.len && 1562 totlen != bus->cur_read.len) { 1563 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", 1564 bus->cur_read.len, totlen, rxseq); 1565 } 1566 pfirst = pnext = NULL; 1567 } else { 1568 brcmf_sdio_free_glom(bus); 1569 num = 0; 1570 } 1571 1572 /* Done with descriptor packet */ 1573 brcmu_pkt_buf_free_skb(bus->glomd); 1574 bus->glomd = NULL; 1575 bus->cur_read.len = 0; 1576 } 1577 1578 /* Ok -- either we just generated a packet chain, 1579 or had one from before */ 1580 if (!skb_queue_empty(&bus->glom)) { 1581 if (BRCMF_GLOM_ON()) { 1582 brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); 1583 skb_queue_walk(&bus->glom, pnext) { 1584 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", 1585 pnext, (u8 *) (pnext->data), 1586 pnext->len, pnext->len); 1587 } 1588 } 1589 1590 pfirst = skb_peek(&bus->glom); 1591 dlen = (u16) brcmf_sdio_glom_len(bus); 1592 1593 /* Do an SDIO read for the superframe. Configurable iovar to 1594 * read directly into the chained packet, or allocate a large 1595 * packet and and copy into the chain. 1596 */ 1597 sdio_claim_host(bus->sdiodev->func1); 1598 errcode = brcmf_sdiod_recv_chain(bus->sdiodev, 1599 &bus->glom, dlen); 1600 sdio_release_host(bus->sdiodev->func1); 1601 bus->sdcnt.f2rxdata++; 1602 1603 /* On failure, kill the superframe */ 1604 if (errcode < 0) { 1605 brcmf_err("glom read of %d bytes failed: %d\n", 1606 dlen, errcode); 1607 1608 sdio_claim_host(bus->sdiodev->func1); 1609 brcmf_sdio_rxfail(bus, true, false); 1610 bus->sdcnt.rxglomfail++; 1611 brcmf_sdio_free_glom(bus); 1612 sdio_release_host(bus->sdiodev->func1); 1613 return 0; 1614 } 1615 1616 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1617 pfirst->data, min_t(int, pfirst->len, 48), 1618 "SUPERFRAME:\n"); 1619 1620 rd_new.seq_num = rxseq; 1621 rd_new.len = dlen; 1622 sdio_claim_host(bus->sdiodev->func1); 1623 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new, 1624 BRCMF_SDIO_FT_SUPER); 1625 sdio_release_host(bus->sdiodev->func1); 1626 bus->cur_read.len = rd_new.len_nxtfrm << 4; 1627 1628 /* Remove superframe header, remember offset */ 1629 skb_pull(pfirst, rd_new.dat_offset); 1630 num = 0; 1631 1632 /* Validate all the subframe headers */ 1633 skb_queue_walk(&bus->glom, pnext) { 1634 /* leave when invalid subframe is found */ 1635 if (errcode) 1636 break; 1637 1638 rd_new.len = pnext->len; 1639 rd_new.seq_num = rxseq++; 1640 sdio_claim_host(bus->sdiodev->func1); 1641 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new, 1642 BRCMF_SDIO_FT_SUB); 1643 sdio_release_host(bus->sdiodev->func1); 1644 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1645 pnext->data, 32, "subframe:\n"); 1646 1647 num++; 1648 } 1649 1650 if (errcode) { 1651 /* Terminate frame on error */ 1652 sdio_claim_host(bus->sdiodev->func1); 1653 brcmf_sdio_rxfail(bus, true, false); 1654 bus->sdcnt.rxglomfail++; 1655 brcmf_sdio_free_glom(bus); 1656 sdio_release_host(bus->sdiodev->func1); 1657 bus->cur_read.len = 0; 1658 return 0; 1659 } 1660 1661 /* Basic SD framing looks ok - process each packet (header) */ 1662 1663 skb_queue_walk_safe(&bus->glom, pfirst, pnext) { 1664 dptr = (u8 *) (pfirst->data); 1665 sublen = get_unaligned_le16(dptr); 1666 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]); 1667 1668 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), 1669 dptr, pfirst->len, 1670 "Rx Subframe Data:\n"); 1671 1672 __skb_trim(pfirst, sublen); 1673 skb_pull(pfirst, doff); 1674 1675 if (pfirst->len == 0) { 1676 skb_unlink(pfirst, &bus->glom); 1677 brcmu_pkt_buf_free_skb(pfirst); 1678 continue; 1679 } 1680 1681 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1682 pfirst->data, 1683 min_t(int, pfirst->len, 32), 1684 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", 1685 bus->glom.qlen, pfirst, pfirst->data, 1686 pfirst->len, pfirst->next, 1687 pfirst->prev); 1688 skb_unlink(pfirst, &bus->glom); 1689 if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN])) 1690 brcmf_rx_event(bus->sdiodev->dev, pfirst); 1691 else 1692 brcmf_rx_frame(bus->sdiodev->dev, pfirst, 1693 false); 1694 bus->sdcnt.rxglompkts++; 1695 } 1696 1697 bus->sdcnt.rxglomframes++; 1698 } 1699 return num; 1700 } 1701 1702 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, 1703 bool *pending) 1704 { 1705 DECLARE_WAITQUEUE(wait, current); 1706 int timeout = DCMD_RESP_TIMEOUT; 1707 1708 /* Wait until control frame is available */ 1709 add_wait_queue(&bus->dcmd_resp_wait, &wait); 1710 set_current_state(TASK_INTERRUPTIBLE); 1711 1712 while (!(*condition) && (!signal_pending(current) && timeout)) 1713 timeout = schedule_timeout(timeout); 1714 1715 if (signal_pending(current)) 1716 *pending = true; 1717 1718 set_current_state(TASK_RUNNING); 1719 remove_wait_queue(&bus->dcmd_resp_wait, &wait); 1720 1721 return timeout; 1722 } 1723 1724 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus) 1725 { 1726 wake_up_interruptible(&bus->dcmd_resp_wait); 1727 1728 return 0; 1729 } 1730 static void 1731 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) 1732 { 1733 uint rdlen, pad; 1734 u8 *buf = NULL, *rbuf; 1735 int sdret; 1736 1737 brcmf_dbg(SDIO, "Enter\n"); 1738 if (bus->rxblen) 1739 buf = vzalloc(bus->rxblen); 1740 if (!buf) 1741 goto done; 1742 1743 rbuf = bus->rxbuf; 1744 pad = ((unsigned long)rbuf % bus->head_align); 1745 if (pad) 1746 rbuf += (bus->head_align - pad); 1747 1748 /* Copy the already-read portion over */ 1749 memcpy(buf, hdr, BRCMF_FIRSTREAD); 1750 if (len <= BRCMF_FIRSTREAD) 1751 goto gotpkt; 1752 1753 /* Raise rdlen to next SDIO block to avoid tail command */ 1754 rdlen = len - BRCMF_FIRSTREAD; 1755 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { 1756 pad = bus->blocksize - (rdlen % bus->blocksize); 1757 if ((pad <= bus->roundup) && (pad < bus->blocksize) && 1758 ((len + pad) < bus->sdiodev->bus_if->maxctl)) 1759 rdlen += pad; 1760 } else if (rdlen % bus->head_align) { 1761 rdlen += bus->head_align - (rdlen % bus->head_align); 1762 } 1763 1764 /* Drop if the read is too big or it exceeds our maximum */ 1765 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) { 1766 brcmf_err("%d-byte control read exceeds %d-byte buffer\n", 1767 rdlen, bus->sdiodev->bus_if->maxctl); 1768 brcmf_sdio_rxfail(bus, false, false); 1769 goto done; 1770 } 1771 1772 if ((len - doff) > bus->sdiodev->bus_if->maxctl) { 1773 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", 1774 len, len - doff, bus->sdiodev->bus_if->maxctl); 1775 bus->sdcnt.rx_toolong++; 1776 brcmf_sdio_rxfail(bus, false, false); 1777 goto done; 1778 } 1779 1780 /* Read remain of frame body */ 1781 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen); 1782 bus->sdcnt.f2rxdata++; 1783 1784 /* Control frame failures need retransmission */ 1785 if (sdret < 0) { 1786 brcmf_err("read %d control bytes failed: %d\n", 1787 rdlen, sdret); 1788 bus->sdcnt.rxc_errors++; 1789 brcmf_sdio_rxfail(bus, true, true); 1790 goto done; 1791 } else 1792 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen); 1793 1794 gotpkt: 1795 1796 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), 1797 buf, len, "RxCtrl:\n"); 1798 1799 /* Point to valid data and indicate its length */ 1800 spin_lock_bh(&bus->rxctl_lock); 1801 if (bus->rxctl) { 1802 brcmf_err("last control frame is being processed.\n"); 1803 spin_unlock_bh(&bus->rxctl_lock); 1804 vfree(buf); 1805 goto done; 1806 } 1807 bus->rxctl = buf + doff; 1808 bus->rxctl_orig = buf; 1809 bus->rxlen = len - doff; 1810 spin_unlock_bh(&bus->rxctl_lock); 1811 1812 done: 1813 /* Awake any waiters */ 1814 brcmf_sdio_dcmd_resp_wake(bus); 1815 } 1816 1817 /* Pad read to blocksize for efficiency */ 1818 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) 1819 { 1820 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { 1821 *pad = bus->blocksize - (*rdlen % bus->blocksize); 1822 if (*pad <= bus->roundup && *pad < bus->blocksize && 1823 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) 1824 *rdlen += *pad; 1825 } else if (*rdlen % bus->head_align) { 1826 *rdlen += bus->head_align - (*rdlen % bus->head_align); 1827 } 1828 } 1829 1830 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes) 1831 { 1832 struct sk_buff *pkt; /* Packet for event or data frames */ 1833 u16 pad; /* Number of pad bytes to read */ 1834 uint rxleft = 0; /* Remaining number of frames allowed */ 1835 int ret; /* Return code from calls */ 1836 uint rxcount = 0; /* Total frames read */ 1837 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new; 1838 u8 head_read = 0; 1839 1840 brcmf_dbg(SDIO, "Enter\n"); 1841 1842 /* Not finished unless we encounter no more frames indication */ 1843 bus->rxpending = true; 1844 1845 for (rd->seq_num = bus->rx_seq, rxleft = maxframes; 1846 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA; 1847 rd->seq_num++, rxleft--) { 1848 1849 /* Handle glomming separately */ 1850 if (bus->glomd || !skb_queue_empty(&bus->glom)) { 1851 u8 cnt; 1852 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", 1853 bus->glomd, skb_peek(&bus->glom)); 1854 cnt = brcmf_sdio_rxglom(bus, rd->seq_num); 1855 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); 1856 rd->seq_num += cnt - 1; 1857 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; 1858 continue; 1859 } 1860 1861 rd->len_left = rd->len; 1862 /* read header first for unknow frame length */ 1863 sdio_claim_host(bus->sdiodev->func1); 1864 if (!rd->len) { 1865 ret = brcmf_sdiod_recv_buf(bus->sdiodev, 1866 bus->rxhdr, BRCMF_FIRSTREAD); 1867 bus->sdcnt.f2rxhdrs++; 1868 if (ret < 0) { 1869 brcmf_err("RXHEADER FAILED: %d\n", 1870 ret); 1871 bus->sdcnt.rx_hdrfail++; 1872 brcmf_sdio_rxfail(bus, true, true); 1873 sdio_release_host(bus->sdiodev->func1); 1874 continue; 1875 } 1876 1877 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(), 1878 bus->rxhdr, SDPCM_HDRLEN, 1879 "RxHdr:\n"); 1880 1881 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd, 1882 BRCMF_SDIO_FT_NORMAL)) { 1883 sdio_release_host(bus->sdiodev->func1); 1884 if (!bus->rxpending) 1885 break; 1886 else 1887 continue; 1888 } 1889 1890 if (rd->channel == SDPCM_CONTROL_CHANNEL) { 1891 brcmf_sdio_read_control(bus, bus->rxhdr, 1892 rd->len, 1893 rd->dat_offset); 1894 /* prepare the descriptor for the next read */ 1895 rd->len = rd->len_nxtfrm << 4; 1896 rd->len_nxtfrm = 0; 1897 /* treat all packet as event if we don't know */ 1898 rd->channel = SDPCM_EVENT_CHANNEL; 1899 sdio_release_host(bus->sdiodev->func1); 1900 continue; 1901 } 1902 rd->len_left = rd->len > BRCMF_FIRSTREAD ? 1903 rd->len - BRCMF_FIRSTREAD : 0; 1904 head_read = BRCMF_FIRSTREAD; 1905 } 1906 1907 brcmf_sdio_pad(bus, &pad, &rd->len_left); 1908 1909 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read + 1910 bus->head_align); 1911 if (!pkt) { 1912 /* Give up on data, request rtx of events */ 1913 brcmf_err("brcmu_pkt_buf_get_skb failed\n"); 1914 brcmf_sdio_rxfail(bus, false, 1915 RETRYCHAN(rd->channel)); 1916 sdio_release_host(bus->sdiodev->func1); 1917 continue; 1918 } 1919 skb_pull(pkt, head_read); 1920 pkt_align(pkt, rd->len_left, bus->head_align); 1921 1922 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt); 1923 bus->sdcnt.f2rxdata++; 1924 sdio_release_host(bus->sdiodev->func1); 1925 1926 if (ret < 0) { 1927 brcmf_err("read %d bytes from channel %d failed: %d\n", 1928 rd->len, rd->channel, ret); 1929 brcmu_pkt_buf_free_skb(pkt); 1930 sdio_claim_host(bus->sdiodev->func1); 1931 brcmf_sdio_rxfail(bus, true, 1932 RETRYCHAN(rd->channel)); 1933 sdio_release_host(bus->sdiodev->func1); 1934 continue; 1935 } 1936 1937 if (head_read) { 1938 skb_push(pkt, head_read); 1939 memcpy(pkt->data, bus->rxhdr, head_read); 1940 head_read = 0; 1941 } else { 1942 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN); 1943 rd_new.seq_num = rd->seq_num; 1944 sdio_claim_host(bus->sdiodev->func1); 1945 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new, 1946 BRCMF_SDIO_FT_NORMAL)) { 1947 rd->len = 0; 1948 brcmu_pkt_buf_free_skb(pkt); 1949 } 1950 bus->sdcnt.rx_readahead_cnt++; 1951 if (rd->len != roundup(rd_new.len, 16)) { 1952 brcmf_err("frame length mismatch:read %d, should be %d\n", 1953 rd->len, 1954 roundup(rd_new.len, 16) >> 4); 1955 rd->len = 0; 1956 brcmf_sdio_rxfail(bus, true, true); 1957 sdio_release_host(bus->sdiodev->func1); 1958 brcmu_pkt_buf_free_skb(pkt); 1959 continue; 1960 } 1961 sdio_release_host(bus->sdiodev->func1); 1962 rd->len_nxtfrm = rd_new.len_nxtfrm; 1963 rd->channel = rd_new.channel; 1964 rd->dat_offset = rd_new.dat_offset; 1965 1966 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && 1967 BRCMF_DATA_ON()) && 1968 BRCMF_HDRS_ON(), 1969 bus->rxhdr, SDPCM_HDRLEN, 1970 "RxHdr:\n"); 1971 1972 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) { 1973 brcmf_err("readahead on control packet %d?\n", 1974 rd_new.seq_num); 1975 /* Force retry w/normal header read */ 1976 rd->len = 0; 1977 sdio_claim_host(bus->sdiodev->func1); 1978 brcmf_sdio_rxfail(bus, false, true); 1979 sdio_release_host(bus->sdiodev->func1); 1980 brcmu_pkt_buf_free_skb(pkt); 1981 continue; 1982 } 1983 } 1984 1985 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), 1986 pkt->data, rd->len, "Rx Data:\n"); 1987 1988 /* Save superframe descriptor and allocate packet frame */ 1989 if (rd->channel == SDPCM_GLOM_CHANNEL) { 1990 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) { 1991 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", 1992 rd->len); 1993 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1994 pkt->data, rd->len, 1995 "Glom Data:\n"); 1996 __skb_trim(pkt, rd->len); 1997 skb_pull(pkt, SDPCM_HDRLEN); 1998 bus->glomd = pkt; 1999 } else { 2000 brcmf_err("%s: glom superframe w/o " 2001 "descriptor!\n", __func__); 2002 sdio_claim_host(bus->sdiodev->func1); 2003 brcmf_sdio_rxfail(bus, false, false); 2004 sdio_release_host(bus->sdiodev->func1); 2005 } 2006 /* prepare the descriptor for the next read */ 2007 rd->len = rd->len_nxtfrm << 4; 2008 rd->len_nxtfrm = 0; 2009 /* treat all packet as event if we don't know */ 2010 rd->channel = SDPCM_EVENT_CHANNEL; 2011 continue; 2012 } 2013 2014 /* Fill in packet len and prio, deliver upward */ 2015 __skb_trim(pkt, rd->len); 2016 skb_pull(pkt, rd->dat_offset); 2017 2018 if (pkt->len == 0) 2019 brcmu_pkt_buf_free_skb(pkt); 2020 else if (rd->channel == SDPCM_EVENT_CHANNEL) 2021 brcmf_rx_event(bus->sdiodev->dev, pkt); 2022 else 2023 brcmf_rx_frame(bus->sdiodev->dev, pkt, 2024 false); 2025 2026 /* prepare the descriptor for the next read */ 2027 rd->len = rd->len_nxtfrm << 4; 2028 rd->len_nxtfrm = 0; 2029 /* treat all packet as event if we don't know */ 2030 rd->channel = SDPCM_EVENT_CHANNEL; 2031 } 2032 2033 rxcount = maxframes - rxleft; 2034 /* Message if we hit the limit */ 2035 if (!rxleft) 2036 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes); 2037 else 2038 brcmf_dbg(DATA, "processed %d frames\n", rxcount); 2039 /* Back off rxseq if awaiting rtx, update rx_seq */ 2040 if (bus->rxskip) 2041 rd->seq_num--; 2042 bus->rx_seq = rd->seq_num; 2043 2044 return rxcount; 2045 } 2046 2047 static void 2048 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus) 2049 { 2050 wake_up_interruptible(&bus->ctrl_wait); 2051 return; 2052 } 2053 2054 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt) 2055 { 2056 struct brcmf_bus_stats *stats; 2057 u16 head_pad; 2058 u8 *dat_buf; 2059 2060 dat_buf = (u8 *)(pkt->data); 2061 2062 /* Check head padding */ 2063 head_pad = ((unsigned long)dat_buf % bus->head_align); 2064 if (head_pad) { 2065 if (skb_headroom(pkt) < head_pad) { 2066 stats = &bus->sdiodev->bus_if->stats; 2067 atomic_inc(&stats->pktcowed); 2068 if (skb_cow_head(pkt, head_pad)) { 2069 atomic_inc(&stats->pktcow_failed); 2070 return -ENOMEM; 2071 } 2072 head_pad = 0; 2073 } 2074 skb_push(pkt, head_pad); 2075 dat_buf = (u8 *)(pkt->data); 2076 } 2077 memset(dat_buf, 0, head_pad + bus->tx_hdrlen); 2078 return head_pad; 2079 } 2080 2081 /* 2082 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for 2083 * bus layer usage. 2084 */ 2085 /* flag marking a dummy skb added for DMA alignment requirement */ 2086 #define ALIGN_SKB_FLAG 0x8000 2087 /* bit mask of data length chopped from the previous packet */ 2088 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff 2089 2090 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus, 2091 struct sk_buff_head *pktq, 2092 struct sk_buff *pkt, u16 total_len) 2093 { 2094 struct brcmf_sdio_dev *sdiodev; 2095 struct sk_buff *pkt_pad; 2096 u16 tail_pad, tail_chop, chain_pad; 2097 unsigned int blksize; 2098 bool lastfrm; 2099 int ntail, ret; 2100 2101 sdiodev = bus->sdiodev; 2102 blksize = sdiodev->func2->cur_blksize; 2103 /* sg entry alignment should be a divisor of block size */ 2104 WARN_ON(blksize % bus->sgentry_align); 2105 2106 /* Check tail padding */ 2107 lastfrm = skb_queue_is_last(pktq, pkt); 2108 tail_pad = 0; 2109 tail_chop = pkt->len % bus->sgentry_align; 2110 if (tail_chop) 2111 tail_pad = bus->sgentry_align - tail_chop; 2112 chain_pad = (total_len + tail_pad) % blksize; 2113 if (lastfrm && chain_pad) 2114 tail_pad += blksize - chain_pad; 2115 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) { 2116 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop + 2117 bus->head_align); 2118 if (pkt_pad == NULL) 2119 return -ENOMEM; 2120 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad); 2121 if (unlikely(ret < 0)) { 2122 kfree_skb(pkt_pad); 2123 return ret; 2124 } 2125 memcpy(pkt_pad->data, 2126 pkt->data + pkt->len - tail_chop, 2127 tail_chop); 2128 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop; 2129 skb_trim(pkt, pkt->len - tail_chop); 2130 skb_trim(pkt_pad, tail_pad + tail_chop); 2131 __skb_queue_after(pktq, pkt, pkt_pad); 2132 } else { 2133 ntail = pkt->data_len + tail_pad - 2134 (pkt->end - pkt->tail); 2135 if (skb_cloned(pkt) || ntail > 0) 2136 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC)) 2137 return -ENOMEM; 2138 if (skb_linearize(pkt)) 2139 return -ENOMEM; 2140 __skb_put(pkt, tail_pad); 2141 } 2142 2143 return tail_pad; 2144 } 2145 2146 /** 2147 * brcmf_sdio_txpkt_prep - packet preparation for transmit 2148 * @bus: brcmf_sdio structure pointer 2149 * @pktq: packet list pointer 2150 * @chan: virtual channel to transmit the packet 2151 * 2152 * Processes to be applied to the packet 2153 * - Align data buffer pointer 2154 * - Align data buffer length 2155 * - Prepare header 2156 * Return: negative value if there is error 2157 */ 2158 static int 2159 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq, 2160 uint chan) 2161 { 2162 u16 head_pad, total_len; 2163 struct sk_buff *pkt_next; 2164 u8 txseq; 2165 int ret; 2166 struct brcmf_sdio_hdrinfo hd_info = {0}; 2167 2168 txseq = bus->tx_seq; 2169 total_len = 0; 2170 skb_queue_walk(pktq, pkt_next) { 2171 /* alignment packet inserted in previous 2172 * loop cycle can be skipped as it is 2173 * already properly aligned and does not 2174 * need an sdpcm header. 2175 */ 2176 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG) 2177 continue; 2178 2179 /* align packet data pointer */ 2180 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next); 2181 if (ret < 0) 2182 return ret; 2183 head_pad = (u16)ret; 2184 if (head_pad) 2185 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad); 2186 2187 total_len += pkt_next->len; 2188 2189 hd_info.len = pkt_next->len; 2190 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next); 2191 if (bus->txglom && pktq->qlen > 1) { 2192 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq, 2193 pkt_next, total_len); 2194 if (ret < 0) 2195 return ret; 2196 hd_info.tail_pad = (u16)ret; 2197 total_len += (u16)ret; 2198 } 2199 2200 hd_info.channel = chan; 2201 hd_info.dat_offset = head_pad + bus->tx_hdrlen; 2202 hd_info.seq_num = txseq++; 2203 2204 /* Now fill the header */ 2205 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info); 2206 2207 if (BRCMF_BYTES_ON() && 2208 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) || 2209 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL))) 2210 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len, 2211 "Tx Frame:\n"); 2212 else if (BRCMF_HDRS_ON()) 2213 brcmf_dbg_hex_dump(true, pkt_next->data, 2214 head_pad + bus->tx_hdrlen, 2215 "Tx Header:\n"); 2216 } 2217 /* Hardware length tag of the first packet should be total 2218 * length of the chain (including padding) 2219 */ 2220 if (bus->txglom) 2221 brcmf_sdio_update_hwhdr(__skb_peek(pktq)->data, total_len); 2222 return 0; 2223 } 2224 2225 /** 2226 * brcmf_sdio_txpkt_postp - packet post processing for transmit 2227 * @bus: brcmf_sdio structure pointer 2228 * @pktq: packet list pointer 2229 * 2230 * Processes to be applied to the packet 2231 * - Remove head padding 2232 * - Remove tail padding 2233 */ 2234 static void 2235 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq) 2236 { 2237 u8 *hdr; 2238 u32 dat_offset; 2239 u16 tail_pad; 2240 u16 dummy_flags, chop_len; 2241 struct sk_buff *pkt_next, *tmp, *pkt_prev; 2242 2243 skb_queue_walk_safe(pktq, pkt_next, tmp) { 2244 dummy_flags = *(u16 *)(pkt_next->cb); 2245 if (dummy_flags & ALIGN_SKB_FLAG) { 2246 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK; 2247 if (chop_len) { 2248 pkt_prev = pkt_next->prev; 2249 skb_put(pkt_prev, chop_len); 2250 } 2251 __skb_unlink(pkt_next, pktq); 2252 brcmu_pkt_buf_free_skb(pkt_next); 2253 } else { 2254 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN; 2255 dat_offset = le32_to_cpu(*(__le32 *)hdr); 2256 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >> 2257 SDPCM_DOFFSET_SHIFT; 2258 skb_pull(pkt_next, dat_offset); 2259 if (bus->txglom) { 2260 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2)); 2261 skb_trim(pkt_next, pkt_next->len - tail_pad); 2262 } 2263 } 2264 } 2265 } 2266 2267 /* Writes a HW/SW header into the packet and sends it. */ 2268 /* Assumes: (a) header space already there, (b) caller holds lock */ 2269 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq, 2270 uint chan) 2271 { 2272 int ret; 2273 struct sk_buff *pkt_next, *tmp; 2274 2275 brcmf_dbg(TRACE, "Enter\n"); 2276 2277 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan); 2278 if (ret) 2279 goto done; 2280 2281 sdio_claim_host(bus->sdiodev->func1); 2282 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq); 2283 bus->sdcnt.f2txdata++; 2284 2285 if (ret < 0) 2286 brcmf_sdio_txfail(bus); 2287 2288 sdio_release_host(bus->sdiodev->func1); 2289 2290 done: 2291 brcmf_sdio_txpkt_postp(bus, pktq); 2292 if (ret == 0) 2293 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP; 2294 skb_queue_walk_safe(pktq, pkt_next, tmp) { 2295 __skb_unlink(pkt_next, pktq); 2296 brcmf_proto_bcdc_txcomplete(bus->sdiodev->dev, pkt_next, 2297 ret == 0); 2298 } 2299 return ret; 2300 } 2301 2302 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes) 2303 { 2304 struct sk_buff *pkt; 2305 struct sk_buff_head pktq; 2306 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus); 2307 u32 intstatus = 0; 2308 int ret = 0, prec_out, i; 2309 uint cnt = 0; 2310 u8 tx_prec_map, pkt_num; 2311 2312 brcmf_dbg(TRACE, "Enter\n"); 2313 2314 tx_prec_map = ~bus->flowcontrol; 2315 2316 /* Send frames until the limit or some other event */ 2317 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) { 2318 pkt_num = 1; 2319 if (bus->txglom) 2320 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq, 2321 bus->sdiodev->txglomsz); 2322 pkt_num = min_t(u32, pkt_num, 2323 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)); 2324 __skb_queue_head_init(&pktq); 2325 spin_lock_bh(&bus->txq_lock); 2326 for (i = 0; i < pkt_num; i++) { 2327 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, 2328 &prec_out); 2329 if (pkt == NULL) 2330 break; 2331 __skb_queue_tail(&pktq, pkt); 2332 } 2333 spin_unlock_bh(&bus->txq_lock); 2334 if (i == 0) 2335 break; 2336 2337 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL); 2338 2339 cnt += i; 2340 2341 /* In poll mode, need to check for other events */ 2342 if (!bus->intr) { 2343 /* Check device status, signal pending interrupt */ 2344 sdio_claim_host(bus->sdiodev->func1); 2345 intstatus = brcmf_sdiod_readl(bus->sdiodev, 2346 intstat_addr, &ret); 2347 sdio_release_host(bus->sdiodev->func1); 2348 2349 bus->sdcnt.f2txdata++; 2350 if (ret != 0) 2351 break; 2352 if (intstatus & bus->hostintmask) 2353 atomic_set(&bus->ipend, 1); 2354 } 2355 } 2356 2357 /* Deflow-control stack if needed */ 2358 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) && 2359 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) { 2360 bus->txoff = false; 2361 brcmf_proto_bcdc_txflowblock(bus->sdiodev->dev, false); 2362 } 2363 2364 return cnt; 2365 } 2366 2367 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len) 2368 { 2369 u8 doff; 2370 u16 pad; 2371 uint retries = 0; 2372 struct brcmf_sdio_hdrinfo hd_info = {0}; 2373 int ret; 2374 2375 brcmf_dbg(SDIO, "Enter\n"); 2376 2377 /* Back the pointer to make room for bus header */ 2378 frame -= bus->tx_hdrlen; 2379 len += bus->tx_hdrlen; 2380 2381 /* Add alignment padding (optional for ctl frames) */ 2382 doff = ((unsigned long)frame % bus->head_align); 2383 if (doff) { 2384 frame -= doff; 2385 len += doff; 2386 memset(frame + bus->tx_hdrlen, 0, doff); 2387 } 2388 2389 /* Round send length to next SDIO block */ 2390 pad = 0; 2391 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { 2392 pad = bus->blocksize - (len % bus->blocksize); 2393 if ((pad > bus->roundup) || (pad >= bus->blocksize)) 2394 pad = 0; 2395 } else if (len % bus->head_align) { 2396 pad = bus->head_align - (len % bus->head_align); 2397 } 2398 len += pad; 2399 2400 hd_info.len = len - pad; 2401 hd_info.channel = SDPCM_CONTROL_CHANNEL; 2402 hd_info.dat_offset = doff + bus->tx_hdrlen; 2403 hd_info.seq_num = bus->tx_seq; 2404 hd_info.lastfrm = true; 2405 hd_info.tail_pad = pad; 2406 brcmf_sdio_hdpack(bus, frame, &hd_info); 2407 2408 if (bus->txglom) 2409 brcmf_sdio_update_hwhdr(frame, len); 2410 2411 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), 2412 frame, len, "Tx Frame:\n"); 2413 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) && 2414 BRCMF_HDRS_ON(), 2415 frame, min_t(u16, len, 16), "TxHdr:\n"); 2416 2417 do { 2418 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len); 2419 2420 if (ret < 0) 2421 brcmf_sdio_txfail(bus); 2422 else 2423 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; 2424 } while (ret < 0 && retries++ < TXRETRIES); 2425 2426 return ret; 2427 } 2428 2429 static bool brcmf_chip_is_ulp(struct brcmf_chip *ci) 2430 { 2431 if (ci->chip == CY_CC_43012_CHIP_ID) 2432 return true; 2433 else 2434 return false; 2435 } 2436 2437 static void brcmf_sdio_bus_stop(struct device *dev) 2438 { 2439 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2440 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2441 struct brcmf_sdio *bus = sdiodev->bus; 2442 struct brcmf_core *core = bus->sdio_core; 2443 u32 local_hostintmask; 2444 u8 saveclk, bpreq; 2445 int err; 2446 2447 brcmf_dbg(TRACE, "Enter\n"); 2448 2449 if (bus->watchdog_tsk) { 2450 send_sig(SIGTERM, bus->watchdog_tsk, 1); 2451 kthread_stop(bus->watchdog_tsk); 2452 bus->watchdog_tsk = NULL; 2453 } 2454 2455 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { 2456 sdio_claim_host(sdiodev->func1); 2457 2458 /* Enable clock for device interrupts */ 2459 brcmf_sdio_bus_sleep(bus, false, false); 2460 2461 /* Disable and clear interrupts at the chip level also */ 2462 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(hostintmask), 2463 0, NULL); 2464 2465 local_hostintmask = bus->hostintmask; 2466 bus->hostintmask = 0; 2467 2468 /* Force backplane clocks to assure F2 interrupt propagates */ 2469 saveclk = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 2470 &err); 2471 if (!err) { 2472 bpreq = saveclk; 2473 bpreq |= brcmf_chip_is_ulp(bus->ci) ? 2474 SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT; 2475 brcmf_sdiod_writeb(sdiodev, 2476 SBSDIO_FUNC1_CHIPCLKCSR, 2477 bpreq, &err); 2478 } 2479 if (err) 2480 brcmf_err("Failed to force clock for F2: err %d\n", 2481 err); 2482 2483 /* Turn off the bus (F2), free any pending packets */ 2484 brcmf_dbg(INTR, "disable SDIO interrupts\n"); 2485 sdio_disable_func(sdiodev->func2); 2486 2487 /* Clear any pending interrupts now that F2 is disabled */ 2488 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(intstatus), 2489 local_hostintmask, NULL); 2490 2491 sdio_release_host(sdiodev->func1); 2492 } 2493 /* Clear the data packet queues */ 2494 brcmu_pktq_flush(&bus->txq, true, NULL, NULL); 2495 2496 /* Clear any held glomming stuff */ 2497 brcmu_pkt_buf_free_skb(bus->glomd); 2498 brcmf_sdio_free_glom(bus); 2499 2500 /* Clear rx control and wake any waiters */ 2501 spin_lock_bh(&bus->rxctl_lock); 2502 bus->rxlen = 0; 2503 spin_unlock_bh(&bus->rxctl_lock); 2504 brcmf_sdio_dcmd_resp_wake(bus); 2505 2506 /* Reset some F2 state stuff */ 2507 bus->rxskip = false; 2508 bus->tx_seq = bus->rx_seq = 0; 2509 } 2510 2511 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus) 2512 { 2513 struct brcmf_sdio_dev *sdiodev; 2514 unsigned long flags; 2515 2516 sdiodev = bus->sdiodev; 2517 if (sdiodev->oob_irq_requested) { 2518 spin_lock_irqsave(&sdiodev->irq_en_lock, flags); 2519 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) { 2520 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr); 2521 sdiodev->irq_en = true; 2522 } 2523 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags); 2524 } 2525 } 2526 2527 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus) 2528 { 2529 struct brcmf_core *core = bus->sdio_core; 2530 u32 addr; 2531 unsigned long val; 2532 int ret; 2533 2534 addr = core->base + SD_REG(intstatus); 2535 2536 val = brcmf_sdiod_readl(bus->sdiodev, addr, &ret); 2537 bus->sdcnt.f1regdata++; 2538 if (ret != 0) 2539 return ret; 2540 2541 val &= bus->hostintmask; 2542 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE)); 2543 2544 /* Clear interrupts */ 2545 if (val) { 2546 brcmf_sdiod_writel(bus->sdiodev, addr, val, &ret); 2547 bus->sdcnt.f1regdata++; 2548 atomic_or(val, &bus->intstatus); 2549 } 2550 2551 return ret; 2552 } 2553 2554 static void brcmf_sdio_dpc(struct brcmf_sdio *bus) 2555 { 2556 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 2557 u32 newstatus = 0; 2558 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus); 2559 unsigned long intstatus; 2560 uint txlimit = bus->txbound; /* Tx frames to send before resched */ 2561 uint framecnt; /* Temporary counter of tx/rx frames */ 2562 int err = 0; 2563 2564 brcmf_dbg(SDIO, "Enter\n"); 2565 2566 sdio_claim_host(bus->sdiodev->func1); 2567 2568 /* If waiting for HTAVAIL, check status */ 2569 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) { 2570 u8 clkctl, devctl = 0; 2571 2572 #ifdef DEBUG 2573 /* Check for inconsistent device control */ 2574 devctl = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_DEVICE_CTL, 2575 &err); 2576 #endif /* DEBUG */ 2577 2578 /* Read CSR, if clock on switch to AVAIL, else ignore */ 2579 clkctl = brcmf_sdiod_readb(bus->sdiodev, 2580 SBSDIO_FUNC1_CHIPCLKCSR, &err); 2581 2582 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", 2583 devctl, clkctl); 2584 2585 if (SBSDIO_HTAV(clkctl)) { 2586 devctl = brcmf_sdiod_readb(bus->sdiodev, 2587 SBSDIO_DEVICE_CTL, &err); 2588 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 2589 brcmf_sdiod_writeb(bus->sdiodev, 2590 SBSDIO_DEVICE_CTL, devctl, &err); 2591 bus->clkstate = CLK_AVAIL; 2592 } 2593 } 2594 2595 /* Make sure backplane clock is on */ 2596 brcmf_sdio_bus_sleep(bus, false, true); 2597 2598 /* Pending interrupt indicates new device status */ 2599 if (atomic_read(&bus->ipend) > 0) { 2600 atomic_set(&bus->ipend, 0); 2601 err = brcmf_sdio_intr_rstatus(bus); 2602 } 2603 2604 /* Start with leftover status bits */ 2605 intstatus = atomic_xchg(&bus->intstatus, 0); 2606 2607 /* Handle flow-control change: read new state in case our ack 2608 * crossed another change interrupt. If change still set, assume 2609 * FC ON for safety, let next loop through do the debounce. 2610 */ 2611 if (intstatus & I_HMB_FC_CHANGE) { 2612 intstatus &= ~I_HMB_FC_CHANGE; 2613 brcmf_sdiod_writel(sdiod, intstat_addr, I_HMB_FC_CHANGE, &err); 2614 2615 newstatus = brcmf_sdiod_readl(sdiod, intstat_addr, &err); 2616 2617 bus->sdcnt.f1regdata += 2; 2618 atomic_set(&bus->fcstate, 2619 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE))); 2620 intstatus |= (newstatus & bus->hostintmask); 2621 } 2622 2623 /* Handle host mailbox indication */ 2624 if (intstatus & I_HMB_HOST_INT) { 2625 intstatus &= ~I_HMB_HOST_INT; 2626 intstatus |= brcmf_sdio_hostmail(bus); 2627 } 2628 2629 sdio_release_host(bus->sdiodev->func1); 2630 2631 /* Generally don't ask for these, can get CRC errors... */ 2632 if (intstatus & I_WR_OOSYNC) { 2633 brcmf_err("Dongle reports WR_OOSYNC\n"); 2634 intstatus &= ~I_WR_OOSYNC; 2635 } 2636 2637 if (intstatus & I_RD_OOSYNC) { 2638 brcmf_err("Dongle reports RD_OOSYNC\n"); 2639 intstatus &= ~I_RD_OOSYNC; 2640 } 2641 2642 if (intstatus & I_SBINT) { 2643 brcmf_err("Dongle reports SBINT\n"); 2644 intstatus &= ~I_SBINT; 2645 } 2646 2647 /* Would be active due to wake-wlan in gSPI */ 2648 if (intstatus & I_CHIPACTIVE) { 2649 brcmf_dbg(SDIO, "Dongle reports CHIPACTIVE\n"); 2650 intstatus &= ~I_CHIPACTIVE; 2651 } 2652 2653 /* Ignore frame indications if rxskip is set */ 2654 if (bus->rxskip) 2655 intstatus &= ~I_HMB_FRAME_IND; 2656 2657 /* On frame indication, read available frames */ 2658 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) { 2659 brcmf_sdio_readframes(bus, bus->rxbound); 2660 if (!bus->rxpending) 2661 intstatus &= ~I_HMB_FRAME_IND; 2662 } 2663 2664 /* Keep still-pending events for next scheduling */ 2665 if (intstatus) 2666 atomic_or(intstatus, &bus->intstatus); 2667 2668 brcmf_sdio_clrintr(bus); 2669 2670 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) && 2671 data_ok(bus)) { 2672 sdio_claim_host(bus->sdiodev->func1); 2673 if (bus->ctrl_frame_stat) { 2674 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf, 2675 bus->ctrl_frame_len); 2676 bus->ctrl_frame_err = err; 2677 wmb(); 2678 bus->ctrl_frame_stat = false; 2679 } 2680 sdio_release_host(bus->sdiodev->func1); 2681 brcmf_sdio_wait_event_wakeup(bus); 2682 } 2683 /* Send queued frames (limit 1 if rx may still be pending) */ 2684 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) && 2685 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && 2686 data_ok(bus)) { 2687 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) : 2688 txlimit; 2689 brcmf_sdio_sendfromq(bus, framecnt); 2690 } 2691 2692 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) { 2693 brcmf_err("failed backplane access over SDIO, halting operation\n"); 2694 atomic_set(&bus->intstatus, 0); 2695 if (bus->ctrl_frame_stat) { 2696 sdio_claim_host(bus->sdiodev->func1); 2697 if (bus->ctrl_frame_stat) { 2698 bus->ctrl_frame_err = -ENODEV; 2699 wmb(); 2700 bus->ctrl_frame_stat = false; 2701 brcmf_sdio_wait_event_wakeup(bus); 2702 } 2703 sdio_release_host(bus->sdiodev->func1); 2704 } 2705 } else if (atomic_read(&bus->intstatus) || 2706 atomic_read(&bus->ipend) > 0 || 2707 (!atomic_read(&bus->fcstate) && 2708 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && 2709 data_ok(bus))) { 2710 bus->dpc_triggered = true; 2711 } 2712 } 2713 2714 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev) 2715 { 2716 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2717 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2718 struct brcmf_sdio *bus = sdiodev->bus; 2719 2720 return &bus->txq; 2721 } 2722 2723 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec) 2724 { 2725 struct sk_buff *p; 2726 int eprec = -1; /* precedence to evict from */ 2727 2728 /* Fast case, precedence queue is not full and we are also not 2729 * exceeding total queue length 2730 */ 2731 if (!pktq_pfull(q, prec) && !pktq_full(q)) { 2732 brcmu_pktq_penq(q, prec, pkt); 2733 return true; 2734 } 2735 2736 /* Determine precedence from which to evict packet, if any */ 2737 if (pktq_pfull(q, prec)) { 2738 eprec = prec; 2739 } else if (pktq_full(q)) { 2740 p = brcmu_pktq_peek_tail(q, &eprec); 2741 if (eprec > prec) 2742 return false; 2743 } 2744 2745 /* Evict if needed */ 2746 if (eprec >= 0) { 2747 /* Detect queueing to unconfigured precedence */ 2748 if (eprec == prec) 2749 return false; /* refuse newer (incoming) packet */ 2750 /* Evict packet according to discard policy */ 2751 p = brcmu_pktq_pdeq_tail(q, eprec); 2752 if (p == NULL) 2753 brcmf_err("brcmu_pktq_pdeq_tail() failed\n"); 2754 brcmu_pkt_buf_free_skb(p); 2755 } 2756 2757 /* Enqueue */ 2758 p = brcmu_pktq_penq(q, prec, pkt); 2759 if (p == NULL) 2760 brcmf_err("brcmu_pktq_penq() failed\n"); 2761 2762 return p != NULL; 2763 } 2764 2765 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt) 2766 { 2767 int ret = -EBADE; 2768 uint prec; 2769 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2770 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2771 struct brcmf_sdio *bus = sdiodev->bus; 2772 2773 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len); 2774 if (sdiodev->state != BRCMF_SDIOD_DATA) 2775 return -EIO; 2776 2777 /* Add space for the header */ 2778 skb_push(pkt, bus->tx_hdrlen); 2779 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ 2780 2781 prec = prio2prec((pkt->priority & PRIOMASK)); 2782 2783 /* Check for existing queue, current flow-control, 2784 pending event, or pending clock */ 2785 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); 2786 bus->sdcnt.fcqueued++; 2787 2788 /* Priority based enq */ 2789 spin_lock_bh(&bus->txq_lock); 2790 /* reset bus_flags in packet cb */ 2791 *(u16 *)(pkt->cb) = 0; 2792 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) { 2793 skb_pull(pkt, bus->tx_hdrlen); 2794 brcmf_err("out of bus->txq !!!\n"); 2795 ret = -ENOSR; 2796 } else { 2797 ret = 0; 2798 } 2799 2800 if (pktq_len(&bus->txq) >= TXHI) { 2801 bus->txoff = true; 2802 brcmf_proto_bcdc_txflowblock(dev, true); 2803 } 2804 spin_unlock_bh(&bus->txq_lock); 2805 2806 #ifdef DEBUG 2807 if (pktq_plen(&bus->txq, prec) > qcount[prec]) 2808 qcount[prec] = pktq_plen(&bus->txq, prec); 2809 #endif 2810 2811 brcmf_sdio_trigger_dpc(bus); 2812 return ret; 2813 } 2814 2815 #ifdef DEBUG 2816 #define CONSOLE_LINE_MAX 192 2817 2818 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus) 2819 { 2820 struct brcmf_console *c = &bus->console; 2821 u8 line[CONSOLE_LINE_MAX], ch; 2822 u32 n, idx, addr; 2823 int rv; 2824 2825 /* Don't do anything until FWREADY updates console address */ 2826 if (bus->console_addr == 0) 2827 return 0; 2828 2829 /* Read console log struct */ 2830 addr = bus->console_addr + offsetof(struct rte_console, log_le); 2831 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le, 2832 sizeof(c->log_le)); 2833 if (rv < 0) 2834 return rv; 2835 2836 /* Allocate console buffer (one time only) */ 2837 if (c->buf == NULL) { 2838 c->bufsize = le32_to_cpu(c->log_le.buf_size); 2839 c->buf = kmalloc(c->bufsize, GFP_ATOMIC); 2840 if (c->buf == NULL) 2841 return -ENOMEM; 2842 } 2843 2844 idx = le32_to_cpu(c->log_le.idx); 2845 2846 /* Protect against corrupt value */ 2847 if (idx > c->bufsize) 2848 return -EBADE; 2849 2850 /* Skip reading the console buffer if the index pointer 2851 has not moved */ 2852 if (idx == c->last) 2853 return 0; 2854 2855 /* Read the console buffer */ 2856 addr = le32_to_cpu(c->log_le.buf); 2857 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize); 2858 if (rv < 0) 2859 return rv; 2860 2861 while (c->last != idx) { 2862 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { 2863 if (c->last == idx) { 2864 /* This would output a partial line. 2865 * Instead, back up 2866 * the buffer pointer and output this 2867 * line next time around. 2868 */ 2869 if (c->last >= n) 2870 c->last -= n; 2871 else 2872 c->last = c->bufsize - n; 2873 goto break2; 2874 } 2875 ch = c->buf[c->last]; 2876 c->last = (c->last + 1) % c->bufsize; 2877 if (ch == '\n') 2878 break; 2879 line[n] = ch; 2880 } 2881 2882 if (n > 0) { 2883 if (line[n - 1] == '\r') 2884 n--; 2885 line[n] = 0; 2886 pr_debug("CONSOLE: %s\n", line); 2887 } 2888 } 2889 break2: 2890 2891 return 0; 2892 } 2893 #endif /* DEBUG */ 2894 2895 static int 2896 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) 2897 { 2898 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2899 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2900 struct brcmf_sdio *bus = sdiodev->bus; 2901 int ret; 2902 2903 brcmf_dbg(TRACE, "Enter\n"); 2904 if (sdiodev->state != BRCMF_SDIOD_DATA) 2905 return -EIO; 2906 2907 /* Send from dpc */ 2908 bus->ctrl_frame_buf = msg; 2909 bus->ctrl_frame_len = msglen; 2910 wmb(); 2911 bus->ctrl_frame_stat = true; 2912 2913 brcmf_sdio_trigger_dpc(bus); 2914 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat, 2915 CTL_DONE_TIMEOUT); 2916 ret = 0; 2917 if (bus->ctrl_frame_stat) { 2918 sdio_claim_host(bus->sdiodev->func1); 2919 if (bus->ctrl_frame_stat) { 2920 brcmf_dbg(SDIO, "ctrl_frame timeout\n"); 2921 bus->ctrl_frame_stat = false; 2922 ret = -ETIMEDOUT; 2923 } 2924 sdio_release_host(bus->sdiodev->func1); 2925 } 2926 if (!ret) { 2927 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n", 2928 bus->ctrl_frame_err); 2929 rmb(); 2930 ret = bus->ctrl_frame_err; 2931 } 2932 2933 if (ret) 2934 bus->sdcnt.tx_ctlerrs++; 2935 else 2936 bus->sdcnt.tx_ctlpkts++; 2937 2938 return ret; 2939 } 2940 2941 #ifdef DEBUG 2942 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus, 2943 struct sdpcm_shared *sh) 2944 { 2945 u32 addr, console_ptr, console_size, console_index; 2946 char *conbuf = NULL; 2947 __le32 sh_val; 2948 int rv; 2949 2950 /* obtain console information from device memory */ 2951 addr = sh->console_addr + offsetof(struct rte_console, log_le); 2952 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2953 (u8 *)&sh_val, sizeof(u32)); 2954 if (rv < 0) 2955 return rv; 2956 console_ptr = le32_to_cpu(sh_val); 2957 2958 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size); 2959 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2960 (u8 *)&sh_val, sizeof(u32)); 2961 if (rv < 0) 2962 return rv; 2963 console_size = le32_to_cpu(sh_val); 2964 2965 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx); 2966 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2967 (u8 *)&sh_val, sizeof(u32)); 2968 if (rv < 0) 2969 return rv; 2970 console_index = le32_to_cpu(sh_val); 2971 2972 /* allocate buffer for console data */ 2973 if (console_size <= CONSOLE_BUFFER_MAX) 2974 conbuf = vzalloc(console_size+1); 2975 2976 if (!conbuf) 2977 return -ENOMEM; 2978 2979 /* obtain the console data from device */ 2980 conbuf[console_size] = '\0'; 2981 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf, 2982 console_size); 2983 if (rv < 0) 2984 goto done; 2985 2986 rv = seq_write(seq, conbuf + console_index, 2987 console_size - console_index); 2988 if (rv < 0) 2989 goto done; 2990 2991 if (console_index > 0) 2992 rv = seq_write(seq, conbuf, console_index - 1); 2993 2994 done: 2995 vfree(conbuf); 2996 return rv; 2997 } 2998 2999 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus, 3000 struct sdpcm_shared *sh) 3001 { 3002 int error; 3003 struct brcmf_trap_info tr; 3004 3005 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) { 3006 brcmf_dbg(INFO, "no trap in firmware\n"); 3007 return 0; 3008 } 3009 3010 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr, 3011 sizeof(struct brcmf_trap_info)); 3012 if (error < 0) 3013 return error; 3014 3015 if (seq) 3016 seq_printf(seq, 3017 "dongle trap info: type 0x%x @ epc 0x%08x\n" 3018 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" 3019 " lr 0x%08x pc 0x%08x offset 0x%x\n" 3020 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" 3021 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", 3022 le32_to_cpu(tr.type), le32_to_cpu(tr.epc), 3023 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), 3024 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), 3025 le32_to_cpu(tr.pc), sh->trap_addr, 3026 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), 3027 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), 3028 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), 3029 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); 3030 else 3031 pr_debug("dongle trap info: type 0x%x @ epc 0x%08x\n" 3032 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" 3033 " lr 0x%08x pc 0x%08x offset 0x%x\n" 3034 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" 3035 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", 3036 le32_to_cpu(tr.type), le32_to_cpu(tr.epc), 3037 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), 3038 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), 3039 le32_to_cpu(tr.pc), sh->trap_addr, 3040 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), 3041 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), 3042 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), 3043 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); 3044 return 0; 3045 } 3046 3047 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus, 3048 struct sdpcm_shared *sh) 3049 { 3050 int error = 0; 3051 char file[80] = "?"; 3052 char expr[80] = "<???>"; 3053 3054 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) { 3055 brcmf_dbg(INFO, "firmware not built with -assert\n"); 3056 return 0; 3057 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) { 3058 brcmf_dbg(INFO, "no assert in dongle\n"); 3059 return 0; 3060 } 3061 3062 sdio_claim_host(bus->sdiodev->func1); 3063 if (sh->assert_file_addr != 0) { 3064 error = brcmf_sdiod_ramrw(bus->sdiodev, false, 3065 sh->assert_file_addr, (u8 *)file, 80); 3066 if (error < 0) 3067 return error; 3068 } 3069 if (sh->assert_exp_addr != 0) { 3070 error = brcmf_sdiod_ramrw(bus->sdiodev, false, 3071 sh->assert_exp_addr, (u8 *)expr, 80); 3072 if (error < 0) 3073 return error; 3074 } 3075 sdio_release_host(bus->sdiodev->func1); 3076 3077 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n", 3078 file, sh->assert_line, expr); 3079 return 0; 3080 } 3081 3082 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) 3083 { 3084 int error; 3085 struct sdpcm_shared sh; 3086 3087 error = brcmf_sdio_readshared(bus, &sh); 3088 3089 if (error < 0) 3090 return error; 3091 3092 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) 3093 brcmf_dbg(INFO, "firmware not built with -assert\n"); 3094 else if (sh.flags & SDPCM_SHARED_ASSERT) 3095 brcmf_err("assertion in dongle\n"); 3096 3097 if (sh.flags & SDPCM_SHARED_TRAP) { 3098 brcmf_err("firmware trap in dongle\n"); 3099 brcmf_sdio_trap_info(NULL, bus, &sh); 3100 } 3101 3102 return 0; 3103 } 3104 3105 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus) 3106 { 3107 int error = 0; 3108 struct sdpcm_shared sh; 3109 3110 error = brcmf_sdio_readshared(bus, &sh); 3111 if (error < 0) 3112 goto done; 3113 3114 error = brcmf_sdio_assert_info(seq, bus, &sh); 3115 if (error < 0) 3116 goto done; 3117 3118 error = brcmf_sdio_trap_info(seq, bus, &sh); 3119 if (error < 0) 3120 goto done; 3121 3122 error = brcmf_sdio_dump_console(seq, bus, &sh); 3123 3124 done: 3125 return error; 3126 } 3127 3128 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data) 3129 { 3130 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); 3131 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus; 3132 3133 return brcmf_sdio_died_dump(seq, bus); 3134 } 3135 3136 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data) 3137 { 3138 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); 3139 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3140 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt; 3141 3142 seq_printf(seq, 3143 "intrcount: %u\nlastintrs: %u\n" 3144 "pollcnt: %u\nregfails: %u\n" 3145 "tx_sderrs: %u\nfcqueued: %u\n" 3146 "rxrtx: %u\nrx_toolong: %u\n" 3147 "rxc_errors: %u\nrx_hdrfail: %u\n" 3148 "rx_badhdr: %u\nrx_badseq: %u\n" 3149 "fc_rcvd: %u\nfc_xoff: %u\n" 3150 "fc_xon: %u\nrxglomfail: %u\n" 3151 "rxglomframes: %u\nrxglompkts: %u\n" 3152 "f2rxhdrs: %u\nf2rxdata: %u\n" 3153 "f2txdata: %u\nf1regdata: %u\n" 3154 "tickcnt: %u\ntx_ctlerrs: %lu\n" 3155 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n" 3156 "rx_ctlpkts: %lu\nrx_readahead: %lu\n", 3157 sdcnt->intrcount, sdcnt->lastintrs, 3158 sdcnt->pollcnt, sdcnt->regfails, 3159 sdcnt->tx_sderrs, sdcnt->fcqueued, 3160 sdcnt->rxrtx, sdcnt->rx_toolong, 3161 sdcnt->rxc_errors, sdcnt->rx_hdrfail, 3162 sdcnt->rx_badhdr, sdcnt->rx_badseq, 3163 sdcnt->fc_rcvd, sdcnt->fc_xoff, 3164 sdcnt->fc_xon, sdcnt->rxglomfail, 3165 sdcnt->rxglomframes, sdcnt->rxglompkts, 3166 sdcnt->f2rxhdrs, sdcnt->f2rxdata, 3167 sdcnt->f2txdata, sdcnt->f1regdata, 3168 sdcnt->tickcnt, sdcnt->tx_ctlerrs, 3169 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs, 3170 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt); 3171 3172 return 0; 3173 } 3174 3175 static void brcmf_sdio_debugfs_create(struct device *dev) 3176 { 3177 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3178 struct brcmf_pub *drvr = bus_if->drvr; 3179 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3180 struct brcmf_sdio *bus = sdiodev->bus; 3181 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); 3182 3183 if (IS_ERR_OR_NULL(dentry)) 3184 return; 3185 3186 bus->console_interval = BRCMF_CONSOLE; 3187 3188 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read); 3189 brcmf_debugfs_add_entry(drvr, "counters", 3190 brcmf_debugfs_sdio_count_read); 3191 debugfs_create_u32("console_interval", 0644, dentry, 3192 &bus->console_interval); 3193 } 3194 #else 3195 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) 3196 { 3197 return 0; 3198 } 3199 3200 static void brcmf_sdio_debugfs_create(struct device *dev) 3201 { 3202 } 3203 #endif /* DEBUG */ 3204 3205 static int 3206 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) 3207 { 3208 int timeleft; 3209 uint rxlen = 0; 3210 bool pending; 3211 u8 *buf; 3212 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3213 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3214 struct brcmf_sdio *bus = sdiodev->bus; 3215 3216 brcmf_dbg(TRACE, "Enter\n"); 3217 if (sdiodev->state != BRCMF_SDIOD_DATA) 3218 return -EIO; 3219 3220 /* Wait until control frame is available */ 3221 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending); 3222 3223 spin_lock_bh(&bus->rxctl_lock); 3224 rxlen = bus->rxlen; 3225 memcpy(msg, bus->rxctl, min(msglen, rxlen)); 3226 bus->rxctl = NULL; 3227 buf = bus->rxctl_orig; 3228 bus->rxctl_orig = NULL; 3229 bus->rxlen = 0; 3230 spin_unlock_bh(&bus->rxctl_lock); 3231 vfree(buf); 3232 3233 if (rxlen) { 3234 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", 3235 rxlen, msglen); 3236 } else if (timeleft == 0) { 3237 brcmf_err("resumed on timeout\n"); 3238 brcmf_sdio_checkdied(bus); 3239 } else if (pending) { 3240 brcmf_dbg(CTL, "cancelled\n"); 3241 return -ERESTARTSYS; 3242 } else { 3243 brcmf_dbg(CTL, "resumed for unknown reason?\n"); 3244 brcmf_sdio_checkdied(bus); 3245 } 3246 3247 if (rxlen) 3248 bus->sdcnt.rx_ctlpkts++; 3249 else 3250 bus->sdcnt.rx_ctlerrs++; 3251 3252 return rxlen ? (int)rxlen : -ETIMEDOUT; 3253 } 3254 3255 #ifdef DEBUG 3256 static bool 3257 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, 3258 u8 *ram_data, uint ram_sz) 3259 { 3260 char *ram_cmp; 3261 int err; 3262 bool ret = true; 3263 int address; 3264 int offset; 3265 int len; 3266 3267 /* read back and verify */ 3268 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr, 3269 ram_sz); 3270 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL); 3271 /* do not proceed while no memory but */ 3272 if (!ram_cmp) 3273 return true; 3274 3275 address = ram_addr; 3276 offset = 0; 3277 while (offset < ram_sz) { 3278 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK : 3279 ram_sz - offset; 3280 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len); 3281 if (err) { 3282 brcmf_err("error %d on reading %d membytes at 0x%08x\n", 3283 err, len, address); 3284 ret = false; 3285 break; 3286 } else if (memcmp(ram_cmp, &ram_data[offset], len)) { 3287 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n", 3288 offset, len); 3289 ret = false; 3290 break; 3291 } 3292 offset += len; 3293 address += len; 3294 } 3295 3296 kfree(ram_cmp); 3297 3298 return ret; 3299 } 3300 #else /* DEBUG */ 3301 static bool 3302 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, 3303 u8 *ram_data, uint ram_sz) 3304 { 3305 return true; 3306 } 3307 #endif /* DEBUG */ 3308 3309 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus, 3310 const struct firmware *fw) 3311 { 3312 int err; 3313 3314 brcmf_dbg(TRACE, "Enter\n"); 3315 3316 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase, 3317 (u8 *)fw->data, fw->size); 3318 if (err) 3319 brcmf_err("error %d on writing %d membytes at 0x%08x\n", 3320 err, (int)fw->size, bus->ci->rambase); 3321 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase, 3322 (u8 *)fw->data, fw->size)) 3323 err = -EIO; 3324 3325 return err; 3326 } 3327 3328 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus, 3329 void *vars, u32 varsz) 3330 { 3331 int address; 3332 int err; 3333 3334 brcmf_dbg(TRACE, "Enter\n"); 3335 3336 address = bus->ci->ramsize - varsz + bus->ci->rambase; 3337 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz); 3338 if (err) 3339 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n", 3340 err, varsz, address); 3341 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz)) 3342 err = -EIO; 3343 3344 return err; 3345 } 3346 3347 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus, 3348 const struct firmware *fw, 3349 void *nvram, u32 nvlen) 3350 { 3351 int bcmerror; 3352 u32 rstvec; 3353 3354 sdio_claim_host(bus->sdiodev->func1); 3355 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 3356 3357 rstvec = get_unaligned_le32(fw->data); 3358 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec); 3359 3360 bcmerror = brcmf_sdio_download_code_file(bus, fw); 3361 release_firmware(fw); 3362 if (bcmerror) { 3363 brcmf_err("dongle image file download failed\n"); 3364 brcmf_fw_nvram_free(nvram); 3365 goto err; 3366 } 3367 3368 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen); 3369 brcmf_fw_nvram_free(nvram); 3370 if (bcmerror) { 3371 brcmf_err("dongle nvram file download failed\n"); 3372 goto err; 3373 } 3374 3375 /* Take arm out of reset */ 3376 if (!brcmf_chip_set_active(bus->ci, rstvec)) { 3377 brcmf_err("error getting out of ARM core reset\n"); 3378 goto err; 3379 } 3380 3381 err: 3382 brcmf_sdio_clkctl(bus, CLK_SDONLY, false); 3383 sdio_release_host(bus->sdiodev->func1); 3384 return bcmerror; 3385 } 3386 3387 static bool brcmf_sdio_aos_no_decode(struct brcmf_sdio *bus) 3388 { 3389 if (bus->ci->chip == CY_CC_43012_CHIP_ID) 3390 return true; 3391 else 3392 return false; 3393 } 3394 3395 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus) 3396 { 3397 int err = 0; 3398 u8 val; 3399 u8 wakeupctrl; 3400 u8 cardcap; 3401 u8 chipclkcsr; 3402 3403 brcmf_dbg(TRACE, "Enter\n"); 3404 3405 if (brcmf_chip_is_ulp(bus->ci)) { 3406 wakeupctrl = SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT; 3407 chipclkcsr = SBSDIO_HT_AVAIL_REQ; 3408 } else { 3409 wakeupctrl = SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT; 3410 chipclkcsr = SBSDIO_FORCE_HT; 3411 } 3412 3413 if (brcmf_sdio_aos_no_decode(bus)) { 3414 cardcap = SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC; 3415 } else { 3416 cardcap = (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | 3417 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT); 3418 } 3419 3420 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err); 3421 if (err) { 3422 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n"); 3423 return; 3424 } 3425 val |= 1 << wakeupctrl; 3426 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err); 3427 if (err) { 3428 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n"); 3429 return; 3430 } 3431 3432 /* Add CMD14 Support */ 3433 brcmf_sdiod_func0_wb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP, 3434 cardcap, 3435 &err); 3436 if (err) { 3437 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n"); 3438 return; 3439 } 3440 3441 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3442 chipclkcsr, &err); 3443 if (err) { 3444 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n"); 3445 return; 3446 } 3447 3448 /* set flag */ 3449 bus->sr_enabled = true; 3450 brcmf_dbg(INFO, "SR enabled\n"); 3451 } 3452 3453 /* enable KSO bit */ 3454 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus) 3455 { 3456 struct brcmf_core *core = bus->sdio_core; 3457 u8 val; 3458 int err = 0; 3459 3460 brcmf_dbg(TRACE, "Enter\n"); 3461 3462 /* KSO bit added in SDIO core rev 12 */ 3463 if (core->rev < 12) 3464 return 0; 3465 3466 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err); 3467 if (err) { 3468 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n"); 3469 return err; 3470 } 3471 3472 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { 3473 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << 3474 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); 3475 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 3476 val, &err); 3477 if (err) { 3478 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n"); 3479 return err; 3480 } 3481 } 3482 3483 return 0; 3484 } 3485 3486 3487 static int brcmf_sdio_bus_preinit(struct device *dev) 3488 { 3489 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3490 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3491 struct brcmf_sdio *bus = sdiodev->bus; 3492 struct brcmf_core *core = bus->sdio_core; 3493 u32 value; 3494 int err; 3495 3496 /* maxctl provided by common layer */ 3497 if (WARN_ON(!bus_if->maxctl)) 3498 return -EINVAL; 3499 3500 /* Allocate control receive buffer */ 3501 bus_if->maxctl += bus->roundup; 3502 value = roundup((bus_if->maxctl + SDPCM_HDRLEN), ALIGNMENT); 3503 value += bus->head_align; 3504 bus->rxbuf = kmalloc(value, GFP_ATOMIC); 3505 if (bus->rxbuf) 3506 bus->rxblen = value; 3507 3508 /* the commands below use the terms tx and rx from 3509 * a device perspective, ie. bus:txglom affects the 3510 * bus transfers from device to host. 3511 */ 3512 if (core->rev < 12) { 3513 /* for sdio core rev < 12, disable txgloming */ 3514 value = 0; 3515 err = brcmf_iovar_data_set(dev, "bus:txglom", &value, 3516 sizeof(u32)); 3517 } else { 3518 /* otherwise, set txglomalign */ 3519 value = sdiodev->settings->bus.sdio.sd_sgentry_align; 3520 /* SDIO ADMA requires at least 32 bit alignment */ 3521 value = max_t(u32, value, ALIGNMENT); 3522 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value, 3523 sizeof(u32)); 3524 } 3525 3526 if (err < 0) 3527 goto done; 3528 3529 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; 3530 if (sdiodev->sg_support) { 3531 bus->txglom = false; 3532 value = 1; 3533 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom", 3534 &value, sizeof(u32)); 3535 if (err < 0) { 3536 /* bus:rxglom is allowed to fail */ 3537 err = 0; 3538 } else { 3539 bus->txglom = true; 3540 bus->tx_hdrlen += SDPCM_HWEXT_LEN; 3541 } 3542 } 3543 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen); 3544 3545 done: 3546 return err; 3547 } 3548 3549 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev) 3550 { 3551 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3552 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3553 struct brcmf_sdio *bus = sdiodev->bus; 3554 3555 return bus->ci->ramsize - bus->ci->srsize; 3556 } 3557 3558 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data, 3559 size_t mem_size) 3560 { 3561 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3562 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3563 struct brcmf_sdio *bus = sdiodev->bus; 3564 int err; 3565 int address; 3566 int offset; 3567 int len; 3568 3569 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase, 3570 mem_size); 3571 3572 address = bus->ci->rambase; 3573 offset = err = 0; 3574 sdio_claim_host(sdiodev->func1); 3575 while (offset < mem_size) { 3576 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK : 3577 mem_size - offset; 3578 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len); 3579 if (err) { 3580 brcmf_err("error %d on reading %d membytes at 0x%08x\n", 3581 err, len, address); 3582 goto done; 3583 } 3584 data += len; 3585 offset += len; 3586 address += len; 3587 } 3588 3589 done: 3590 sdio_release_host(sdiodev->func1); 3591 return err; 3592 } 3593 3594 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus) 3595 { 3596 if (!bus->dpc_triggered) { 3597 bus->dpc_triggered = true; 3598 queue_work(bus->brcmf_wq, &bus->datawork); 3599 } 3600 } 3601 3602 void brcmf_sdio_isr(struct brcmf_sdio *bus) 3603 { 3604 brcmf_dbg(TRACE, "Enter\n"); 3605 3606 if (!bus) { 3607 brcmf_err("bus is null pointer, exiting\n"); 3608 return; 3609 } 3610 3611 /* Count the interrupt call */ 3612 bus->sdcnt.intrcount++; 3613 if (in_interrupt()) 3614 atomic_set(&bus->ipend, 1); 3615 else 3616 if (brcmf_sdio_intr_rstatus(bus)) { 3617 brcmf_err("failed backplane access\n"); 3618 } 3619 3620 /* Disable additional interrupts (is this needed now)? */ 3621 if (!bus->intr) 3622 brcmf_err("isr w/o interrupt configured!\n"); 3623 3624 bus->dpc_triggered = true; 3625 queue_work(bus->brcmf_wq, &bus->datawork); 3626 } 3627 3628 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus) 3629 { 3630 brcmf_dbg(TIMER, "Enter\n"); 3631 3632 /* Poll period: check device if appropriate. */ 3633 if (!bus->sr_enabled && 3634 bus->poll && (++bus->polltick >= bus->pollrate)) { 3635 u32 intstatus = 0; 3636 3637 /* Reset poll tick */ 3638 bus->polltick = 0; 3639 3640 /* Check device if no interrupts */ 3641 if (!bus->intr || 3642 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) { 3643 3644 if (!bus->dpc_triggered) { 3645 u8 devpend; 3646 3647 sdio_claim_host(bus->sdiodev->func1); 3648 devpend = brcmf_sdiod_func0_rb(bus->sdiodev, 3649 SDIO_CCCR_INTx, NULL); 3650 sdio_release_host(bus->sdiodev->func1); 3651 intstatus = devpend & (INTR_STATUS_FUNC1 | 3652 INTR_STATUS_FUNC2); 3653 } 3654 3655 /* If there is something, make like the ISR and 3656 schedule the DPC */ 3657 if (intstatus) { 3658 bus->sdcnt.pollcnt++; 3659 atomic_set(&bus->ipend, 1); 3660 3661 bus->dpc_triggered = true; 3662 queue_work(bus->brcmf_wq, &bus->datawork); 3663 } 3664 } 3665 3666 /* Update interrupt tracking */ 3667 bus->sdcnt.lastintrs = bus->sdcnt.intrcount; 3668 } 3669 #ifdef DEBUG 3670 /* Poll for console output periodically */ 3671 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() && 3672 bus->console_interval != 0) { 3673 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL); 3674 if (bus->console.count >= bus->console_interval) { 3675 bus->console.count -= bus->console_interval; 3676 sdio_claim_host(bus->sdiodev->func1); 3677 /* Make sure backplane clock is on */ 3678 brcmf_sdio_bus_sleep(bus, false, false); 3679 if (brcmf_sdio_readconsole(bus) < 0) 3680 /* stop on error */ 3681 bus->console_interval = 0; 3682 sdio_release_host(bus->sdiodev->func1); 3683 } 3684 } 3685 #endif /* DEBUG */ 3686 3687 /* On idle timeout clear activity flag and/or turn off clock */ 3688 if (!bus->dpc_triggered) { 3689 rmb(); 3690 if ((!bus->dpc_running) && (bus->idletime > 0) && 3691 (bus->clkstate == CLK_AVAIL)) { 3692 bus->idlecount++; 3693 if (bus->idlecount > bus->idletime) { 3694 brcmf_dbg(SDIO, "idle\n"); 3695 sdio_claim_host(bus->sdiodev->func1); 3696 brcmf_sdio_wd_timer(bus, false); 3697 bus->idlecount = 0; 3698 brcmf_sdio_bus_sleep(bus, true, false); 3699 sdio_release_host(bus->sdiodev->func1); 3700 } 3701 } else { 3702 bus->idlecount = 0; 3703 } 3704 } else { 3705 bus->idlecount = 0; 3706 } 3707 } 3708 3709 static void brcmf_sdio_dataworker(struct work_struct *work) 3710 { 3711 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio, 3712 datawork); 3713 3714 bus->dpc_running = true; 3715 wmb(); 3716 while (READ_ONCE(bus->dpc_triggered)) { 3717 bus->dpc_triggered = false; 3718 brcmf_sdio_dpc(bus); 3719 bus->idlecount = 0; 3720 } 3721 bus->dpc_running = false; 3722 if (brcmf_sdiod_freezing(bus->sdiodev)) { 3723 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN); 3724 brcmf_sdiod_try_freeze(bus->sdiodev); 3725 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); 3726 } 3727 } 3728 3729 static void 3730 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, 3731 struct brcmf_chip *ci, u32 drivestrength) 3732 { 3733 const struct sdiod_drive_str *str_tab = NULL; 3734 u32 str_mask; 3735 u32 str_shift; 3736 u32 i; 3737 u32 drivestrength_sel = 0; 3738 u32 cc_data_temp; 3739 u32 addr; 3740 3741 if (!(ci->cc_caps & CC_CAP_PMU)) 3742 return; 3743 3744 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) { 3745 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12): 3746 str_tab = sdiod_drvstr_tab1_1v8; 3747 str_mask = 0x00003800; 3748 str_shift = 11; 3749 break; 3750 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17): 3751 str_tab = sdiod_drvstr_tab6_1v8; 3752 str_mask = 0x00001800; 3753 str_shift = 11; 3754 break; 3755 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17): 3756 /* note: 43143 does not support tristate */ 3757 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1; 3758 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) { 3759 str_tab = sdiod_drvstr_tab2_3v3; 3760 str_mask = 0x00000007; 3761 str_shift = 0; 3762 } else 3763 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n", 3764 ci->name, drivestrength); 3765 break; 3766 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13): 3767 str_tab = sdiod_drive_strength_tab5_1v8; 3768 str_mask = 0x00003800; 3769 str_shift = 11; 3770 break; 3771 default: 3772 brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n", 3773 ci->name, ci->chiprev, ci->pmurev); 3774 break; 3775 } 3776 3777 if (str_tab != NULL) { 3778 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci); 3779 3780 for (i = 0; str_tab[i].strength != 0; i++) { 3781 if (drivestrength >= str_tab[i].strength) { 3782 drivestrength_sel = str_tab[i].sel; 3783 break; 3784 } 3785 } 3786 addr = CORE_CC_REG(pmu->base, chipcontrol_addr); 3787 brcmf_sdiod_writel(sdiodev, addr, 1, NULL); 3788 cc_data_temp = brcmf_sdiod_readl(sdiodev, addr, NULL); 3789 cc_data_temp &= ~str_mask; 3790 drivestrength_sel <<= str_shift; 3791 cc_data_temp |= drivestrength_sel; 3792 brcmf_sdiod_writel(sdiodev, addr, cc_data_temp, NULL); 3793 3794 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n", 3795 str_tab[i].strength, drivestrength, cc_data_temp); 3796 } 3797 } 3798 3799 static int brcmf_sdio_buscoreprep(void *ctx) 3800 { 3801 struct brcmf_sdio_dev *sdiodev = ctx; 3802 int err = 0; 3803 u8 clkval, clkset; 3804 3805 /* Try forcing SDIO core to do ALPAvail request only */ 3806 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; 3807 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); 3808 if (err) { 3809 brcmf_err("error writing for HT off\n"); 3810 return err; 3811 } 3812 3813 /* If register supported, wait for ALPAvail and then force ALP */ 3814 /* This may take up to 15 milliseconds */ 3815 clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, NULL); 3816 3817 if ((clkval & ~SBSDIO_AVBITS) != clkset) { 3818 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n", 3819 clkset, clkval); 3820 return -EACCES; 3821 } 3822 3823 SPINWAIT(((clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3824 NULL)), 3825 !SBSDIO_ALPAV(clkval)), 3826 PMU_MAX_TRANSITION_DLY); 3827 3828 if (!SBSDIO_ALPAV(clkval)) { 3829 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n", 3830 clkval); 3831 return -EBUSY; 3832 } 3833 3834 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP; 3835 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); 3836 udelay(65); 3837 3838 /* Also, disable the extra SDIO pull-ups */ 3839 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); 3840 3841 return 0; 3842 } 3843 3844 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip, 3845 u32 rstvec) 3846 { 3847 struct brcmf_sdio_dev *sdiodev = ctx; 3848 struct brcmf_core *core = sdiodev->bus->sdio_core; 3849 u32 reg_addr; 3850 3851 /* clear all interrupts */ 3852 reg_addr = core->base + SD_REG(intstatus); 3853 brcmf_sdiod_writel(sdiodev, reg_addr, 0xFFFFFFFF, NULL); 3854 3855 if (rstvec) 3856 /* Write reset vector to address 0 */ 3857 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec, 3858 sizeof(rstvec)); 3859 } 3860 3861 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr) 3862 { 3863 struct brcmf_sdio_dev *sdiodev = ctx; 3864 u32 val, rev; 3865 3866 val = brcmf_sdiod_readl(sdiodev, addr, NULL); 3867 3868 /* 3869 * this is a bit of special handling if reading the chipcommon chipid 3870 * register. The 4339 is a next-gen of the 4335. It uses the same 3871 * SDIO device id as 4335 and the chipid register returns 4335 as well. 3872 * It can be identified as 4339 by looking at the chip revision. It 3873 * is corrected here so the chip.c module has the right info. 3874 */ 3875 if (addr == CORE_CC_REG(SI_ENUM_BASE, chipid) && 3876 (sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4339 || 3877 sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4335_4339)) { 3878 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT; 3879 if (rev >= 2) { 3880 val &= ~CID_ID_MASK; 3881 val |= BRCM_CC_4339_CHIP_ID; 3882 } 3883 } 3884 3885 return val; 3886 } 3887 3888 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val) 3889 { 3890 struct brcmf_sdio_dev *sdiodev = ctx; 3891 3892 brcmf_sdiod_writel(sdiodev, addr, val, NULL); 3893 } 3894 3895 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = { 3896 .prepare = brcmf_sdio_buscoreprep, 3897 .activate = brcmf_sdio_buscore_activate, 3898 .read32 = brcmf_sdio_buscore_read32, 3899 .write32 = brcmf_sdio_buscore_write32, 3900 }; 3901 3902 static bool 3903 brcmf_sdio_probe_attach(struct brcmf_sdio *bus) 3904 { 3905 struct brcmf_sdio_dev *sdiodev; 3906 u8 clkctl = 0; 3907 int err = 0; 3908 int reg_addr; 3909 u32 reg_val; 3910 u32 drivestrength; 3911 3912 sdiodev = bus->sdiodev; 3913 sdio_claim_host(sdiodev->func1); 3914 3915 pr_debug("F1 signature read @0x18000000=0x%4x\n", 3916 brcmf_sdiod_readl(sdiodev, SI_ENUM_BASE, NULL)); 3917 3918 /* 3919 * Force PLL off until brcmf_chip_attach() 3920 * programs PLL control regs 3921 */ 3922 3923 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, BRCMF_INIT_CLKCTL1, 3924 &err); 3925 if (!err) 3926 clkctl = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3927 &err); 3928 3929 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { 3930 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", 3931 err, BRCMF_INIT_CLKCTL1, clkctl); 3932 goto fail; 3933 } 3934 3935 bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops); 3936 if (IS_ERR(bus->ci)) { 3937 brcmf_err("brcmf_chip_attach failed!\n"); 3938 bus->ci = NULL; 3939 goto fail; 3940 } 3941 3942 /* Pick up the SDIO core info struct from chip.c */ 3943 bus->sdio_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); 3944 if (!bus->sdio_core) 3945 goto fail; 3946 3947 /* Pick up the CHIPCOMMON core info struct, for bulk IO in bcmsdh.c */ 3948 sdiodev->cc_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_CHIPCOMMON); 3949 if (!sdiodev->cc_core) 3950 goto fail; 3951 3952 sdiodev->settings = brcmf_get_module_param(sdiodev->dev, 3953 BRCMF_BUSTYPE_SDIO, 3954 bus->ci->chip, 3955 bus->ci->chiprev); 3956 if (!sdiodev->settings) { 3957 brcmf_err("Failed to get device parameters\n"); 3958 goto fail; 3959 } 3960 /* platform specific configuration: 3961 * alignments must be at least 4 bytes for ADMA 3962 */ 3963 bus->head_align = ALIGNMENT; 3964 bus->sgentry_align = ALIGNMENT; 3965 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT) 3966 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align; 3967 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT) 3968 bus->sgentry_align = 3969 sdiodev->settings->bus.sdio.sd_sgentry_align; 3970 3971 /* allocate scatter-gather table. sg support 3972 * will be disabled upon allocation failure. 3973 */ 3974 brcmf_sdiod_sgtable_alloc(sdiodev); 3975 3976 #ifdef CONFIG_PM_SLEEP 3977 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ 3978 * is true or when platform data OOB irq is true). 3979 */ 3980 if ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_KEEP_POWER) && 3981 ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_WAKE_SDIO_IRQ) || 3982 (sdiodev->settings->bus.sdio.oob_irq_supported))) 3983 sdiodev->bus_if->wowl_supported = true; 3984 #endif 3985 3986 if (brcmf_sdio_kso_init(bus)) { 3987 brcmf_err("error enabling KSO\n"); 3988 goto fail; 3989 } 3990 3991 if (sdiodev->settings->bus.sdio.drive_strength) 3992 drivestrength = sdiodev->settings->bus.sdio.drive_strength; 3993 else 3994 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH; 3995 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength); 3996 3997 /* Set card control so an SDIO card reset does a WLAN backplane reset */ 3998 reg_val = brcmf_sdiod_func0_rb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err); 3999 if (err) 4000 goto fail; 4001 4002 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET; 4003 4004 brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err); 4005 if (err) 4006 goto fail; 4007 4008 /* set PMUControl so a backplane reset does PMU state reload */ 4009 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol); 4010 reg_val = brcmf_sdiod_readl(sdiodev, reg_addr, &err); 4011 if (err) 4012 goto fail; 4013 4014 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT); 4015 4016 brcmf_sdiod_writel(sdiodev, reg_addr, reg_val, &err); 4017 if (err) 4018 goto fail; 4019 4020 sdio_release_host(sdiodev->func1); 4021 4022 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); 4023 4024 /* allocate header buffer */ 4025 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL); 4026 if (!bus->hdrbuf) 4027 return false; 4028 /* Locate an appropriately-aligned portion of hdrbuf */ 4029 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], 4030 bus->head_align); 4031 4032 /* Set the poll and/or interrupt flags */ 4033 bus->intr = true; 4034 bus->poll = false; 4035 if (bus->poll) 4036 bus->pollrate = 1; 4037 4038 return true; 4039 4040 fail: 4041 sdio_release_host(sdiodev->func1); 4042 return false; 4043 } 4044 4045 static int 4046 brcmf_sdio_watchdog_thread(void *data) 4047 { 4048 struct brcmf_sdio *bus = (struct brcmf_sdio *)data; 4049 int wait; 4050 4051 allow_signal(SIGTERM); 4052 /* Run until signal received */ 4053 brcmf_sdiod_freezer_count(bus->sdiodev); 4054 while (1) { 4055 if (kthread_should_stop()) 4056 break; 4057 brcmf_sdiod_freezer_uncount(bus->sdiodev); 4058 wait = wait_for_completion_interruptible(&bus->watchdog_wait); 4059 brcmf_sdiod_freezer_count(bus->sdiodev); 4060 brcmf_sdiod_try_freeze(bus->sdiodev); 4061 if (!wait) { 4062 brcmf_sdio_bus_watchdog(bus); 4063 /* Count the tick for reference */ 4064 bus->sdcnt.tickcnt++; 4065 reinit_completion(&bus->watchdog_wait); 4066 } else 4067 break; 4068 } 4069 return 0; 4070 } 4071 4072 static void 4073 brcmf_sdio_watchdog(struct timer_list *t) 4074 { 4075 struct brcmf_sdio *bus = from_timer(bus, t, timer); 4076 4077 if (bus->watchdog_tsk) { 4078 complete(&bus->watchdog_wait); 4079 /* Reschedule the watchdog */ 4080 if (bus->wd_active) 4081 mod_timer(&bus->timer, 4082 jiffies + BRCMF_WD_POLL); 4083 } 4084 } 4085 4086 static 4087 int brcmf_sdio_get_fwname(struct device *dev, const char *ext, u8 *fw_name) 4088 { 4089 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4090 struct brcmf_fw_request *fwreq; 4091 struct brcmf_fw_name fwnames[] = { 4092 { ext, fw_name }, 4093 }; 4094 4095 fwreq = brcmf_fw_alloc_request(bus_if->chip, bus_if->chiprev, 4096 brcmf_sdio_fwnames, 4097 ARRAY_SIZE(brcmf_sdio_fwnames), 4098 fwnames, ARRAY_SIZE(fwnames)); 4099 if (!fwreq) 4100 return -ENOMEM; 4101 4102 kfree(fwreq); 4103 return 0; 4104 } 4105 4106 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = { 4107 .stop = brcmf_sdio_bus_stop, 4108 .preinit = brcmf_sdio_bus_preinit, 4109 .txdata = brcmf_sdio_bus_txdata, 4110 .txctl = brcmf_sdio_bus_txctl, 4111 .rxctl = brcmf_sdio_bus_rxctl, 4112 .gettxq = brcmf_sdio_bus_gettxq, 4113 .wowl_config = brcmf_sdio_wowl_config, 4114 .get_ramsize = brcmf_sdio_bus_get_ramsize, 4115 .get_memdump = brcmf_sdio_bus_get_memdump, 4116 .get_fwname = brcmf_sdio_get_fwname, 4117 .debugfs_create = brcmf_sdio_debugfs_create 4118 }; 4119 4120 #define BRCMF_SDIO_FW_CODE 0 4121 #define BRCMF_SDIO_FW_NVRAM 1 4122 4123 static void brcmf_sdio_firmware_callback(struct device *dev, int err, 4124 struct brcmf_fw_request *fwreq) 4125 { 4126 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4127 struct brcmf_sdio_dev *sdiod = bus_if->bus_priv.sdio; 4128 struct brcmf_sdio *bus = sdiod->bus; 4129 struct brcmf_core *core = bus->sdio_core; 4130 const struct firmware *code; 4131 void *nvram; 4132 u32 nvram_len; 4133 u8 saveclk, bpreq; 4134 u8 devctl; 4135 4136 brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err); 4137 4138 if (err) 4139 goto fail; 4140 4141 code = fwreq->items[BRCMF_SDIO_FW_CODE].binary; 4142 nvram = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.data; 4143 nvram_len = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.len; 4144 kfree(fwreq); 4145 4146 /* try to download image and nvram to the dongle */ 4147 bus->alp_only = true; 4148 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len); 4149 if (err) 4150 goto fail; 4151 bus->alp_only = false; 4152 4153 /* Start the watchdog timer */ 4154 bus->sdcnt.tickcnt = 0; 4155 brcmf_sdio_wd_timer(bus, true); 4156 4157 sdio_claim_host(sdiod->func1); 4158 4159 /* Make sure backplane clock is on, needed to generate F2 interrupt */ 4160 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 4161 if (bus->clkstate != CLK_AVAIL) 4162 goto release; 4163 4164 /* Force clocks on backplane to be sure F2 interrupt propagates */ 4165 saveclk = brcmf_sdiod_readb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, &err); 4166 if (!err) { 4167 bpreq = saveclk; 4168 bpreq |= brcmf_chip_is_ulp(bus->ci) ? 4169 SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT; 4170 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, 4171 bpreq, &err); 4172 } 4173 if (err) { 4174 brcmf_err("Failed to force clock for F2: err %d\n", err); 4175 goto release; 4176 } 4177 4178 /* Enable function 2 (frame transfers) */ 4179 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailboxdata), 4180 SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, NULL); 4181 4182 err = sdio_enable_func(sdiod->func2); 4183 4184 brcmf_dbg(INFO, "enable F2: err=%d\n", err); 4185 4186 /* If F2 successfully enabled, set core and enable interrupts */ 4187 if (!err) { 4188 /* Set up the interrupt mask and enable interrupts */ 4189 bus->hostintmask = HOSTINTMASK; 4190 brcmf_sdiod_writel(sdiod, core->base + SD_REG(hostintmask), 4191 bus->hostintmask, NULL); 4192 4193 switch (sdiod->func1->device) { 4194 case SDIO_DEVICE_ID_CYPRESS_4373: 4195 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4196 CY_4373_F2_WATERMARK); 4197 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4198 CY_4373_F2_WATERMARK, &err); 4199 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4200 &err); 4201 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4202 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4203 &err); 4204 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4205 CY_4373_F2_WATERMARK | 4206 SBSDIO_MESBUSYCTRL_ENAB, &err); 4207 break; 4208 case SDIO_DEVICE_ID_CYPRESS_43012: 4209 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4210 CY_43012_F2_WATERMARK); 4211 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4212 CY_43012_F2_WATERMARK, &err); 4213 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4214 &err); 4215 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4216 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4217 &err); 4218 break; 4219 default: 4220 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4221 DEFAULT_F2_WATERMARK, &err); 4222 break; 4223 } 4224 } else { 4225 /* Disable F2 again */ 4226 sdio_disable_func(sdiod->func2); 4227 goto checkdied; 4228 } 4229 4230 if (brcmf_chip_sr_capable(bus->ci)) { 4231 brcmf_sdio_sr_init(bus); 4232 } else { 4233 /* Restore previous clock setting */ 4234 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, 4235 saveclk, &err); 4236 } 4237 4238 if (err == 0) { 4239 /* Allow full data communication using DPC from now on. */ 4240 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); 4241 4242 err = brcmf_sdiod_intr_register(sdiod); 4243 if (err != 0) 4244 brcmf_err("intr register failed:%d\n", err); 4245 } 4246 4247 /* If we didn't come up, turn off backplane clock */ 4248 if (err != 0) { 4249 brcmf_sdio_clkctl(bus, CLK_NONE, false); 4250 goto checkdied; 4251 } 4252 4253 sdio_release_host(sdiod->func1); 4254 4255 /* Assign bus interface call back */ 4256 sdiod->bus_if->dev = sdiod->dev; 4257 sdiod->bus_if->ops = &brcmf_sdio_bus_ops; 4258 sdiod->bus_if->chip = bus->ci->chip; 4259 sdiod->bus_if->chiprev = bus->ci->chiprev; 4260 4261 /* Attach to the common layer, reserve hdr space */ 4262 err = brcmf_attach(sdiod->dev, sdiod->settings); 4263 if (err != 0) { 4264 brcmf_err("brcmf_attach failed\n"); 4265 sdio_claim_host(sdiod->func1); 4266 goto checkdied; 4267 } 4268 4269 /* ready */ 4270 return; 4271 4272 checkdied: 4273 brcmf_sdio_checkdied(bus); 4274 release: 4275 sdio_release_host(sdiod->func1); 4276 fail: 4277 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err); 4278 device_release_driver(&sdiod->func2->dev); 4279 device_release_driver(dev); 4280 } 4281 4282 static struct brcmf_fw_request * 4283 brcmf_sdio_prepare_fw_request(struct brcmf_sdio *bus) 4284 { 4285 struct brcmf_fw_request *fwreq; 4286 struct brcmf_fw_name fwnames[] = { 4287 { ".bin", bus->sdiodev->fw_name }, 4288 { ".txt", bus->sdiodev->nvram_name }, 4289 }; 4290 4291 fwreq = brcmf_fw_alloc_request(bus->ci->chip, bus->ci->chiprev, 4292 brcmf_sdio_fwnames, 4293 ARRAY_SIZE(brcmf_sdio_fwnames), 4294 fwnames, ARRAY_SIZE(fwnames)); 4295 if (!fwreq) 4296 return NULL; 4297 4298 fwreq->items[BRCMF_SDIO_FW_CODE].type = BRCMF_FW_TYPE_BINARY; 4299 fwreq->items[BRCMF_SDIO_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM; 4300 fwreq->board_type = bus->sdiodev->settings->board_type; 4301 4302 return fwreq; 4303 } 4304 4305 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev) 4306 { 4307 int ret; 4308 struct brcmf_sdio *bus; 4309 struct workqueue_struct *wq; 4310 struct brcmf_fw_request *fwreq; 4311 4312 brcmf_dbg(TRACE, "Enter\n"); 4313 4314 /* Allocate private bus interface state */ 4315 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC); 4316 if (!bus) 4317 goto fail; 4318 4319 bus->sdiodev = sdiodev; 4320 sdiodev->bus = bus; 4321 skb_queue_head_init(&bus->glom); 4322 bus->txbound = BRCMF_TXBOUND; 4323 bus->rxbound = BRCMF_RXBOUND; 4324 bus->txminmax = BRCMF_TXMINMAX; 4325 bus->tx_seq = SDPCM_SEQ_WRAP - 1; 4326 4327 /* single-threaded workqueue */ 4328 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM, 4329 dev_name(&sdiodev->func1->dev)); 4330 if (!wq) { 4331 brcmf_err("insufficient memory to create txworkqueue\n"); 4332 goto fail; 4333 } 4334 brcmf_sdiod_freezer_count(sdiodev); 4335 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker); 4336 bus->brcmf_wq = wq; 4337 4338 /* attempt to attach to the dongle */ 4339 if (!(brcmf_sdio_probe_attach(bus))) { 4340 brcmf_err("brcmf_sdio_probe_attach failed\n"); 4341 goto fail; 4342 } 4343 4344 spin_lock_init(&bus->rxctl_lock); 4345 spin_lock_init(&bus->txq_lock); 4346 init_waitqueue_head(&bus->ctrl_wait); 4347 init_waitqueue_head(&bus->dcmd_resp_wait); 4348 4349 /* Set up the watchdog timer */ 4350 timer_setup(&bus->timer, brcmf_sdio_watchdog, 0); 4351 /* Initialize watchdog thread */ 4352 init_completion(&bus->watchdog_wait); 4353 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread, 4354 bus, "brcmf_wdog/%s", 4355 dev_name(&sdiodev->func1->dev)); 4356 if (IS_ERR(bus->watchdog_tsk)) { 4357 pr_warn("brcmf_watchdog thread failed to start\n"); 4358 bus->watchdog_tsk = NULL; 4359 } 4360 /* Initialize DPC thread */ 4361 bus->dpc_triggered = false; 4362 bus->dpc_running = false; 4363 4364 /* default sdio bus header length for tx packet */ 4365 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; 4366 4367 /* Query the F2 block size, set roundup accordingly */ 4368 bus->blocksize = bus->sdiodev->func2->cur_blksize; 4369 bus->roundup = min(max_roundup, bus->blocksize); 4370 4371 sdio_claim_host(bus->sdiodev->func1); 4372 4373 /* Disable F2 to clear any intermediate frame state on the dongle */ 4374 sdio_disable_func(bus->sdiodev->func2); 4375 4376 bus->rxflow = false; 4377 4378 /* Done with backplane-dependent accesses, can drop clock... */ 4379 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); 4380 4381 sdio_release_host(bus->sdiodev->func1); 4382 4383 /* ...and initialize clock/power states */ 4384 bus->clkstate = CLK_SDONLY; 4385 bus->idletime = BRCMF_IDLE_INTERVAL; 4386 bus->idleclock = BRCMF_IDLE_ACTIVE; 4387 4388 /* SR state */ 4389 bus->sr_enabled = false; 4390 4391 brcmf_dbg(INFO, "completed!!\n"); 4392 4393 fwreq = brcmf_sdio_prepare_fw_request(bus); 4394 if (!fwreq) { 4395 ret = -ENOMEM; 4396 goto fail; 4397 } 4398 4399 ret = brcmf_fw_get_firmwares(sdiodev->dev, fwreq, 4400 brcmf_sdio_firmware_callback); 4401 if (ret != 0) { 4402 brcmf_err("async firmware request failed: %d\n", ret); 4403 kfree(fwreq); 4404 goto fail; 4405 } 4406 4407 return bus; 4408 4409 fail: 4410 brcmf_sdio_remove(bus); 4411 return NULL; 4412 } 4413 4414 /* Detach and free everything */ 4415 void brcmf_sdio_remove(struct brcmf_sdio *bus) 4416 { 4417 brcmf_dbg(TRACE, "Enter\n"); 4418 4419 if (bus) { 4420 /* Stop watchdog task */ 4421 if (bus->watchdog_tsk) { 4422 send_sig(SIGTERM, bus->watchdog_tsk, 1); 4423 kthread_stop(bus->watchdog_tsk); 4424 bus->watchdog_tsk = NULL; 4425 } 4426 4427 /* De-register interrupt handler */ 4428 brcmf_sdiod_intr_unregister(bus->sdiodev); 4429 4430 brcmf_detach(bus->sdiodev->dev); 4431 4432 cancel_work_sync(&bus->datawork); 4433 if (bus->brcmf_wq) 4434 destroy_workqueue(bus->brcmf_wq); 4435 4436 if (bus->ci) { 4437 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { 4438 sdio_claim_host(bus->sdiodev->func1); 4439 brcmf_sdio_wd_timer(bus, false); 4440 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 4441 /* Leave the device in state where it is 4442 * 'passive'. This is done by resetting all 4443 * necessary cores. 4444 */ 4445 msleep(20); 4446 brcmf_chip_set_passive(bus->ci); 4447 brcmf_sdio_clkctl(bus, CLK_NONE, false); 4448 sdio_release_host(bus->sdiodev->func1); 4449 } 4450 brcmf_chip_detach(bus->ci); 4451 } 4452 if (bus->sdiodev->settings) 4453 brcmf_release_module_param(bus->sdiodev->settings); 4454 4455 kfree(bus->rxbuf); 4456 kfree(bus->hdrbuf); 4457 kfree(bus); 4458 } 4459 4460 brcmf_dbg(TRACE, "Disconnected\n"); 4461 } 4462 4463 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active) 4464 { 4465 /* Totally stop the timer */ 4466 if (!active && bus->wd_active) { 4467 del_timer_sync(&bus->timer); 4468 bus->wd_active = false; 4469 return; 4470 } 4471 4472 /* don't start the wd until fw is loaded */ 4473 if (bus->sdiodev->state != BRCMF_SDIOD_DATA) 4474 return; 4475 4476 if (active) { 4477 if (!bus->wd_active) { 4478 /* Create timer again when watchdog period is 4479 dynamically changed or in the first instance 4480 */ 4481 bus->timer.expires = jiffies + BRCMF_WD_POLL; 4482 add_timer(&bus->timer); 4483 bus->wd_active = true; 4484 } else { 4485 /* Re arm the timer, at last watchdog period */ 4486 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL); 4487 } 4488 } 4489 } 4490 4491 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep) 4492 { 4493 int ret; 4494 4495 sdio_claim_host(bus->sdiodev->func1); 4496 ret = brcmf_sdio_bus_sleep(bus, sleep, false); 4497 sdio_release_host(bus->sdiodev->func1); 4498 4499 return ret; 4500 } 4501 4502