1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/types.h> 18 #include <linux/atomic.h> 19 #include <linux/kernel.h> 20 #include <linux/kthread.h> 21 #include <linux/printk.h> 22 #include <linux/pci_ids.h> 23 #include <linux/netdevice.h> 24 #include <linux/interrupt.h> 25 #include <linux/sched/signal.h> 26 #include <linux/mmc/sdio.h> 27 #include <linux/mmc/sdio_ids.h> 28 #include <linux/mmc/sdio_func.h> 29 #include <linux/mmc/card.h> 30 #include <linux/semaphore.h> 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <linux/bcma/bcma.h> 34 #include <linux/debugfs.h> 35 #include <linux/vmalloc.h> 36 #include <asm/unaligned.h> 37 #include <defs.h> 38 #include <brcmu_wifi.h> 39 #include <brcmu_utils.h> 40 #include <brcm_hw_ids.h> 41 #include <soc.h> 42 #include "sdio.h" 43 #include "chip.h" 44 #include "firmware.h" 45 #include "core.h" 46 #include "common.h" 47 #include "bcdc.h" 48 49 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500) 50 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500) 51 52 #ifdef DEBUG 53 54 #define BRCMF_TRAP_INFO_SIZE 80 55 56 #define CBUF_LEN (128) 57 58 /* Device console log buffer state */ 59 #define CONSOLE_BUFFER_MAX 2024 60 61 struct rte_log_le { 62 __le32 buf; /* Can't be pointer on (64-bit) hosts */ 63 __le32 buf_size; 64 __le32 idx; 65 char *_buf_compat; /* Redundant pointer for backward compat. */ 66 }; 67 68 struct rte_console { 69 /* Virtual UART 70 * When there is no UART (e.g. Quickturn), 71 * the host should write a complete 72 * input line directly into cbuf and then write 73 * the length into vcons_in. 74 * This may also be used when there is a real UART 75 * (at risk of conflicting with 76 * the real UART). vcons_out is currently unused. 77 */ 78 uint vcons_in; 79 uint vcons_out; 80 81 /* Output (logging) buffer 82 * Console output is written to a ring buffer log_buf at index log_idx. 83 * The host may read the output when it sees log_idx advance. 84 * Output will be lost if the output wraps around faster than the host 85 * polls. 86 */ 87 struct rte_log_le log_le; 88 89 /* Console input line buffer 90 * Characters are read one at a time into cbuf 91 * until <CR> is received, then 92 * the buffer is processed as a command line. 93 * Also used for virtual UART. 94 */ 95 uint cbuf_idx; 96 char cbuf[CBUF_LEN]; 97 }; 98 99 #endif /* DEBUG */ 100 #include <chipcommon.h> 101 102 #include "bus.h" 103 #include "debug.h" 104 #include "tracepoint.h" 105 106 #define TXQLEN 2048 /* bulk tx queue length */ 107 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ 108 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ 109 #define PRIOMASK 7 110 111 #define TXRETRIES 2 /* # of retries for tx frames */ 112 113 #define BRCMF_RXBOUND 50 /* Default for max rx frames in 114 one scheduling */ 115 116 #define BRCMF_TXBOUND 20 /* Default for max tx frames in 117 one scheduling */ 118 119 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ 120 121 #define MEMBLOCK 2048 /* Block size used for downloading 122 of dongle image */ 123 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold 124 biggest possible glom */ 125 126 #define BRCMF_FIRSTREAD (1 << 6) 127 128 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */ 129 130 /* SBSDIO_DEVICE_CTL */ 131 132 /* 1: device will assert busy signal when receiving CMD53 */ 133 #define SBSDIO_DEVCTL_SETBUSY 0x01 134 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ 135 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 136 /* 1: mask all interrupts to host except the chipActive (rev 8) */ 137 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 138 /* 1: isolate internal sdio signals, put external pads in tri-state; requires 139 * sdio bus power cycle to clear (rev 9) */ 140 #define SBSDIO_DEVCTL_PADS_ISO 0x08 141 /* Force SD->SB reset mapping (rev 11) */ 142 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 143 /* Determined by CoreControl bit */ 144 #define SBSDIO_DEVCTL_RST_CORECTL 0x00 145 /* Force backplane reset */ 146 #define SBSDIO_DEVCTL_RST_BPRESET 0x10 147 /* Force no backplane reset */ 148 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 149 150 /* direct(mapped) cis space */ 151 152 /* MAPPED common CIS address */ 153 #define SBSDIO_CIS_BASE_COMMON 0x1000 154 /* maximum bytes in one CIS */ 155 #define SBSDIO_CIS_SIZE_LIMIT 0x200 156 /* cis offset addr is < 17 bits */ 157 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF 158 159 /* manfid tuple length, include tuple, link bytes */ 160 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 161 162 #define SD_REG(field) \ 163 (offsetof(struct sdpcmd_regs, field)) 164 165 /* SDIO function 1 register CHIPCLKCSR */ 166 /* Force ALP request to backplane */ 167 #define SBSDIO_FORCE_ALP 0x01 168 /* Force HT request to backplane */ 169 #define SBSDIO_FORCE_HT 0x02 170 /* Force ILP request to backplane */ 171 #define SBSDIO_FORCE_ILP 0x04 172 /* Make ALP ready (power up xtal) */ 173 #define SBSDIO_ALP_AVAIL_REQ 0x08 174 /* Make HT ready (power up PLL) */ 175 #define SBSDIO_HT_AVAIL_REQ 0x10 176 /* Squelch clock requests from HW */ 177 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 178 /* Status: ALP is ready */ 179 #define SBSDIO_ALP_AVAIL 0x40 180 /* Status: HT is ready */ 181 #define SBSDIO_HT_AVAIL 0x80 182 #define SBSDIO_CSR_MASK 0x1F 183 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) 184 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) 185 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) 186 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) 187 #define SBSDIO_CLKAV(regval, alponly) \ 188 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) 189 190 /* intstatus */ 191 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ 192 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ 193 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ 194 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ 195 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ 196 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ 197 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ 198 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ 199 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ 200 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ 201 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ 202 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ 203 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ 204 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ 205 #define I_PC (1 << 10) /* descriptor error */ 206 #define I_PD (1 << 11) /* data error */ 207 #define I_DE (1 << 12) /* Descriptor protocol Error */ 208 #define I_RU (1 << 13) /* Receive descriptor Underflow */ 209 #define I_RO (1 << 14) /* Receive fifo Overflow */ 210 #define I_XU (1 << 15) /* Transmit fifo Underflow */ 211 #define I_RI (1 << 16) /* Receive Interrupt */ 212 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ 213 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ 214 #define I_XI (1 << 24) /* Transmit Interrupt */ 215 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ 216 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ 217 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ 218 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ 219 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ 220 #define I_SRESET (1 << 30) /* CCCR RES interrupt */ 221 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ 222 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) 223 #define I_DMA (I_RI | I_XI | I_ERRORS) 224 225 /* corecontrol */ 226 #define CC_CISRDY (1 << 0) /* CIS Ready */ 227 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */ 228 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ 229 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ 230 #define CC_XMTDATAAVAIL_MODE (1 << 4) 231 #define CC_XMTDATAAVAIL_CTRL (1 << 5) 232 233 /* SDA_FRAMECTRL */ 234 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ 235 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ 236 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ 237 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ 238 239 /* 240 * Software allocation of To SB Mailbox resources 241 */ 242 243 /* tosbmailbox bits corresponding to intstatus bits */ 244 #define SMB_NAK (1 << 0) /* Frame NAK */ 245 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ 246 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ 247 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ 248 249 /* tosbmailboxdata */ 250 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ 251 252 /* 253 * Software allocation of To Host Mailbox resources 254 */ 255 256 /* intstatus bits */ 257 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ 258 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ 259 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ 260 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ 261 262 /* tohostmailboxdata */ 263 #define HMB_DATA_NAKHANDLED 0x0001 /* retransmit NAK'd frame */ 264 #define HMB_DATA_DEVREADY 0x0002 /* talk to host after enable */ 265 #define HMB_DATA_FC 0x0004 /* per prio flowcontrol update flag */ 266 #define HMB_DATA_FWREADY 0x0008 /* fw ready for protocol activity */ 267 #define HMB_DATA_FWHALT 0x0010 /* firmware halted */ 268 269 #define HMB_DATA_FCDATA_MASK 0xff000000 270 #define HMB_DATA_FCDATA_SHIFT 24 271 272 #define HMB_DATA_VERSION_MASK 0x00ff0000 273 #define HMB_DATA_VERSION_SHIFT 16 274 275 /* 276 * Software-defined protocol header 277 */ 278 279 /* Current protocol version */ 280 #define SDPCM_PROT_VERSION 4 281 282 /* 283 * Shared structure between dongle and the host. 284 * The structure contains pointers to trap or assert information. 285 */ 286 #define SDPCM_SHARED_VERSION 0x0003 287 #define SDPCM_SHARED_VERSION_MASK 0x00FF 288 #define SDPCM_SHARED_ASSERT_BUILT 0x0100 289 #define SDPCM_SHARED_ASSERT 0x0200 290 #define SDPCM_SHARED_TRAP 0x0400 291 292 /* Space for header read, limit for data packets */ 293 #define MAX_HDR_READ (1 << 6) 294 #define MAX_RX_DATASZ 2048 295 296 /* Bump up limit on waiting for HT to account for first startup; 297 * if the image is doing a CRC calculation before programming the PMU 298 * for HT availability, it could take a couple hundred ms more, so 299 * max out at a 1 second (1000000us). 300 */ 301 #undef PMU_MAX_TRANSITION_DLY 302 #define PMU_MAX_TRANSITION_DLY 1000000 303 304 /* Value for ChipClockCSR during initial setup */ 305 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ 306 SBSDIO_ALP_AVAIL_REQ) 307 308 /* Flags for SDH calls */ 309 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) 310 311 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change 312 * when idle 313 */ 314 #define BRCMF_IDLE_INTERVAL 1 315 316 #define KSO_WAIT_US 50 317 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US) 318 #define BRCMF_SDIO_MAX_ACCESS_ERRORS 5 319 320 /* 321 * Conversion of 802.1D priority to precedence level 322 */ 323 static uint prio2prec(u32 prio) 324 { 325 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ? 326 (prio^2) : prio; 327 } 328 329 #ifdef DEBUG 330 /* Device console log buffer state */ 331 struct brcmf_console { 332 uint count; /* Poll interval msec counter */ 333 uint log_addr; /* Log struct address (fixed) */ 334 struct rte_log_le log_le; /* Log struct (host copy) */ 335 uint bufsize; /* Size of log buffer */ 336 u8 *buf; /* Log buffer (host copy) */ 337 uint last; /* Last buffer read index */ 338 }; 339 340 struct brcmf_trap_info { 341 __le32 type; 342 __le32 epc; 343 __le32 cpsr; 344 __le32 spsr; 345 __le32 r0; /* a1 */ 346 __le32 r1; /* a2 */ 347 __le32 r2; /* a3 */ 348 __le32 r3; /* a4 */ 349 __le32 r4; /* v1 */ 350 __le32 r5; /* v2 */ 351 __le32 r6; /* v3 */ 352 __le32 r7; /* v4 */ 353 __le32 r8; /* v5 */ 354 __le32 r9; /* sb/v6 */ 355 __le32 r10; /* sl/v7 */ 356 __le32 r11; /* fp/v8 */ 357 __le32 r12; /* ip */ 358 __le32 r13; /* sp */ 359 __le32 r14; /* lr */ 360 __le32 pc; /* r15 */ 361 }; 362 #endif /* DEBUG */ 363 364 struct sdpcm_shared { 365 u32 flags; 366 u32 trap_addr; 367 u32 assert_exp_addr; 368 u32 assert_file_addr; 369 u32 assert_line; 370 u32 console_addr; /* Address of struct rte_console */ 371 u32 msgtrace_addr; 372 u8 tag[32]; 373 u32 brpt_addr; 374 }; 375 376 struct sdpcm_shared_le { 377 __le32 flags; 378 __le32 trap_addr; 379 __le32 assert_exp_addr; 380 __le32 assert_file_addr; 381 __le32 assert_line; 382 __le32 console_addr; /* Address of struct rte_console */ 383 __le32 msgtrace_addr; 384 u8 tag[32]; 385 __le32 brpt_addr; 386 }; 387 388 /* dongle SDIO bus specific header info */ 389 struct brcmf_sdio_hdrinfo { 390 u8 seq_num; 391 u8 channel; 392 u16 len; 393 u16 len_left; 394 u16 len_nxtfrm; 395 u8 dat_offset; 396 bool lastfrm; 397 u16 tail_pad; 398 }; 399 400 /* 401 * hold counter variables 402 */ 403 struct brcmf_sdio_count { 404 uint intrcount; /* Count of device interrupt callbacks */ 405 uint lastintrs; /* Count as of last watchdog timer */ 406 uint pollcnt; /* Count of active polls */ 407 uint regfails; /* Count of R_REG failures */ 408 uint tx_sderrs; /* Count of tx attempts with sd errors */ 409 uint fcqueued; /* Tx packets that got queued */ 410 uint rxrtx; /* Count of rtx requests (NAK to dongle) */ 411 uint rx_toolong; /* Receive frames too long to receive */ 412 uint rxc_errors; /* SDIO errors when reading control frames */ 413 uint rx_hdrfail; /* SDIO errors on header reads */ 414 uint rx_badhdr; /* Bad received headers (roosync?) */ 415 uint rx_badseq; /* Mismatched rx sequence number */ 416 uint fc_rcvd; /* Number of flow-control events received */ 417 uint fc_xoff; /* Number which turned on flow-control */ 418 uint fc_xon; /* Number which turned off flow-control */ 419 uint rxglomfail; /* Failed deglom attempts */ 420 uint rxglomframes; /* Number of glom frames (superframes) */ 421 uint rxglompkts; /* Number of packets from glom frames */ 422 uint f2rxhdrs; /* Number of header reads */ 423 uint f2rxdata; /* Number of frame data reads */ 424 uint f2txdata; /* Number of f2 frame writes */ 425 uint f1regdata; /* Number of f1 register accesses */ 426 uint tickcnt; /* Number of watchdog been schedule */ 427 ulong tx_ctlerrs; /* Err of sending ctrl frames */ 428 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */ 429 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */ 430 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */ 431 ulong rx_readahead_cnt; /* packets where header read-ahead was used */ 432 }; 433 434 /* misc chip info needed by some of the routines */ 435 /* Private data for SDIO bus interaction */ 436 struct brcmf_sdio { 437 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ 438 struct brcmf_chip *ci; /* Chip info struct */ 439 struct brcmf_core *sdio_core; /* sdio core info struct */ 440 441 u32 hostintmask; /* Copy of Host Interrupt Mask */ 442 atomic_t intstatus; /* Intstatus bits (events) pending */ 443 atomic_t fcstate; /* State of dongle flow-control */ 444 445 uint blocksize; /* Block size of SDIO transfers */ 446 uint roundup; /* Max roundup limit */ 447 448 struct pktq txq; /* Queue length used for flow-control */ 449 u8 flowcontrol; /* per prio flow control bitmask */ 450 u8 tx_seq; /* Transmit sequence number (next) */ 451 u8 tx_max; /* Maximum transmit sequence allowed */ 452 453 u8 *hdrbuf; /* buffer for handling rx frame */ 454 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ 455 u8 rx_seq; /* Receive sequence number (expected) */ 456 struct brcmf_sdio_hdrinfo cur_read; 457 /* info of current read frame */ 458 bool rxskip; /* Skip receive (awaiting NAK ACK) */ 459 bool rxpending; /* Data frame pending in dongle */ 460 461 uint rxbound; /* Rx frames to read before resched */ 462 uint txbound; /* Tx frames to send before resched */ 463 uint txminmax; 464 465 struct sk_buff *glomd; /* Packet containing glomming descriptor */ 466 struct sk_buff_head glom; /* Packet list for glommed superframe */ 467 468 u8 *rxbuf; /* Buffer for receiving control packets */ 469 uint rxblen; /* Allocated length of rxbuf */ 470 u8 *rxctl; /* Aligned pointer into rxbuf */ 471 u8 *rxctl_orig; /* pointer for freeing rxctl */ 472 uint rxlen; /* Length of valid data in buffer */ 473 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */ 474 475 u8 sdpcm_ver; /* Bus protocol reported by dongle */ 476 477 bool intr; /* Use interrupts */ 478 bool poll; /* Use polling */ 479 atomic_t ipend; /* Device interrupt is pending */ 480 uint spurious; /* Count of spurious interrupts */ 481 uint pollrate; /* Ticks between device polls */ 482 uint polltick; /* Tick counter */ 483 484 #ifdef DEBUG 485 uint console_interval; 486 struct brcmf_console console; /* Console output polling support */ 487 uint console_addr; /* Console address from shared struct */ 488 #endif /* DEBUG */ 489 490 uint clkstate; /* State of sd and backplane clock(s) */ 491 s32 idletime; /* Control for activity timeout */ 492 s32 idlecount; /* Activity timeout counter */ 493 s32 idleclock; /* How to set bus driver when idle */ 494 bool rxflow_mode; /* Rx flow control mode */ 495 bool rxflow; /* Is rx flow control on */ 496 bool alp_only; /* Don't use HT clock (ALP only) */ 497 498 u8 *ctrl_frame_buf; 499 u16 ctrl_frame_len; 500 bool ctrl_frame_stat; 501 int ctrl_frame_err; 502 503 spinlock_t txq_lock; /* protect bus->txq */ 504 wait_queue_head_t ctrl_wait; 505 wait_queue_head_t dcmd_resp_wait; 506 507 struct timer_list timer; 508 struct completion watchdog_wait; 509 struct task_struct *watchdog_tsk; 510 bool wd_active; 511 512 struct workqueue_struct *brcmf_wq; 513 struct work_struct datawork; 514 bool dpc_triggered; 515 bool dpc_running; 516 517 bool txoff; /* Transmit flow-controlled */ 518 struct brcmf_sdio_count sdcnt; 519 bool sr_enabled; /* SaveRestore enabled */ 520 bool sleeping; 521 522 u8 tx_hdrlen; /* sdio bus header length for tx packet */ 523 bool txglom; /* host tx glomming enable flag */ 524 u16 head_align; /* buffer pointer alignment */ 525 u16 sgentry_align; /* scatter-gather buffer alignment */ 526 }; 527 528 /* clkstate */ 529 #define CLK_NONE 0 530 #define CLK_SDONLY 1 531 #define CLK_PENDING 2 532 #define CLK_AVAIL 3 533 534 #ifdef DEBUG 535 static int qcount[NUMPRIO]; 536 #endif /* DEBUG */ 537 538 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */ 539 540 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) 541 542 /* Limit on rounding up frames */ 543 static const uint max_roundup = 512; 544 545 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 546 #define ALIGNMENT 8 547 #else 548 #define ALIGNMENT 4 549 #endif 550 551 enum brcmf_sdio_frmtype { 552 BRCMF_SDIO_FT_NORMAL, 553 BRCMF_SDIO_FT_SUPER, 554 BRCMF_SDIO_FT_SUB, 555 }; 556 557 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) 558 559 /* SDIO Pad drive strength to select value mappings */ 560 struct sdiod_drive_str { 561 u8 strength; /* Pad Drive Strength in mA */ 562 u8 sel; /* Chip-specific select value */ 563 }; 564 565 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */ 566 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = { 567 {32, 0x6}, 568 {26, 0x7}, 569 {22, 0x4}, 570 {16, 0x5}, 571 {12, 0x2}, 572 {8, 0x3}, 573 {4, 0x0}, 574 {0, 0x1} 575 }; 576 577 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */ 578 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = { 579 {6, 0x7}, 580 {5, 0x6}, 581 {4, 0x5}, 582 {3, 0x4}, 583 {2, 0x2}, 584 {1, 0x1}, 585 {0, 0x0} 586 }; 587 588 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */ 589 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = { 590 {3, 0x3}, 591 {2, 0x2}, 592 {1, 0x1}, 593 {0, 0x0} }; 594 595 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */ 596 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = { 597 {16, 0x7}, 598 {12, 0x5}, 599 {8, 0x3}, 600 {4, 0x1} 601 }; 602 603 BRCMF_FW_DEF(43143, "brcmfmac43143-sdio"); 604 BRCMF_FW_DEF(43241B0, "brcmfmac43241b0-sdio"); 605 BRCMF_FW_DEF(43241B4, "brcmfmac43241b4-sdio"); 606 BRCMF_FW_DEF(43241B5, "brcmfmac43241b5-sdio"); 607 BRCMF_FW_DEF(4329, "brcmfmac4329-sdio"); 608 BRCMF_FW_DEF(4330, "brcmfmac4330-sdio"); 609 BRCMF_FW_DEF(4334, "brcmfmac4334-sdio"); 610 BRCMF_FW_DEF(43340, "brcmfmac43340-sdio"); 611 BRCMF_FW_DEF(4335, "brcmfmac4335-sdio"); 612 BRCMF_FW_DEF(43362, "brcmfmac43362-sdio"); 613 BRCMF_FW_DEF(4339, "brcmfmac4339-sdio"); 614 BRCMF_FW_DEF(43430A0, "brcmfmac43430a0-sdio"); 615 /* Note the names are not postfixed with a1 for backward compatibility */ 616 BRCMF_FW_DEF(43430A1, "brcmfmac43430-sdio"); 617 BRCMF_FW_DEF(43455, "brcmfmac43455-sdio"); 618 BRCMF_FW_DEF(4354, "brcmfmac4354-sdio"); 619 BRCMF_FW_DEF(4356, "brcmfmac4356-sdio"); 620 BRCMF_FW_DEF(4373, "brcmfmac4373-sdio"); 621 622 static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = { 623 BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143), 624 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0), 625 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4), 626 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5), 627 BRCMF_FW_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329), 628 BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330), 629 BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334), 630 BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340), 631 BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340), 632 BRCMF_FW_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335), 633 BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362), 634 BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339), 635 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0), 636 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFE, 43430A1), 637 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455), 638 BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354), 639 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 640 BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373) 641 }; 642 643 static void pkt_align(struct sk_buff *p, int len, int align) 644 { 645 uint datalign; 646 datalign = (unsigned long)(p->data); 647 datalign = roundup(datalign, (align)) - datalign; 648 if (datalign) 649 skb_pull(p, datalign); 650 __skb_trim(p, len); 651 } 652 653 /* To check if there's window offered */ 654 static bool data_ok(struct brcmf_sdio *bus) 655 { 656 return (u8)(bus->tx_max - bus->tx_seq) != 0 && 657 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0; 658 } 659 660 static int 661 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on) 662 { 663 u8 wr_val = 0, rd_val, cmp_val, bmask; 664 int err = 0; 665 int err_cnt = 0; 666 int try_cnt = 0; 667 668 brcmf_dbg(TRACE, "Enter: on=%d\n", on); 669 670 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); 671 /* 1st KSO write goes to AOS wake up core if device is asleep */ 672 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err); 673 674 if (on) { 675 /* device WAKEUP through KSO: 676 * write bit 0 & read back until 677 * both bits 0 (kso bit) & 1 (dev on status) are set 678 */ 679 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | 680 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK; 681 bmask = cmp_val; 682 usleep_range(2000, 3000); 683 } else { 684 /* Put device to sleep, turn off KSO */ 685 cmp_val = 0; 686 /* only check for bit0, bit1(dev on status) may not 687 * get cleared right away 688 */ 689 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK; 690 } 691 692 do { 693 /* reliable KSO bit set/clr: 694 * the sdiod sleep write access is synced to PMU 32khz clk 695 * just one write attempt may fail, 696 * read it back until it matches written value 697 */ 698 rd_val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 699 &err); 700 if (!err) { 701 if ((rd_val & bmask) == cmp_val) 702 break; 703 err_cnt = 0; 704 } 705 /* bail out upon subsequent access errors */ 706 if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS)) 707 break; 708 709 udelay(KSO_WAIT_US); 710 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, 711 &err); 712 713 } while (try_cnt++ < MAX_KSO_ATTEMPTS); 714 715 if (try_cnt > 2) 716 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt, 717 rd_val, err); 718 719 if (try_cnt > MAX_KSO_ATTEMPTS) 720 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err); 721 722 return err; 723 } 724 725 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) 726 727 /* Turn backplane clock on or off */ 728 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok) 729 { 730 int err; 731 u8 clkctl, clkreq, devctl; 732 unsigned long timeout; 733 734 brcmf_dbg(SDIO, "Enter\n"); 735 736 clkctl = 0; 737 738 if (bus->sr_enabled) { 739 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY); 740 return 0; 741 } 742 743 if (on) { 744 /* Request HT Avail */ 745 clkreq = 746 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; 747 748 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 749 clkreq, &err); 750 if (err) { 751 brcmf_err("HT Avail request error: %d\n", err); 752 return -EBADE; 753 } 754 755 /* Check current status */ 756 clkctl = brcmf_sdiod_readb(bus->sdiodev, 757 SBSDIO_FUNC1_CHIPCLKCSR, &err); 758 if (err) { 759 brcmf_err("HT Avail read error: %d\n", err); 760 return -EBADE; 761 } 762 763 /* Go to pending and await interrupt if appropriate */ 764 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { 765 /* Allow only clock-available interrupt */ 766 devctl = brcmf_sdiod_readb(bus->sdiodev, 767 SBSDIO_DEVICE_CTL, &err); 768 if (err) { 769 brcmf_err("Devctl error setting CA: %d\n", err); 770 return -EBADE; 771 } 772 773 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; 774 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 775 devctl, &err); 776 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n"); 777 bus->clkstate = CLK_PENDING; 778 779 return 0; 780 } else if (bus->clkstate == CLK_PENDING) { 781 /* Cancel CA-only interrupt filter */ 782 devctl = brcmf_sdiod_readb(bus->sdiodev, 783 SBSDIO_DEVICE_CTL, &err); 784 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 785 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 786 devctl, &err); 787 } 788 789 /* Otherwise, wait here (polling) for HT Avail */ 790 timeout = jiffies + 791 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); 792 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 793 clkctl = brcmf_sdiod_readb(bus->sdiodev, 794 SBSDIO_FUNC1_CHIPCLKCSR, 795 &err); 796 if (time_after(jiffies, timeout)) 797 break; 798 else 799 usleep_range(5000, 10000); 800 } 801 if (err) { 802 brcmf_err("HT Avail request error: %d\n", err); 803 return -EBADE; 804 } 805 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 806 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n", 807 PMU_MAX_TRANSITION_DLY, clkctl); 808 return -EBADE; 809 } 810 811 /* Mark clock available */ 812 bus->clkstate = CLK_AVAIL; 813 brcmf_dbg(SDIO, "CLKCTL: turned ON\n"); 814 815 #if defined(DEBUG) 816 if (!bus->alp_only) { 817 if (SBSDIO_ALPONLY(clkctl)) 818 brcmf_err("HT Clock should be on\n"); 819 } 820 #endif /* defined (DEBUG) */ 821 822 } else { 823 clkreq = 0; 824 825 if (bus->clkstate == CLK_PENDING) { 826 /* Cancel CA-only interrupt filter */ 827 devctl = brcmf_sdiod_readb(bus->sdiodev, 828 SBSDIO_DEVICE_CTL, &err); 829 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 830 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 831 devctl, &err); 832 } 833 834 bus->clkstate = CLK_SDONLY; 835 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 836 clkreq, &err); 837 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n"); 838 if (err) { 839 brcmf_err("Failed access turning clock off: %d\n", 840 err); 841 return -EBADE; 842 } 843 } 844 return 0; 845 } 846 847 /* Change idle/active SD state */ 848 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on) 849 { 850 brcmf_dbg(SDIO, "Enter\n"); 851 852 if (on) 853 bus->clkstate = CLK_SDONLY; 854 else 855 bus->clkstate = CLK_NONE; 856 857 return 0; 858 } 859 860 /* Transition SD and backplane clock readiness */ 861 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) 862 { 863 #ifdef DEBUG 864 uint oldstate = bus->clkstate; 865 #endif /* DEBUG */ 866 867 brcmf_dbg(SDIO, "Enter\n"); 868 869 /* Early exit if we're already there */ 870 if (bus->clkstate == target) 871 return 0; 872 873 switch (target) { 874 case CLK_AVAIL: 875 /* Make sure SD clock is available */ 876 if (bus->clkstate == CLK_NONE) 877 brcmf_sdio_sdclk(bus, true); 878 /* Now request HT Avail on the backplane */ 879 brcmf_sdio_htclk(bus, true, pendok); 880 break; 881 882 case CLK_SDONLY: 883 /* Remove HT request, or bring up SD clock */ 884 if (bus->clkstate == CLK_NONE) 885 brcmf_sdio_sdclk(bus, true); 886 else if (bus->clkstate == CLK_AVAIL) 887 brcmf_sdio_htclk(bus, false, false); 888 else 889 brcmf_err("request for %d -> %d\n", 890 bus->clkstate, target); 891 break; 892 893 case CLK_NONE: 894 /* Make sure to remove HT request */ 895 if (bus->clkstate == CLK_AVAIL) 896 brcmf_sdio_htclk(bus, false, false); 897 /* Now remove the SD clock */ 898 brcmf_sdio_sdclk(bus, false); 899 break; 900 } 901 #ifdef DEBUG 902 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate); 903 #endif /* DEBUG */ 904 905 return 0; 906 } 907 908 static int 909 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok) 910 { 911 int err = 0; 912 u8 clkcsr; 913 914 brcmf_dbg(SDIO, "Enter: request %s currently %s\n", 915 (sleep ? "SLEEP" : "WAKE"), 916 (bus->sleeping ? "SLEEP" : "WAKE")); 917 918 /* If SR is enabled control bus state with KSO */ 919 if (bus->sr_enabled) { 920 /* Done if we're already in the requested state */ 921 if (sleep == bus->sleeping) 922 goto end; 923 924 /* Going to sleep */ 925 if (sleep) { 926 clkcsr = brcmf_sdiod_readb(bus->sdiodev, 927 SBSDIO_FUNC1_CHIPCLKCSR, 928 &err); 929 if ((clkcsr & SBSDIO_CSR_MASK) == 0) { 930 brcmf_dbg(SDIO, "no clock, set ALP\n"); 931 brcmf_sdiod_writeb(bus->sdiodev, 932 SBSDIO_FUNC1_CHIPCLKCSR, 933 SBSDIO_ALP_AVAIL_REQ, &err); 934 } 935 err = brcmf_sdio_kso_control(bus, false); 936 } else { 937 err = brcmf_sdio_kso_control(bus, true); 938 } 939 if (err) { 940 brcmf_err("error while changing bus sleep state %d\n", 941 err); 942 goto done; 943 } 944 } 945 946 end: 947 /* control clocks */ 948 if (sleep) { 949 if (!bus->sr_enabled) 950 brcmf_sdio_clkctl(bus, CLK_NONE, pendok); 951 } else { 952 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok); 953 brcmf_sdio_wd_timer(bus, true); 954 } 955 bus->sleeping = sleep; 956 brcmf_dbg(SDIO, "new state %s\n", 957 (sleep ? "SLEEP" : "WAKE")); 958 done: 959 brcmf_dbg(SDIO, "Exit: err=%d\n", err); 960 return err; 961 962 } 963 964 #ifdef DEBUG 965 static inline bool brcmf_sdio_valid_shared_address(u32 addr) 966 { 967 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)); 968 } 969 970 static int brcmf_sdio_readshared(struct brcmf_sdio *bus, 971 struct sdpcm_shared *sh) 972 { 973 u32 addr = 0; 974 int rv; 975 u32 shaddr = 0; 976 struct sdpcm_shared_le sh_le; 977 __le32 addr_le; 978 979 sdio_claim_host(bus->sdiodev->func1); 980 brcmf_sdio_bus_sleep(bus, false, false); 981 982 /* 983 * Read last word in socram to determine 984 * address of sdpcm_shared structure 985 */ 986 shaddr = bus->ci->rambase + bus->ci->ramsize - 4; 987 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci)) 988 shaddr -= bus->ci->srsize; 989 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, 990 (u8 *)&addr_le, 4); 991 if (rv < 0) 992 goto fail; 993 994 /* 995 * Check if addr is valid. 996 * NVRAM length at the end of memory should have been overwritten. 997 */ 998 addr = le32_to_cpu(addr_le); 999 if (!brcmf_sdio_valid_shared_address(addr)) { 1000 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr); 1001 rv = -EINVAL; 1002 goto fail; 1003 } 1004 1005 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr); 1006 1007 /* Read hndrte_shared structure */ 1008 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le, 1009 sizeof(struct sdpcm_shared_le)); 1010 if (rv < 0) 1011 goto fail; 1012 1013 sdio_release_host(bus->sdiodev->func1); 1014 1015 /* Endianness */ 1016 sh->flags = le32_to_cpu(sh_le.flags); 1017 sh->trap_addr = le32_to_cpu(sh_le.trap_addr); 1018 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr); 1019 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr); 1020 sh->assert_line = le32_to_cpu(sh_le.assert_line); 1021 sh->console_addr = le32_to_cpu(sh_le.console_addr); 1022 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr); 1023 1024 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) { 1025 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n", 1026 SDPCM_SHARED_VERSION, 1027 sh->flags & SDPCM_SHARED_VERSION_MASK); 1028 return -EPROTO; 1029 } 1030 return 0; 1031 1032 fail: 1033 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n", 1034 rv, addr); 1035 sdio_release_host(bus->sdiodev->func1); 1036 return rv; 1037 } 1038 1039 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) 1040 { 1041 struct sdpcm_shared sh; 1042 1043 if (brcmf_sdio_readshared(bus, &sh) == 0) 1044 bus->console_addr = sh.console_addr; 1045 } 1046 #else 1047 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) 1048 { 1049 } 1050 #endif /* DEBUG */ 1051 1052 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus) 1053 { 1054 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 1055 struct brcmf_core *core = bus->sdio_core; 1056 u32 intstatus = 0; 1057 u32 hmb_data; 1058 u8 fcbits; 1059 int ret; 1060 1061 brcmf_dbg(SDIO, "Enter\n"); 1062 1063 /* Read mailbox data and ack that we did so */ 1064 hmb_data = brcmf_sdiod_readl(sdiod, 1065 core->base + SD_REG(tohostmailboxdata), 1066 &ret); 1067 1068 if (!ret) 1069 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox), 1070 SMB_INT_ACK, &ret); 1071 1072 bus->sdcnt.f1regdata += 2; 1073 1074 /* dongle indicates the firmware has halted/crashed */ 1075 if (hmb_data & HMB_DATA_FWHALT) { 1076 brcmf_err("mailbox indicates firmware halted\n"); 1077 brcmf_dev_coredump(&sdiod->func1->dev); 1078 } 1079 1080 /* Dongle recomposed rx frames, accept them again */ 1081 if (hmb_data & HMB_DATA_NAKHANDLED) { 1082 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n", 1083 bus->rx_seq); 1084 if (!bus->rxskip) 1085 brcmf_err("unexpected NAKHANDLED!\n"); 1086 1087 bus->rxskip = false; 1088 intstatus |= I_HMB_FRAME_IND; 1089 } 1090 1091 /* 1092 * DEVREADY does not occur with gSPI. 1093 */ 1094 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { 1095 bus->sdpcm_ver = 1096 (hmb_data & HMB_DATA_VERSION_MASK) >> 1097 HMB_DATA_VERSION_SHIFT; 1098 if (bus->sdpcm_ver != SDPCM_PROT_VERSION) 1099 brcmf_err("Version mismatch, dongle reports %d, " 1100 "expecting %d\n", 1101 bus->sdpcm_ver, SDPCM_PROT_VERSION); 1102 else 1103 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n", 1104 bus->sdpcm_ver); 1105 1106 /* 1107 * Retrieve console state address now that firmware should have 1108 * updated it. 1109 */ 1110 brcmf_sdio_get_console_addr(bus); 1111 } 1112 1113 /* 1114 * Flow Control has been moved into the RX headers and this out of band 1115 * method isn't used any more. 1116 * remaining backward compatible with older dongles. 1117 */ 1118 if (hmb_data & HMB_DATA_FC) { 1119 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> 1120 HMB_DATA_FCDATA_SHIFT; 1121 1122 if (fcbits & ~bus->flowcontrol) 1123 bus->sdcnt.fc_xoff++; 1124 1125 if (bus->flowcontrol & ~fcbits) 1126 bus->sdcnt.fc_xon++; 1127 1128 bus->sdcnt.fc_rcvd++; 1129 bus->flowcontrol = fcbits; 1130 } 1131 1132 /* Shouldn't be any others */ 1133 if (hmb_data & ~(HMB_DATA_DEVREADY | 1134 HMB_DATA_NAKHANDLED | 1135 HMB_DATA_FC | 1136 HMB_DATA_FWREADY | 1137 HMB_DATA_FWHALT | 1138 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) 1139 brcmf_err("Unknown mailbox data content: 0x%02x\n", 1140 hmb_data); 1141 1142 return intstatus; 1143 } 1144 1145 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) 1146 { 1147 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 1148 struct brcmf_core *core = bus->sdio_core; 1149 uint retries = 0; 1150 u16 lastrbc; 1151 u8 hi, lo; 1152 int err; 1153 1154 brcmf_err("%sterminate frame%s\n", 1155 abort ? "abort command, " : "", 1156 rtx ? ", send NAK" : ""); 1157 1158 if (abort) 1159 brcmf_sdiod_abort(bus->sdiodev, bus->sdiodev->func2); 1160 1161 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM, 1162 &err); 1163 bus->sdcnt.f1regdata++; 1164 1165 /* Wait until the packet has been flushed (device/FIFO stable) */ 1166 for (lastrbc = retries = 0xffff; retries > 0; retries--) { 1167 hi = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCHI, 1168 &err); 1169 lo = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCLO, 1170 &err); 1171 bus->sdcnt.f1regdata += 2; 1172 1173 if ((hi == 0) && (lo == 0)) 1174 break; 1175 1176 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { 1177 brcmf_err("count growing: last 0x%04x now 0x%04x\n", 1178 lastrbc, (hi << 8) + lo); 1179 } 1180 lastrbc = (hi << 8) + lo; 1181 } 1182 1183 if (!retries) 1184 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc); 1185 else 1186 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries); 1187 1188 if (rtx) { 1189 bus->sdcnt.rxrtx++; 1190 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox), 1191 SMB_NAK, &err); 1192 1193 bus->sdcnt.f1regdata++; 1194 if (err == 0) 1195 bus->rxskip = true; 1196 } 1197 1198 /* Clear partial in any case */ 1199 bus->cur_read.len = 0; 1200 } 1201 1202 static void brcmf_sdio_txfail(struct brcmf_sdio *bus) 1203 { 1204 struct brcmf_sdio_dev *sdiodev = bus->sdiodev; 1205 u8 i, hi, lo; 1206 1207 /* On failure, abort the command and terminate the frame */ 1208 brcmf_err("sdio error, abort command and terminate frame\n"); 1209 bus->sdcnt.tx_sderrs++; 1210 1211 brcmf_sdiod_abort(sdiodev, sdiodev->func2); 1212 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL); 1213 bus->sdcnt.f1regdata++; 1214 1215 for (i = 0; i < 3; i++) { 1216 hi = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL); 1217 lo = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL); 1218 bus->sdcnt.f1regdata += 2; 1219 if ((hi == 0) && (lo == 0)) 1220 break; 1221 } 1222 } 1223 1224 /* return total length of buffer chain */ 1225 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus) 1226 { 1227 struct sk_buff *p; 1228 uint total; 1229 1230 total = 0; 1231 skb_queue_walk(&bus->glom, p) 1232 total += p->len; 1233 return total; 1234 } 1235 1236 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus) 1237 { 1238 struct sk_buff *cur, *next; 1239 1240 skb_queue_walk_safe(&bus->glom, cur, next) { 1241 skb_unlink(cur, &bus->glom); 1242 brcmu_pkt_buf_free_skb(cur); 1243 } 1244 } 1245 1246 /** 1247 * brcmfmac sdio bus specific header 1248 * This is the lowest layer header wrapped on the packets transmitted between 1249 * host and WiFi dongle which contains information needed for SDIO core and 1250 * firmware 1251 * 1252 * It consists of 3 parts: hardware header, hardware extension header and 1253 * software header 1254 * hardware header (frame tag) - 4 bytes 1255 * Byte 0~1: Frame length 1256 * Byte 2~3: Checksum, bit-wise inverse of frame length 1257 * hardware extension header - 8 bytes 1258 * Tx glom mode only, N/A for Rx or normal Tx 1259 * Byte 0~1: Packet length excluding hw frame tag 1260 * Byte 2: Reserved 1261 * Byte 3: Frame flags, bit 0: last frame indication 1262 * Byte 4~5: Reserved 1263 * Byte 6~7: Tail padding length 1264 * software header - 8 bytes 1265 * Byte 0: Rx/Tx sequence number 1266 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag 1267 * Byte 2: Length of next data frame, reserved for Tx 1268 * Byte 3: Data offset 1269 * Byte 4: Flow control bits, reserved for Tx 1270 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet 1271 * Byte 6~7: Reserved 1272 */ 1273 #define SDPCM_HWHDR_LEN 4 1274 #define SDPCM_HWEXT_LEN 8 1275 #define SDPCM_SWHDR_LEN 8 1276 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN) 1277 /* software header */ 1278 #define SDPCM_SEQ_MASK 0x000000ff 1279 #define SDPCM_SEQ_WRAP 256 1280 #define SDPCM_CHANNEL_MASK 0x00000f00 1281 #define SDPCM_CHANNEL_SHIFT 8 1282 #define SDPCM_CONTROL_CHANNEL 0 /* Control */ 1283 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */ 1284 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */ 1285 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */ 1286 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */ 1287 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) 1288 #define SDPCM_NEXTLEN_MASK 0x00ff0000 1289 #define SDPCM_NEXTLEN_SHIFT 16 1290 #define SDPCM_DOFFSET_MASK 0xff000000 1291 #define SDPCM_DOFFSET_SHIFT 24 1292 #define SDPCM_FCMASK_MASK 0x000000ff 1293 #define SDPCM_WINDOW_MASK 0x0000ff00 1294 #define SDPCM_WINDOW_SHIFT 8 1295 1296 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader) 1297 { 1298 u32 hdrvalue; 1299 hdrvalue = *(u32 *)swheader; 1300 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT); 1301 } 1302 1303 static inline bool brcmf_sdio_fromevntchan(u8 *swheader) 1304 { 1305 u32 hdrvalue; 1306 u8 ret; 1307 1308 hdrvalue = *(u32 *)swheader; 1309 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT); 1310 1311 return (ret == SDPCM_EVENT_CHANNEL); 1312 } 1313 1314 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header, 1315 struct brcmf_sdio_hdrinfo *rd, 1316 enum brcmf_sdio_frmtype type) 1317 { 1318 u16 len, checksum; 1319 u8 rx_seq, fc, tx_seq_max; 1320 u32 swheader; 1321 1322 trace_brcmf_sdpcm_hdr(SDPCM_RX, header); 1323 1324 /* hw header */ 1325 len = get_unaligned_le16(header); 1326 checksum = get_unaligned_le16(header + sizeof(u16)); 1327 /* All zero means no more to read */ 1328 if (!(len | checksum)) { 1329 bus->rxpending = false; 1330 return -ENODATA; 1331 } 1332 if ((u16)(~(len ^ checksum))) { 1333 brcmf_err("HW header checksum error\n"); 1334 bus->sdcnt.rx_badhdr++; 1335 brcmf_sdio_rxfail(bus, false, false); 1336 return -EIO; 1337 } 1338 if (len < SDPCM_HDRLEN) { 1339 brcmf_err("HW header length error\n"); 1340 return -EPROTO; 1341 } 1342 if (type == BRCMF_SDIO_FT_SUPER && 1343 (roundup(len, bus->blocksize) != rd->len)) { 1344 brcmf_err("HW superframe header length error\n"); 1345 return -EPROTO; 1346 } 1347 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) { 1348 brcmf_err("HW subframe header length error\n"); 1349 return -EPROTO; 1350 } 1351 rd->len = len; 1352 1353 /* software header */ 1354 header += SDPCM_HWHDR_LEN; 1355 swheader = le32_to_cpu(*(__le32 *)header); 1356 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) { 1357 brcmf_err("Glom descriptor found in superframe head\n"); 1358 rd->len = 0; 1359 return -EINVAL; 1360 } 1361 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK); 1362 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT; 1363 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL && 1364 type != BRCMF_SDIO_FT_SUPER) { 1365 brcmf_err("HW header length too long\n"); 1366 bus->sdcnt.rx_toolong++; 1367 brcmf_sdio_rxfail(bus, false, false); 1368 rd->len = 0; 1369 return -EPROTO; 1370 } 1371 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) { 1372 brcmf_err("Wrong channel for superframe\n"); 1373 rd->len = 0; 1374 return -EINVAL; 1375 } 1376 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL && 1377 rd->channel != SDPCM_EVENT_CHANNEL) { 1378 brcmf_err("Wrong channel for subframe\n"); 1379 rd->len = 0; 1380 return -EINVAL; 1381 } 1382 rd->dat_offset = brcmf_sdio_getdatoffset(header); 1383 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) { 1384 brcmf_err("seq %d: bad data offset\n", rx_seq); 1385 bus->sdcnt.rx_badhdr++; 1386 brcmf_sdio_rxfail(bus, false, false); 1387 rd->len = 0; 1388 return -ENXIO; 1389 } 1390 if (rd->seq_num != rx_seq) { 1391 brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num); 1392 bus->sdcnt.rx_badseq++; 1393 rd->seq_num = rx_seq; 1394 } 1395 /* no need to check the reset for subframe */ 1396 if (type == BRCMF_SDIO_FT_SUB) 1397 return 0; 1398 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT; 1399 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) { 1400 /* only warm for NON glom packet */ 1401 if (rd->channel != SDPCM_GLOM_CHANNEL) 1402 brcmf_err("seq %d: next length error\n", rx_seq); 1403 rd->len_nxtfrm = 0; 1404 } 1405 swheader = le32_to_cpu(*(__le32 *)(header + 4)); 1406 fc = swheader & SDPCM_FCMASK_MASK; 1407 if (bus->flowcontrol != fc) { 1408 if (~bus->flowcontrol & fc) 1409 bus->sdcnt.fc_xoff++; 1410 if (bus->flowcontrol & ~fc) 1411 bus->sdcnt.fc_xon++; 1412 bus->sdcnt.fc_rcvd++; 1413 bus->flowcontrol = fc; 1414 } 1415 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT; 1416 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) { 1417 brcmf_err("seq %d: max tx seq number error\n", rx_seq); 1418 tx_seq_max = bus->tx_seq + 2; 1419 } 1420 bus->tx_max = tx_seq_max; 1421 1422 return 0; 1423 } 1424 1425 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length) 1426 { 1427 *(__le16 *)header = cpu_to_le16(frm_length); 1428 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length); 1429 } 1430 1431 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header, 1432 struct brcmf_sdio_hdrinfo *hd_info) 1433 { 1434 u32 hdrval; 1435 u8 hdr_offset; 1436 1437 brcmf_sdio_update_hwhdr(header, hd_info->len); 1438 hdr_offset = SDPCM_HWHDR_LEN; 1439 1440 if (bus->txglom) { 1441 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24); 1442 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); 1443 hdrval = (u16)hd_info->tail_pad << 16; 1444 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval); 1445 hdr_offset += SDPCM_HWEXT_LEN; 1446 } 1447 1448 hdrval = hd_info->seq_num; 1449 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) & 1450 SDPCM_CHANNEL_MASK; 1451 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) & 1452 SDPCM_DOFFSET_MASK; 1453 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); 1454 *(((__le32 *)(header + hdr_offset)) + 1) = 0; 1455 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header); 1456 } 1457 1458 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq) 1459 { 1460 u16 dlen, totlen; 1461 u8 *dptr, num = 0; 1462 u16 sublen; 1463 struct sk_buff *pfirst, *pnext; 1464 1465 int errcode; 1466 u8 doff; 1467 1468 struct brcmf_sdio_hdrinfo rd_new; 1469 1470 /* If packets, issue read(s) and send up packet chain */ 1471 /* Return sequence numbers consumed? */ 1472 1473 brcmf_dbg(SDIO, "start: glomd %p glom %p\n", 1474 bus->glomd, skb_peek(&bus->glom)); 1475 1476 /* If there's a descriptor, generate the packet chain */ 1477 if (bus->glomd) { 1478 pfirst = pnext = NULL; 1479 dlen = (u16) (bus->glomd->len); 1480 dptr = bus->glomd->data; 1481 if (!dlen || (dlen & 1)) { 1482 brcmf_err("bad glomd len(%d), ignore descriptor\n", 1483 dlen); 1484 dlen = 0; 1485 } 1486 1487 for (totlen = num = 0; dlen; num++) { 1488 /* Get (and move past) next length */ 1489 sublen = get_unaligned_le16(dptr); 1490 dlen -= sizeof(u16); 1491 dptr += sizeof(u16); 1492 if ((sublen < SDPCM_HDRLEN) || 1493 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { 1494 brcmf_err("descriptor len %d bad: %d\n", 1495 num, sublen); 1496 pnext = NULL; 1497 break; 1498 } 1499 if (sublen % bus->sgentry_align) { 1500 brcmf_err("sublen %d not multiple of %d\n", 1501 sublen, bus->sgentry_align); 1502 } 1503 totlen += sublen; 1504 1505 /* For last frame, adjust read len so total 1506 is a block multiple */ 1507 if (!dlen) { 1508 sublen += 1509 (roundup(totlen, bus->blocksize) - totlen); 1510 totlen = roundup(totlen, bus->blocksize); 1511 } 1512 1513 /* Allocate/chain packet for next subframe */ 1514 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align); 1515 if (pnext == NULL) { 1516 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n", 1517 num, sublen); 1518 break; 1519 } 1520 skb_queue_tail(&bus->glom, pnext); 1521 1522 /* Adhere to start alignment requirements */ 1523 pkt_align(pnext, sublen, bus->sgentry_align); 1524 } 1525 1526 /* If all allocations succeeded, save packet chain 1527 in bus structure */ 1528 if (pnext) { 1529 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", 1530 totlen, num); 1531 if (BRCMF_GLOM_ON() && bus->cur_read.len && 1532 totlen != bus->cur_read.len) { 1533 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", 1534 bus->cur_read.len, totlen, rxseq); 1535 } 1536 pfirst = pnext = NULL; 1537 } else { 1538 brcmf_sdio_free_glom(bus); 1539 num = 0; 1540 } 1541 1542 /* Done with descriptor packet */ 1543 brcmu_pkt_buf_free_skb(bus->glomd); 1544 bus->glomd = NULL; 1545 bus->cur_read.len = 0; 1546 } 1547 1548 /* Ok -- either we just generated a packet chain, 1549 or had one from before */ 1550 if (!skb_queue_empty(&bus->glom)) { 1551 if (BRCMF_GLOM_ON()) { 1552 brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); 1553 skb_queue_walk(&bus->glom, pnext) { 1554 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", 1555 pnext, (u8 *) (pnext->data), 1556 pnext->len, pnext->len); 1557 } 1558 } 1559 1560 pfirst = skb_peek(&bus->glom); 1561 dlen = (u16) brcmf_sdio_glom_len(bus); 1562 1563 /* Do an SDIO read for the superframe. Configurable iovar to 1564 * read directly into the chained packet, or allocate a large 1565 * packet and and copy into the chain. 1566 */ 1567 sdio_claim_host(bus->sdiodev->func1); 1568 errcode = brcmf_sdiod_recv_chain(bus->sdiodev, 1569 &bus->glom, dlen); 1570 sdio_release_host(bus->sdiodev->func1); 1571 bus->sdcnt.f2rxdata++; 1572 1573 /* On failure, kill the superframe */ 1574 if (errcode < 0) { 1575 brcmf_err("glom read of %d bytes failed: %d\n", 1576 dlen, errcode); 1577 1578 sdio_claim_host(bus->sdiodev->func1); 1579 brcmf_sdio_rxfail(bus, true, false); 1580 bus->sdcnt.rxglomfail++; 1581 brcmf_sdio_free_glom(bus); 1582 sdio_release_host(bus->sdiodev->func1); 1583 return 0; 1584 } 1585 1586 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1587 pfirst->data, min_t(int, pfirst->len, 48), 1588 "SUPERFRAME:\n"); 1589 1590 rd_new.seq_num = rxseq; 1591 rd_new.len = dlen; 1592 sdio_claim_host(bus->sdiodev->func1); 1593 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new, 1594 BRCMF_SDIO_FT_SUPER); 1595 sdio_release_host(bus->sdiodev->func1); 1596 bus->cur_read.len = rd_new.len_nxtfrm << 4; 1597 1598 /* Remove superframe header, remember offset */ 1599 skb_pull(pfirst, rd_new.dat_offset); 1600 num = 0; 1601 1602 /* Validate all the subframe headers */ 1603 skb_queue_walk(&bus->glom, pnext) { 1604 /* leave when invalid subframe is found */ 1605 if (errcode) 1606 break; 1607 1608 rd_new.len = pnext->len; 1609 rd_new.seq_num = rxseq++; 1610 sdio_claim_host(bus->sdiodev->func1); 1611 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new, 1612 BRCMF_SDIO_FT_SUB); 1613 sdio_release_host(bus->sdiodev->func1); 1614 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1615 pnext->data, 32, "subframe:\n"); 1616 1617 num++; 1618 } 1619 1620 if (errcode) { 1621 /* Terminate frame on error */ 1622 sdio_claim_host(bus->sdiodev->func1); 1623 brcmf_sdio_rxfail(bus, true, false); 1624 bus->sdcnt.rxglomfail++; 1625 brcmf_sdio_free_glom(bus); 1626 sdio_release_host(bus->sdiodev->func1); 1627 bus->cur_read.len = 0; 1628 return 0; 1629 } 1630 1631 /* Basic SD framing looks ok - process each packet (header) */ 1632 1633 skb_queue_walk_safe(&bus->glom, pfirst, pnext) { 1634 dptr = (u8 *) (pfirst->data); 1635 sublen = get_unaligned_le16(dptr); 1636 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]); 1637 1638 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), 1639 dptr, pfirst->len, 1640 "Rx Subframe Data:\n"); 1641 1642 __skb_trim(pfirst, sublen); 1643 skb_pull(pfirst, doff); 1644 1645 if (pfirst->len == 0) { 1646 skb_unlink(pfirst, &bus->glom); 1647 brcmu_pkt_buf_free_skb(pfirst); 1648 continue; 1649 } 1650 1651 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1652 pfirst->data, 1653 min_t(int, pfirst->len, 32), 1654 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", 1655 bus->glom.qlen, pfirst, pfirst->data, 1656 pfirst->len, pfirst->next, 1657 pfirst->prev); 1658 skb_unlink(pfirst, &bus->glom); 1659 if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN])) 1660 brcmf_rx_event(bus->sdiodev->dev, pfirst); 1661 else 1662 brcmf_rx_frame(bus->sdiodev->dev, pfirst, 1663 false); 1664 bus->sdcnt.rxglompkts++; 1665 } 1666 1667 bus->sdcnt.rxglomframes++; 1668 } 1669 return num; 1670 } 1671 1672 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, 1673 bool *pending) 1674 { 1675 DECLARE_WAITQUEUE(wait, current); 1676 int timeout = DCMD_RESP_TIMEOUT; 1677 1678 /* Wait until control frame is available */ 1679 add_wait_queue(&bus->dcmd_resp_wait, &wait); 1680 set_current_state(TASK_INTERRUPTIBLE); 1681 1682 while (!(*condition) && (!signal_pending(current) && timeout)) 1683 timeout = schedule_timeout(timeout); 1684 1685 if (signal_pending(current)) 1686 *pending = true; 1687 1688 set_current_state(TASK_RUNNING); 1689 remove_wait_queue(&bus->dcmd_resp_wait, &wait); 1690 1691 return timeout; 1692 } 1693 1694 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus) 1695 { 1696 wake_up_interruptible(&bus->dcmd_resp_wait); 1697 1698 return 0; 1699 } 1700 static void 1701 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) 1702 { 1703 uint rdlen, pad; 1704 u8 *buf = NULL, *rbuf; 1705 int sdret; 1706 1707 brcmf_dbg(SDIO, "Enter\n"); 1708 if (bus->rxblen) 1709 buf = vzalloc(bus->rxblen); 1710 if (!buf) 1711 goto done; 1712 1713 rbuf = bus->rxbuf; 1714 pad = ((unsigned long)rbuf % bus->head_align); 1715 if (pad) 1716 rbuf += (bus->head_align - pad); 1717 1718 /* Copy the already-read portion over */ 1719 memcpy(buf, hdr, BRCMF_FIRSTREAD); 1720 if (len <= BRCMF_FIRSTREAD) 1721 goto gotpkt; 1722 1723 /* Raise rdlen to next SDIO block to avoid tail command */ 1724 rdlen = len - BRCMF_FIRSTREAD; 1725 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { 1726 pad = bus->blocksize - (rdlen % bus->blocksize); 1727 if ((pad <= bus->roundup) && (pad < bus->blocksize) && 1728 ((len + pad) < bus->sdiodev->bus_if->maxctl)) 1729 rdlen += pad; 1730 } else if (rdlen % bus->head_align) { 1731 rdlen += bus->head_align - (rdlen % bus->head_align); 1732 } 1733 1734 /* Drop if the read is too big or it exceeds our maximum */ 1735 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) { 1736 brcmf_err("%d-byte control read exceeds %d-byte buffer\n", 1737 rdlen, bus->sdiodev->bus_if->maxctl); 1738 brcmf_sdio_rxfail(bus, false, false); 1739 goto done; 1740 } 1741 1742 if ((len - doff) > bus->sdiodev->bus_if->maxctl) { 1743 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", 1744 len, len - doff, bus->sdiodev->bus_if->maxctl); 1745 bus->sdcnt.rx_toolong++; 1746 brcmf_sdio_rxfail(bus, false, false); 1747 goto done; 1748 } 1749 1750 /* Read remain of frame body */ 1751 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen); 1752 bus->sdcnt.f2rxdata++; 1753 1754 /* Control frame failures need retransmission */ 1755 if (sdret < 0) { 1756 brcmf_err("read %d control bytes failed: %d\n", 1757 rdlen, sdret); 1758 bus->sdcnt.rxc_errors++; 1759 brcmf_sdio_rxfail(bus, true, true); 1760 goto done; 1761 } else 1762 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen); 1763 1764 gotpkt: 1765 1766 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), 1767 buf, len, "RxCtrl:\n"); 1768 1769 /* Point to valid data and indicate its length */ 1770 spin_lock_bh(&bus->rxctl_lock); 1771 if (bus->rxctl) { 1772 brcmf_err("last control frame is being processed.\n"); 1773 spin_unlock_bh(&bus->rxctl_lock); 1774 vfree(buf); 1775 goto done; 1776 } 1777 bus->rxctl = buf + doff; 1778 bus->rxctl_orig = buf; 1779 bus->rxlen = len - doff; 1780 spin_unlock_bh(&bus->rxctl_lock); 1781 1782 done: 1783 /* Awake any waiters */ 1784 brcmf_sdio_dcmd_resp_wake(bus); 1785 } 1786 1787 /* Pad read to blocksize for efficiency */ 1788 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) 1789 { 1790 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { 1791 *pad = bus->blocksize - (*rdlen % bus->blocksize); 1792 if (*pad <= bus->roundup && *pad < bus->blocksize && 1793 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) 1794 *rdlen += *pad; 1795 } else if (*rdlen % bus->head_align) { 1796 *rdlen += bus->head_align - (*rdlen % bus->head_align); 1797 } 1798 } 1799 1800 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes) 1801 { 1802 struct sk_buff *pkt; /* Packet for event or data frames */ 1803 u16 pad; /* Number of pad bytes to read */ 1804 uint rxleft = 0; /* Remaining number of frames allowed */ 1805 int ret; /* Return code from calls */ 1806 uint rxcount = 0; /* Total frames read */ 1807 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new; 1808 u8 head_read = 0; 1809 1810 brcmf_dbg(SDIO, "Enter\n"); 1811 1812 /* Not finished unless we encounter no more frames indication */ 1813 bus->rxpending = true; 1814 1815 for (rd->seq_num = bus->rx_seq, rxleft = maxframes; 1816 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA; 1817 rd->seq_num++, rxleft--) { 1818 1819 /* Handle glomming separately */ 1820 if (bus->glomd || !skb_queue_empty(&bus->glom)) { 1821 u8 cnt; 1822 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", 1823 bus->glomd, skb_peek(&bus->glom)); 1824 cnt = brcmf_sdio_rxglom(bus, rd->seq_num); 1825 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); 1826 rd->seq_num += cnt - 1; 1827 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; 1828 continue; 1829 } 1830 1831 rd->len_left = rd->len; 1832 /* read header first for unknow frame length */ 1833 sdio_claim_host(bus->sdiodev->func1); 1834 if (!rd->len) { 1835 ret = brcmf_sdiod_recv_buf(bus->sdiodev, 1836 bus->rxhdr, BRCMF_FIRSTREAD); 1837 bus->sdcnt.f2rxhdrs++; 1838 if (ret < 0) { 1839 brcmf_err("RXHEADER FAILED: %d\n", 1840 ret); 1841 bus->sdcnt.rx_hdrfail++; 1842 brcmf_sdio_rxfail(bus, true, true); 1843 sdio_release_host(bus->sdiodev->func1); 1844 continue; 1845 } 1846 1847 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(), 1848 bus->rxhdr, SDPCM_HDRLEN, 1849 "RxHdr:\n"); 1850 1851 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd, 1852 BRCMF_SDIO_FT_NORMAL)) { 1853 sdio_release_host(bus->sdiodev->func1); 1854 if (!bus->rxpending) 1855 break; 1856 else 1857 continue; 1858 } 1859 1860 if (rd->channel == SDPCM_CONTROL_CHANNEL) { 1861 brcmf_sdio_read_control(bus, bus->rxhdr, 1862 rd->len, 1863 rd->dat_offset); 1864 /* prepare the descriptor for the next read */ 1865 rd->len = rd->len_nxtfrm << 4; 1866 rd->len_nxtfrm = 0; 1867 /* treat all packet as event if we don't know */ 1868 rd->channel = SDPCM_EVENT_CHANNEL; 1869 sdio_release_host(bus->sdiodev->func1); 1870 continue; 1871 } 1872 rd->len_left = rd->len > BRCMF_FIRSTREAD ? 1873 rd->len - BRCMF_FIRSTREAD : 0; 1874 head_read = BRCMF_FIRSTREAD; 1875 } 1876 1877 brcmf_sdio_pad(bus, &pad, &rd->len_left); 1878 1879 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read + 1880 bus->head_align); 1881 if (!pkt) { 1882 /* Give up on data, request rtx of events */ 1883 brcmf_err("brcmu_pkt_buf_get_skb failed\n"); 1884 brcmf_sdio_rxfail(bus, false, 1885 RETRYCHAN(rd->channel)); 1886 sdio_release_host(bus->sdiodev->func1); 1887 continue; 1888 } 1889 skb_pull(pkt, head_read); 1890 pkt_align(pkt, rd->len_left, bus->head_align); 1891 1892 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt); 1893 bus->sdcnt.f2rxdata++; 1894 sdio_release_host(bus->sdiodev->func1); 1895 1896 if (ret < 0) { 1897 brcmf_err("read %d bytes from channel %d failed: %d\n", 1898 rd->len, rd->channel, ret); 1899 brcmu_pkt_buf_free_skb(pkt); 1900 sdio_claim_host(bus->sdiodev->func1); 1901 brcmf_sdio_rxfail(bus, true, 1902 RETRYCHAN(rd->channel)); 1903 sdio_release_host(bus->sdiodev->func1); 1904 continue; 1905 } 1906 1907 if (head_read) { 1908 skb_push(pkt, head_read); 1909 memcpy(pkt->data, bus->rxhdr, head_read); 1910 head_read = 0; 1911 } else { 1912 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN); 1913 rd_new.seq_num = rd->seq_num; 1914 sdio_claim_host(bus->sdiodev->func1); 1915 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new, 1916 BRCMF_SDIO_FT_NORMAL)) { 1917 rd->len = 0; 1918 brcmu_pkt_buf_free_skb(pkt); 1919 } 1920 bus->sdcnt.rx_readahead_cnt++; 1921 if (rd->len != roundup(rd_new.len, 16)) { 1922 brcmf_err("frame length mismatch:read %d, should be %d\n", 1923 rd->len, 1924 roundup(rd_new.len, 16) >> 4); 1925 rd->len = 0; 1926 brcmf_sdio_rxfail(bus, true, true); 1927 sdio_release_host(bus->sdiodev->func1); 1928 brcmu_pkt_buf_free_skb(pkt); 1929 continue; 1930 } 1931 sdio_release_host(bus->sdiodev->func1); 1932 rd->len_nxtfrm = rd_new.len_nxtfrm; 1933 rd->channel = rd_new.channel; 1934 rd->dat_offset = rd_new.dat_offset; 1935 1936 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && 1937 BRCMF_DATA_ON()) && 1938 BRCMF_HDRS_ON(), 1939 bus->rxhdr, SDPCM_HDRLEN, 1940 "RxHdr:\n"); 1941 1942 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) { 1943 brcmf_err("readahead on control packet %d?\n", 1944 rd_new.seq_num); 1945 /* Force retry w/normal header read */ 1946 rd->len = 0; 1947 sdio_claim_host(bus->sdiodev->func1); 1948 brcmf_sdio_rxfail(bus, false, true); 1949 sdio_release_host(bus->sdiodev->func1); 1950 brcmu_pkt_buf_free_skb(pkt); 1951 continue; 1952 } 1953 } 1954 1955 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), 1956 pkt->data, rd->len, "Rx Data:\n"); 1957 1958 /* Save superframe descriptor and allocate packet frame */ 1959 if (rd->channel == SDPCM_GLOM_CHANNEL) { 1960 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) { 1961 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", 1962 rd->len); 1963 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1964 pkt->data, rd->len, 1965 "Glom Data:\n"); 1966 __skb_trim(pkt, rd->len); 1967 skb_pull(pkt, SDPCM_HDRLEN); 1968 bus->glomd = pkt; 1969 } else { 1970 brcmf_err("%s: glom superframe w/o " 1971 "descriptor!\n", __func__); 1972 sdio_claim_host(bus->sdiodev->func1); 1973 brcmf_sdio_rxfail(bus, false, false); 1974 sdio_release_host(bus->sdiodev->func1); 1975 } 1976 /* prepare the descriptor for the next read */ 1977 rd->len = rd->len_nxtfrm << 4; 1978 rd->len_nxtfrm = 0; 1979 /* treat all packet as event if we don't know */ 1980 rd->channel = SDPCM_EVENT_CHANNEL; 1981 continue; 1982 } 1983 1984 /* Fill in packet len and prio, deliver upward */ 1985 __skb_trim(pkt, rd->len); 1986 skb_pull(pkt, rd->dat_offset); 1987 1988 if (pkt->len == 0) 1989 brcmu_pkt_buf_free_skb(pkt); 1990 else if (rd->channel == SDPCM_EVENT_CHANNEL) 1991 brcmf_rx_event(bus->sdiodev->dev, pkt); 1992 else 1993 brcmf_rx_frame(bus->sdiodev->dev, pkt, 1994 false); 1995 1996 /* prepare the descriptor for the next read */ 1997 rd->len = rd->len_nxtfrm << 4; 1998 rd->len_nxtfrm = 0; 1999 /* treat all packet as event if we don't know */ 2000 rd->channel = SDPCM_EVENT_CHANNEL; 2001 } 2002 2003 rxcount = maxframes - rxleft; 2004 /* Message if we hit the limit */ 2005 if (!rxleft) 2006 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes); 2007 else 2008 brcmf_dbg(DATA, "processed %d frames\n", rxcount); 2009 /* Back off rxseq if awaiting rtx, update rx_seq */ 2010 if (bus->rxskip) 2011 rd->seq_num--; 2012 bus->rx_seq = rd->seq_num; 2013 2014 return rxcount; 2015 } 2016 2017 static void 2018 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus) 2019 { 2020 wake_up_interruptible(&bus->ctrl_wait); 2021 return; 2022 } 2023 2024 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt) 2025 { 2026 struct brcmf_bus_stats *stats; 2027 u16 head_pad; 2028 u8 *dat_buf; 2029 2030 dat_buf = (u8 *)(pkt->data); 2031 2032 /* Check head padding */ 2033 head_pad = ((unsigned long)dat_buf % bus->head_align); 2034 if (head_pad) { 2035 if (skb_headroom(pkt) < head_pad) { 2036 stats = &bus->sdiodev->bus_if->stats; 2037 atomic_inc(&stats->pktcowed); 2038 if (skb_cow_head(pkt, head_pad)) { 2039 atomic_inc(&stats->pktcow_failed); 2040 return -ENOMEM; 2041 } 2042 head_pad = 0; 2043 } 2044 skb_push(pkt, head_pad); 2045 dat_buf = (u8 *)(pkt->data); 2046 } 2047 memset(dat_buf, 0, head_pad + bus->tx_hdrlen); 2048 return head_pad; 2049 } 2050 2051 /* 2052 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for 2053 * bus layer usage. 2054 */ 2055 /* flag marking a dummy skb added for DMA alignment requirement */ 2056 #define ALIGN_SKB_FLAG 0x8000 2057 /* bit mask of data length chopped from the previous packet */ 2058 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff 2059 2060 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus, 2061 struct sk_buff_head *pktq, 2062 struct sk_buff *pkt, u16 total_len) 2063 { 2064 struct brcmf_sdio_dev *sdiodev; 2065 struct sk_buff *pkt_pad; 2066 u16 tail_pad, tail_chop, chain_pad; 2067 unsigned int blksize; 2068 bool lastfrm; 2069 int ntail, ret; 2070 2071 sdiodev = bus->sdiodev; 2072 blksize = sdiodev->func2->cur_blksize; 2073 /* sg entry alignment should be a divisor of block size */ 2074 WARN_ON(blksize % bus->sgentry_align); 2075 2076 /* Check tail padding */ 2077 lastfrm = skb_queue_is_last(pktq, pkt); 2078 tail_pad = 0; 2079 tail_chop = pkt->len % bus->sgentry_align; 2080 if (tail_chop) 2081 tail_pad = bus->sgentry_align - tail_chop; 2082 chain_pad = (total_len + tail_pad) % blksize; 2083 if (lastfrm && chain_pad) 2084 tail_pad += blksize - chain_pad; 2085 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) { 2086 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop + 2087 bus->head_align); 2088 if (pkt_pad == NULL) 2089 return -ENOMEM; 2090 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad); 2091 if (unlikely(ret < 0)) { 2092 kfree_skb(pkt_pad); 2093 return ret; 2094 } 2095 memcpy(pkt_pad->data, 2096 pkt->data + pkt->len - tail_chop, 2097 tail_chop); 2098 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop; 2099 skb_trim(pkt, pkt->len - tail_chop); 2100 skb_trim(pkt_pad, tail_pad + tail_chop); 2101 __skb_queue_after(pktq, pkt, pkt_pad); 2102 } else { 2103 ntail = pkt->data_len + tail_pad - 2104 (pkt->end - pkt->tail); 2105 if (skb_cloned(pkt) || ntail > 0) 2106 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC)) 2107 return -ENOMEM; 2108 if (skb_linearize(pkt)) 2109 return -ENOMEM; 2110 __skb_put(pkt, tail_pad); 2111 } 2112 2113 return tail_pad; 2114 } 2115 2116 /** 2117 * brcmf_sdio_txpkt_prep - packet preparation for transmit 2118 * @bus: brcmf_sdio structure pointer 2119 * @pktq: packet list pointer 2120 * @chan: virtual channel to transmit the packet 2121 * 2122 * Processes to be applied to the packet 2123 * - Align data buffer pointer 2124 * - Align data buffer length 2125 * - Prepare header 2126 * Return: negative value if there is error 2127 */ 2128 static int 2129 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq, 2130 uint chan) 2131 { 2132 u16 head_pad, total_len; 2133 struct sk_buff *pkt_next; 2134 u8 txseq; 2135 int ret; 2136 struct brcmf_sdio_hdrinfo hd_info = {0}; 2137 2138 txseq = bus->tx_seq; 2139 total_len = 0; 2140 skb_queue_walk(pktq, pkt_next) { 2141 /* alignment packet inserted in previous 2142 * loop cycle can be skipped as it is 2143 * already properly aligned and does not 2144 * need an sdpcm header. 2145 */ 2146 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG) 2147 continue; 2148 2149 /* align packet data pointer */ 2150 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next); 2151 if (ret < 0) 2152 return ret; 2153 head_pad = (u16)ret; 2154 if (head_pad) 2155 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad); 2156 2157 total_len += pkt_next->len; 2158 2159 hd_info.len = pkt_next->len; 2160 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next); 2161 if (bus->txglom && pktq->qlen > 1) { 2162 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq, 2163 pkt_next, total_len); 2164 if (ret < 0) 2165 return ret; 2166 hd_info.tail_pad = (u16)ret; 2167 total_len += (u16)ret; 2168 } 2169 2170 hd_info.channel = chan; 2171 hd_info.dat_offset = head_pad + bus->tx_hdrlen; 2172 hd_info.seq_num = txseq++; 2173 2174 /* Now fill the header */ 2175 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info); 2176 2177 if (BRCMF_BYTES_ON() && 2178 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) || 2179 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL))) 2180 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len, 2181 "Tx Frame:\n"); 2182 else if (BRCMF_HDRS_ON()) 2183 brcmf_dbg_hex_dump(true, pkt_next->data, 2184 head_pad + bus->tx_hdrlen, 2185 "Tx Header:\n"); 2186 } 2187 /* Hardware length tag of the first packet should be total 2188 * length of the chain (including padding) 2189 */ 2190 if (bus->txglom) 2191 brcmf_sdio_update_hwhdr(__skb_peek(pktq)->data, total_len); 2192 return 0; 2193 } 2194 2195 /** 2196 * brcmf_sdio_txpkt_postp - packet post processing for transmit 2197 * @bus: brcmf_sdio structure pointer 2198 * @pktq: packet list pointer 2199 * 2200 * Processes to be applied to the packet 2201 * - Remove head padding 2202 * - Remove tail padding 2203 */ 2204 static void 2205 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq) 2206 { 2207 u8 *hdr; 2208 u32 dat_offset; 2209 u16 tail_pad; 2210 u16 dummy_flags, chop_len; 2211 struct sk_buff *pkt_next, *tmp, *pkt_prev; 2212 2213 skb_queue_walk_safe(pktq, pkt_next, tmp) { 2214 dummy_flags = *(u16 *)(pkt_next->cb); 2215 if (dummy_flags & ALIGN_SKB_FLAG) { 2216 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK; 2217 if (chop_len) { 2218 pkt_prev = pkt_next->prev; 2219 skb_put(pkt_prev, chop_len); 2220 } 2221 __skb_unlink(pkt_next, pktq); 2222 brcmu_pkt_buf_free_skb(pkt_next); 2223 } else { 2224 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN; 2225 dat_offset = le32_to_cpu(*(__le32 *)hdr); 2226 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >> 2227 SDPCM_DOFFSET_SHIFT; 2228 skb_pull(pkt_next, dat_offset); 2229 if (bus->txglom) { 2230 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2)); 2231 skb_trim(pkt_next, pkt_next->len - tail_pad); 2232 } 2233 } 2234 } 2235 } 2236 2237 /* Writes a HW/SW header into the packet and sends it. */ 2238 /* Assumes: (a) header space already there, (b) caller holds lock */ 2239 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq, 2240 uint chan) 2241 { 2242 int ret; 2243 struct sk_buff *pkt_next, *tmp; 2244 2245 brcmf_dbg(TRACE, "Enter\n"); 2246 2247 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan); 2248 if (ret) 2249 goto done; 2250 2251 sdio_claim_host(bus->sdiodev->func1); 2252 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq); 2253 bus->sdcnt.f2txdata++; 2254 2255 if (ret < 0) 2256 brcmf_sdio_txfail(bus); 2257 2258 sdio_release_host(bus->sdiodev->func1); 2259 2260 done: 2261 brcmf_sdio_txpkt_postp(bus, pktq); 2262 if (ret == 0) 2263 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP; 2264 skb_queue_walk_safe(pktq, pkt_next, tmp) { 2265 __skb_unlink(pkt_next, pktq); 2266 brcmf_proto_bcdc_txcomplete(bus->sdiodev->dev, pkt_next, 2267 ret == 0); 2268 } 2269 return ret; 2270 } 2271 2272 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes) 2273 { 2274 struct sk_buff *pkt; 2275 struct sk_buff_head pktq; 2276 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus); 2277 u32 intstatus = 0; 2278 int ret = 0, prec_out, i; 2279 uint cnt = 0; 2280 u8 tx_prec_map, pkt_num; 2281 2282 brcmf_dbg(TRACE, "Enter\n"); 2283 2284 tx_prec_map = ~bus->flowcontrol; 2285 2286 /* Send frames until the limit or some other event */ 2287 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) { 2288 pkt_num = 1; 2289 if (bus->txglom) 2290 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq, 2291 bus->sdiodev->txglomsz); 2292 pkt_num = min_t(u32, pkt_num, 2293 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)); 2294 __skb_queue_head_init(&pktq); 2295 spin_lock_bh(&bus->txq_lock); 2296 for (i = 0; i < pkt_num; i++) { 2297 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, 2298 &prec_out); 2299 if (pkt == NULL) 2300 break; 2301 __skb_queue_tail(&pktq, pkt); 2302 } 2303 spin_unlock_bh(&bus->txq_lock); 2304 if (i == 0) 2305 break; 2306 2307 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL); 2308 2309 cnt += i; 2310 2311 /* In poll mode, need to check for other events */ 2312 if (!bus->intr) { 2313 /* Check device status, signal pending interrupt */ 2314 sdio_claim_host(bus->sdiodev->func1); 2315 intstatus = brcmf_sdiod_readl(bus->sdiodev, 2316 intstat_addr, &ret); 2317 sdio_release_host(bus->sdiodev->func1); 2318 2319 bus->sdcnt.f2txdata++; 2320 if (ret != 0) 2321 break; 2322 if (intstatus & bus->hostintmask) 2323 atomic_set(&bus->ipend, 1); 2324 } 2325 } 2326 2327 /* Deflow-control stack if needed */ 2328 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) && 2329 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) { 2330 bus->txoff = false; 2331 brcmf_proto_bcdc_txflowblock(bus->sdiodev->dev, false); 2332 } 2333 2334 return cnt; 2335 } 2336 2337 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len) 2338 { 2339 u8 doff; 2340 u16 pad; 2341 uint retries = 0; 2342 struct brcmf_sdio_hdrinfo hd_info = {0}; 2343 int ret; 2344 2345 brcmf_dbg(SDIO, "Enter\n"); 2346 2347 /* Back the pointer to make room for bus header */ 2348 frame -= bus->tx_hdrlen; 2349 len += bus->tx_hdrlen; 2350 2351 /* Add alignment padding (optional for ctl frames) */ 2352 doff = ((unsigned long)frame % bus->head_align); 2353 if (doff) { 2354 frame -= doff; 2355 len += doff; 2356 memset(frame + bus->tx_hdrlen, 0, doff); 2357 } 2358 2359 /* Round send length to next SDIO block */ 2360 pad = 0; 2361 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { 2362 pad = bus->blocksize - (len % bus->blocksize); 2363 if ((pad > bus->roundup) || (pad >= bus->blocksize)) 2364 pad = 0; 2365 } else if (len % bus->head_align) { 2366 pad = bus->head_align - (len % bus->head_align); 2367 } 2368 len += pad; 2369 2370 hd_info.len = len - pad; 2371 hd_info.channel = SDPCM_CONTROL_CHANNEL; 2372 hd_info.dat_offset = doff + bus->tx_hdrlen; 2373 hd_info.seq_num = bus->tx_seq; 2374 hd_info.lastfrm = true; 2375 hd_info.tail_pad = pad; 2376 brcmf_sdio_hdpack(bus, frame, &hd_info); 2377 2378 if (bus->txglom) 2379 brcmf_sdio_update_hwhdr(frame, len); 2380 2381 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), 2382 frame, len, "Tx Frame:\n"); 2383 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) && 2384 BRCMF_HDRS_ON(), 2385 frame, min_t(u16, len, 16), "TxHdr:\n"); 2386 2387 do { 2388 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len); 2389 2390 if (ret < 0) 2391 brcmf_sdio_txfail(bus); 2392 else 2393 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; 2394 } while (ret < 0 && retries++ < TXRETRIES); 2395 2396 return ret; 2397 } 2398 2399 static void brcmf_sdio_bus_stop(struct device *dev) 2400 { 2401 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2402 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2403 struct brcmf_sdio *bus = sdiodev->bus; 2404 struct brcmf_core *core = bus->sdio_core; 2405 u32 local_hostintmask; 2406 u8 saveclk; 2407 int err; 2408 2409 brcmf_dbg(TRACE, "Enter\n"); 2410 2411 if (bus->watchdog_tsk) { 2412 send_sig(SIGTERM, bus->watchdog_tsk, 1); 2413 kthread_stop(bus->watchdog_tsk); 2414 bus->watchdog_tsk = NULL; 2415 } 2416 2417 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { 2418 sdio_claim_host(sdiodev->func1); 2419 2420 /* Enable clock for device interrupts */ 2421 brcmf_sdio_bus_sleep(bus, false, false); 2422 2423 /* Disable and clear interrupts at the chip level also */ 2424 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(hostintmask), 2425 0, NULL); 2426 2427 local_hostintmask = bus->hostintmask; 2428 bus->hostintmask = 0; 2429 2430 /* Force backplane clocks to assure F2 interrupt propagates */ 2431 saveclk = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 2432 &err); 2433 if (!err) 2434 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 2435 (saveclk | SBSDIO_FORCE_HT), &err); 2436 if (err) 2437 brcmf_err("Failed to force clock for F2: err %d\n", 2438 err); 2439 2440 /* Turn off the bus (F2), free any pending packets */ 2441 brcmf_dbg(INTR, "disable SDIO interrupts\n"); 2442 sdio_disable_func(sdiodev->func2); 2443 2444 /* Clear any pending interrupts now that F2 is disabled */ 2445 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(intstatus), 2446 local_hostintmask, NULL); 2447 2448 sdio_release_host(sdiodev->func1); 2449 } 2450 /* Clear the data packet queues */ 2451 brcmu_pktq_flush(&bus->txq, true, NULL, NULL); 2452 2453 /* Clear any held glomming stuff */ 2454 brcmu_pkt_buf_free_skb(bus->glomd); 2455 brcmf_sdio_free_glom(bus); 2456 2457 /* Clear rx control and wake any waiters */ 2458 spin_lock_bh(&bus->rxctl_lock); 2459 bus->rxlen = 0; 2460 spin_unlock_bh(&bus->rxctl_lock); 2461 brcmf_sdio_dcmd_resp_wake(bus); 2462 2463 /* Reset some F2 state stuff */ 2464 bus->rxskip = false; 2465 bus->tx_seq = bus->rx_seq = 0; 2466 } 2467 2468 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus) 2469 { 2470 struct brcmf_sdio_dev *sdiodev; 2471 unsigned long flags; 2472 2473 sdiodev = bus->sdiodev; 2474 if (sdiodev->oob_irq_requested) { 2475 spin_lock_irqsave(&sdiodev->irq_en_lock, flags); 2476 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) { 2477 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr); 2478 sdiodev->irq_en = true; 2479 } 2480 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags); 2481 } 2482 } 2483 2484 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus) 2485 { 2486 struct brcmf_core *core = bus->sdio_core; 2487 u32 addr; 2488 unsigned long val; 2489 int ret; 2490 2491 addr = core->base + SD_REG(intstatus); 2492 2493 val = brcmf_sdiod_readl(bus->sdiodev, addr, &ret); 2494 bus->sdcnt.f1regdata++; 2495 if (ret != 0) 2496 return ret; 2497 2498 val &= bus->hostintmask; 2499 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE)); 2500 2501 /* Clear interrupts */ 2502 if (val) { 2503 brcmf_sdiod_writel(bus->sdiodev, addr, val, &ret); 2504 bus->sdcnt.f1regdata++; 2505 atomic_or(val, &bus->intstatus); 2506 } 2507 2508 return ret; 2509 } 2510 2511 static void brcmf_sdio_dpc(struct brcmf_sdio *bus) 2512 { 2513 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 2514 u32 newstatus = 0; 2515 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus); 2516 unsigned long intstatus; 2517 uint txlimit = bus->txbound; /* Tx frames to send before resched */ 2518 uint framecnt; /* Temporary counter of tx/rx frames */ 2519 int err = 0; 2520 2521 brcmf_dbg(SDIO, "Enter\n"); 2522 2523 sdio_claim_host(bus->sdiodev->func1); 2524 2525 /* If waiting for HTAVAIL, check status */ 2526 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) { 2527 u8 clkctl, devctl = 0; 2528 2529 #ifdef DEBUG 2530 /* Check for inconsistent device control */ 2531 devctl = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_DEVICE_CTL, 2532 &err); 2533 #endif /* DEBUG */ 2534 2535 /* Read CSR, if clock on switch to AVAIL, else ignore */ 2536 clkctl = brcmf_sdiod_readb(bus->sdiodev, 2537 SBSDIO_FUNC1_CHIPCLKCSR, &err); 2538 2539 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", 2540 devctl, clkctl); 2541 2542 if (SBSDIO_HTAV(clkctl)) { 2543 devctl = brcmf_sdiod_readb(bus->sdiodev, 2544 SBSDIO_DEVICE_CTL, &err); 2545 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 2546 brcmf_sdiod_writeb(bus->sdiodev, 2547 SBSDIO_DEVICE_CTL, devctl, &err); 2548 bus->clkstate = CLK_AVAIL; 2549 } 2550 } 2551 2552 /* Make sure backplane clock is on */ 2553 brcmf_sdio_bus_sleep(bus, false, true); 2554 2555 /* Pending interrupt indicates new device status */ 2556 if (atomic_read(&bus->ipend) > 0) { 2557 atomic_set(&bus->ipend, 0); 2558 err = brcmf_sdio_intr_rstatus(bus); 2559 } 2560 2561 /* Start with leftover status bits */ 2562 intstatus = atomic_xchg(&bus->intstatus, 0); 2563 2564 /* Handle flow-control change: read new state in case our ack 2565 * crossed another change interrupt. If change still set, assume 2566 * FC ON for safety, let next loop through do the debounce. 2567 */ 2568 if (intstatus & I_HMB_FC_CHANGE) { 2569 intstatus &= ~I_HMB_FC_CHANGE; 2570 brcmf_sdiod_writel(sdiod, intstat_addr, I_HMB_FC_CHANGE, &err); 2571 2572 newstatus = brcmf_sdiod_readl(sdiod, intstat_addr, &err); 2573 2574 bus->sdcnt.f1regdata += 2; 2575 atomic_set(&bus->fcstate, 2576 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE))); 2577 intstatus |= (newstatus & bus->hostintmask); 2578 } 2579 2580 /* Handle host mailbox indication */ 2581 if (intstatus & I_HMB_HOST_INT) { 2582 intstatus &= ~I_HMB_HOST_INT; 2583 intstatus |= brcmf_sdio_hostmail(bus); 2584 } 2585 2586 sdio_release_host(bus->sdiodev->func1); 2587 2588 /* Generally don't ask for these, can get CRC errors... */ 2589 if (intstatus & I_WR_OOSYNC) { 2590 brcmf_err("Dongle reports WR_OOSYNC\n"); 2591 intstatus &= ~I_WR_OOSYNC; 2592 } 2593 2594 if (intstatus & I_RD_OOSYNC) { 2595 brcmf_err("Dongle reports RD_OOSYNC\n"); 2596 intstatus &= ~I_RD_OOSYNC; 2597 } 2598 2599 if (intstatus & I_SBINT) { 2600 brcmf_err("Dongle reports SBINT\n"); 2601 intstatus &= ~I_SBINT; 2602 } 2603 2604 /* Would be active due to wake-wlan in gSPI */ 2605 if (intstatus & I_CHIPACTIVE) { 2606 brcmf_dbg(SDIO, "Dongle reports CHIPACTIVE\n"); 2607 intstatus &= ~I_CHIPACTIVE; 2608 } 2609 2610 /* Ignore frame indications if rxskip is set */ 2611 if (bus->rxskip) 2612 intstatus &= ~I_HMB_FRAME_IND; 2613 2614 /* On frame indication, read available frames */ 2615 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) { 2616 brcmf_sdio_readframes(bus, bus->rxbound); 2617 if (!bus->rxpending) 2618 intstatus &= ~I_HMB_FRAME_IND; 2619 } 2620 2621 /* Keep still-pending events for next scheduling */ 2622 if (intstatus) 2623 atomic_or(intstatus, &bus->intstatus); 2624 2625 brcmf_sdio_clrintr(bus); 2626 2627 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) && 2628 data_ok(bus)) { 2629 sdio_claim_host(bus->sdiodev->func1); 2630 if (bus->ctrl_frame_stat) { 2631 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf, 2632 bus->ctrl_frame_len); 2633 bus->ctrl_frame_err = err; 2634 wmb(); 2635 bus->ctrl_frame_stat = false; 2636 } 2637 sdio_release_host(bus->sdiodev->func1); 2638 brcmf_sdio_wait_event_wakeup(bus); 2639 } 2640 /* Send queued frames (limit 1 if rx may still be pending) */ 2641 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) && 2642 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && 2643 data_ok(bus)) { 2644 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) : 2645 txlimit; 2646 brcmf_sdio_sendfromq(bus, framecnt); 2647 } 2648 2649 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) { 2650 brcmf_err("failed backplane access over SDIO, halting operation\n"); 2651 atomic_set(&bus->intstatus, 0); 2652 if (bus->ctrl_frame_stat) { 2653 sdio_claim_host(bus->sdiodev->func1); 2654 if (bus->ctrl_frame_stat) { 2655 bus->ctrl_frame_err = -ENODEV; 2656 wmb(); 2657 bus->ctrl_frame_stat = false; 2658 brcmf_sdio_wait_event_wakeup(bus); 2659 } 2660 sdio_release_host(bus->sdiodev->func1); 2661 } 2662 } else if (atomic_read(&bus->intstatus) || 2663 atomic_read(&bus->ipend) > 0 || 2664 (!atomic_read(&bus->fcstate) && 2665 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && 2666 data_ok(bus))) { 2667 bus->dpc_triggered = true; 2668 } 2669 } 2670 2671 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev) 2672 { 2673 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2674 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2675 struct brcmf_sdio *bus = sdiodev->bus; 2676 2677 return &bus->txq; 2678 } 2679 2680 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec) 2681 { 2682 struct sk_buff *p; 2683 int eprec = -1; /* precedence to evict from */ 2684 2685 /* Fast case, precedence queue is not full and we are also not 2686 * exceeding total queue length 2687 */ 2688 if (!pktq_pfull(q, prec) && !pktq_full(q)) { 2689 brcmu_pktq_penq(q, prec, pkt); 2690 return true; 2691 } 2692 2693 /* Determine precedence from which to evict packet, if any */ 2694 if (pktq_pfull(q, prec)) { 2695 eprec = prec; 2696 } else if (pktq_full(q)) { 2697 p = brcmu_pktq_peek_tail(q, &eprec); 2698 if (eprec > prec) 2699 return false; 2700 } 2701 2702 /* Evict if needed */ 2703 if (eprec >= 0) { 2704 /* Detect queueing to unconfigured precedence */ 2705 if (eprec == prec) 2706 return false; /* refuse newer (incoming) packet */ 2707 /* Evict packet according to discard policy */ 2708 p = brcmu_pktq_pdeq_tail(q, eprec); 2709 if (p == NULL) 2710 brcmf_err("brcmu_pktq_pdeq_tail() failed\n"); 2711 brcmu_pkt_buf_free_skb(p); 2712 } 2713 2714 /* Enqueue */ 2715 p = brcmu_pktq_penq(q, prec, pkt); 2716 if (p == NULL) 2717 brcmf_err("brcmu_pktq_penq() failed\n"); 2718 2719 return p != NULL; 2720 } 2721 2722 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt) 2723 { 2724 int ret = -EBADE; 2725 uint prec; 2726 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2727 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2728 struct brcmf_sdio *bus = sdiodev->bus; 2729 2730 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len); 2731 if (sdiodev->state != BRCMF_SDIOD_DATA) 2732 return -EIO; 2733 2734 /* Add space for the header */ 2735 skb_push(pkt, bus->tx_hdrlen); 2736 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ 2737 2738 prec = prio2prec((pkt->priority & PRIOMASK)); 2739 2740 /* Check for existing queue, current flow-control, 2741 pending event, or pending clock */ 2742 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); 2743 bus->sdcnt.fcqueued++; 2744 2745 /* Priority based enq */ 2746 spin_lock_bh(&bus->txq_lock); 2747 /* reset bus_flags in packet cb */ 2748 *(u16 *)(pkt->cb) = 0; 2749 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) { 2750 skb_pull(pkt, bus->tx_hdrlen); 2751 brcmf_err("out of bus->txq !!!\n"); 2752 ret = -ENOSR; 2753 } else { 2754 ret = 0; 2755 } 2756 2757 if (pktq_len(&bus->txq) >= TXHI) { 2758 bus->txoff = true; 2759 brcmf_proto_bcdc_txflowblock(dev, true); 2760 } 2761 spin_unlock_bh(&bus->txq_lock); 2762 2763 #ifdef DEBUG 2764 if (pktq_plen(&bus->txq, prec) > qcount[prec]) 2765 qcount[prec] = pktq_plen(&bus->txq, prec); 2766 #endif 2767 2768 brcmf_sdio_trigger_dpc(bus); 2769 return ret; 2770 } 2771 2772 #ifdef DEBUG 2773 #define CONSOLE_LINE_MAX 192 2774 2775 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus) 2776 { 2777 struct brcmf_console *c = &bus->console; 2778 u8 line[CONSOLE_LINE_MAX], ch; 2779 u32 n, idx, addr; 2780 int rv; 2781 2782 /* Don't do anything until FWREADY updates console address */ 2783 if (bus->console_addr == 0) 2784 return 0; 2785 2786 /* Read console log struct */ 2787 addr = bus->console_addr + offsetof(struct rte_console, log_le); 2788 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le, 2789 sizeof(c->log_le)); 2790 if (rv < 0) 2791 return rv; 2792 2793 /* Allocate console buffer (one time only) */ 2794 if (c->buf == NULL) { 2795 c->bufsize = le32_to_cpu(c->log_le.buf_size); 2796 c->buf = kmalloc(c->bufsize, GFP_ATOMIC); 2797 if (c->buf == NULL) 2798 return -ENOMEM; 2799 } 2800 2801 idx = le32_to_cpu(c->log_le.idx); 2802 2803 /* Protect against corrupt value */ 2804 if (idx > c->bufsize) 2805 return -EBADE; 2806 2807 /* Skip reading the console buffer if the index pointer 2808 has not moved */ 2809 if (idx == c->last) 2810 return 0; 2811 2812 /* Read the console buffer */ 2813 addr = le32_to_cpu(c->log_le.buf); 2814 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize); 2815 if (rv < 0) 2816 return rv; 2817 2818 while (c->last != idx) { 2819 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { 2820 if (c->last == idx) { 2821 /* This would output a partial line. 2822 * Instead, back up 2823 * the buffer pointer and output this 2824 * line next time around. 2825 */ 2826 if (c->last >= n) 2827 c->last -= n; 2828 else 2829 c->last = c->bufsize - n; 2830 goto break2; 2831 } 2832 ch = c->buf[c->last]; 2833 c->last = (c->last + 1) % c->bufsize; 2834 if (ch == '\n') 2835 break; 2836 line[n] = ch; 2837 } 2838 2839 if (n > 0) { 2840 if (line[n - 1] == '\r') 2841 n--; 2842 line[n] = 0; 2843 pr_debug("CONSOLE: %s\n", line); 2844 } 2845 } 2846 break2: 2847 2848 return 0; 2849 } 2850 #endif /* DEBUG */ 2851 2852 static int 2853 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) 2854 { 2855 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2856 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2857 struct brcmf_sdio *bus = sdiodev->bus; 2858 int ret; 2859 2860 brcmf_dbg(TRACE, "Enter\n"); 2861 if (sdiodev->state != BRCMF_SDIOD_DATA) 2862 return -EIO; 2863 2864 /* Send from dpc */ 2865 bus->ctrl_frame_buf = msg; 2866 bus->ctrl_frame_len = msglen; 2867 wmb(); 2868 bus->ctrl_frame_stat = true; 2869 2870 brcmf_sdio_trigger_dpc(bus); 2871 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat, 2872 CTL_DONE_TIMEOUT); 2873 ret = 0; 2874 if (bus->ctrl_frame_stat) { 2875 sdio_claim_host(bus->sdiodev->func1); 2876 if (bus->ctrl_frame_stat) { 2877 brcmf_dbg(SDIO, "ctrl_frame timeout\n"); 2878 bus->ctrl_frame_stat = false; 2879 ret = -ETIMEDOUT; 2880 } 2881 sdio_release_host(bus->sdiodev->func1); 2882 } 2883 if (!ret) { 2884 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n", 2885 bus->ctrl_frame_err); 2886 rmb(); 2887 ret = bus->ctrl_frame_err; 2888 } 2889 2890 if (ret) 2891 bus->sdcnt.tx_ctlerrs++; 2892 else 2893 bus->sdcnt.tx_ctlpkts++; 2894 2895 return ret; 2896 } 2897 2898 #ifdef DEBUG 2899 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus, 2900 struct sdpcm_shared *sh) 2901 { 2902 u32 addr, console_ptr, console_size, console_index; 2903 char *conbuf = NULL; 2904 __le32 sh_val; 2905 int rv; 2906 2907 /* obtain console information from device memory */ 2908 addr = sh->console_addr + offsetof(struct rte_console, log_le); 2909 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2910 (u8 *)&sh_val, sizeof(u32)); 2911 if (rv < 0) 2912 return rv; 2913 console_ptr = le32_to_cpu(sh_val); 2914 2915 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size); 2916 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2917 (u8 *)&sh_val, sizeof(u32)); 2918 if (rv < 0) 2919 return rv; 2920 console_size = le32_to_cpu(sh_val); 2921 2922 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx); 2923 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2924 (u8 *)&sh_val, sizeof(u32)); 2925 if (rv < 0) 2926 return rv; 2927 console_index = le32_to_cpu(sh_val); 2928 2929 /* allocate buffer for console data */ 2930 if (console_size <= CONSOLE_BUFFER_MAX) 2931 conbuf = vzalloc(console_size+1); 2932 2933 if (!conbuf) 2934 return -ENOMEM; 2935 2936 /* obtain the console data from device */ 2937 conbuf[console_size] = '\0'; 2938 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf, 2939 console_size); 2940 if (rv < 0) 2941 goto done; 2942 2943 rv = seq_write(seq, conbuf + console_index, 2944 console_size - console_index); 2945 if (rv < 0) 2946 goto done; 2947 2948 if (console_index > 0) 2949 rv = seq_write(seq, conbuf, console_index - 1); 2950 2951 done: 2952 vfree(conbuf); 2953 return rv; 2954 } 2955 2956 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus, 2957 struct sdpcm_shared *sh) 2958 { 2959 int error; 2960 struct brcmf_trap_info tr; 2961 2962 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) { 2963 brcmf_dbg(INFO, "no trap in firmware\n"); 2964 return 0; 2965 } 2966 2967 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr, 2968 sizeof(struct brcmf_trap_info)); 2969 if (error < 0) 2970 return error; 2971 2972 seq_printf(seq, 2973 "dongle trap info: type 0x%x @ epc 0x%08x\n" 2974 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" 2975 " lr 0x%08x pc 0x%08x offset 0x%x\n" 2976 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" 2977 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", 2978 le32_to_cpu(tr.type), le32_to_cpu(tr.epc), 2979 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), 2980 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), 2981 le32_to_cpu(tr.pc), sh->trap_addr, 2982 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), 2983 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), 2984 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), 2985 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); 2986 2987 return 0; 2988 } 2989 2990 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus, 2991 struct sdpcm_shared *sh) 2992 { 2993 int error = 0; 2994 char file[80] = "?"; 2995 char expr[80] = "<???>"; 2996 2997 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) { 2998 brcmf_dbg(INFO, "firmware not built with -assert\n"); 2999 return 0; 3000 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) { 3001 brcmf_dbg(INFO, "no assert in dongle\n"); 3002 return 0; 3003 } 3004 3005 sdio_claim_host(bus->sdiodev->func1); 3006 if (sh->assert_file_addr != 0) { 3007 error = brcmf_sdiod_ramrw(bus->sdiodev, false, 3008 sh->assert_file_addr, (u8 *)file, 80); 3009 if (error < 0) 3010 return error; 3011 } 3012 if (sh->assert_exp_addr != 0) { 3013 error = brcmf_sdiod_ramrw(bus->sdiodev, false, 3014 sh->assert_exp_addr, (u8 *)expr, 80); 3015 if (error < 0) 3016 return error; 3017 } 3018 sdio_release_host(bus->sdiodev->func1); 3019 3020 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n", 3021 file, sh->assert_line, expr); 3022 return 0; 3023 } 3024 3025 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) 3026 { 3027 int error; 3028 struct sdpcm_shared sh; 3029 3030 error = brcmf_sdio_readshared(bus, &sh); 3031 3032 if (error < 0) 3033 return error; 3034 3035 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) 3036 brcmf_dbg(INFO, "firmware not built with -assert\n"); 3037 else if (sh.flags & SDPCM_SHARED_ASSERT) 3038 brcmf_err("assertion in dongle\n"); 3039 3040 if (sh.flags & SDPCM_SHARED_TRAP) 3041 brcmf_err("firmware trap in dongle\n"); 3042 3043 return 0; 3044 } 3045 3046 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus) 3047 { 3048 int error = 0; 3049 struct sdpcm_shared sh; 3050 3051 error = brcmf_sdio_readshared(bus, &sh); 3052 if (error < 0) 3053 goto done; 3054 3055 error = brcmf_sdio_assert_info(seq, bus, &sh); 3056 if (error < 0) 3057 goto done; 3058 3059 error = brcmf_sdio_trap_info(seq, bus, &sh); 3060 if (error < 0) 3061 goto done; 3062 3063 error = brcmf_sdio_dump_console(seq, bus, &sh); 3064 3065 done: 3066 return error; 3067 } 3068 3069 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data) 3070 { 3071 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); 3072 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus; 3073 3074 return brcmf_sdio_died_dump(seq, bus); 3075 } 3076 3077 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data) 3078 { 3079 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); 3080 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3081 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt; 3082 3083 seq_printf(seq, 3084 "intrcount: %u\nlastintrs: %u\n" 3085 "pollcnt: %u\nregfails: %u\n" 3086 "tx_sderrs: %u\nfcqueued: %u\n" 3087 "rxrtx: %u\nrx_toolong: %u\n" 3088 "rxc_errors: %u\nrx_hdrfail: %u\n" 3089 "rx_badhdr: %u\nrx_badseq: %u\n" 3090 "fc_rcvd: %u\nfc_xoff: %u\n" 3091 "fc_xon: %u\nrxglomfail: %u\n" 3092 "rxglomframes: %u\nrxglompkts: %u\n" 3093 "f2rxhdrs: %u\nf2rxdata: %u\n" 3094 "f2txdata: %u\nf1regdata: %u\n" 3095 "tickcnt: %u\ntx_ctlerrs: %lu\n" 3096 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n" 3097 "rx_ctlpkts: %lu\nrx_readahead: %lu\n", 3098 sdcnt->intrcount, sdcnt->lastintrs, 3099 sdcnt->pollcnt, sdcnt->regfails, 3100 sdcnt->tx_sderrs, sdcnt->fcqueued, 3101 sdcnt->rxrtx, sdcnt->rx_toolong, 3102 sdcnt->rxc_errors, sdcnt->rx_hdrfail, 3103 sdcnt->rx_badhdr, sdcnt->rx_badseq, 3104 sdcnt->fc_rcvd, sdcnt->fc_xoff, 3105 sdcnt->fc_xon, sdcnt->rxglomfail, 3106 sdcnt->rxglomframes, sdcnt->rxglompkts, 3107 sdcnt->f2rxhdrs, sdcnt->f2rxdata, 3108 sdcnt->f2txdata, sdcnt->f1regdata, 3109 sdcnt->tickcnt, sdcnt->tx_ctlerrs, 3110 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs, 3111 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt); 3112 3113 return 0; 3114 } 3115 3116 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) 3117 { 3118 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr; 3119 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); 3120 3121 if (IS_ERR_OR_NULL(dentry)) 3122 return; 3123 3124 bus->console_interval = BRCMF_CONSOLE; 3125 3126 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read); 3127 brcmf_debugfs_add_entry(drvr, "counters", 3128 brcmf_debugfs_sdio_count_read); 3129 debugfs_create_u32("console_interval", 0644, dentry, 3130 &bus->console_interval); 3131 } 3132 #else 3133 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) 3134 { 3135 return 0; 3136 } 3137 3138 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) 3139 { 3140 } 3141 #endif /* DEBUG */ 3142 3143 static int 3144 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) 3145 { 3146 int timeleft; 3147 uint rxlen = 0; 3148 bool pending; 3149 u8 *buf; 3150 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3151 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3152 struct brcmf_sdio *bus = sdiodev->bus; 3153 3154 brcmf_dbg(TRACE, "Enter\n"); 3155 if (sdiodev->state != BRCMF_SDIOD_DATA) 3156 return -EIO; 3157 3158 /* Wait until control frame is available */ 3159 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending); 3160 3161 spin_lock_bh(&bus->rxctl_lock); 3162 rxlen = bus->rxlen; 3163 memcpy(msg, bus->rxctl, min(msglen, rxlen)); 3164 bus->rxctl = NULL; 3165 buf = bus->rxctl_orig; 3166 bus->rxctl_orig = NULL; 3167 bus->rxlen = 0; 3168 spin_unlock_bh(&bus->rxctl_lock); 3169 vfree(buf); 3170 3171 if (rxlen) { 3172 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", 3173 rxlen, msglen); 3174 } else if (timeleft == 0) { 3175 brcmf_err("resumed on timeout\n"); 3176 brcmf_sdio_checkdied(bus); 3177 } else if (pending) { 3178 brcmf_dbg(CTL, "cancelled\n"); 3179 return -ERESTARTSYS; 3180 } else { 3181 brcmf_dbg(CTL, "resumed for unknown reason?\n"); 3182 brcmf_sdio_checkdied(bus); 3183 } 3184 3185 if (rxlen) 3186 bus->sdcnt.rx_ctlpkts++; 3187 else 3188 bus->sdcnt.rx_ctlerrs++; 3189 3190 return rxlen ? (int)rxlen : -ETIMEDOUT; 3191 } 3192 3193 #ifdef DEBUG 3194 static bool 3195 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, 3196 u8 *ram_data, uint ram_sz) 3197 { 3198 char *ram_cmp; 3199 int err; 3200 bool ret = true; 3201 int address; 3202 int offset; 3203 int len; 3204 3205 /* read back and verify */ 3206 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr, 3207 ram_sz); 3208 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL); 3209 /* do not proceed while no memory but */ 3210 if (!ram_cmp) 3211 return true; 3212 3213 address = ram_addr; 3214 offset = 0; 3215 while (offset < ram_sz) { 3216 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK : 3217 ram_sz - offset; 3218 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len); 3219 if (err) { 3220 brcmf_err("error %d on reading %d membytes at 0x%08x\n", 3221 err, len, address); 3222 ret = false; 3223 break; 3224 } else if (memcmp(ram_cmp, &ram_data[offset], len)) { 3225 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n", 3226 offset, len); 3227 ret = false; 3228 break; 3229 } 3230 offset += len; 3231 address += len; 3232 } 3233 3234 kfree(ram_cmp); 3235 3236 return ret; 3237 } 3238 #else /* DEBUG */ 3239 static bool 3240 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, 3241 u8 *ram_data, uint ram_sz) 3242 { 3243 return true; 3244 } 3245 #endif /* DEBUG */ 3246 3247 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus, 3248 const struct firmware *fw) 3249 { 3250 int err; 3251 3252 brcmf_dbg(TRACE, "Enter\n"); 3253 3254 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase, 3255 (u8 *)fw->data, fw->size); 3256 if (err) 3257 brcmf_err("error %d on writing %d membytes at 0x%08x\n", 3258 err, (int)fw->size, bus->ci->rambase); 3259 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase, 3260 (u8 *)fw->data, fw->size)) 3261 err = -EIO; 3262 3263 return err; 3264 } 3265 3266 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus, 3267 void *vars, u32 varsz) 3268 { 3269 int address; 3270 int err; 3271 3272 brcmf_dbg(TRACE, "Enter\n"); 3273 3274 address = bus->ci->ramsize - varsz + bus->ci->rambase; 3275 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz); 3276 if (err) 3277 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n", 3278 err, varsz, address); 3279 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz)) 3280 err = -EIO; 3281 3282 return err; 3283 } 3284 3285 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus, 3286 const struct firmware *fw, 3287 void *nvram, u32 nvlen) 3288 { 3289 int bcmerror; 3290 u32 rstvec; 3291 3292 sdio_claim_host(bus->sdiodev->func1); 3293 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 3294 3295 rstvec = get_unaligned_le32(fw->data); 3296 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec); 3297 3298 bcmerror = brcmf_sdio_download_code_file(bus, fw); 3299 release_firmware(fw); 3300 if (bcmerror) { 3301 brcmf_err("dongle image file download failed\n"); 3302 brcmf_fw_nvram_free(nvram); 3303 goto err; 3304 } 3305 3306 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen); 3307 brcmf_fw_nvram_free(nvram); 3308 if (bcmerror) { 3309 brcmf_err("dongle nvram file download failed\n"); 3310 goto err; 3311 } 3312 3313 /* Take arm out of reset */ 3314 if (!brcmf_chip_set_active(bus->ci, rstvec)) { 3315 brcmf_err("error getting out of ARM core reset\n"); 3316 goto err; 3317 } 3318 3319 err: 3320 brcmf_sdio_clkctl(bus, CLK_SDONLY, false); 3321 sdio_release_host(bus->sdiodev->func1); 3322 return bcmerror; 3323 } 3324 3325 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus) 3326 { 3327 int err = 0; 3328 u8 val; 3329 3330 brcmf_dbg(TRACE, "Enter\n"); 3331 3332 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err); 3333 if (err) { 3334 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n"); 3335 return; 3336 } 3337 3338 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT; 3339 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err); 3340 if (err) { 3341 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n"); 3342 return; 3343 } 3344 3345 /* Add CMD14 Support */ 3346 brcmf_sdiod_func0_wb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP, 3347 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | 3348 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT), 3349 &err); 3350 if (err) { 3351 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n"); 3352 return; 3353 } 3354 3355 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3356 SBSDIO_FORCE_HT, &err); 3357 if (err) { 3358 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n"); 3359 return; 3360 } 3361 3362 /* set flag */ 3363 bus->sr_enabled = true; 3364 brcmf_dbg(INFO, "SR enabled\n"); 3365 } 3366 3367 /* enable KSO bit */ 3368 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus) 3369 { 3370 struct brcmf_core *core = bus->sdio_core; 3371 u8 val; 3372 int err = 0; 3373 3374 brcmf_dbg(TRACE, "Enter\n"); 3375 3376 /* KSO bit added in SDIO core rev 12 */ 3377 if (core->rev < 12) 3378 return 0; 3379 3380 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err); 3381 if (err) { 3382 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n"); 3383 return err; 3384 } 3385 3386 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { 3387 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << 3388 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); 3389 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 3390 val, &err); 3391 if (err) { 3392 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n"); 3393 return err; 3394 } 3395 } 3396 3397 return 0; 3398 } 3399 3400 3401 static int brcmf_sdio_bus_preinit(struct device *dev) 3402 { 3403 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3404 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3405 struct brcmf_sdio *bus = sdiodev->bus; 3406 struct brcmf_core *core = bus->sdio_core; 3407 u32 value; 3408 int err; 3409 3410 /* maxctl provided by common layer */ 3411 if (WARN_ON(!bus_if->maxctl)) 3412 return -EINVAL; 3413 3414 /* Allocate control receive buffer */ 3415 bus_if->maxctl += bus->roundup; 3416 value = roundup((bus_if->maxctl + SDPCM_HDRLEN), ALIGNMENT); 3417 value += bus->head_align; 3418 bus->rxbuf = kmalloc(value, GFP_ATOMIC); 3419 if (bus->rxbuf) 3420 bus->rxblen = value; 3421 3422 brcmf_sdio_debugfs_create(bus); 3423 3424 /* the commands below use the terms tx and rx from 3425 * a device perspective, ie. bus:txglom affects the 3426 * bus transfers from device to host. 3427 */ 3428 if (core->rev < 12) { 3429 /* for sdio core rev < 12, disable txgloming */ 3430 value = 0; 3431 err = brcmf_iovar_data_set(dev, "bus:txglom", &value, 3432 sizeof(u32)); 3433 } else { 3434 /* otherwise, set txglomalign */ 3435 value = sdiodev->settings->bus.sdio.sd_sgentry_align; 3436 /* SDIO ADMA requires at least 32 bit alignment */ 3437 value = max_t(u32, value, ALIGNMENT); 3438 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value, 3439 sizeof(u32)); 3440 } 3441 3442 if (err < 0) 3443 goto done; 3444 3445 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; 3446 if (sdiodev->sg_support) { 3447 bus->txglom = false; 3448 value = 1; 3449 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom", 3450 &value, sizeof(u32)); 3451 if (err < 0) { 3452 /* bus:rxglom is allowed to fail */ 3453 err = 0; 3454 } else { 3455 bus->txglom = true; 3456 bus->tx_hdrlen += SDPCM_HWEXT_LEN; 3457 } 3458 } 3459 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen); 3460 3461 done: 3462 return err; 3463 } 3464 3465 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev) 3466 { 3467 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3468 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3469 struct brcmf_sdio *bus = sdiodev->bus; 3470 3471 return bus->ci->ramsize - bus->ci->srsize; 3472 } 3473 3474 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data, 3475 size_t mem_size) 3476 { 3477 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3478 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3479 struct brcmf_sdio *bus = sdiodev->bus; 3480 int err; 3481 int address; 3482 int offset; 3483 int len; 3484 3485 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase, 3486 mem_size); 3487 3488 address = bus->ci->rambase; 3489 offset = err = 0; 3490 sdio_claim_host(sdiodev->func1); 3491 while (offset < mem_size) { 3492 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK : 3493 mem_size - offset; 3494 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len); 3495 if (err) { 3496 brcmf_err("error %d on reading %d membytes at 0x%08x\n", 3497 err, len, address); 3498 goto done; 3499 } 3500 data += len; 3501 offset += len; 3502 address += len; 3503 } 3504 3505 done: 3506 sdio_release_host(sdiodev->func1); 3507 return err; 3508 } 3509 3510 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus) 3511 { 3512 if (!bus->dpc_triggered) { 3513 bus->dpc_triggered = true; 3514 queue_work(bus->brcmf_wq, &bus->datawork); 3515 } 3516 } 3517 3518 void brcmf_sdio_isr(struct brcmf_sdio *bus) 3519 { 3520 brcmf_dbg(TRACE, "Enter\n"); 3521 3522 if (!bus) { 3523 brcmf_err("bus is null pointer, exiting\n"); 3524 return; 3525 } 3526 3527 /* Count the interrupt call */ 3528 bus->sdcnt.intrcount++; 3529 if (in_interrupt()) 3530 atomic_set(&bus->ipend, 1); 3531 else 3532 if (brcmf_sdio_intr_rstatus(bus)) { 3533 brcmf_err("failed backplane access\n"); 3534 } 3535 3536 /* Disable additional interrupts (is this needed now)? */ 3537 if (!bus->intr) 3538 brcmf_err("isr w/o interrupt configured!\n"); 3539 3540 bus->dpc_triggered = true; 3541 queue_work(bus->brcmf_wq, &bus->datawork); 3542 } 3543 3544 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus) 3545 { 3546 brcmf_dbg(TIMER, "Enter\n"); 3547 3548 /* Poll period: check device if appropriate. */ 3549 if (!bus->sr_enabled && 3550 bus->poll && (++bus->polltick >= bus->pollrate)) { 3551 u32 intstatus = 0; 3552 3553 /* Reset poll tick */ 3554 bus->polltick = 0; 3555 3556 /* Check device if no interrupts */ 3557 if (!bus->intr || 3558 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) { 3559 3560 if (!bus->dpc_triggered) { 3561 u8 devpend; 3562 3563 sdio_claim_host(bus->sdiodev->func1); 3564 devpend = brcmf_sdiod_func0_rb(bus->sdiodev, 3565 SDIO_CCCR_INTx, NULL); 3566 sdio_release_host(bus->sdiodev->func1); 3567 intstatus = devpend & (INTR_STATUS_FUNC1 | 3568 INTR_STATUS_FUNC2); 3569 } 3570 3571 /* If there is something, make like the ISR and 3572 schedule the DPC */ 3573 if (intstatus) { 3574 bus->sdcnt.pollcnt++; 3575 atomic_set(&bus->ipend, 1); 3576 3577 bus->dpc_triggered = true; 3578 queue_work(bus->brcmf_wq, &bus->datawork); 3579 } 3580 } 3581 3582 /* Update interrupt tracking */ 3583 bus->sdcnt.lastintrs = bus->sdcnt.intrcount; 3584 } 3585 #ifdef DEBUG 3586 /* Poll for console output periodically */ 3587 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() && 3588 bus->console_interval != 0) { 3589 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL); 3590 if (bus->console.count >= bus->console_interval) { 3591 bus->console.count -= bus->console_interval; 3592 sdio_claim_host(bus->sdiodev->func1); 3593 /* Make sure backplane clock is on */ 3594 brcmf_sdio_bus_sleep(bus, false, false); 3595 if (brcmf_sdio_readconsole(bus) < 0) 3596 /* stop on error */ 3597 bus->console_interval = 0; 3598 sdio_release_host(bus->sdiodev->func1); 3599 } 3600 } 3601 #endif /* DEBUG */ 3602 3603 /* On idle timeout clear activity flag and/or turn off clock */ 3604 if (!bus->dpc_triggered) { 3605 rmb(); 3606 if ((!bus->dpc_running) && (bus->idletime > 0) && 3607 (bus->clkstate == CLK_AVAIL)) { 3608 bus->idlecount++; 3609 if (bus->idlecount > bus->idletime) { 3610 brcmf_dbg(SDIO, "idle\n"); 3611 sdio_claim_host(bus->sdiodev->func1); 3612 brcmf_sdio_wd_timer(bus, false); 3613 bus->idlecount = 0; 3614 brcmf_sdio_bus_sleep(bus, true, false); 3615 sdio_release_host(bus->sdiodev->func1); 3616 } 3617 } else { 3618 bus->idlecount = 0; 3619 } 3620 } else { 3621 bus->idlecount = 0; 3622 } 3623 } 3624 3625 static void brcmf_sdio_dataworker(struct work_struct *work) 3626 { 3627 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio, 3628 datawork); 3629 3630 bus->dpc_running = true; 3631 wmb(); 3632 while (READ_ONCE(bus->dpc_triggered)) { 3633 bus->dpc_triggered = false; 3634 brcmf_sdio_dpc(bus); 3635 bus->idlecount = 0; 3636 } 3637 bus->dpc_running = false; 3638 if (brcmf_sdiod_freezing(bus->sdiodev)) { 3639 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN); 3640 brcmf_sdiod_try_freeze(bus->sdiodev); 3641 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); 3642 } 3643 } 3644 3645 static void 3646 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, 3647 struct brcmf_chip *ci, u32 drivestrength) 3648 { 3649 const struct sdiod_drive_str *str_tab = NULL; 3650 u32 str_mask; 3651 u32 str_shift; 3652 u32 i; 3653 u32 drivestrength_sel = 0; 3654 u32 cc_data_temp; 3655 u32 addr; 3656 3657 if (!(ci->cc_caps & CC_CAP_PMU)) 3658 return; 3659 3660 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) { 3661 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12): 3662 str_tab = sdiod_drvstr_tab1_1v8; 3663 str_mask = 0x00003800; 3664 str_shift = 11; 3665 break; 3666 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17): 3667 str_tab = sdiod_drvstr_tab6_1v8; 3668 str_mask = 0x00001800; 3669 str_shift = 11; 3670 break; 3671 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17): 3672 /* note: 43143 does not support tristate */ 3673 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1; 3674 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) { 3675 str_tab = sdiod_drvstr_tab2_3v3; 3676 str_mask = 0x00000007; 3677 str_shift = 0; 3678 } else 3679 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n", 3680 ci->name, drivestrength); 3681 break; 3682 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13): 3683 str_tab = sdiod_drive_strength_tab5_1v8; 3684 str_mask = 0x00003800; 3685 str_shift = 11; 3686 break; 3687 default: 3688 brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n", 3689 ci->name, ci->chiprev, ci->pmurev); 3690 break; 3691 } 3692 3693 if (str_tab != NULL) { 3694 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci); 3695 3696 for (i = 0; str_tab[i].strength != 0; i++) { 3697 if (drivestrength >= str_tab[i].strength) { 3698 drivestrength_sel = str_tab[i].sel; 3699 break; 3700 } 3701 } 3702 addr = CORE_CC_REG(pmu->base, chipcontrol_addr); 3703 brcmf_sdiod_writel(sdiodev, addr, 1, NULL); 3704 cc_data_temp = brcmf_sdiod_readl(sdiodev, addr, NULL); 3705 cc_data_temp &= ~str_mask; 3706 drivestrength_sel <<= str_shift; 3707 cc_data_temp |= drivestrength_sel; 3708 brcmf_sdiod_writel(sdiodev, addr, cc_data_temp, NULL); 3709 3710 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n", 3711 str_tab[i].strength, drivestrength, cc_data_temp); 3712 } 3713 } 3714 3715 static int brcmf_sdio_buscoreprep(void *ctx) 3716 { 3717 struct brcmf_sdio_dev *sdiodev = ctx; 3718 int err = 0; 3719 u8 clkval, clkset; 3720 3721 /* Try forcing SDIO core to do ALPAvail request only */ 3722 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; 3723 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); 3724 if (err) { 3725 brcmf_err("error writing for HT off\n"); 3726 return err; 3727 } 3728 3729 /* If register supported, wait for ALPAvail and then force ALP */ 3730 /* This may take up to 15 milliseconds */ 3731 clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, NULL); 3732 3733 if ((clkval & ~SBSDIO_AVBITS) != clkset) { 3734 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n", 3735 clkset, clkval); 3736 return -EACCES; 3737 } 3738 3739 SPINWAIT(((clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3740 NULL)), 3741 !SBSDIO_ALPAV(clkval)), 3742 PMU_MAX_TRANSITION_DLY); 3743 3744 if (!SBSDIO_ALPAV(clkval)) { 3745 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n", 3746 clkval); 3747 return -EBUSY; 3748 } 3749 3750 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP; 3751 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); 3752 udelay(65); 3753 3754 /* Also, disable the extra SDIO pull-ups */ 3755 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); 3756 3757 return 0; 3758 } 3759 3760 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip, 3761 u32 rstvec) 3762 { 3763 struct brcmf_sdio_dev *sdiodev = ctx; 3764 struct brcmf_core *core = sdiodev->bus->sdio_core; 3765 u32 reg_addr; 3766 3767 /* clear all interrupts */ 3768 reg_addr = core->base + SD_REG(intstatus); 3769 brcmf_sdiod_writel(sdiodev, reg_addr, 0xFFFFFFFF, NULL); 3770 3771 if (rstvec) 3772 /* Write reset vector to address 0 */ 3773 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec, 3774 sizeof(rstvec)); 3775 } 3776 3777 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr) 3778 { 3779 struct brcmf_sdio_dev *sdiodev = ctx; 3780 u32 val, rev; 3781 3782 val = brcmf_sdiod_readl(sdiodev, addr, NULL); 3783 3784 /* 3785 * this is a bit of special handling if reading the chipcommon chipid 3786 * register. The 4339 is a next-gen of the 4335. It uses the same 3787 * SDIO device id as 4335 and the chipid register returns 4335 as well. 3788 * It can be identified as 4339 by looking at the chip revision. It 3789 * is corrected here so the chip.c module has the right info. 3790 */ 3791 if (addr == CORE_CC_REG(SI_ENUM_BASE, chipid) && 3792 (sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4339 || 3793 sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4335_4339)) { 3794 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT; 3795 if (rev >= 2) { 3796 val &= ~CID_ID_MASK; 3797 val |= BRCM_CC_4339_CHIP_ID; 3798 } 3799 } 3800 3801 return val; 3802 } 3803 3804 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val) 3805 { 3806 struct brcmf_sdio_dev *sdiodev = ctx; 3807 3808 brcmf_sdiod_writel(sdiodev, addr, val, NULL); 3809 } 3810 3811 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = { 3812 .prepare = brcmf_sdio_buscoreprep, 3813 .activate = brcmf_sdio_buscore_activate, 3814 .read32 = brcmf_sdio_buscore_read32, 3815 .write32 = brcmf_sdio_buscore_write32, 3816 }; 3817 3818 static bool 3819 brcmf_sdio_probe_attach(struct brcmf_sdio *bus) 3820 { 3821 struct brcmf_sdio_dev *sdiodev; 3822 u8 clkctl = 0; 3823 int err = 0; 3824 int reg_addr; 3825 u32 reg_val; 3826 u32 drivestrength; 3827 3828 sdiodev = bus->sdiodev; 3829 sdio_claim_host(sdiodev->func1); 3830 3831 pr_debug("F1 signature read @0x18000000=0x%4x\n", 3832 brcmf_sdiod_readl(sdiodev, SI_ENUM_BASE, NULL)); 3833 3834 /* 3835 * Force PLL off until brcmf_chip_attach() 3836 * programs PLL control regs 3837 */ 3838 3839 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, BRCMF_INIT_CLKCTL1, 3840 &err); 3841 if (!err) 3842 clkctl = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3843 &err); 3844 3845 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { 3846 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", 3847 err, BRCMF_INIT_CLKCTL1, clkctl); 3848 goto fail; 3849 } 3850 3851 bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops); 3852 if (IS_ERR(bus->ci)) { 3853 brcmf_err("brcmf_chip_attach failed!\n"); 3854 bus->ci = NULL; 3855 goto fail; 3856 } 3857 3858 /* Pick up the SDIO core info struct from chip.c */ 3859 bus->sdio_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); 3860 if (!bus->sdio_core) 3861 goto fail; 3862 3863 /* Pick up the CHIPCOMMON core info struct, for bulk IO in bcmsdh.c */ 3864 sdiodev->cc_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_CHIPCOMMON); 3865 if (!sdiodev->cc_core) 3866 goto fail; 3867 3868 sdiodev->settings = brcmf_get_module_param(sdiodev->dev, 3869 BRCMF_BUSTYPE_SDIO, 3870 bus->ci->chip, 3871 bus->ci->chiprev); 3872 if (!sdiodev->settings) { 3873 brcmf_err("Failed to get device parameters\n"); 3874 goto fail; 3875 } 3876 /* platform specific configuration: 3877 * alignments must be at least 4 bytes for ADMA 3878 */ 3879 bus->head_align = ALIGNMENT; 3880 bus->sgentry_align = ALIGNMENT; 3881 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT) 3882 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align; 3883 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT) 3884 bus->sgentry_align = 3885 sdiodev->settings->bus.sdio.sd_sgentry_align; 3886 3887 /* allocate scatter-gather table. sg support 3888 * will be disabled upon allocation failure. 3889 */ 3890 brcmf_sdiod_sgtable_alloc(sdiodev); 3891 3892 #ifdef CONFIG_PM_SLEEP 3893 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ 3894 * is true or when platform data OOB irq is true). 3895 */ 3896 if ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_KEEP_POWER) && 3897 ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_WAKE_SDIO_IRQ) || 3898 (sdiodev->settings->bus.sdio.oob_irq_supported))) 3899 sdiodev->bus_if->wowl_supported = true; 3900 #endif 3901 3902 if (brcmf_sdio_kso_init(bus)) { 3903 brcmf_err("error enabling KSO\n"); 3904 goto fail; 3905 } 3906 3907 if (sdiodev->settings->bus.sdio.drive_strength) 3908 drivestrength = sdiodev->settings->bus.sdio.drive_strength; 3909 else 3910 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH; 3911 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength); 3912 3913 /* Set card control so an SDIO card reset does a WLAN backplane reset */ 3914 reg_val = brcmf_sdiod_func0_rb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err); 3915 if (err) 3916 goto fail; 3917 3918 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET; 3919 3920 brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err); 3921 if (err) 3922 goto fail; 3923 3924 /* set PMUControl so a backplane reset does PMU state reload */ 3925 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol); 3926 reg_val = brcmf_sdiod_readl(sdiodev, reg_addr, &err); 3927 if (err) 3928 goto fail; 3929 3930 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT); 3931 3932 brcmf_sdiod_writel(sdiodev, reg_addr, reg_val, &err); 3933 if (err) 3934 goto fail; 3935 3936 sdio_release_host(sdiodev->func1); 3937 3938 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); 3939 3940 /* allocate header buffer */ 3941 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL); 3942 if (!bus->hdrbuf) 3943 return false; 3944 /* Locate an appropriately-aligned portion of hdrbuf */ 3945 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], 3946 bus->head_align); 3947 3948 /* Set the poll and/or interrupt flags */ 3949 bus->intr = true; 3950 bus->poll = false; 3951 if (bus->poll) 3952 bus->pollrate = 1; 3953 3954 return true; 3955 3956 fail: 3957 sdio_release_host(sdiodev->func1); 3958 return false; 3959 } 3960 3961 static int 3962 brcmf_sdio_watchdog_thread(void *data) 3963 { 3964 struct brcmf_sdio *bus = (struct brcmf_sdio *)data; 3965 int wait; 3966 3967 allow_signal(SIGTERM); 3968 /* Run until signal received */ 3969 brcmf_sdiod_freezer_count(bus->sdiodev); 3970 while (1) { 3971 if (kthread_should_stop()) 3972 break; 3973 brcmf_sdiod_freezer_uncount(bus->sdiodev); 3974 wait = wait_for_completion_interruptible(&bus->watchdog_wait); 3975 brcmf_sdiod_freezer_count(bus->sdiodev); 3976 brcmf_sdiod_try_freeze(bus->sdiodev); 3977 if (!wait) { 3978 brcmf_sdio_bus_watchdog(bus); 3979 /* Count the tick for reference */ 3980 bus->sdcnt.tickcnt++; 3981 reinit_completion(&bus->watchdog_wait); 3982 } else 3983 break; 3984 } 3985 return 0; 3986 } 3987 3988 static void 3989 brcmf_sdio_watchdog(struct timer_list *t) 3990 { 3991 struct brcmf_sdio *bus = from_timer(bus, t, timer); 3992 3993 if (bus->watchdog_tsk) { 3994 complete(&bus->watchdog_wait); 3995 /* Reschedule the watchdog */ 3996 if (bus->wd_active) 3997 mod_timer(&bus->timer, 3998 jiffies + BRCMF_WD_POLL); 3999 } 4000 } 4001 4002 static 4003 int brcmf_sdio_get_fwname(struct device *dev, const char *ext, u8 *fw_name) 4004 { 4005 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4006 struct brcmf_fw_request *fwreq; 4007 struct brcmf_fw_name fwnames[] = { 4008 { ext, fw_name }, 4009 }; 4010 4011 fwreq = brcmf_fw_alloc_request(bus_if->chip, bus_if->chiprev, 4012 brcmf_sdio_fwnames, 4013 ARRAY_SIZE(brcmf_sdio_fwnames), 4014 fwnames, ARRAY_SIZE(fwnames)); 4015 if (!fwreq) 4016 return -ENOMEM; 4017 4018 kfree(fwreq); 4019 return 0; 4020 } 4021 4022 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = { 4023 .stop = brcmf_sdio_bus_stop, 4024 .preinit = brcmf_sdio_bus_preinit, 4025 .txdata = brcmf_sdio_bus_txdata, 4026 .txctl = brcmf_sdio_bus_txctl, 4027 .rxctl = brcmf_sdio_bus_rxctl, 4028 .gettxq = brcmf_sdio_bus_gettxq, 4029 .wowl_config = brcmf_sdio_wowl_config, 4030 .get_ramsize = brcmf_sdio_bus_get_ramsize, 4031 .get_memdump = brcmf_sdio_bus_get_memdump, 4032 .get_fwname = brcmf_sdio_get_fwname, 4033 }; 4034 4035 #define BRCMF_SDIO_FW_CODE 0 4036 #define BRCMF_SDIO_FW_NVRAM 1 4037 4038 static void brcmf_sdio_firmware_callback(struct device *dev, int err, 4039 struct brcmf_fw_request *fwreq) 4040 { 4041 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4042 struct brcmf_sdio_dev *sdiod = bus_if->bus_priv.sdio; 4043 struct brcmf_sdio *bus = sdiod->bus; 4044 struct brcmf_core *core = bus->sdio_core; 4045 const struct firmware *code; 4046 void *nvram; 4047 u32 nvram_len; 4048 u8 saveclk; 4049 4050 brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err); 4051 4052 if (err) 4053 goto fail; 4054 4055 code = fwreq->items[BRCMF_SDIO_FW_CODE].binary; 4056 nvram = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.data; 4057 nvram_len = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.len; 4058 kfree(fwreq); 4059 4060 /* try to download image and nvram to the dongle */ 4061 bus->alp_only = true; 4062 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len); 4063 if (err) 4064 goto fail; 4065 bus->alp_only = false; 4066 4067 /* Start the watchdog timer */ 4068 bus->sdcnt.tickcnt = 0; 4069 brcmf_sdio_wd_timer(bus, true); 4070 4071 sdio_claim_host(sdiod->func1); 4072 4073 /* Make sure backplane clock is on, needed to generate F2 interrupt */ 4074 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 4075 if (bus->clkstate != CLK_AVAIL) 4076 goto release; 4077 4078 /* Force clocks on backplane to be sure F2 interrupt propagates */ 4079 saveclk = brcmf_sdiod_readb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, &err); 4080 if (!err) { 4081 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, 4082 (saveclk | SBSDIO_FORCE_HT), &err); 4083 } 4084 if (err) { 4085 brcmf_err("Failed to force clock for F2: err %d\n", err); 4086 goto release; 4087 } 4088 4089 /* Enable function 2 (frame transfers) */ 4090 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailboxdata), 4091 SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, NULL); 4092 4093 err = sdio_enable_func(sdiod->func2); 4094 4095 brcmf_dbg(INFO, "enable F2: err=%d\n", err); 4096 4097 /* If F2 successfully enabled, set core and enable interrupts */ 4098 if (!err) { 4099 /* Set up the interrupt mask and enable interrupts */ 4100 bus->hostintmask = HOSTINTMASK; 4101 brcmf_sdiod_writel(sdiod, core->base + SD_REG(hostintmask), 4102 bus->hostintmask, NULL); 4103 4104 4105 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 8, &err); 4106 } else { 4107 /* Disable F2 again */ 4108 sdio_disable_func(sdiod->func2); 4109 goto release; 4110 } 4111 4112 if (brcmf_chip_sr_capable(bus->ci)) { 4113 brcmf_sdio_sr_init(bus); 4114 } else { 4115 /* Restore previous clock setting */ 4116 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, 4117 saveclk, &err); 4118 } 4119 4120 if (err == 0) { 4121 /* Allow full data communication using DPC from now on. */ 4122 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); 4123 4124 err = brcmf_sdiod_intr_register(sdiod); 4125 if (err != 0) 4126 brcmf_err("intr register failed:%d\n", err); 4127 } 4128 4129 /* If we didn't come up, turn off backplane clock */ 4130 if (err != 0) 4131 brcmf_sdio_clkctl(bus, CLK_NONE, false); 4132 4133 sdio_release_host(sdiod->func1); 4134 4135 /* Assign bus interface call back */ 4136 sdiod->bus_if->dev = sdiod->dev; 4137 sdiod->bus_if->ops = &brcmf_sdio_bus_ops; 4138 sdiod->bus_if->chip = bus->ci->chip; 4139 sdiod->bus_if->chiprev = bus->ci->chiprev; 4140 4141 /* Attach to the common layer, reserve hdr space */ 4142 err = brcmf_attach(sdiod->dev, sdiod->settings); 4143 if (err != 0) { 4144 brcmf_err("brcmf_attach failed\n"); 4145 goto fail; 4146 } 4147 4148 /* ready */ 4149 return; 4150 4151 release: 4152 sdio_release_host(sdiod->func1); 4153 fail: 4154 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err); 4155 device_release_driver(&sdiod->func2->dev); 4156 device_release_driver(dev); 4157 } 4158 4159 static struct brcmf_fw_request * 4160 brcmf_sdio_prepare_fw_request(struct brcmf_sdio *bus) 4161 { 4162 struct brcmf_fw_request *fwreq; 4163 struct brcmf_fw_name fwnames[] = { 4164 { ".bin", bus->sdiodev->fw_name }, 4165 { ".txt", bus->sdiodev->nvram_name }, 4166 }; 4167 4168 fwreq = brcmf_fw_alloc_request(bus->ci->chip, bus->ci->chiprev, 4169 brcmf_sdio_fwnames, 4170 ARRAY_SIZE(brcmf_sdio_fwnames), 4171 fwnames, ARRAY_SIZE(fwnames)); 4172 if (!fwreq) 4173 return NULL; 4174 4175 fwreq->items[BRCMF_SDIO_FW_CODE].type = BRCMF_FW_TYPE_BINARY; 4176 fwreq->items[BRCMF_SDIO_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM; 4177 4178 return fwreq; 4179 } 4180 4181 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev) 4182 { 4183 int ret; 4184 struct brcmf_sdio *bus; 4185 struct workqueue_struct *wq; 4186 struct brcmf_fw_request *fwreq; 4187 4188 brcmf_dbg(TRACE, "Enter\n"); 4189 4190 /* Allocate private bus interface state */ 4191 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC); 4192 if (!bus) 4193 goto fail; 4194 4195 bus->sdiodev = sdiodev; 4196 sdiodev->bus = bus; 4197 skb_queue_head_init(&bus->glom); 4198 bus->txbound = BRCMF_TXBOUND; 4199 bus->rxbound = BRCMF_RXBOUND; 4200 bus->txminmax = BRCMF_TXMINMAX; 4201 bus->tx_seq = SDPCM_SEQ_WRAP - 1; 4202 4203 /* single-threaded workqueue */ 4204 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM, 4205 dev_name(&sdiodev->func1->dev)); 4206 if (!wq) { 4207 brcmf_err("insufficient memory to create txworkqueue\n"); 4208 goto fail; 4209 } 4210 brcmf_sdiod_freezer_count(sdiodev); 4211 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker); 4212 bus->brcmf_wq = wq; 4213 4214 /* attempt to attach to the dongle */ 4215 if (!(brcmf_sdio_probe_attach(bus))) { 4216 brcmf_err("brcmf_sdio_probe_attach failed\n"); 4217 goto fail; 4218 } 4219 4220 spin_lock_init(&bus->rxctl_lock); 4221 spin_lock_init(&bus->txq_lock); 4222 init_waitqueue_head(&bus->ctrl_wait); 4223 init_waitqueue_head(&bus->dcmd_resp_wait); 4224 4225 /* Set up the watchdog timer */ 4226 timer_setup(&bus->timer, brcmf_sdio_watchdog, 0); 4227 /* Initialize watchdog thread */ 4228 init_completion(&bus->watchdog_wait); 4229 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread, 4230 bus, "brcmf_wdog/%s", 4231 dev_name(&sdiodev->func1->dev)); 4232 if (IS_ERR(bus->watchdog_tsk)) { 4233 pr_warn("brcmf_watchdog thread failed to start\n"); 4234 bus->watchdog_tsk = NULL; 4235 } 4236 /* Initialize DPC thread */ 4237 bus->dpc_triggered = false; 4238 bus->dpc_running = false; 4239 4240 /* default sdio bus header length for tx packet */ 4241 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; 4242 4243 /* Query the F2 block size, set roundup accordingly */ 4244 bus->blocksize = bus->sdiodev->func2->cur_blksize; 4245 bus->roundup = min(max_roundup, bus->blocksize); 4246 4247 sdio_claim_host(bus->sdiodev->func1); 4248 4249 /* Disable F2 to clear any intermediate frame state on the dongle */ 4250 sdio_disable_func(bus->sdiodev->func2); 4251 4252 bus->rxflow = false; 4253 4254 /* Done with backplane-dependent accesses, can drop clock... */ 4255 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); 4256 4257 sdio_release_host(bus->sdiodev->func1); 4258 4259 /* ...and initialize clock/power states */ 4260 bus->clkstate = CLK_SDONLY; 4261 bus->idletime = BRCMF_IDLE_INTERVAL; 4262 bus->idleclock = BRCMF_IDLE_ACTIVE; 4263 4264 /* SR state */ 4265 bus->sr_enabled = false; 4266 4267 brcmf_dbg(INFO, "completed!!\n"); 4268 4269 fwreq = brcmf_sdio_prepare_fw_request(bus); 4270 if (!fwreq) { 4271 ret = -ENOMEM; 4272 goto fail; 4273 } 4274 4275 ret = brcmf_fw_get_firmwares(sdiodev->dev, fwreq, 4276 brcmf_sdio_firmware_callback); 4277 if (ret != 0) { 4278 brcmf_err("async firmware request failed: %d\n", ret); 4279 kfree(fwreq); 4280 goto fail; 4281 } 4282 4283 return bus; 4284 4285 fail: 4286 brcmf_sdio_remove(bus); 4287 return NULL; 4288 } 4289 4290 /* Detach and free everything */ 4291 void brcmf_sdio_remove(struct brcmf_sdio *bus) 4292 { 4293 brcmf_dbg(TRACE, "Enter\n"); 4294 4295 if (bus) { 4296 /* Stop watchdog task */ 4297 if (bus->watchdog_tsk) { 4298 send_sig(SIGTERM, bus->watchdog_tsk, 1); 4299 kthread_stop(bus->watchdog_tsk); 4300 bus->watchdog_tsk = NULL; 4301 } 4302 4303 /* De-register interrupt handler */ 4304 brcmf_sdiod_intr_unregister(bus->sdiodev); 4305 4306 brcmf_detach(bus->sdiodev->dev); 4307 4308 cancel_work_sync(&bus->datawork); 4309 if (bus->brcmf_wq) 4310 destroy_workqueue(bus->brcmf_wq); 4311 4312 if (bus->ci) { 4313 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { 4314 sdio_claim_host(bus->sdiodev->func1); 4315 brcmf_sdio_wd_timer(bus, false); 4316 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 4317 /* Leave the device in state where it is 4318 * 'passive'. This is done by resetting all 4319 * necessary cores. 4320 */ 4321 msleep(20); 4322 brcmf_chip_set_passive(bus->ci); 4323 brcmf_sdio_clkctl(bus, CLK_NONE, false); 4324 sdio_release_host(bus->sdiodev->func1); 4325 } 4326 brcmf_chip_detach(bus->ci); 4327 } 4328 if (bus->sdiodev->settings) 4329 brcmf_release_module_param(bus->sdiodev->settings); 4330 4331 kfree(bus->rxbuf); 4332 kfree(bus->hdrbuf); 4333 kfree(bus); 4334 } 4335 4336 brcmf_dbg(TRACE, "Disconnected\n"); 4337 } 4338 4339 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active) 4340 { 4341 /* Totally stop the timer */ 4342 if (!active && bus->wd_active) { 4343 del_timer_sync(&bus->timer); 4344 bus->wd_active = false; 4345 return; 4346 } 4347 4348 /* don't start the wd until fw is loaded */ 4349 if (bus->sdiodev->state != BRCMF_SDIOD_DATA) 4350 return; 4351 4352 if (active) { 4353 if (!bus->wd_active) { 4354 /* Create timer again when watchdog period is 4355 dynamically changed or in the first instance 4356 */ 4357 bus->timer.expires = jiffies + BRCMF_WD_POLL; 4358 add_timer(&bus->timer); 4359 bus->wd_active = true; 4360 } else { 4361 /* Re arm the timer, at last watchdog period */ 4362 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL); 4363 } 4364 } 4365 } 4366 4367 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep) 4368 { 4369 int ret; 4370 4371 sdio_claim_host(bus->sdiodev->func1); 4372 ret = brcmf_sdio_bus_sleep(bus, sleep, false); 4373 sdio_release_host(bus->sdiodev->func1); 4374 4375 return ret; 4376 } 4377 4378