1 /* Copyright (c) 2014 Broadcom Corporation 2 * 3 * Permission to use, copy, modify, and/or distribute this software for any 4 * purpose with or without fee is hereby granted, provided that the above 5 * copyright notice and this permission notice appear in all copies. 6 * 7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 10 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 12 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 13 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/firmware.h> 19 #include <linux/pci.h> 20 #include <linux/vmalloc.h> 21 #include <linux/delay.h> 22 #include <linux/interrupt.h> 23 #include <linux/bcma/bcma.h> 24 #include <linux/sched.h> 25 #include <asm/unaligned.h> 26 27 #include <soc.h> 28 #include <chipcommon.h> 29 #include <brcmu_utils.h> 30 #include <brcmu_wifi.h> 31 #include <brcm_hw_ids.h> 32 33 #include "debug.h" 34 #include "bus.h" 35 #include "commonring.h" 36 #include "msgbuf.h" 37 #include "pcie.h" 38 #include "firmware.h" 39 #include "chip.h" 40 #include "core.h" 41 #include "common.h" 42 43 44 enum brcmf_pcie_state { 45 BRCMFMAC_PCIE_STATE_DOWN, 46 BRCMFMAC_PCIE_STATE_UP 47 }; 48 49 BRCMF_FW_NVRAM_DEF(43602, "brcmfmac43602-pcie.bin", "brcmfmac43602-pcie.txt"); 50 BRCMF_FW_NVRAM_DEF(4350, "brcmfmac4350-pcie.bin", "brcmfmac4350-pcie.txt"); 51 BRCMF_FW_NVRAM_DEF(4350C, "brcmfmac4350c2-pcie.bin", "brcmfmac4350c2-pcie.txt"); 52 BRCMF_FW_NVRAM_DEF(4356, "brcmfmac4356-pcie.bin", "brcmfmac4356-pcie.txt"); 53 BRCMF_FW_NVRAM_DEF(43570, "brcmfmac43570-pcie.bin", "brcmfmac43570-pcie.txt"); 54 BRCMF_FW_NVRAM_DEF(4358, "brcmfmac4358-pcie.bin", "brcmfmac4358-pcie.txt"); 55 BRCMF_FW_NVRAM_DEF(4359, "brcmfmac4359-pcie.bin", "brcmfmac4359-pcie.txt"); 56 BRCMF_FW_NVRAM_DEF(4365B, "brcmfmac4365b-pcie.bin", "brcmfmac4365b-pcie.txt"); 57 BRCMF_FW_NVRAM_DEF(4365C, "brcmfmac4365c-pcie.bin", "brcmfmac4365c-pcie.txt"); 58 BRCMF_FW_NVRAM_DEF(4366B, "brcmfmac4366b-pcie.bin", "brcmfmac4366b-pcie.txt"); 59 BRCMF_FW_NVRAM_DEF(4366C, "brcmfmac4366c-pcie.bin", "brcmfmac4366c-pcie.txt"); 60 BRCMF_FW_NVRAM_DEF(4371, "brcmfmac4371-pcie.bin", "brcmfmac4371-pcie.txt"); 61 62 static struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = { 63 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602), 64 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C), 65 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C), 66 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350), 67 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C), 68 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 69 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570), 70 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570), 71 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570), 72 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358), 73 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359), 74 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B), 75 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C), 76 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B), 77 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C), 78 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371), 79 }; 80 81 #define BRCMF_PCIE_FW_UP_TIMEOUT 2000 /* msec */ 82 83 #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024) 84 85 /* backplane addres space accessed by BAR0 */ 86 #define BRCMF_PCIE_BAR0_WINDOW 0x80 87 #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000 88 #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70 89 90 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000 91 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000 92 93 #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40 94 #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C 95 96 #define BRCMF_PCIE_REG_INTSTATUS 0x90 97 #define BRCMF_PCIE_REG_INTMASK 0x94 98 #define BRCMF_PCIE_REG_SBMBX 0x98 99 100 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC 101 102 #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24 103 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48 104 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C 105 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120 106 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124 107 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX 0x140 108 109 #define BRCMF_PCIE2_INTA 0x01 110 #define BRCMF_PCIE2_INTB 0x02 111 112 #define BRCMF_PCIE_INT_0 0x01 113 #define BRCMF_PCIE_INT_1 0x02 114 #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \ 115 BRCMF_PCIE_INT_1) 116 117 #define BRCMF_PCIE_MB_INT_FN0_0 0x0100 118 #define BRCMF_PCIE_MB_INT_FN0_1 0x0200 119 #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000 120 #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000 121 #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000 122 #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000 123 #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000 124 #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000 125 #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000 126 #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000 127 128 #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \ 129 BRCMF_PCIE_MB_INT_D2H0_DB1 | \ 130 BRCMF_PCIE_MB_INT_D2H1_DB0 | \ 131 BRCMF_PCIE_MB_INT_D2H1_DB1 | \ 132 BRCMF_PCIE_MB_INT_D2H2_DB0 | \ 133 BRCMF_PCIE_MB_INT_D2H2_DB1 | \ 134 BRCMF_PCIE_MB_INT_D2H3_DB0 | \ 135 BRCMF_PCIE_MB_INT_D2H3_DB1) 136 137 #define BRCMF_PCIE_MIN_SHARED_VERSION 5 138 #define BRCMF_PCIE_MAX_SHARED_VERSION 5 139 #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF 140 #define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000 141 #define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000 142 143 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000 144 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000 145 146 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34 147 #define BRCMF_SHARED_RING_BASE_OFFSET 52 148 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36 149 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20 150 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40 151 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44 152 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48 153 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52 154 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56 155 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64 156 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68 157 158 #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0 159 #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1 160 #define BRCMF_RING_H2D_RING_MEM_OFFSET 4 161 #define BRCMF_RING_H2D_RING_STATE_OFFSET 8 162 163 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8 164 #define BRCMF_RING_MAX_ITEM_OFFSET 4 165 #define BRCMF_RING_LEN_ITEMS_OFFSET 6 166 #define BRCMF_RING_MEM_SZ 16 167 #define BRCMF_RING_STATE_SZ 8 168 169 #define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET 4 170 #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET 8 171 #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET 12 172 #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET 16 173 #define BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET 20 174 #define BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET 28 175 #define BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET 36 176 #define BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET 44 177 #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET 0 178 #define BRCMF_SHARED_RING_MAX_SUB_QUEUES 52 179 180 #define BRCMF_DEF_MAX_RXBUFPOST 255 181 182 #define BRCMF_CONSOLE_BUFADDR_OFFSET 8 183 #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12 184 #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16 185 186 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8 187 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024 188 189 #define BRCMF_D2H_DEV_D3_ACK 0x00000001 190 #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002 191 #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004 192 193 #define BRCMF_H2D_HOST_D3_INFORM 0x00000001 194 #define BRCMF_H2D_HOST_DS_ACK 0x00000002 195 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008 196 #define BRCMF_H2D_HOST_D0_INFORM 0x00000010 197 198 #define BRCMF_PCIE_MBDATA_TIMEOUT msecs_to_jiffies(2000) 199 200 #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4 201 #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C 202 #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58 203 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C 204 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60 205 #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64 206 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC 207 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC 208 #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228 209 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248 210 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0 211 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4 212 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3 213 214 /* Magic number at a magic location to find RAM size */ 215 #define BRCMF_RAMSIZE_MAGIC 0x534d4152 /* SMAR */ 216 #define BRCMF_RAMSIZE_OFFSET 0x6c 217 218 219 struct brcmf_pcie_console { 220 u32 base_addr; 221 u32 buf_addr; 222 u32 bufsize; 223 u32 read_idx; 224 u8 log_str[256]; 225 u8 log_idx; 226 }; 227 228 struct brcmf_pcie_shared_info { 229 u32 tcm_base_address; 230 u32 flags; 231 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS]; 232 struct brcmf_pcie_ringbuf *flowrings; 233 u16 max_rxbufpost; 234 u32 nrof_flowrings; 235 u32 rx_dataoffset; 236 u32 htod_mb_data_addr; 237 u32 dtoh_mb_data_addr; 238 u32 ring_info_addr; 239 struct brcmf_pcie_console console; 240 void *scratch; 241 dma_addr_t scratch_dmahandle; 242 void *ringupd; 243 dma_addr_t ringupd_dmahandle; 244 }; 245 246 struct brcmf_pcie_core_info { 247 u32 base; 248 u32 wrapbase; 249 }; 250 251 struct brcmf_pciedev_info { 252 enum brcmf_pcie_state state; 253 bool in_irq; 254 struct pci_dev *pdev; 255 char fw_name[BRCMF_FW_NAME_LEN]; 256 char nvram_name[BRCMF_FW_NAME_LEN]; 257 void __iomem *regs; 258 void __iomem *tcm; 259 u32 ram_base; 260 u32 ram_size; 261 struct brcmf_chip *ci; 262 u32 coreid; 263 struct brcmf_pcie_shared_info shared; 264 wait_queue_head_t mbdata_resp_wait; 265 bool mbdata_completed; 266 bool irq_allocated; 267 bool wowl_enabled; 268 u8 dma_idx_sz; 269 void *idxbuf; 270 u32 idxbuf_sz; 271 dma_addr_t idxbuf_dmahandle; 272 u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset); 273 void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 274 u16 value); 275 struct brcmf_mp_device *settings; 276 }; 277 278 struct brcmf_pcie_ringbuf { 279 struct brcmf_commonring commonring; 280 dma_addr_t dma_handle; 281 u32 w_idx_addr; 282 u32 r_idx_addr; 283 struct brcmf_pciedev_info *devinfo; 284 u8 id; 285 }; 286 287 288 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = { 289 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM, 290 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM, 291 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM, 292 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM, 293 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM 294 }; 295 296 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = { 297 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 298 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 299 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 300 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE, 301 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE 302 }; 303 304 305 static u32 306 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset) 307 { 308 void __iomem *address = devinfo->regs + reg_offset; 309 310 return (ioread32(address)); 311 } 312 313 314 static void 315 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset, 316 u32 value) 317 { 318 void __iomem *address = devinfo->regs + reg_offset; 319 320 iowrite32(value, address); 321 } 322 323 324 static u8 325 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 326 { 327 void __iomem *address = devinfo->tcm + mem_offset; 328 329 return (ioread8(address)); 330 } 331 332 333 static u16 334 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 335 { 336 void __iomem *address = devinfo->tcm + mem_offset; 337 338 return (ioread16(address)); 339 } 340 341 342 static void 343 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 344 u16 value) 345 { 346 void __iomem *address = devinfo->tcm + mem_offset; 347 348 iowrite16(value, address); 349 } 350 351 352 static u16 353 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 354 { 355 u16 *address = devinfo->idxbuf + mem_offset; 356 357 return (*(address)); 358 } 359 360 361 static void 362 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 363 u16 value) 364 { 365 u16 *address = devinfo->idxbuf + mem_offset; 366 367 *(address) = value; 368 } 369 370 371 static u32 372 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 373 { 374 void __iomem *address = devinfo->tcm + mem_offset; 375 376 return (ioread32(address)); 377 } 378 379 380 static void 381 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 382 u32 value) 383 { 384 void __iomem *address = devinfo->tcm + mem_offset; 385 386 iowrite32(value, address); 387 } 388 389 390 static u32 391 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 392 { 393 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 394 395 return (ioread32(addr)); 396 } 397 398 399 static void 400 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 401 u32 value) 402 { 403 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 404 405 iowrite32(value, addr); 406 } 407 408 409 static void 410 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 411 void *srcaddr, u32 len) 412 { 413 void __iomem *address = devinfo->tcm + mem_offset; 414 __le32 *src32; 415 __le16 *src16; 416 u8 *src8; 417 418 if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) { 419 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) { 420 src8 = (u8 *)srcaddr; 421 while (len) { 422 iowrite8(*src8, address); 423 address++; 424 src8++; 425 len--; 426 } 427 } else { 428 len = len / 2; 429 src16 = (__le16 *)srcaddr; 430 while (len) { 431 iowrite16(le16_to_cpu(*src16), address); 432 address += 2; 433 src16++; 434 len--; 435 } 436 } 437 } else { 438 len = len / 4; 439 src32 = (__le32 *)srcaddr; 440 while (len) { 441 iowrite32(le32_to_cpu(*src32), address); 442 address += 4; 443 src32++; 444 len--; 445 } 446 } 447 } 448 449 450 static void 451 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 452 void *dstaddr, u32 len) 453 { 454 void __iomem *address = devinfo->tcm + mem_offset; 455 __le32 *dst32; 456 __le16 *dst16; 457 u8 *dst8; 458 459 if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) { 460 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) { 461 dst8 = (u8 *)dstaddr; 462 while (len) { 463 *dst8 = ioread8(address); 464 address++; 465 dst8++; 466 len--; 467 } 468 } else { 469 len = len / 2; 470 dst16 = (__le16 *)dstaddr; 471 while (len) { 472 *dst16 = cpu_to_le16(ioread16(address)); 473 address += 2; 474 dst16++; 475 len--; 476 } 477 } 478 } else { 479 len = len / 4; 480 dst32 = (__le32 *)dstaddr; 481 while (len) { 482 *dst32 = cpu_to_le32(ioread32(address)); 483 address += 4; 484 dst32++; 485 len--; 486 } 487 } 488 } 489 490 491 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \ 492 CHIPCREGOFFS(reg), value) 493 494 495 static void 496 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid) 497 { 498 const struct pci_dev *pdev = devinfo->pdev; 499 struct brcmf_core *core; 500 u32 bar0_win; 501 502 core = brcmf_chip_get_core(devinfo->ci, coreid); 503 if (core) { 504 bar0_win = core->base; 505 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win); 506 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, 507 &bar0_win) == 0) { 508 if (bar0_win != core->base) { 509 bar0_win = core->base; 510 pci_write_config_dword(pdev, 511 BRCMF_PCIE_BAR0_WINDOW, 512 bar0_win); 513 } 514 } 515 } else { 516 brcmf_err("Unsupported core selected %x\n", coreid); 517 } 518 } 519 520 521 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo) 522 { 523 struct brcmf_core *core; 524 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD, 525 BRCMF_PCIE_CFGREG_PM_CSR, 526 BRCMF_PCIE_CFGREG_MSI_CAP, 527 BRCMF_PCIE_CFGREG_MSI_ADDR_L, 528 BRCMF_PCIE_CFGREG_MSI_ADDR_H, 529 BRCMF_PCIE_CFGREG_MSI_DATA, 530 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2, 531 BRCMF_PCIE_CFGREG_RBAR_CTRL, 532 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1, 533 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG, 534 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG }; 535 u32 i; 536 u32 val; 537 u32 lsc; 538 539 if (!devinfo->ci) 540 return; 541 542 /* Disable ASPM */ 543 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 544 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 545 &lsc); 546 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB); 547 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 548 val); 549 550 /* Watchdog reset */ 551 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON); 552 WRITECC32(devinfo, watchdog, 4); 553 msleep(100); 554 555 /* Restore ASPM */ 556 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 557 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 558 lsc); 559 560 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 561 if (core->rev <= 13) { 562 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) { 563 brcmf_pcie_write_reg32(devinfo, 564 BRCMF_PCIE_PCIE2REG_CONFIGADDR, 565 cfg_offset[i]); 566 val = brcmf_pcie_read_reg32(devinfo, 567 BRCMF_PCIE_PCIE2REG_CONFIGDATA); 568 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n", 569 cfg_offset[i], val); 570 brcmf_pcie_write_reg32(devinfo, 571 BRCMF_PCIE_PCIE2REG_CONFIGDATA, 572 val); 573 } 574 } 575 } 576 577 578 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo) 579 { 580 u32 config; 581 582 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 583 /* BAR1 window may not be sized properly */ 584 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 585 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0); 586 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA); 587 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config); 588 589 device_wakeup_enable(&devinfo->pdev->dev); 590 } 591 592 593 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo) 594 { 595 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 596 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4); 597 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 598 5); 599 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 600 0); 601 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 602 7); 603 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 604 0); 605 } 606 return 0; 607 } 608 609 610 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo, 611 u32 resetintr) 612 { 613 struct brcmf_core *core; 614 615 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 616 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM); 617 brcmf_chip_resetcore(core, 0, 0, 0); 618 } 619 620 if (!brcmf_chip_set_active(devinfo->ci, resetintr)) 621 return -EINVAL; 622 return 0; 623 } 624 625 626 static int 627 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data) 628 { 629 struct brcmf_pcie_shared_info *shared; 630 u32 addr; 631 u32 cur_htod_mb_data; 632 u32 i; 633 634 shared = &devinfo->shared; 635 addr = shared->htod_mb_data_addr; 636 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 637 638 if (cur_htod_mb_data != 0) 639 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n", 640 cur_htod_mb_data); 641 642 i = 0; 643 while (cur_htod_mb_data != 0) { 644 msleep(10); 645 i++; 646 if (i > 100) 647 return -EIO; 648 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 649 } 650 651 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data); 652 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 653 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 654 655 return 0; 656 } 657 658 659 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo) 660 { 661 struct brcmf_pcie_shared_info *shared; 662 u32 addr; 663 u32 dtoh_mb_data; 664 665 shared = &devinfo->shared; 666 addr = shared->dtoh_mb_data_addr; 667 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 668 669 if (!dtoh_mb_data) 670 return; 671 672 brcmf_pcie_write_tcm32(devinfo, addr, 0); 673 674 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data); 675 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) { 676 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n"); 677 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK); 678 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n"); 679 } 680 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE) 681 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n"); 682 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) { 683 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n"); 684 devinfo->mbdata_completed = true; 685 wake_up(&devinfo->mbdata_resp_wait); 686 } 687 } 688 689 690 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo) 691 { 692 struct brcmf_pcie_shared_info *shared; 693 struct brcmf_pcie_console *console; 694 u32 addr; 695 696 shared = &devinfo->shared; 697 console = &shared->console; 698 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET; 699 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr); 700 701 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET; 702 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr); 703 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET; 704 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr); 705 706 brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n", 707 console->base_addr, console->buf_addr, console->bufsize); 708 } 709 710 711 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo) 712 { 713 struct brcmf_pcie_console *console; 714 u32 addr; 715 u8 ch; 716 u32 newidx; 717 718 if (!BRCMF_FWCON_ON()) 719 return; 720 721 console = &devinfo->shared.console; 722 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET; 723 newidx = brcmf_pcie_read_tcm32(devinfo, addr); 724 while (newidx != console->read_idx) { 725 addr = console->buf_addr + console->read_idx; 726 ch = brcmf_pcie_read_tcm8(devinfo, addr); 727 console->read_idx++; 728 if (console->read_idx == console->bufsize) 729 console->read_idx = 0; 730 if (ch == '\r') 731 continue; 732 console->log_str[console->log_idx] = ch; 733 console->log_idx++; 734 if ((ch != '\n') && 735 (console->log_idx == (sizeof(console->log_str) - 2))) { 736 ch = '\n'; 737 console->log_str[console->log_idx] = ch; 738 console->log_idx++; 739 } 740 if (ch == '\n') { 741 console->log_str[console->log_idx] = 0; 742 pr_debug("CONSOLE: %s", console->log_str); 743 console->log_idx = 0; 744 } 745 } 746 } 747 748 749 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo) 750 { 751 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 0); 752 } 753 754 755 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo) 756 { 757 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 758 BRCMF_PCIE_MB_INT_D2H_DB | 759 BRCMF_PCIE_MB_INT_FN0_0 | 760 BRCMF_PCIE_MB_INT_FN0_1); 761 } 762 763 764 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg) 765 { 766 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 767 768 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) { 769 brcmf_pcie_intr_disable(devinfo); 770 brcmf_dbg(PCIE, "Enter\n"); 771 return IRQ_WAKE_THREAD; 772 } 773 return IRQ_NONE; 774 } 775 776 777 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg) 778 { 779 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 780 u32 status; 781 782 devinfo->in_irq = true; 783 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 784 brcmf_dbg(PCIE, "Enter %x\n", status); 785 if (status) { 786 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, 787 status); 788 if (status & (BRCMF_PCIE_MB_INT_FN0_0 | 789 BRCMF_PCIE_MB_INT_FN0_1)) 790 brcmf_pcie_handle_mb_data(devinfo); 791 if (status & BRCMF_PCIE_MB_INT_D2H_DB) { 792 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 793 brcmf_proto_msgbuf_rx_trigger( 794 &devinfo->pdev->dev); 795 } 796 } 797 brcmf_pcie_bus_console_read(devinfo); 798 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 799 brcmf_pcie_intr_enable(devinfo); 800 devinfo->in_irq = false; 801 return IRQ_HANDLED; 802 } 803 804 805 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo) 806 { 807 struct pci_dev *pdev; 808 809 pdev = devinfo->pdev; 810 811 brcmf_pcie_intr_disable(devinfo); 812 813 brcmf_dbg(PCIE, "Enter\n"); 814 815 pci_enable_msi(pdev); 816 if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr, 817 brcmf_pcie_isr_thread, IRQF_SHARED, 818 "brcmf_pcie_intr", devinfo)) { 819 pci_disable_msi(pdev); 820 brcmf_err("Failed to request IRQ %d\n", pdev->irq); 821 return -EIO; 822 } 823 devinfo->irq_allocated = true; 824 return 0; 825 } 826 827 828 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo) 829 { 830 struct pci_dev *pdev; 831 u32 status; 832 u32 count; 833 834 if (!devinfo->irq_allocated) 835 return; 836 837 pdev = devinfo->pdev; 838 839 brcmf_pcie_intr_disable(devinfo); 840 free_irq(pdev->irq, devinfo); 841 pci_disable_msi(pdev); 842 843 msleep(50); 844 count = 0; 845 while ((devinfo->in_irq) && (count < 20)) { 846 msleep(50); 847 count++; 848 } 849 if (devinfo->in_irq) 850 brcmf_err("Still in IRQ (processing) !!!\n"); 851 852 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 853 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, status); 854 855 devinfo->irq_allocated = false; 856 } 857 858 859 static int brcmf_pcie_ring_mb_write_rptr(void *ctx) 860 { 861 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 862 struct brcmf_pciedev_info *devinfo = ring->devinfo; 863 struct brcmf_commonring *commonring = &ring->commonring; 864 865 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 866 return -EIO; 867 868 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr, 869 commonring->w_ptr, ring->id); 870 871 devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr); 872 873 return 0; 874 } 875 876 877 static int brcmf_pcie_ring_mb_write_wptr(void *ctx) 878 { 879 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 880 struct brcmf_pciedev_info *devinfo = ring->devinfo; 881 struct brcmf_commonring *commonring = &ring->commonring; 882 883 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 884 return -EIO; 885 886 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr, 887 commonring->r_ptr, ring->id); 888 889 devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr); 890 891 return 0; 892 } 893 894 895 static int brcmf_pcie_ring_mb_ring_bell(void *ctx) 896 { 897 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 898 struct brcmf_pciedev_info *devinfo = ring->devinfo; 899 900 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 901 return -EIO; 902 903 brcmf_dbg(PCIE, "RING !\n"); 904 /* Any arbitrary value will do, lets use 1 */ 905 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1); 906 907 return 0; 908 } 909 910 911 static int brcmf_pcie_ring_mb_update_rptr(void *ctx) 912 { 913 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 914 struct brcmf_pciedev_info *devinfo = ring->devinfo; 915 struct brcmf_commonring *commonring = &ring->commonring; 916 917 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 918 return -EIO; 919 920 commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr); 921 922 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr, 923 commonring->w_ptr, ring->id); 924 925 return 0; 926 } 927 928 929 static int brcmf_pcie_ring_mb_update_wptr(void *ctx) 930 { 931 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 932 struct brcmf_pciedev_info *devinfo = ring->devinfo; 933 struct brcmf_commonring *commonring = &ring->commonring; 934 935 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 936 return -EIO; 937 938 commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr); 939 940 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr, 941 commonring->r_ptr, ring->id); 942 943 return 0; 944 } 945 946 947 static void * 948 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo, 949 u32 size, u32 tcm_dma_phys_addr, 950 dma_addr_t *dma_handle) 951 { 952 void *ring; 953 u64 address; 954 955 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle, 956 GFP_KERNEL); 957 if (!ring) 958 return NULL; 959 960 address = (u64)*dma_handle; 961 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr, 962 address & 0xffffffff); 963 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32); 964 965 memset(ring, 0, size); 966 967 return (ring); 968 } 969 970 971 static struct brcmf_pcie_ringbuf * 972 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id, 973 u32 tcm_ring_phys_addr) 974 { 975 void *dma_buf; 976 dma_addr_t dma_handle; 977 struct brcmf_pcie_ringbuf *ring; 978 u32 size; 979 u32 addr; 980 981 size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id]; 982 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size, 983 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET, 984 &dma_handle); 985 if (!dma_buf) 986 return NULL; 987 988 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET; 989 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]); 990 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET; 991 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]); 992 993 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 994 if (!ring) { 995 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf, 996 dma_handle); 997 return NULL; 998 } 999 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id], 1000 brcmf_ring_itemsize[ring_id], dma_buf); 1001 ring->dma_handle = dma_handle; 1002 ring->devinfo = devinfo; 1003 brcmf_commonring_register_cb(&ring->commonring, 1004 brcmf_pcie_ring_mb_ring_bell, 1005 brcmf_pcie_ring_mb_update_rptr, 1006 brcmf_pcie_ring_mb_update_wptr, 1007 brcmf_pcie_ring_mb_write_rptr, 1008 brcmf_pcie_ring_mb_write_wptr, ring); 1009 1010 return (ring); 1011 } 1012 1013 1014 static void brcmf_pcie_release_ringbuffer(struct device *dev, 1015 struct brcmf_pcie_ringbuf *ring) 1016 { 1017 void *dma_buf; 1018 u32 size; 1019 1020 if (!ring) 1021 return; 1022 1023 dma_buf = ring->commonring.buf_addr; 1024 if (dma_buf) { 1025 size = ring->commonring.depth * ring->commonring.item_len; 1026 dma_free_coherent(dev, size, dma_buf, ring->dma_handle); 1027 } 1028 kfree(ring); 1029 } 1030 1031 1032 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo) 1033 { 1034 u32 i; 1035 1036 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1037 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev, 1038 devinfo->shared.commonrings[i]); 1039 devinfo->shared.commonrings[i] = NULL; 1040 } 1041 kfree(devinfo->shared.flowrings); 1042 devinfo->shared.flowrings = NULL; 1043 if (devinfo->idxbuf) { 1044 dma_free_coherent(&devinfo->pdev->dev, 1045 devinfo->idxbuf_sz, 1046 devinfo->idxbuf, 1047 devinfo->idxbuf_dmahandle); 1048 devinfo->idxbuf = NULL; 1049 } 1050 } 1051 1052 1053 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo) 1054 { 1055 struct brcmf_pcie_ringbuf *ring; 1056 struct brcmf_pcie_ringbuf *rings; 1057 u32 ring_addr; 1058 u32 d2h_w_idx_ptr; 1059 u32 d2h_r_idx_ptr; 1060 u32 h2d_w_idx_ptr; 1061 u32 h2d_r_idx_ptr; 1062 u32 addr; 1063 u32 ring_mem_ptr; 1064 u32 i; 1065 u64 address; 1066 u32 bufsz; 1067 u16 max_sub_queues; 1068 u8 idx_offset; 1069 1070 ring_addr = devinfo->shared.ring_info_addr; 1071 brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr); 1072 addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES; 1073 max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr); 1074 1075 if (devinfo->dma_idx_sz != 0) { 1076 bufsz = (BRCMF_NROF_D2H_COMMON_MSGRINGS + max_sub_queues) * 1077 devinfo->dma_idx_sz * 2; 1078 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz, 1079 &devinfo->idxbuf_dmahandle, 1080 GFP_KERNEL); 1081 if (!devinfo->idxbuf) 1082 devinfo->dma_idx_sz = 0; 1083 } 1084 1085 if (devinfo->dma_idx_sz == 0) { 1086 addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET; 1087 d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr); 1088 addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET; 1089 d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr); 1090 addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET; 1091 h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr); 1092 addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET; 1093 h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr); 1094 idx_offset = sizeof(u32); 1095 devinfo->write_ptr = brcmf_pcie_write_tcm16; 1096 devinfo->read_ptr = brcmf_pcie_read_tcm16; 1097 brcmf_dbg(PCIE, "Using TCM indices\n"); 1098 } else { 1099 memset(devinfo->idxbuf, 0, bufsz); 1100 devinfo->idxbuf_sz = bufsz; 1101 idx_offset = devinfo->dma_idx_sz; 1102 devinfo->write_ptr = brcmf_pcie_write_idx; 1103 devinfo->read_ptr = brcmf_pcie_read_idx; 1104 1105 h2d_w_idx_ptr = 0; 1106 addr = ring_addr + BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET; 1107 address = (u64)devinfo->idxbuf_dmahandle; 1108 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1109 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1110 1111 h2d_r_idx_ptr = h2d_w_idx_ptr + max_sub_queues * idx_offset; 1112 addr = ring_addr + BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET; 1113 address += max_sub_queues * idx_offset; 1114 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1115 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1116 1117 d2h_w_idx_ptr = h2d_r_idx_ptr + max_sub_queues * idx_offset; 1118 addr = ring_addr + BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET; 1119 address += max_sub_queues * idx_offset; 1120 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1121 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1122 1123 d2h_r_idx_ptr = d2h_w_idx_ptr + 1124 BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset; 1125 addr = ring_addr + BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET; 1126 address += BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset; 1127 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1128 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1129 brcmf_dbg(PCIE, "Using host memory indices\n"); 1130 } 1131 1132 addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET; 1133 ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr); 1134 1135 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) { 1136 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1137 if (!ring) 1138 goto fail; 1139 ring->w_idx_addr = h2d_w_idx_ptr; 1140 ring->r_idx_addr = h2d_r_idx_ptr; 1141 ring->id = i; 1142 devinfo->shared.commonrings[i] = ring; 1143 1144 h2d_w_idx_ptr += idx_offset; 1145 h2d_r_idx_ptr += idx_offset; 1146 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1147 } 1148 1149 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS; 1150 i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1151 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1152 if (!ring) 1153 goto fail; 1154 ring->w_idx_addr = d2h_w_idx_ptr; 1155 ring->r_idx_addr = d2h_r_idx_ptr; 1156 ring->id = i; 1157 devinfo->shared.commonrings[i] = ring; 1158 1159 d2h_w_idx_ptr += idx_offset; 1160 d2h_r_idx_ptr += idx_offset; 1161 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1162 } 1163 1164 devinfo->shared.nrof_flowrings = 1165 max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS; 1166 rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring), 1167 GFP_KERNEL); 1168 if (!rings) 1169 goto fail; 1170 1171 brcmf_dbg(PCIE, "Nr of flowrings is %d\n", 1172 devinfo->shared.nrof_flowrings); 1173 1174 for (i = 0; i < devinfo->shared.nrof_flowrings; i++) { 1175 ring = &rings[i]; 1176 ring->devinfo = devinfo; 1177 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS; 1178 brcmf_commonring_register_cb(&ring->commonring, 1179 brcmf_pcie_ring_mb_ring_bell, 1180 brcmf_pcie_ring_mb_update_rptr, 1181 brcmf_pcie_ring_mb_update_wptr, 1182 brcmf_pcie_ring_mb_write_rptr, 1183 brcmf_pcie_ring_mb_write_wptr, 1184 ring); 1185 ring->w_idx_addr = h2d_w_idx_ptr; 1186 ring->r_idx_addr = h2d_r_idx_ptr; 1187 h2d_w_idx_ptr += idx_offset; 1188 h2d_r_idx_ptr += idx_offset; 1189 } 1190 devinfo->shared.flowrings = rings; 1191 1192 return 0; 1193 1194 fail: 1195 brcmf_err("Allocating ring buffers failed\n"); 1196 brcmf_pcie_release_ringbuffers(devinfo); 1197 return -ENOMEM; 1198 } 1199 1200 1201 static void 1202 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1203 { 1204 if (devinfo->shared.scratch) 1205 dma_free_coherent(&devinfo->pdev->dev, 1206 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1207 devinfo->shared.scratch, 1208 devinfo->shared.scratch_dmahandle); 1209 if (devinfo->shared.ringupd) 1210 dma_free_coherent(&devinfo->pdev->dev, 1211 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1212 devinfo->shared.ringupd, 1213 devinfo->shared.ringupd_dmahandle); 1214 } 1215 1216 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1217 { 1218 u64 address; 1219 u32 addr; 1220 1221 devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev, 1222 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1223 &devinfo->shared.scratch_dmahandle, GFP_KERNEL); 1224 if (!devinfo->shared.scratch) 1225 goto fail; 1226 1227 memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); 1228 1229 addr = devinfo->shared.tcm_base_address + 1230 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET; 1231 address = (u64)devinfo->shared.scratch_dmahandle; 1232 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1233 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1234 addr = devinfo->shared.tcm_base_address + 1235 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET; 1236 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); 1237 1238 devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev, 1239 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1240 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL); 1241 if (!devinfo->shared.ringupd) 1242 goto fail; 1243 1244 memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); 1245 1246 addr = devinfo->shared.tcm_base_address + 1247 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET; 1248 address = (u64)devinfo->shared.ringupd_dmahandle; 1249 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1250 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1251 addr = devinfo->shared.tcm_base_address + 1252 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET; 1253 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); 1254 return 0; 1255 1256 fail: 1257 brcmf_err("Allocating scratch buffers failed\n"); 1258 brcmf_pcie_release_scratchbuffers(devinfo); 1259 return -ENOMEM; 1260 } 1261 1262 1263 static void brcmf_pcie_down(struct device *dev) 1264 { 1265 } 1266 1267 1268 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb) 1269 { 1270 return 0; 1271 } 1272 1273 1274 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg, 1275 uint len) 1276 { 1277 return 0; 1278 } 1279 1280 1281 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg, 1282 uint len) 1283 { 1284 return 0; 1285 } 1286 1287 1288 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled) 1289 { 1290 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1291 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1292 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1293 1294 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled); 1295 devinfo->wowl_enabled = enabled; 1296 } 1297 1298 1299 static size_t brcmf_pcie_get_ramsize(struct device *dev) 1300 { 1301 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1302 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1303 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1304 1305 return devinfo->ci->ramsize - devinfo->ci->srsize; 1306 } 1307 1308 1309 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len) 1310 { 1311 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1312 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1313 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1314 1315 brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len); 1316 brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len); 1317 return 0; 1318 } 1319 1320 1321 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = { 1322 .txdata = brcmf_pcie_tx, 1323 .stop = brcmf_pcie_down, 1324 .txctl = brcmf_pcie_tx_ctlpkt, 1325 .rxctl = brcmf_pcie_rx_ctlpkt, 1326 .wowl_config = brcmf_pcie_wowl_config, 1327 .get_ramsize = brcmf_pcie_get_ramsize, 1328 .get_memdump = brcmf_pcie_get_memdump, 1329 }; 1330 1331 1332 static void 1333 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data, 1334 u32 data_len) 1335 { 1336 __le32 *field; 1337 u32 newsize; 1338 1339 if (data_len < BRCMF_RAMSIZE_OFFSET + 8) 1340 return; 1341 1342 field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET]; 1343 if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC) 1344 return; 1345 field++; 1346 newsize = le32_to_cpup(field); 1347 1348 brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n", 1349 newsize); 1350 devinfo->ci->ramsize = newsize; 1351 } 1352 1353 1354 static int 1355 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo, 1356 u32 sharedram_addr) 1357 { 1358 struct brcmf_pcie_shared_info *shared; 1359 u32 addr; 1360 u32 version; 1361 1362 shared = &devinfo->shared; 1363 shared->tcm_base_address = sharedram_addr; 1364 1365 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr); 1366 version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK; 1367 brcmf_dbg(PCIE, "PCIe protocol version %d\n", version); 1368 if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) || 1369 (version < BRCMF_PCIE_MIN_SHARED_VERSION)) { 1370 brcmf_err("Unsupported PCIE version %d\n", version); 1371 return -EINVAL; 1372 } 1373 1374 /* check firmware support dma indicies */ 1375 if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) { 1376 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX) 1377 devinfo->dma_idx_sz = sizeof(u16); 1378 else 1379 devinfo->dma_idx_sz = sizeof(u32); 1380 } 1381 1382 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET; 1383 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr); 1384 if (shared->max_rxbufpost == 0) 1385 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST; 1386 1387 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET; 1388 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr); 1389 1390 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET; 1391 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1392 1393 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET; 1394 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1395 1396 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET; 1397 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1398 1399 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n", 1400 shared->max_rxbufpost, shared->rx_dataoffset); 1401 1402 brcmf_pcie_bus_console_init(devinfo); 1403 1404 return 0; 1405 } 1406 1407 1408 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo, 1409 const struct firmware *fw, void *nvram, 1410 u32 nvram_len) 1411 { 1412 u32 sharedram_addr; 1413 u32 sharedram_addr_written; 1414 u32 loop_counter; 1415 int err; 1416 u32 address; 1417 u32 resetintr; 1418 1419 brcmf_dbg(PCIE, "Halt ARM.\n"); 1420 err = brcmf_pcie_enter_download_state(devinfo); 1421 if (err) 1422 return err; 1423 1424 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name); 1425 brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase, 1426 (void *)fw->data, fw->size); 1427 1428 resetintr = get_unaligned_le32(fw->data); 1429 release_firmware(fw); 1430 1431 /* reset last 4 bytes of RAM address. to be used for shared 1432 * area. This identifies when FW is running 1433 */ 1434 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0); 1435 1436 if (nvram) { 1437 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name); 1438 address = devinfo->ci->rambase + devinfo->ci->ramsize - 1439 nvram_len; 1440 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len); 1441 brcmf_fw_nvram_free(nvram); 1442 } else { 1443 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n", 1444 devinfo->nvram_name); 1445 } 1446 1447 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo, 1448 devinfo->ci->ramsize - 1449 4); 1450 brcmf_dbg(PCIE, "Bring ARM in running state\n"); 1451 err = brcmf_pcie_exit_download_state(devinfo, resetintr); 1452 if (err) 1453 return err; 1454 1455 brcmf_dbg(PCIE, "Wait for FW init\n"); 1456 sharedram_addr = sharedram_addr_written; 1457 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50; 1458 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) { 1459 msleep(50); 1460 sharedram_addr = brcmf_pcie_read_ram32(devinfo, 1461 devinfo->ci->ramsize - 1462 4); 1463 loop_counter--; 1464 } 1465 if (sharedram_addr == sharedram_addr_written) { 1466 brcmf_err("FW failed to initialize\n"); 1467 return -ENODEV; 1468 } 1469 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr); 1470 1471 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr)); 1472 } 1473 1474 1475 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo) 1476 { 1477 struct pci_dev *pdev; 1478 int err; 1479 phys_addr_t bar0_addr, bar1_addr; 1480 ulong bar1_size; 1481 1482 pdev = devinfo->pdev; 1483 1484 err = pci_enable_device(pdev); 1485 if (err) { 1486 brcmf_err("pci_enable_device failed err=%d\n", err); 1487 return err; 1488 } 1489 1490 pci_set_master(pdev); 1491 1492 /* Bar-0 mapped address */ 1493 bar0_addr = pci_resource_start(pdev, 0); 1494 /* Bar-1 mapped address */ 1495 bar1_addr = pci_resource_start(pdev, 2); 1496 /* read Bar-1 mapped memory range */ 1497 bar1_size = pci_resource_len(pdev, 2); 1498 if ((bar1_size == 0) || (bar1_addr == 0)) { 1499 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n", 1500 bar1_size, (unsigned long long)bar1_addr); 1501 return -EINVAL; 1502 } 1503 1504 devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE); 1505 devinfo->tcm = ioremap_nocache(bar1_addr, bar1_size); 1506 1507 if (!devinfo->regs || !devinfo->tcm) { 1508 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs, 1509 devinfo->tcm); 1510 return -EINVAL; 1511 } 1512 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n", 1513 devinfo->regs, (unsigned long long)bar0_addr); 1514 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n", 1515 devinfo->tcm, (unsigned long long)bar1_addr, 1516 (unsigned int)bar1_size); 1517 1518 return 0; 1519 } 1520 1521 1522 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo) 1523 { 1524 if (devinfo->tcm) 1525 iounmap(devinfo->tcm); 1526 if (devinfo->regs) 1527 iounmap(devinfo->regs); 1528 1529 pci_disable_device(devinfo->pdev); 1530 } 1531 1532 1533 static int brcmf_pcie_attach_bus(struct brcmf_pciedev_info *devinfo) 1534 { 1535 int ret; 1536 1537 /* Attach to the common driver interface */ 1538 ret = brcmf_attach(&devinfo->pdev->dev, devinfo->settings); 1539 if (ret) { 1540 brcmf_err("brcmf_attach failed\n"); 1541 } else { 1542 ret = brcmf_bus_start(&devinfo->pdev->dev); 1543 if (ret) 1544 brcmf_err("dongle is not responding\n"); 1545 } 1546 1547 return ret; 1548 } 1549 1550 1551 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr) 1552 { 1553 u32 ret_addr; 1554 1555 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1); 1556 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1); 1557 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr); 1558 1559 return ret_addr; 1560 } 1561 1562 1563 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr) 1564 { 1565 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1566 1567 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1568 return brcmf_pcie_read_reg32(devinfo, addr); 1569 } 1570 1571 1572 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value) 1573 { 1574 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1575 1576 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1577 brcmf_pcie_write_reg32(devinfo, addr, value); 1578 } 1579 1580 1581 static int brcmf_pcie_buscoreprep(void *ctx) 1582 { 1583 return brcmf_pcie_get_resource(ctx); 1584 } 1585 1586 1587 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip) 1588 { 1589 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1590 u32 val; 1591 1592 devinfo->ci = chip; 1593 brcmf_pcie_reset_device(devinfo); 1594 1595 val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 1596 if (val != 0xffffffff) 1597 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, 1598 val); 1599 1600 return 0; 1601 } 1602 1603 1604 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip, 1605 u32 rstvec) 1606 { 1607 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1608 1609 brcmf_pcie_write_tcm32(devinfo, 0, rstvec); 1610 } 1611 1612 1613 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = { 1614 .prepare = brcmf_pcie_buscoreprep, 1615 .reset = brcmf_pcie_buscore_reset, 1616 .activate = brcmf_pcie_buscore_activate, 1617 .read32 = brcmf_pcie_buscore_read32, 1618 .write32 = brcmf_pcie_buscore_write32, 1619 }; 1620 1621 static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw, 1622 void *nvram, u32 nvram_len) 1623 { 1624 struct brcmf_bus *bus = dev_get_drvdata(dev); 1625 struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie; 1626 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo; 1627 struct brcmf_commonring **flowrings; 1628 int ret; 1629 u32 i; 1630 1631 brcmf_pcie_attach(devinfo); 1632 1633 /* Some of the firmwares have the size of the memory of the device 1634 * defined inside the firmware. This is because part of the memory in 1635 * the device is shared and the devision is determined by FW. Parse 1636 * the firmware and adjust the chip memory size now. 1637 */ 1638 brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size); 1639 1640 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len); 1641 if (ret) 1642 goto fail; 1643 1644 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 1645 1646 ret = brcmf_pcie_init_ringbuffers(devinfo); 1647 if (ret) 1648 goto fail; 1649 1650 ret = brcmf_pcie_init_scratchbuffers(devinfo); 1651 if (ret) 1652 goto fail; 1653 1654 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 1655 ret = brcmf_pcie_request_irq(devinfo); 1656 if (ret) 1657 goto fail; 1658 1659 /* hook the commonrings in the bus structure. */ 1660 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) 1661 bus->msgbuf->commonrings[i] = 1662 &devinfo->shared.commonrings[i]->commonring; 1663 1664 flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*flowrings), 1665 GFP_KERNEL); 1666 if (!flowrings) 1667 goto fail; 1668 1669 for (i = 0; i < devinfo->shared.nrof_flowrings; i++) 1670 flowrings[i] = &devinfo->shared.flowrings[i].commonring; 1671 bus->msgbuf->flowrings = flowrings; 1672 1673 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset; 1674 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost; 1675 bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings; 1676 1677 init_waitqueue_head(&devinfo->mbdata_resp_wait); 1678 1679 brcmf_pcie_intr_enable(devinfo); 1680 if (brcmf_pcie_attach_bus(devinfo) == 0) 1681 return; 1682 1683 brcmf_pcie_bus_console_read(devinfo); 1684 1685 fail: 1686 device_release_driver(dev); 1687 } 1688 1689 static int 1690 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1691 { 1692 int ret; 1693 struct brcmf_pciedev_info *devinfo; 1694 struct brcmf_pciedev *pcie_bus_dev; 1695 struct brcmf_bus *bus; 1696 u16 domain_nr; 1697 u16 bus_nr; 1698 1699 domain_nr = pci_domain_nr(pdev->bus) + 1; 1700 bus_nr = pdev->bus->number; 1701 brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device, 1702 domain_nr, bus_nr); 1703 1704 ret = -ENOMEM; 1705 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL); 1706 if (devinfo == NULL) 1707 return ret; 1708 1709 devinfo->pdev = pdev; 1710 pcie_bus_dev = NULL; 1711 devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops); 1712 if (IS_ERR(devinfo->ci)) { 1713 ret = PTR_ERR(devinfo->ci); 1714 devinfo->ci = NULL; 1715 goto fail; 1716 } 1717 1718 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL); 1719 if (pcie_bus_dev == NULL) { 1720 ret = -ENOMEM; 1721 goto fail; 1722 } 1723 1724 devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev, 1725 BRCMF_BUSTYPE_PCIE, 1726 devinfo->ci->chip, 1727 devinfo->ci->chiprev); 1728 if (!devinfo->settings) { 1729 ret = -ENOMEM; 1730 goto fail; 1731 } 1732 1733 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 1734 if (!bus) { 1735 ret = -ENOMEM; 1736 goto fail; 1737 } 1738 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL); 1739 if (!bus->msgbuf) { 1740 ret = -ENOMEM; 1741 kfree(bus); 1742 goto fail; 1743 } 1744 1745 /* hook it all together. */ 1746 pcie_bus_dev->devinfo = devinfo; 1747 pcie_bus_dev->bus = bus; 1748 bus->dev = &pdev->dev; 1749 bus->bus_priv.pcie = pcie_bus_dev; 1750 bus->ops = &brcmf_pcie_bus_ops; 1751 bus->proto_type = BRCMF_PROTO_MSGBUF; 1752 bus->chip = devinfo->coreid; 1753 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot); 1754 dev_set_drvdata(&pdev->dev, bus); 1755 1756 ret = brcmf_fw_map_chip_to_name(devinfo->ci->chip, devinfo->ci->chiprev, 1757 brcmf_pcie_fwnames, 1758 ARRAY_SIZE(brcmf_pcie_fwnames), 1759 devinfo->fw_name, devinfo->nvram_name); 1760 if (ret) 1761 goto fail_bus; 1762 1763 ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM | 1764 BRCMF_FW_REQ_NV_OPTIONAL, 1765 devinfo->fw_name, devinfo->nvram_name, 1766 brcmf_pcie_setup, domain_nr, bus_nr); 1767 if (ret == 0) 1768 return 0; 1769 fail_bus: 1770 kfree(bus->msgbuf); 1771 kfree(bus); 1772 fail: 1773 brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device); 1774 brcmf_pcie_release_resource(devinfo); 1775 if (devinfo->ci) 1776 brcmf_chip_detach(devinfo->ci); 1777 if (devinfo->settings) 1778 brcmf_release_module_param(devinfo->settings); 1779 kfree(pcie_bus_dev); 1780 kfree(devinfo); 1781 return ret; 1782 } 1783 1784 1785 static void 1786 brcmf_pcie_remove(struct pci_dev *pdev) 1787 { 1788 struct brcmf_pciedev_info *devinfo; 1789 struct brcmf_bus *bus; 1790 1791 brcmf_dbg(PCIE, "Enter\n"); 1792 1793 bus = dev_get_drvdata(&pdev->dev); 1794 if (bus == NULL) 1795 return; 1796 1797 devinfo = bus->bus_priv.pcie->devinfo; 1798 1799 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 1800 if (devinfo->ci) 1801 brcmf_pcie_intr_disable(devinfo); 1802 1803 brcmf_detach(&pdev->dev); 1804 1805 kfree(bus->bus_priv.pcie); 1806 kfree(bus->msgbuf->flowrings); 1807 kfree(bus->msgbuf); 1808 kfree(bus); 1809 1810 brcmf_pcie_release_irq(devinfo); 1811 brcmf_pcie_release_scratchbuffers(devinfo); 1812 brcmf_pcie_release_ringbuffers(devinfo); 1813 brcmf_pcie_reset_device(devinfo); 1814 brcmf_pcie_release_resource(devinfo); 1815 1816 if (devinfo->ci) 1817 brcmf_chip_detach(devinfo->ci); 1818 if (devinfo->settings) 1819 brcmf_release_module_param(devinfo->settings); 1820 1821 kfree(devinfo); 1822 dev_set_drvdata(&pdev->dev, NULL); 1823 } 1824 1825 1826 #ifdef CONFIG_PM 1827 1828 1829 static int brcmf_pcie_pm_enter_D3(struct device *dev) 1830 { 1831 struct brcmf_pciedev_info *devinfo; 1832 struct brcmf_bus *bus; 1833 1834 brcmf_dbg(PCIE, "Enter\n"); 1835 1836 bus = dev_get_drvdata(dev); 1837 devinfo = bus->bus_priv.pcie->devinfo; 1838 1839 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN); 1840 1841 devinfo->mbdata_completed = false; 1842 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM); 1843 1844 wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed, 1845 BRCMF_PCIE_MBDATA_TIMEOUT); 1846 if (!devinfo->mbdata_completed) { 1847 brcmf_err("Timeout on response for entering D3 substate\n"); 1848 return -EIO; 1849 } 1850 1851 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 1852 1853 return 0; 1854 } 1855 1856 1857 static int brcmf_pcie_pm_leave_D3(struct device *dev) 1858 { 1859 struct brcmf_pciedev_info *devinfo; 1860 struct brcmf_bus *bus; 1861 struct pci_dev *pdev; 1862 int err; 1863 1864 brcmf_dbg(PCIE, "Enter\n"); 1865 1866 bus = dev_get_drvdata(dev); 1867 devinfo = bus->bus_priv.pcie->devinfo; 1868 brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus); 1869 1870 /* Check if device is still up and running, if so we are ready */ 1871 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0) { 1872 brcmf_dbg(PCIE, "Try to wakeup device....\n"); 1873 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM)) 1874 goto cleanup; 1875 brcmf_dbg(PCIE, "Hot resume, continue....\n"); 1876 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 1877 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 1878 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 1879 brcmf_pcie_intr_enable(devinfo); 1880 return 0; 1881 } 1882 1883 cleanup: 1884 brcmf_chip_detach(devinfo->ci); 1885 devinfo->ci = NULL; 1886 pdev = devinfo->pdev; 1887 brcmf_pcie_remove(pdev); 1888 1889 err = brcmf_pcie_probe(pdev, NULL); 1890 if (err) 1891 brcmf_err("probe after resume failed, err=%d\n", err); 1892 1893 return err; 1894 } 1895 1896 1897 static const struct dev_pm_ops brcmf_pciedrvr_pm = { 1898 .suspend = brcmf_pcie_pm_enter_D3, 1899 .resume = brcmf_pcie_pm_leave_D3, 1900 .freeze = brcmf_pcie_pm_enter_D3, 1901 .restore = brcmf_pcie_pm_leave_D3, 1902 }; 1903 1904 1905 #endif /* CONFIG_PM */ 1906 1907 1908 #define BRCMF_PCIE_DEVICE(dev_id) { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\ 1909 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 } 1910 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev) { \ 1911 BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\ 1912 subvend, subdev, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 } 1913 1914 static struct pci_device_id brcmf_pcie_devid_table[] = { 1915 BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID), 1916 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID), 1917 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID), 1918 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID), 1919 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID), 1920 BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID), 1921 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID), 1922 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID), 1923 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID), 1924 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID), 1925 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID), 1926 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID), 1927 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID), 1928 BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365), 1929 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID), 1930 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID), 1931 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID), 1932 BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID), 1933 { /* end: all zeroes */ } 1934 }; 1935 1936 1937 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table); 1938 1939 1940 static struct pci_driver brcmf_pciedrvr = { 1941 .node = {}, 1942 .name = KBUILD_MODNAME, 1943 .id_table = brcmf_pcie_devid_table, 1944 .probe = brcmf_pcie_probe, 1945 .remove = brcmf_pcie_remove, 1946 #ifdef CONFIG_PM 1947 .driver.pm = &brcmf_pciedrvr_pm, 1948 #endif 1949 }; 1950 1951 1952 void brcmf_pcie_register(void) 1953 { 1954 int err; 1955 1956 brcmf_dbg(PCIE, "Enter\n"); 1957 err = pci_register_driver(&brcmf_pciedrvr); 1958 if (err) 1959 brcmf_err("PCIE driver registration failed, err=%d\n", err); 1960 } 1961 1962 1963 void brcmf_pcie_exit(void) 1964 { 1965 brcmf_dbg(PCIE, "Enter\n"); 1966 pci_unregister_driver(&brcmf_pciedrvr); 1967 } 1968