1 /* Copyright (c) 2014 Broadcom Corporation 2 * 3 * Permission to use, copy, modify, and/or distribute this software for any 4 * purpose with or without fee is hereby granted, provided that the above 5 * copyright notice and this permission notice appear in all copies. 6 * 7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 10 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 12 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 13 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/firmware.h> 19 #include <linux/pci.h> 20 #include <linux/vmalloc.h> 21 #include <linux/delay.h> 22 #include <linux/interrupt.h> 23 #include <linux/bcma/bcma.h> 24 #include <linux/sched.h> 25 #include <asm/unaligned.h> 26 27 #include <soc.h> 28 #include <chipcommon.h> 29 #include <brcmu_utils.h> 30 #include <brcmu_wifi.h> 31 #include <brcm_hw_ids.h> 32 33 #include "debug.h" 34 #include "bus.h" 35 #include "commonring.h" 36 #include "msgbuf.h" 37 #include "pcie.h" 38 #include "firmware.h" 39 #include "chip.h" 40 #include "core.h" 41 #include "common.h" 42 43 44 enum brcmf_pcie_state { 45 BRCMFMAC_PCIE_STATE_DOWN, 46 BRCMFMAC_PCIE_STATE_UP 47 }; 48 49 BRCMF_FW_NVRAM_DEF(43602, "brcmfmac43602-pcie.bin", "brcmfmac43602-pcie.txt"); 50 BRCMF_FW_NVRAM_DEF(4350, "brcmfmac4350-pcie.bin", "brcmfmac4350-pcie.txt"); 51 BRCMF_FW_NVRAM_DEF(4350C, "brcmfmac4350c2-pcie.bin", "brcmfmac4350c2-pcie.txt"); 52 BRCMF_FW_NVRAM_DEF(4356, "brcmfmac4356-pcie.bin", "brcmfmac4356-pcie.txt"); 53 BRCMF_FW_NVRAM_DEF(43570, "brcmfmac43570-pcie.bin", "brcmfmac43570-pcie.txt"); 54 BRCMF_FW_NVRAM_DEF(4358, "brcmfmac4358-pcie.bin", "brcmfmac4358-pcie.txt"); 55 BRCMF_FW_NVRAM_DEF(4359, "brcmfmac4359-pcie.bin", "brcmfmac4359-pcie.txt"); 56 BRCMF_FW_NVRAM_DEF(4365B, "brcmfmac4365b-pcie.bin", "brcmfmac4365b-pcie.txt"); 57 BRCMF_FW_NVRAM_DEF(4365C, "brcmfmac4365c-pcie.bin", "brcmfmac4365c-pcie.txt"); 58 BRCMF_FW_NVRAM_DEF(4366B, "brcmfmac4366b-pcie.bin", "brcmfmac4366b-pcie.txt"); 59 BRCMF_FW_NVRAM_DEF(4366C, "brcmfmac4366c-pcie.bin", "brcmfmac4366c-pcie.txt"); 60 BRCMF_FW_NVRAM_DEF(4371, "brcmfmac4371-pcie.bin", "brcmfmac4371-pcie.txt"); 61 62 static struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = { 63 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602), 64 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C), 65 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C), 66 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350), 67 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C), 68 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 69 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570), 70 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570), 71 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570), 72 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358), 73 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359), 74 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B), 75 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C), 76 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B), 77 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C), 78 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371), 79 }; 80 81 #define BRCMF_PCIE_FW_UP_TIMEOUT 2000 /* msec */ 82 83 #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024) 84 85 /* backplane addres space accessed by BAR0 */ 86 #define BRCMF_PCIE_BAR0_WINDOW 0x80 87 #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000 88 #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70 89 90 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000 91 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000 92 93 #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40 94 #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C 95 96 #define BRCMF_PCIE_REG_INTSTATUS 0x90 97 #define BRCMF_PCIE_REG_INTMASK 0x94 98 #define BRCMF_PCIE_REG_SBMBX 0x98 99 100 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC 101 102 #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24 103 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48 104 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C 105 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120 106 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124 107 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX 0x140 108 109 #define BRCMF_PCIE2_INTA 0x01 110 #define BRCMF_PCIE2_INTB 0x02 111 112 #define BRCMF_PCIE_INT_0 0x01 113 #define BRCMF_PCIE_INT_1 0x02 114 #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \ 115 BRCMF_PCIE_INT_1) 116 117 #define BRCMF_PCIE_MB_INT_FN0_0 0x0100 118 #define BRCMF_PCIE_MB_INT_FN0_1 0x0200 119 #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000 120 #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000 121 #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000 122 #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000 123 #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000 124 #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000 125 #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000 126 #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000 127 128 #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \ 129 BRCMF_PCIE_MB_INT_D2H0_DB1 | \ 130 BRCMF_PCIE_MB_INT_D2H1_DB0 | \ 131 BRCMF_PCIE_MB_INT_D2H1_DB1 | \ 132 BRCMF_PCIE_MB_INT_D2H2_DB0 | \ 133 BRCMF_PCIE_MB_INT_D2H2_DB1 | \ 134 BRCMF_PCIE_MB_INT_D2H3_DB0 | \ 135 BRCMF_PCIE_MB_INT_D2H3_DB1) 136 137 #define BRCMF_PCIE_MIN_SHARED_VERSION 5 138 #define BRCMF_PCIE_MAX_SHARED_VERSION 6 139 #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF 140 #define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000 141 #define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000 142 143 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000 144 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000 145 146 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34 147 #define BRCMF_SHARED_RING_BASE_OFFSET 52 148 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36 149 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20 150 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40 151 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44 152 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48 153 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52 154 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56 155 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64 156 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68 157 158 #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0 159 #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1 160 #define BRCMF_RING_H2D_RING_MEM_OFFSET 4 161 #define BRCMF_RING_H2D_RING_STATE_OFFSET 8 162 163 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8 164 #define BRCMF_RING_MAX_ITEM_OFFSET 4 165 #define BRCMF_RING_LEN_ITEMS_OFFSET 6 166 #define BRCMF_RING_MEM_SZ 16 167 #define BRCMF_RING_STATE_SZ 8 168 169 #define BRCMF_DEF_MAX_RXBUFPOST 255 170 171 #define BRCMF_CONSOLE_BUFADDR_OFFSET 8 172 #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12 173 #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16 174 175 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8 176 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024 177 178 #define BRCMF_D2H_DEV_D3_ACK 0x00000001 179 #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002 180 #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004 181 182 #define BRCMF_H2D_HOST_D3_INFORM 0x00000001 183 #define BRCMF_H2D_HOST_DS_ACK 0x00000002 184 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008 185 #define BRCMF_H2D_HOST_D0_INFORM 0x00000010 186 187 #define BRCMF_PCIE_MBDATA_TIMEOUT msecs_to_jiffies(2000) 188 189 #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4 190 #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C 191 #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58 192 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C 193 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60 194 #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64 195 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC 196 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC 197 #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228 198 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248 199 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0 200 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4 201 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3 202 203 /* Magic number at a magic location to find RAM size */ 204 #define BRCMF_RAMSIZE_MAGIC 0x534d4152 /* SMAR */ 205 #define BRCMF_RAMSIZE_OFFSET 0x6c 206 207 208 struct brcmf_pcie_console { 209 u32 base_addr; 210 u32 buf_addr; 211 u32 bufsize; 212 u32 read_idx; 213 u8 log_str[256]; 214 u8 log_idx; 215 }; 216 217 struct brcmf_pcie_shared_info { 218 u32 tcm_base_address; 219 u32 flags; 220 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS]; 221 struct brcmf_pcie_ringbuf *flowrings; 222 u16 max_rxbufpost; 223 u16 max_flowrings; 224 u16 max_submissionrings; 225 u16 max_completionrings; 226 u32 rx_dataoffset; 227 u32 htod_mb_data_addr; 228 u32 dtoh_mb_data_addr; 229 u32 ring_info_addr; 230 struct brcmf_pcie_console console; 231 void *scratch; 232 dma_addr_t scratch_dmahandle; 233 void *ringupd; 234 dma_addr_t ringupd_dmahandle; 235 u8 version; 236 }; 237 238 struct brcmf_pcie_core_info { 239 u32 base; 240 u32 wrapbase; 241 }; 242 243 struct brcmf_pciedev_info { 244 enum brcmf_pcie_state state; 245 bool in_irq; 246 struct pci_dev *pdev; 247 char fw_name[BRCMF_FW_NAME_LEN]; 248 char nvram_name[BRCMF_FW_NAME_LEN]; 249 void __iomem *regs; 250 void __iomem *tcm; 251 u32 ram_base; 252 u32 ram_size; 253 struct brcmf_chip *ci; 254 u32 coreid; 255 struct brcmf_pcie_shared_info shared; 256 wait_queue_head_t mbdata_resp_wait; 257 bool mbdata_completed; 258 bool irq_allocated; 259 bool wowl_enabled; 260 u8 dma_idx_sz; 261 void *idxbuf; 262 u32 idxbuf_sz; 263 dma_addr_t idxbuf_dmahandle; 264 u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset); 265 void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 266 u16 value); 267 struct brcmf_mp_device *settings; 268 }; 269 270 struct brcmf_pcie_ringbuf { 271 struct brcmf_commonring commonring; 272 dma_addr_t dma_handle; 273 u32 w_idx_addr; 274 u32 r_idx_addr; 275 struct brcmf_pciedev_info *devinfo; 276 u8 id; 277 }; 278 279 /** 280 * struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info 281 * 282 * @ringmem: dongle memory pointer to ring memory location 283 * @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers 284 * @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers 285 * @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers 286 * @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers 287 * @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers 288 * @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers 289 * @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers 290 * @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers 291 * @max_flowrings: maximum number of tx flow rings supported. 292 * @max_submissionrings: maximum number of submission rings(h2d) supported. 293 * @max_completionrings: maximum number of completion rings(d2h) supported. 294 */ 295 struct brcmf_pcie_dhi_ringinfo { 296 __le32 ringmem; 297 __le32 h2d_w_idx_ptr; 298 __le32 h2d_r_idx_ptr; 299 __le32 d2h_w_idx_ptr; 300 __le32 d2h_r_idx_ptr; 301 struct msgbuf_buf_addr h2d_w_idx_hostaddr; 302 struct msgbuf_buf_addr h2d_r_idx_hostaddr; 303 struct msgbuf_buf_addr d2h_w_idx_hostaddr; 304 struct msgbuf_buf_addr d2h_r_idx_hostaddr; 305 __le16 max_flowrings; 306 __le16 max_submissionrings; 307 __le16 max_completionrings; 308 }; 309 310 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = { 311 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM, 312 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM, 313 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM, 314 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM, 315 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM 316 }; 317 318 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = { 319 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 320 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 321 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 322 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE, 323 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE 324 }; 325 326 327 static u32 328 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset) 329 { 330 void __iomem *address = devinfo->regs + reg_offset; 331 332 return (ioread32(address)); 333 } 334 335 336 static void 337 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset, 338 u32 value) 339 { 340 void __iomem *address = devinfo->regs + reg_offset; 341 342 iowrite32(value, address); 343 } 344 345 346 static u8 347 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 348 { 349 void __iomem *address = devinfo->tcm + mem_offset; 350 351 return (ioread8(address)); 352 } 353 354 355 static u16 356 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 357 { 358 void __iomem *address = devinfo->tcm + mem_offset; 359 360 return (ioread16(address)); 361 } 362 363 364 static void 365 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 366 u16 value) 367 { 368 void __iomem *address = devinfo->tcm + mem_offset; 369 370 iowrite16(value, address); 371 } 372 373 374 static u16 375 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 376 { 377 u16 *address = devinfo->idxbuf + mem_offset; 378 379 return (*(address)); 380 } 381 382 383 static void 384 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 385 u16 value) 386 { 387 u16 *address = devinfo->idxbuf + mem_offset; 388 389 *(address) = value; 390 } 391 392 393 static u32 394 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 395 { 396 void __iomem *address = devinfo->tcm + mem_offset; 397 398 return (ioread32(address)); 399 } 400 401 402 static void 403 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 404 u32 value) 405 { 406 void __iomem *address = devinfo->tcm + mem_offset; 407 408 iowrite32(value, address); 409 } 410 411 412 static u32 413 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 414 { 415 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 416 417 return (ioread32(addr)); 418 } 419 420 421 static void 422 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 423 u32 value) 424 { 425 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 426 427 iowrite32(value, addr); 428 } 429 430 431 static void 432 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 433 void *srcaddr, u32 len) 434 { 435 void __iomem *address = devinfo->tcm + mem_offset; 436 __le32 *src32; 437 __le16 *src16; 438 u8 *src8; 439 440 if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) { 441 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) { 442 src8 = (u8 *)srcaddr; 443 while (len) { 444 iowrite8(*src8, address); 445 address++; 446 src8++; 447 len--; 448 } 449 } else { 450 len = len / 2; 451 src16 = (__le16 *)srcaddr; 452 while (len) { 453 iowrite16(le16_to_cpu(*src16), address); 454 address += 2; 455 src16++; 456 len--; 457 } 458 } 459 } else { 460 len = len / 4; 461 src32 = (__le32 *)srcaddr; 462 while (len) { 463 iowrite32(le32_to_cpu(*src32), address); 464 address += 4; 465 src32++; 466 len--; 467 } 468 } 469 } 470 471 472 static void 473 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 474 void *dstaddr, u32 len) 475 { 476 void __iomem *address = devinfo->tcm + mem_offset; 477 __le32 *dst32; 478 __le16 *dst16; 479 u8 *dst8; 480 481 if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) { 482 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) { 483 dst8 = (u8 *)dstaddr; 484 while (len) { 485 *dst8 = ioread8(address); 486 address++; 487 dst8++; 488 len--; 489 } 490 } else { 491 len = len / 2; 492 dst16 = (__le16 *)dstaddr; 493 while (len) { 494 *dst16 = cpu_to_le16(ioread16(address)); 495 address += 2; 496 dst16++; 497 len--; 498 } 499 } 500 } else { 501 len = len / 4; 502 dst32 = (__le32 *)dstaddr; 503 while (len) { 504 *dst32 = cpu_to_le32(ioread32(address)); 505 address += 4; 506 dst32++; 507 len--; 508 } 509 } 510 } 511 512 513 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \ 514 CHIPCREGOFFS(reg), value) 515 516 517 static void 518 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid) 519 { 520 const struct pci_dev *pdev = devinfo->pdev; 521 struct brcmf_core *core; 522 u32 bar0_win; 523 524 core = brcmf_chip_get_core(devinfo->ci, coreid); 525 if (core) { 526 bar0_win = core->base; 527 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win); 528 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, 529 &bar0_win) == 0) { 530 if (bar0_win != core->base) { 531 bar0_win = core->base; 532 pci_write_config_dword(pdev, 533 BRCMF_PCIE_BAR0_WINDOW, 534 bar0_win); 535 } 536 } 537 } else { 538 brcmf_err("Unsupported core selected %x\n", coreid); 539 } 540 } 541 542 543 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo) 544 { 545 struct brcmf_core *core; 546 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD, 547 BRCMF_PCIE_CFGREG_PM_CSR, 548 BRCMF_PCIE_CFGREG_MSI_CAP, 549 BRCMF_PCIE_CFGREG_MSI_ADDR_L, 550 BRCMF_PCIE_CFGREG_MSI_ADDR_H, 551 BRCMF_PCIE_CFGREG_MSI_DATA, 552 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2, 553 BRCMF_PCIE_CFGREG_RBAR_CTRL, 554 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1, 555 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG, 556 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG }; 557 u32 i; 558 u32 val; 559 u32 lsc; 560 561 if (!devinfo->ci) 562 return; 563 564 /* Disable ASPM */ 565 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 566 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 567 &lsc); 568 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB); 569 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 570 val); 571 572 /* Watchdog reset */ 573 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON); 574 WRITECC32(devinfo, watchdog, 4); 575 msleep(100); 576 577 /* Restore ASPM */ 578 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 579 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 580 lsc); 581 582 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 583 if (core->rev <= 13) { 584 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) { 585 brcmf_pcie_write_reg32(devinfo, 586 BRCMF_PCIE_PCIE2REG_CONFIGADDR, 587 cfg_offset[i]); 588 val = brcmf_pcie_read_reg32(devinfo, 589 BRCMF_PCIE_PCIE2REG_CONFIGDATA); 590 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n", 591 cfg_offset[i], val); 592 brcmf_pcie_write_reg32(devinfo, 593 BRCMF_PCIE_PCIE2REG_CONFIGDATA, 594 val); 595 } 596 } 597 } 598 599 600 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo) 601 { 602 u32 config; 603 604 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 605 /* BAR1 window may not be sized properly */ 606 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 607 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0); 608 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA); 609 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config); 610 611 device_wakeup_enable(&devinfo->pdev->dev); 612 } 613 614 615 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo) 616 { 617 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 618 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4); 619 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 620 5); 621 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 622 0); 623 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 624 7); 625 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 626 0); 627 } 628 return 0; 629 } 630 631 632 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo, 633 u32 resetintr) 634 { 635 struct brcmf_core *core; 636 637 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 638 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM); 639 brcmf_chip_resetcore(core, 0, 0, 0); 640 } 641 642 if (!brcmf_chip_set_active(devinfo->ci, resetintr)) 643 return -EINVAL; 644 return 0; 645 } 646 647 648 static int 649 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data) 650 { 651 struct brcmf_pcie_shared_info *shared; 652 u32 addr; 653 u32 cur_htod_mb_data; 654 u32 i; 655 656 shared = &devinfo->shared; 657 addr = shared->htod_mb_data_addr; 658 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 659 660 if (cur_htod_mb_data != 0) 661 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n", 662 cur_htod_mb_data); 663 664 i = 0; 665 while (cur_htod_mb_data != 0) { 666 msleep(10); 667 i++; 668 if (i > 100) 669 return -EIO; 670 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 671 } 672 673 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data); 674 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 675 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 676 677 return 0; 678 } 679 680 681 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo) 682 { 683 struct brcmf_pcie_shared_info *shared; 684 u32 addr; 685 u32 dtoh_mb_data; 686 687 shared = &devinfo->shared; 688 addr = shared->dtoh_mb_data_addr; 689 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 690 691 if (!dtoh_mb_data) 692 return; 693 694 brcmf_pcie_write_tcm32(devinfo, addr, 0); 695 696 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data); 697 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) { 698 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n"); 699 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK); 700 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n"); 701 } 702 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE) 703 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n"); 704 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) { 705 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n"); 706 devinfo->mbdata_completed = true; 707 wake_up(&devinfo->mbdata_resp_wait); 708 } 709 } 710 711 712 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo) 713 { 714 struct brcmf_pcie_shared_info *shared; 715 struct brcmf_pcie_console *console; 716 u32 addr; 717 718 shared = &devinfo->shared; 719 console = &shared->console; 720 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET; 721 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr); 722 723 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET; 724 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr); 725 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET; 726 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr); 727 728 brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n", 729 console->base_addr, console->buf_addr, console->bufsize); 730 } 731 732 733 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo) 734 { 735 struct brcmf_pcie_console *console; 736 u32 addr; 737 u8 ch; 738 u32 newidx; 739 740 if (!BRCMF_FWCON_ON()) 741 return; 742 743 console = &devinfo->shared.console; 744 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET; 745 newidx = brcmf_pcie_read_tcm32(devinfo, addr); 746 while (newidx != console->read_idx) { 747 addr = console->buf_addr + console->read_idx; 748 ch = brcmf_pcie_read_tcm8(devinfo, addr); 749 console->read_idx++; 750 if (console->read_idx == console->bufsize) 751 console->read_idx = 0; 752 if (ch == '\r') 753 continue; 754 console->log_str[console->log_idx] = ch; 755 console->log_idx++; 756 if ((ch != '\n') && 757 (console->log_idx == (sizeof(console->log_str) - 2))) { 758 ch = '\n'; 759 console->log_str[console->log_idx] = ch; 760 console->log_idx++; 761 } 762 if (ch == '\n') { 763 console->log_str[console->log_idx] = 0; 764 pr_debug("CONSOLE: %s", console->log_str); 765 console->log_idx = 0; 766 } 767 } 768 } 769 770 771 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo) 772 { 773 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 0); 774 } 775 776 777 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo) 778 { 779 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 780 BRCMF_PCIE_MB_INT_D2H_DB | 781 BRCMF_PCIE_MB_INT_FN0_0 | 782 BRCMF_PCIE_MB_INT_FN0_1); 783 } 784 785 786 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg) 787 { 788 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 789 790 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) { 791 brcmf_pcie_intr_disable(devinfo); 792 brcmf_dbg(PCIE, "Enter\n"); 793 return IRQ_WAKE_THREAD; 794 } 795 return IRQ_NONE; 796 } 797 798 799 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg) 800 { 801 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 802 u32 status; 803 804 devinfo->in_irq = true; 805 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 806 brcmf_dbg(PCIE, "Enter %x\n", status); 807 if (status) { 808 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, 809 status); 810 if (status & (BRCMF_PCIE_MB_INT_FN0_0 | 811 BRCMF_PCIE_MB_INT_FN0_1)) 812 brcmf_pcie_handle_mb_data(devinfo); 813 if (status & BRCMF_PCIE_MB_INT_D2H_DB) { 814 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 815 brcmf_proto_msgbuf_rx_trigger( 816 &devinfo->pdev->dev); 817 } 818 } 819 brcmf_pcie_bus_console_read(devinfo); 820 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 821 brcmf_pcie_intr_enable(devinfo); 822 devinfo->in_irq = false; 823 return IRQ_HANDLED; 824 } 825 826 827 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo) 828 { 829 struct pci_dev *pdev; 830 831 pdev = devinfo->pdev; 832 833 brcmf_pcie_intr_disable(devinfo); 834 835 brcmf_dbg(PCIE, "Enter\n"); 836 837 pci_enable_msi(pdev); 838 if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr, 839 brcmf_pcie_isr_thread, IRQF_SHARED, 840 "brcmf_pcie_intr", devinfo)) { 841 pci_disable_msi(pdev); 842 brcmf_err("Failed to request IRQ %d\n", pdev->irq); 843 return -EIO; 844 } 845 devinfo->irq_allocated = true; 846 return 0; 847 } 848 849 850 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo) 851 { 852 struct pci_dev *pdev; 853 u32 status; 854 u32 count; 855 856 if (!devinfo->irq_allocated) 857 return; 858 859 pdev = devinfo->pdev; 860 861 brcmf_pcie_intr_disable(devinfo); 862 free_irq(pdev->irq, devinfo); 863 pci_disable_msi(pdev); 864 865 msleep(50); 866 count = 0; 867 while ((devinfo->in_irq) && (count < 20)) { 868 msleep(50); 869 count++; 870 } 871 if (devinfo->in_irq) 872 brcmf_err("Still in IRQ (processing) !!!\n"); 873 874 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 875 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, status); 876 877 devinfo->irq_allocated = false; 878 } 879 880 881 static int brcmf_pcie_ring_mb_write_rptr(void *ctx) 882 { 883 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 884 struct brcmf_pciedev_info *devinfo = ring->devinfo; 885 struct brcmf_commonring *commonring = &ring->commonring; 886 887 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 888 return -EIO; 889 890 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr, 891 commonring->w_ptr, ring->id); 892 893 devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr); 894 895 return 0; 896 } 897 898 899 static int brcmf_pcie_ring_mb_write_wptr(void *ctx) 900 { 901 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 902 struct brcmf_pciedev_info *devinfo = ring->devinfo; 903 struct brcmf_commonring *commonring = &ring->commonring; 904 905 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 906 return -EIO; 907 908 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr, 909 commonring->r_ptr, ring->id); 910 911 devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr); 912 913 return 0; 914 } 915 916 917 static int brcmf_pcie_ring_mb_ring_bell(void *ctx) 918 { 919 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 920 struct brcmf_pciedev_info *devinfo = ring->devinfo; 921 922 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 923 return -EIO; 924 925 brcmf_dbg(PCIE, "RING !\n"); 926 /* Any arbitrary value will do, lets use 1 */ 927 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1); 928 929 return 0; 930 } 931 932 933 static int brcmf_pcie_ring_mb_update_rptr(void *ctx) 934 { 935 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 936 struct brcmf_pciedev_info *devinfo = ring->devinfo; 937 struct brcmf_commonring *commonring = &ring->commonring; 938 939 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 940 return -EIO; 941 942 commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr); 943 944 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr, 945 commonring->w_ptr, ring->id); 946 947 return 0; 948 } 949 950 951 static int brcmf_pcie_ring_mb_update_wptr(void *ctx) 952 { 953 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 954 struct brcmf_pciedev_info *devinfo = ring->devinfo; 955 struct brcmf_commonring *commonring = &ring->commonring; 956 957 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 958 return -EIO; 959 960 commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr); 961 962 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr, 963 commonring->r_ptr, ring->id); 964 965 return 0; 966 } 967 968 969 static void * 970 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo, 971 u32 size, u32 tcm_dma_phys_addr, 972 dma_addr_t *dma_handle) 973 { 974 void *ring; 975 u64 address; 976 977 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle, 978 GFP_KERNEL); 979 if (!ring) 980 return NULL; 981 982 address = (u64)*dma_handle; 983 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr, 984 address & 0xffffffff); 985 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32); 986 987 memset(ring, 0, size); 988 989 return (ring); 990 } 991 992 993 static struct brcmf_pcie_ringbuf * 994 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id, 995 u32 tcm_ring_phys_addr) 996 { 997 void *dma_buf; 998 dma_addr_t dma_handle; 999 struct brcmf_pcie_ringbuf *ring; 1000 u32 size; 1001 u32 addr; 1002 1003 size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id]; 1004 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size, 1005 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET, 1006 &dma_handle); 1007 if (!dma_buf) 1008 return NULL; 1009 1010 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET; 1011 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]); 1012 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET; 1013 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]); 1014 1015 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 1016 if (!ring) { 1017 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf, 1018 dma_handle); 1019 return NULL; 1020 } 1021 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id], 1022 brcmf_ring_itemsize[ring_id], dma_buf); 1023 ring->dma_handle = dma_handle; 1024 ring->devinfo = devinfo; 1025 brcmf_commonring_register_cb(&ring->commonring, 1026 brcmf_pcie_ring_mb_ring_bell, 1027 brcmf_pcie_ring_mb_update_rptr, 1028 brcmf_pcie_ring_mb_update_wptr, 1029 brcmf_pcie_ring_mb_write_rptr, 1030 brcmf_pcie_ring_mb_write_wptr, ring); 1031 1032 return (ring); 1033 } 1034 1035 1036 static void brcmf_pcie_release_ringbuffer(struct device *dev, 1037 struct brcmf_pcie_ringbuf *ring) 1038 { 1039 void *dma_buf; 1040 u32 size; 1041 1042 if (!ring) 1043 return; 1044 1045 dma_buf = ring->commonring.buf_addr; 1046 if (dma_buf) { 1047 size = ring->commonring.depth * ring->commonring.item_len; 1048 dma_free_coherent(dev, size, dma_buf, ring->dma_handle); 1049 } 1050 kfree(ring); 1051 } 1052 1053 1054 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo) 1055 { 1056 u32 i; 1057 1058 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1059 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev, 1060 devinfo->shared.commonrings[i]); 1061 devinfo->shared.commonrings[i] = NULL; 1062 } 1063 kfree(devinfo->shared.flowrings); 1064 devinfo->shared.flowrings = NULL; 1065 if (devinfo->idxbuf) { 1066 dma_free_coherent(&devinfo->pdev->dev, 1067 devinfo->idxbuf_sz, 1068 devinfo->idxbuf, 1069 devinfo->idxbuf_dmahandle); 1070 devinfo->idxbuf = NULL; 1071 } 1072 } 1073 1074 1075 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo) 1076 { 1077 struct brcmf_pcie_ringbuf *ring; 1078 struct brcmf_pcie_ringbuf *rings; 1079 u32 d2h_w_idx_ptr; 1080 u32 d2h_r_idx_ptr; 1081 u32 h2d_w_idx_ptr; 1082 u32 h2d_r_idx_ptr; 1083 u32 ring_mem_ptr; 1084 u32 i; 1085 u64 address; 1086 u32 bufsz; 1087 u8 idx_offset; 1088 struct brcmf_pcie_dhi_ringinfo ringinfo; 1089 u16 max_flowrings; 1090 u16 max_submissionrings; 1091 u16 max_completionrings; 1092 1093 memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr, 1094 sizeof(ringinfo)); 1095 if (devinfo->shared.version >= 6) { 1096 max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings); 1097 max_flowrings = le16_to_cpu(ringinfo.max_flowrings); 1098 max_completionrings = le16_to_cpu(ringinfo.max_completionrings); 1099 } else { 1100 max_submissionrings = le16_to_cpu(ringinfo.max_flowrings); 1101 max_flowrings = max_submissionrings - 1102 BRCMF_NROF_H2D_COMMON_MSGRINGS; 1103 max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS; 1104 } 1105 1106 if (devinfo->dma_idx_sz != 0) { 1107 bufsz = (max_submissionrings + max_completionrings) * 1108 devinfo->dma_idx_sz * 2; 1109 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz, 1110 &devinfo->idxbuf_dmahandle, 1111 GFP_KERNEL); 1112 if (!devinfo->idxbuf) 1113 devinfo->dma_idx_sz = 0; 1114 } 1115 1116 if (devinfo->dma_idx_sz == 0) { 1117 d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr); 1118 d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr); 1119 h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr); 1120 h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr); 1121 idx_offset = sizeof(u32); 1122 devinfo->write_ptr = brcmf_pcie_write_tcm16; 1123 devinfo->read_ptr = brcmf_pcie_read_tcm16; 1124 brcmf_dbg(PCIE, "Using TCM indices\n"); 1125 } else { 1126 memset(devinfo->idxbuf, 0, bufsz); 1127 devinfo->idxbuf_sz = bufsz; 1128 idx_offset = devinfo->dma_idx_sz; 1129 devinfo->write_ptr = brcmf_pcie_write_idx; 1130 devinfo->read_ptr = brcmf_pcie_read_idx; 1131 1132 h2d_w_idx_ptr = 0; 1133 address = (u64)devinfo->idxbuf_dmahandle; 1134 ringinfo.h2d_w_idx_hostaddr.low_addr = 1135 cpu_to_le32(address & 0xffffffff); 1136 ringinfo.h2d_w_idx_hostaddr.high_addr = 1137 cpu_to_le32(address >> 32); 1138 1139 h2d_r_idx_ptr = h2d_w_idx_ptr + 1140 max_submissionrings * idx_offset; 1141 address += max_submissionrings * idx_offset; 1142 ringinfo.h2d_r_idx_hostaddr.low_addr = 1143 cpu_to_le32(address & 0xffffffff); 1144 ringinfo.h2d_r_idx_hostaddr.high_addr = 1145 cpu_to_le32(address >> 32); 1146 1147 d2h_w_idx_ptr = h2d_r_idx_ptr + 1148 max_submissionrings * idx_offset; 1149 address += max_submissionrings * idx_offset; 1150 ringinfo.d2h_w_idx_hostaddr.low_addr = 1151 cpu_to_le32(address & 0xffffffff); 1152 ringinfo.d2h_w_idx_hostaddr.high_addr = 1153 cpu_to_le32(address >> 32); 1154 1155 d2h_r_idx_ptr = d2h_w_idx_ptr + 1156 max_completionrings * idx_offset; 1157 address += max_completionrings * idx_offset; 1158 ringinfo.d2h_r_idx_hostaddr.low_addr = 1159 cpu_to_le32(address & 0xffffffff); 1160 ringinfo.d2h_r_idx_hostaddr.high_addr = 1161 cpu_to_le32(address >> 32); 1162 1163 memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr, 1164 &ringinfo, sizeof(ringinfo)); 1165 brcmf_dbg(PCIE, "Using host memory indices\n"); 1166 } 1167 1168 ring_mem_ptr = le32_to_cpu(ringinfo.ringmem); 1169 1170 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) { 1171 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1172 if (!ring) 1173 goto fail; 1174 ring->w_idx_addr = h2d_w_idx_ptr; 1175 ring->r_idx_addr = h2d_r_idx_ptr; 1176 ring->id = i; 1177 devinfo->shared.commonrings[i] = ring; 1178 1179 h2d_w_idx_ptr += idx_offset; 1180 h2d_r_idx_ptr += idx_offset; 1181 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1182 } 1183 1184 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS; 1185 i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1186 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1187 if (!ring) 1188 goto fail; 1189 ring->w_idx_addr = d2h_w_idx_ptr; 1190 ring->r_idx_addr = d2h_r_idx_ptr; 1191 ring->id = i; 1192 devinfo->shared.commonrings[i] = ring; 1193 1194 d2h_w_idx_ptr += idx_offset; 1195 d2h_r_idx_ptr += idx_offset; 1196 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1197 } 1198 1199 devinfo->shared.max_flowrings = max_flowrings; 1200 devinfo->shared.max_submissionrings = max_submissionrings; 1201 devinfo->shared.max_completionrings = max_completionrings; 1202 rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL); 1203 if (!rings) 1204 goto fail; 1205 1206 brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings); 1207 1208 for (i = 0; i < max_flowrings; i++) { 1209 ring = &rings[i]; 1210 ring->devinfo = devinfo; 1211 ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART; 1212 brcmf_commonring_register_cb(&ring->commonring, 1213 brcmf_pcie_ring_mb_ring_bell, 1214 brcmf_pcie_ring_mb_update_rptr, 1215 brcmf_pcie_ring_mb_update_wptr, 1216 brcmf_pcie_ring_mb_write_rptr, 1217 brcmf_pcie_ring_mb_write_wptr, 1218 ring); 1219 ring->w_idx_addr = h2d_w_idx_ptr; 1220 ring->r_idx_addr = h2d_r_idx_ptr; 1221 h2d_w_idx_ptr += idx_offset; 1222 h2d_r_idx_ptr += idx_offset; 1223 } 1224 devinfo->shared.flowrings = rings; 1225 1226 return 0; 1227 1228 fail: 1229 brcmf_err("Allocating ring buffers failed\n"); 1230 brcmf_pcie_release_ringbuffers(devinfo); 1231 return -ENOMEM; 1232 } 1233 1234 1235 static void 1236 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1237 { 1238 if (devinfo->shared.scratch) 1239 dma_free_coherent(&devinfo->pdev->dev, 1240 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1241 devinfo->shared.scratch, 1242 devinfo->shared.scratch_dmahandle); 1243 if (devinfo->shared.ringupd) 1244 dma_free_coherent(&devinfo->pdev->dev, 1245 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1246 devinfo->shared.ringupd, 1247 devinfo->shared.ringupd_dmahandle); 1248 } 1249 1250 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1251 { 1252 u64 address; 1253 u32 addr; 1254 1255 devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev, 1256 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1257 &devinfo->shared.scratch_dmahandle, GFP_KERNEL); 1258 if (!devinfo->shared.scratch) 1259 goto fail; 1260 1261 memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); 1262 1263 addr = devinfo->shared.tcm_base_address + 1264 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET; 1265 address = (u64)devinfo->shared.scratch_dmahandle; 1266 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1267 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1268 addr = devinfo->shared.tcm_base_address + 1269 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET; 1270 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); 1271 1272 devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev, 1273 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1274 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL); 1275 if (!devinfo->shared.ringupd) 1276 goto fail; 1277 1278 memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); 1279 1280 addr = devinfo->shared.tcm_base_address + 1281 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET; 1282 address = (u64)devinfo->shared.ringupd_dmahandle; 1283 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1284 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1285 addr = devinfo->shared.tcm_base_address + 1286 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET; 1287 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); 1288 return 0; 1289 1290 fail: 1291 brcmf_err("Allocating scratch buffers failed\n"); 1292 brcmf_pcie_release_scratchbuffers(devinfo); 1293 return -ENOMEM; 1294 } 1295 1296 1297 static void brcmf_pcie_down(struct device *dev) 1298 { 1299 } 1300 1301 1302 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb) 1303 { 1304 return 0; 1305 } 1306 1307 1308 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg, 1309 uint len) 1310 { 1311 return 0; 1312 } 1313 1314 1315 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg, 1316 uint len) 1317 { 1318 return 0; 1319 } 1320 1321 1322 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled) 1323 { 1324 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1325 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1326 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1327 1328 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled); 1329 devinfo->wowl_enabled = enabled; 1330 } 1331 1332 1333 static size_t brcmf_pcie_get_ramsize(struct device *dev) 1334 { 1335 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1336 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1337 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1338 1339 return devinfo->ci->ramsize - devinfo->ci->srsize; 1340 } 1341 1342 1343 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len) 1344 { 1345 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1346 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1347 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1348 1349 brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len); 1350 brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len); 1351 return 0; 1352 } 1353 1354 1355 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = { 1356 .txdata = brcmf_pcie_tx, 1357 .stop = brcmf_pcie_down, 1358 .txctl = brcmf_pcie_tx_ctlpkt, 1359 .rxctl = brcmf_pcie_rx_ctlpkt, 1360 .wowl_config = brcmf_pcie_wowl_config, 1361 .get_ramsize = brcmf_pcie_get_ramsize, 1362 .get_memdump = brcmf_pcie_get_memdump, 1363 }; 1364 1365 1366 static void 1367 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data, 1368 u32 data_len) 1369 { 1370 __le32 *field; 1371 u32 newsize; 1372 1373 if (data_len < BRCMF_RAMSIZE_OFFSET + 8) 1374 return; 1375 1376 field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET]; 1377 if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC) 1378 return; 1379 field++; 1380 newsize = le32_to_cpup(field); 1381 1382 brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n", 1383 newsize); 1384 devinfo->ci->ramsize = newsize; 1385 } 1386 1387 1388 static int 1389 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo, 1390 u32 sharedram_addr) 1391 { 1392 struct brcmf_pcie_shared_info *shared; 1393 u32 addr; 1394 1395 shared = &devinfo->shared; 1396 shared->tcm_base_address = sharedram_addr; 1397 1398 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr); 1399 shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK); 1400 brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version); 1401 if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) || 1402 (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) { 1403 brcmf_err("Unsupported PCIE version %d\n", shared->version); 1404 return -EINVAL; 1405 } 1406 1407 /* check firmware support dma indicies */ 1408 if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) { 1409 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX) 1410 devinfo->dma_idx_sz = sizeof(u16); 1411 else 1412 devinfo->dma_idx_sz = sizeof(u32); 1413 } 1414 1415 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET; 1416 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr); 1417 if (shared->max_rxbufpost == 0) 1418 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST; 1419 1420 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET; 1421 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr); 1422 1423 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET; 1424 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1425 1426 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET; 1427 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1428 1429 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET; 1430 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1431 1432 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n", 1433 shared->max_rxbufpost, shared->rx_dataoffset); 1434 1435 brcmf_pcie_bus_console_init(devinfo); 1436 1437 return 0; 1438 } 1439 1440 1441 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo, 1442 const struct firmware *fw, void *nvram, 1443 u32 nvram_len) 1444 { 1445 u32 sharedram_addr; 1446 u32 sharedram_addr_written; 1447 u32 loop_counter; 1448 int err; 1449 u32 address; 1450 u32 resetintr; 1451 1452 brcmf_dbg(PCIE, "Halt ARM.\n"); 1453 err = brcmf_pcie_enter_download_state(devinfo); 1454 if (err) 1455 return err; 1456 1457 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name); 1458 brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase, 1459 (void *)fw->data, fw->size); 1460 1461 resetintr = get_unaligned_le32(fw->data); 1462 release_firmware(fw); 1463 1464 /* reset last 4 bytes of RAM address. to be used for shared 1465 * area. This identifies when FW is running 1466 */ 1467 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0); 1468 1469 if (nvram) { 1470 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name); 1471 address = devinfo->ci->rambase + devinfo->ci->ramsize - 1472 nvram_len; 1473 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len); 1474 brcmf_fw_nvram_free(nvram); 1475 } else { 1476 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n", 1477 devinfo->nvram_name); 1478 } 1479 1480 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo, 1481 devinfo->ci->ramsize - 1482 4); 1483 brcmf_dbg(PCIE, "Bring ARM in running state\n"); 1484 err = brcmf_pcie_exit_download_state(devinfo, resetintr); 1485 if (err) 1486 return err; 1487 1488 brcmf_dbg(PCIE, "Wait for FW init\n"); 1489 sharedram_addr = sharedram_addr_written; 1490 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50; 1491 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) { 1492 msleep(50); 1493 sharedram_addr = brcmf_pcie_read_ram32(devinfo, 1494 devinfo->ci->ramsize - 1495 4); 1496 loop_counter--; 1497 } 1498 if (sharedram_addr == sharedram_addr_written) { 1499 brcmf_err("FW failed to initialize\n"); 1500 return -ENODEV; 1501 } 1502 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr); 1503 1504 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr)); 1505 } 1506 1507 1508 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo) 1509 { 1510 struct pci_dev *pdev; 1511 int err; 1512 phys_addr_t bar0_addr, bar1_addr; 1513 ulong bar1_size; 1514 1515 pdev = devinfo->pdev; 1516 1517 err = pci_enable_device(pdev); 1518 if (err) { 1519 brcmf_err("pci_enable_device failed err=%d\n", err); 1520 return err; 1521 } 1522 1523 pci_set_master(pdev); 1524 1525 /* Bar-0 mapped address */ 1526 bar0_addr = pci_resource_start(pdev, 0); 1527 /* Bar-1 mapped address */ 1528 bar1_addr = pci_resource_start(pdev, 2); 1529 /* read Bar-1 mapped memory range */ 1530 bar1_size = pci_resource_len(pdev, 2); 1531 if ((bar1_size == 0) || (bar1_addr == 0)) { 1532 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n", 1533 bar1_size, (unsigned long long)bar1_addr); 1534 return -EINVAL; 1535 } 1536 1537 devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE); 1538 devinfo->tcm = ioremap_nocache(bar1_addr, bar1_size); 1539 1540 if (!devinfo->regs || !devinfo->tcm) { 1541 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs, 1542 devinfo->tcm); 1543 return -EINVAL; 1544 } 1545 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n", 1546 devinfo->regs, (unsigned long long)bar0_addr); 1547 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n", 1548 devinfo->tcm, (unsigned long long)bar1_addr, 1549 (unsigned int)bar1_size); 1550 1551 return 0; 1552 } 1553 1554 1555 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo) 1556 { 1557 if (devinfo->tcm) 1558 iounmap(devinfo->tcm); 1559 if (devinfo->regs) 1560 iounmap(devinfo->regs); 1561 1562 pci_disable_device(devinfo->pdev); 1563 } 1564 1565 1566 static int brcmf_pcie_attach_bus(struct brcmf_pciedev_info *devinfo) 1567 { 1568 int ret; 1569 1570 /* Attach to the common driver interface */ 1571 ret = brcmf_attach(&devinfo->pdev->dev, devinfo->settings); 1572 if (ret) { 1573 brcmf_err("brcmf_attach failed\n"); 1574 } else { 1575 ret = brcmf_bus_start(&devinfo->pdev->dev); 1576 if (ret) 1577 brcmf_err("dongle is not responding\n"); 1578 } 1579 1580 return ret; 1581 } 1582 1583 1584 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr) 1585 { 1586 u32 ret_addr; 1587 1588 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1); 1589 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1); 1590 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr); 1591 1592 return ret_addr; 1593 } 1594 1595 1596 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr) 1597 { 1598 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1599 1600 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1601 return brcmf_pcie_read_reg32(devinfo, addr); 1602 } 1603 1604 1605 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value) 1606 { 1607 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1608 1609 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1610 brcmf_pcie_write_reg32(devinfo, addr, value); 1611 } 1612 1613 1614 static int brcmf_pcie_buscoreprep(void *ctx) 1615 { 1616 return brcmf_pcie_get_resource(ctx); 1617 } 1618 1619 1620 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip) 1621 { 1622 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1623 u32 val; 1624 1625 devinfo->ci = chip; 1626 brcmf_pcie_reset_device(devinfo); 1627 1628 val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 1629 if (val != 0xffffffff) 1630 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, 1631 val); 1632 1633 return 0; 1634 } 1635 1636 1637 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip, 1638 u32 rstvec) 1639 { 1640 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1641 1642 brcmf_pcie_write_tcm32(devinfo, 0, rstvec); 1643 } 1644 1645 1646 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = { 1647 .prepare = brcmf_pcie_buscoreprep, 1648 .reset = brcmf_pcie_buscore_reset, 1649 .activate = brcmf_pcie_buscore_activate, 1650 .read32 = brcmf_pcie_buscore_read32, 1651 .write32 = brcmf_pcie_buscore_write32, 1652 }; 1653 1654 static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw, 1655 void *nvram, u32 nvram_len) 1656 { 1657 struct brcmf_bus *bus = dev_get_drvdata(dev); 1658 struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie; 1659 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo; 1660 struct brcmf_commonring **flowrings; 1661 int ret; 1662 u32 i; 1663 1664 brcmf_pcie_attach(devinfo); 1665 1666 /* Some of the firmwares have the size of the memory of the device 1667 * defined inside the firmware. This is because part of the memory in 1668 * the device is shared and the devision is determined by FW. Parse 1669 * the firmware and adjust the chip memory size now. 1670 */ 1671 brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size); 1672 1673 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len); 1674 if (ret) 1675 goto fail; 1676 1677 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 1678 1679 ret = brcmf_pcie_init_ringbuffers(devinfo); 1680 if (ret) 1681 goto fail; 1682 1683 ret = brcmf_pcie_init_scratchbuffers(devinfo); 1684 if (ret) 1685 goto fail; 1686 1687 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 1688 ret = brcmf_pcie_request_irq(devinfo); 1689 if (ret) 1690 goto fail; 1691 1692 /* hook the commonrings in the bus structure. */ 1693 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) 1694 bus->msgbuf->commonrings[i] = 1695 &devinfo->shared.commonrings[i]->commonring; 1696 1697 flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings), 1698 GFP_KERNEL); 1699 if (!flowrings) 1700 goto fail; 1701 1702 for (i = 0; i < devinfo->shared.max_flowrings; i++) 1703 flowrings[i] = &devinfo->shared.flowrings[i].commonring; 1704 bus->msgbuf->flowrings = flowrings; 1705 1706 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset; 1707 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost; 1708 bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings; 1709 1710 init_waitqueue_head(&devinfo->mbdata_resp_wait); 1711 1712 brcmf_pcie_intr_enable(devinfo); 1713 if (brcmf_pcie_attach_bus(devinfo) == 0) 1714 return; 1715 1716 brcmf_pcie_bus_console_read(devinfo); 1717 1718 fail: 1719 device_release_driver(dev); 1720 } 1721 1722 static int 1723 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1724 { 1725 int ret; 1726 struct brcmf_pciedev_info *devinfo; 1727 struct brcmf_pciedev *pcie_bus_dev; 1728 struct brcmf_bus *bus; 1729 u16 domain_nr; 1730 u16 bus_nr; 1731 1732 domain_nr = pci_domain_nr(pdev->bus) + 1; 1733 bus_nr = pdev->bus->number; 1734 brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device, 1735 domain_nr, bus_nr); 1736 1737 ret = -ENOMEM; 1738 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL); 1739 if (devinfo == NULL) 1740 return ret; 1741 1742 devinfo->pdev = pdev; 1743 pcie_bus_dev = NULL; 1744 devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops); 1745 if (IS_ERR(devinfo->ci)) { 1746 ret = PTR_ERR(devinfo->ci); 1747 devinfo->ci = NULL; 1748 goto fail; 1749 } 1750 1751 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL); 1752 if (pcie_bus_dev == NULL) { 1753 ret = -ENOMEM; 1754 goto fail; 1755 } 1756 1757 devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev, 1758 BRCMF_BUSTYPE_PCIE, 1759 devinfo->ci->chip, 1760 devinfo->ci->chiprev); 1761 if (!devinfo->settings) { 1762 ret = -ENOMEM; 1763 goto fail; 1764 } 1765 1766 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 1767 if (!bus) { 1768 ret = -ENOMEM; 1769 goto fail; 1770 } 1771 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL); 1772 if (!bus->msgbuf) { 1773 ret = -ENOMEM; 1774 kfree(bus); 1775 goto fail; 1776 } 1777 1778 /* hook it all together. */ 1779 pcie_bus_dev->devinfo = devinfo; 1780 pcie_bus_dev->bus = bus; 1781 bus->dev = &pdev->dev; 1782 bus->bus_priv.pcie = pcie_bus_dev; 1783 bus->ops = &brcmf_pcie_bus_ops; 1784 bus->proto_type = BRCMF_PROTO_MSGBUF; 1785 bus->chip = devinfo->coreid; 1786 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot); 1787 dev_set_drvdata(&pdev->dev, bus); 1788 1789 ret = brcmf_fw_map_chip_to_name(devinfo->ci->chip, devinfo->ci->chiprev, 1790 brcmf_pcie_fwnames, 1791 ARRAY_SIZE(brcmf_pcie_fwnames), 1792 devinfo->fw_name, devinfo->nvram_name); 1793 if (ret) 1794 goto fail_bus; 1795 1796 ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM | 1797 BRCMF_FW_REQ_NV_OPTIONAL, 1798 devinfo->fw_name, devinfo->nvram_name, 1799 brcmf_pcie_setup, domain_nr, bus_nr); 1800 if (ret == 0) 1801 return 0; 1802 fail_bus: 1803 kfree(bus->msgbuf); 1804 kfree(bus); 1805 fail: 1806 brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device); 1807 brcmf_pcie_release_resource(devinfo); 1808 if (devinfo->ci) 1809 brcmf_chip_detach(devinfo->ci); 1810 if (devinfo->settings) 1811 brcmf_release_module_param(devinfo->settings); 1812 kfree(pcie_bus_dev); 1813 kfree(devinfo); 1814 return ret; 1815 } 1816 1817 1818 static void 1819 brcmf_pcie_remove(struct pci_dev *pdev) 1820 { 1821 struct brcmf_pciedev_info *devinfo; 1822 struct brcmf_bus *bus; 1823 1824 brcmf_dbg(PCIE, "Enter\n"); 1825 1826 bus = dev_get_drvdata(&pdev->dev); 1827 if (bus == NULL) 1828 return; 1829 1830 devinfo = bus->bus_priv.pcie->devinfo; 1831 1832 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 1833 if (devinfo->ci) 1834 brcmf_pcie_intr_disable(devinfo); 1835 1836 brcmf_detach(&pdev->dev); 1837 1838 kfree(bus->bus_priv.pcie); 1839 kfree(bus->msgbuf->flowrings); 1840 kfree(bus->msgbuf); 1841 kfree(bus); 1842 1843 brcmf_pcie_release_irq(devinfo); 1844 brcmf_pcie_release_scratchbuffers(devinfo); 1845 brcmf_pcie_release_ringbuffers(devinfo); 1846 brcmf_pcie_reset_device(devinfo); 1847 brcmf_pcie_release_resource(devinfo); 1848 1849 if (devinfo->ci) 1850 brcmf_chip_detach(devinfo->ci); 1851 if (devinfo->settings) 1852 brcmf_release_module_param(devinfo->settings); 1853 1854 kfree(devinfo); 1855 dev_set_drvdata(&pdev->dev, NULL); 1856 } 1857 1858 1859 #ifdef CONFIG_PM 1860 1861 1862 static int brcmf_pcie_pm_enter_D3(struct device *dev) 1863 { 1864 struct brcmf_pciedev_info *devinfo; 1865 struct brcmf_bus *bus; 1866 1867 brcmf_dbg(PCIE, "Enter\n"); 1868 1869 bus = dev_get_drvdata(dev); 1870 devinfo = bus->bus_priv.pcie->devinfo; 1871 1872 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN); 1873 1874 devinfo->mbdata_completed = false; 1875 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM); 1876 1877 wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed, 1878 BRCMF_PCIE_MBDATA_TIMEOUT); 1879 if (!devinfo->mbdata_completed) { 1880 brcmf_err("Timeout on response for entering D3 substate\n"); 1881 return -EIO; 1882 } 1883 1884 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 1885 1886 return 0; 1887 } 1888 1889 1890 static int brcmf_pcie_pm_leave_D3(struct device *dev) 1891 { 1892 struct brcmf_pciedev_info *devinfo; 1893 struct brcmf_bus *bus; 1894 struct pci_dev *pdev; 1895 int err; 1896 1897 brcmf_dbg(PCIE, "Enter\n"); 1898 1899 bus = dev_get_drvdata(dev); 1900 devinfo = bus->bus_priv.pcie->devinfo; 1901 brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus); 1902 1903 /* Check if device is still up and running, if so we are ready */ 1904 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0) { 1905 brcmf_dbg(PCIE, "Try to wakeup device....\n"); 1906 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM)) 1907 goto cleanup; 1908 brcmf_dbg(PCIE, "Hot resume, continue....\n"); 1909 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 1910 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 1911 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 1912 brcmf_pcie_intr_enable(devinfo); 1913 return 0; 1914 } 1915 1916 cleanup: 1917 brcmf_chip_detach(devinfo->ci); 1918 devinfo->ci = NULL; 1919 pdev = devinfo->pdev; 1920 brcmf_pcie_remove(pdev); 1921 1922 err = brcmf_pcie_probe(pdev, NULL); 1923 if (err) 1924 brcmf_err("probe after resume failed, err=%d\n", err); 1925 1926 return err; 1927 } 1928 1929 1930 static const struct dev_pm_ops brcmf_pciedrvr_pm = { 1931 .suspend = brcmf_pcie_pm_enter_D3, 1932 .resume = brcmf_pcie_pm_leave_D3, 1933 .freeze = brcmf_pcie_pm_enter_D3, 1934 .restore = brcmf_pcie_pm_leave_D3, 1935 }; 1936 1937 1938 #endif /* CONFIG_PM */ 1939 1940 1941 #define BRCMF_PCIE_DEVICE(dev_id) { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\ 1942 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 } 1943 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev) { \ 1944 BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\ 1945 subvend, subdev, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 } 1946 1947 static struct pci_device_id brcmf_pcie_devid_table[] = { 1948 BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID), 1949 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID), 1950 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID), 1951 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID), 1952 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID), 1953 BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID), 1954 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID), 1955 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID), 1956 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID), 1957 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID), 1958 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID), 1959 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID), 1960 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID), 1961 BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365), 1962 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID), 1963 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID), 1964 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID), 1965 BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID), 1966 { /* end: all zeroes */ } 1967 }; 1968 1969 1970 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table); 1971 1972 1973 static struct pci_driver brcmf_pciedrvr = { 1974 .node = {}, 1975 .name = KBUILD_MODNAME, 1976 .id_table = brcmf_pcie_devid_table, 1977 .probe = brcmf_pcie_probe, 1978 .remove = brcmf_pcie_remove, 1979 #ifdef CONFIG_PM 1980 .driver.pm = &brcmf_pciedrvr_pm, 1981 #endif 1982 }; 1983 1984 1985 void brcmf_pcie_register(void) 1986 { 1987 int err; 1988 1989 brcmf_dbg(PCIE, "Enter\n"); 1990 err = pci_register_driver(&brcmf_pciedrvr); 1991 if (err) 1992 brcmf_err("PCIE driver registration failed, err=%d\n", err); 1993 } 1994 1995 1996 void brcmf_pcie_exit(void) 1997 { 1998 brcmf_dbg(PCIE, "Enter\n"); 1999 pci_unregister_driver(&brcmf_pciedrvr); 2000 } 2001