1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2014 Broadcom Corporation 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/firmware.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/bcma/bcma.h> 14 #include <linux/sched.h> 15 #include <linux/sched/signal.h> 16 #include <linux/kthread.h> 17 #include <linux/io.h> 18 #include <asm/unaligned.h> 19 20 #include <soc.h> 21 #include <chipcommon.h> 22 #include <brcmu_utils.h> 23 #include <brcmu_wifi.h> 24 #include <brcm_hw_ids.h> 25 26 /* Custom brcmf_err() that takes bus arg and passes it further */ 27 #define brcmf_err(bus, fmt, ...) \ 28 do { \ 29 if (IS_ENABLED(CONFIG_BRCMDBG) || \ 30 IS_ENABLED(CONFIG_BRCM_TRACING) || \ 31 net_ratelimit()) \ 32 __brcmf_err(bus, __func__, fmt, ##__VA_ARGS__); \ 33 } while (0) 34 35 #include "debug.h" 36 #include "bus.h" 37 #include "commonring.h" 38 #include "msgbuf.h" 39 #include "pcie.h" 40 #include "firmware.h" 41 #include "chip.h" 42 #include "core.h" 43 #include "common.h" 44 45 46 enum brcmf_pcie_state { 47 BRCMFMAC_PCIE_STATE_DOWN, 48 BRCMFMAC_PCIE_STATE_UP 49 }; 50 51 BRCMF_FW_DEF(43602, "brcmfmac43602-pcie"); 52 BRCMF_FW_DEF(4350, "brcmfmac4350-pcie"); 53 BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie"); 54 BRCMF_FW_CLM_DEF(4355, "brcmfmac4355-pcie"); 55 BRCMF_FW_CLM_DEF(4355C1, "brcmfmac4355c1-pcie"); 56 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-pcie"); 57 BRCMF_FW_CLM_DEF(43570, "brcmfmac43570-pcie"); 58 BRCMF_FW_DEF(4358, "brcmfmac4358-pcie"); 59 BRCMF_FW_DEF(4359, "brcmfmac4359-pcie"); 60 BRCMF_FW_CLM_DEF(4364B2, "brcmfmac4364b2-pcie"); 61 BRCMF_FW_CLM_DEF(4364B3, "brcmfmac4364b3-pcie"); 62 BRCMF_FW_DEF(4365B, "brcmfmac4365b-pcie"); 63 BRCMF_FW_DEF(4365C, "brcmfmac4365c-pcie"); 64 BRCMF_FW_DEF(4366B, "brcmfmac4366b-pcie"); 65 BRCMF_FW_DEF(4366C, "brcmfmac4366c-pcie"); 66 BRCMF_FW_DEF(4371, "brcmfmac4371-pcie"); 67 BRCMF_FW_CLM_DEF(4377B3, "brcmfmac4377b3-pcie"); 68 BRCMF_FW_CLM_DEF(4378B1, "brcmfmac4378b1-pcie"); 69 70 /* firmware config files */ 71 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt"); 72 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txt"); 73 74 /* per-board firmware binaries */ 75 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.bin"); 76 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.clm_blob"); 77 78 static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = { 79 BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602), 80 BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C), 81 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C), 82 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350), 83 BRCMF_FW_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C), 84 BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0x000007FF, 4355), 85 BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0xFFFFF800, 4355C1), /* rev ID 12/C2 seen */ 86 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 87 BRCMF_FW_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570), 88 BRCMF_FW_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570), 89 BRCMF_FW_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570), 90 BRCMF_FW_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358), 91 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359), 92 BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0x0000000F, 4364B2), /* 3 */ 93 BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0xFFFFFFF0, 4364B3), /* 4 */ 94 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B), 95 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C), 96 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B), 97 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C), 98 BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C), 99 BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C), 100 BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371), 101 BRCMF_FW_ENTRY(BRCM_CC_4377_CHIP_ID, 0xFFFFFFFF, 4377B3), /* revision ID 4 */ 102 BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFFF, 4378B1), /* revision ID 3 */ 103 }; 104 105 #define BRCMF_PCIE_FW_UP_TIMEOUT 5000 /* msec */ 106 107 #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024) 108 109 /* backplane addres space accessed by BAR0 */ 110 #define BRCMF_PCIE_BAR0_WINDOW 0x80 111 #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000 112 #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70 113 114 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000 115 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000 116 117 #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40 118 #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C 119 120 #define BRCMF_PCIE_REG_INTSTATUS 0x90 121 #define BRCMF_PCIE_REG_INTMASK 0x94 122 #define BRCMF_PCIE_REG_SBMBX 0x98 123 124 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC 125 126 #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24 127 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48 128 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C 129 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120 130 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124 131 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0 0x140 132 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1 0x144 133 134 #define BRCMF_PCIE_64_PCIE2REG_INTMASK 0xC14 135 #define BRCMF_PCIE_64_PCIE2REG_MAILBOXINT 0xC30 136 #define BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK 0xC34 137 #define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0 0xA20 138 #define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1 0xA24 139 140 #define BRCMF_PCIE2_INTA 0x01 141 #define BRCMF_PCIE2_INTB 0x02 142 143 #define BRCMF_PCIE_INT_0 0x01 144 #define BRCMF_PCIE_INT_1 0x02 145 #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \ 146 BRCMF_PCIE_INT_1) 147 148 #define BRCMF_PCIE_MB_INT_FN0_0 0x0100 149 #define BRCMF_PCIE_MB_INT_FN0_1 0x0200 150 #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000 151 #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000 152 #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000 153 #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000 154 #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000 155 #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000 156 #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000 157 #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000 158 159 #define BRCMF_PCIE_MB_INT_FN0 (BRCMF_PCIE_MB_INT_FN0_0 | \ 160 BRCMF_PCIE_MB_INT_FN0_1) 161 #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \ 162 BRCMF_PCIE_MB_INT_D2H0_DB1 | \ 163 BRCMF_PCIE_MB_INT_D2H1_DB0 | \ 164 BRCMF_PCIE_MB_INT_D2H1_DB1 | \ 165 BRCMF_PCIE_MB_INT_D2H2_DB0 | \ 166 BRCMF_PCIE_MB_INT_D2H2_DB1 | \ 167 BRCMF_PCIE_MB_INT_D2H3_DB0 | \ 168 BRCMF_PCIE_MB_INT_D2H3_DB1) 169 170 #define BRCMF_PCIE_64_MB_INT_D2H0_DB0 0x1 171 #define BRCMF_PCIE_64_MB_INT_D2H0_DB1 0x2 172 #define BRCMF_PCIE_64_MB_INT_D2H1_DB0 0x4 173 #define BRCMF_PCIE_64_MB_INT_D2H1_DB1 0x8 174 #define BRCMF_PCIE_64_MB_INT_D2H2_DB0 0x10 175 #define BRCMF_PCIE_64_MB_INT_D2H2_DB1 0x20 176 #define BRCMF_PCIE_64_MB_INT_D2H3_DB0 0x40 177 #define BRCMF_PCIE_64_MB_INT_D2H3_DB1 0x80 178 #define BRCMF_PCIE_64_MB_INT_D2H4_DB0 0x100 179 #define BRCMF_PCIE_64_MB_INT_D2H4_DB1 0x200 180 #define BRCMF_PCIE_64_MB_INT_D2H5_DB0 0x400 181 #define BRCMF_PCIE_64_MB_INT_D2H5_DB1 0x800 182 #define BRCMF_PCIE_64_MB_INT_D2H6_DB0 0x1000 183 #define BRCMF_PCIE_64_MB_INT_D2H6_DB1 0x2000 184 #define BRCMF_PCIE_64_MB_INT_D2H7_DB0 0x4000 185 #define BRCMF_PCIE_64_MB_INT_D2H7_DB1 0x8000 186 187 #define BRCMF_PCIE_64_MB_INT_D2H_DB (BRCMF_PCIE_64_MB_INT_D2H0_DB0 | \ 188 BRCMF_PCIE_64_MB_INT_D2H0_DB1 | \ 189 BRCMF_PCIE_64_MB_INT_D2H1_DB0 | \ 190 BRCMF_PCIE_64_MB_INT_D2H1_DB1 | \ 191 BRCMF_PCIE_64_MB_INT_D2H2_DB0 | \ 192 BRCMF_PCIE_64_MB_INT_D2H2_DB1 | \ 193 BRCMF_PCIE_64_MB_INT_D2H3_DB0 | \ 194 BRCMF_PCIE_64_MB_INT_D2H3_DB1 | \ 195 BRCMF_PCIE_64_MB_INT_D2H4_DB0 | \ 196 BRCMF_PCIE_64_MB_INT_D2H4_DB1 | \ 197 BRCMF_PCIE_64_MB_INT_D2H5_DB0 | \ 198 BRCMF_PCIE_64_MB_INT_D2H5_DB1 | \ 199 BRCMF_PCIE_64_MB_INT_D2H6_DB0 | \ 200 BRCMF_PCIE_64_MB_INT_D2H6_DB1 | \ 201 BRCMF_PCIE_64_MB_INT_D2H7_DB0 | \ 202 BRCMF_PCIE_64_MB_INT_D2H7_DB1) 203 204 #define BRCMF_PCIE_SHARED_VERSION_7 7 205 #define BRCMF_PCIE_MIN_SHARED_VERSION 5 206 #define BRCMF_PCIE_MAX_SHARED_VERSION BRCMF_PCIE_SHARED_VERSION_7 207 #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF 208 #define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000 209 #define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000 210 #define BRCMF_PCIE_SHARED_HOSTRDY_DB1 0x10000000 211 212 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000 213 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000 214 215 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34 216 #define BRCMF_SHARED_RING_BASE_OFFSET 52 217 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36 218 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20 219 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40 220 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44 221 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48 222 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52 223 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56 224 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64 225 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68 226 227 #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0 228 #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1 229 #define BRCMF_RING_H2D_RING_MEM_OFFSET 4 230 #define BRCMF_RING_H2D_RING_STATE_OFFSET 8 231 232 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8 233 #define BRCMF_RING_MAX_ITEM_OFFSET 4 234 #define BRCMF_RING_LEN_ITEMS_OFFSET 6 235 #define BRCMF_RING_MEM_SZ 16 236 #define BRCMF_RING_STATE_SZ 8 237 238 #define BRCMF_DEF_MAX_RXBUFPOST 255 239 240 #define BRCMF_CONSOLE_BUFADDR_OFFSET 8 241 #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12 242 #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16 243 244 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8 245 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024 246 247 #define BRCMF_D2H_DEV_D3_ACK 0x00000001 248 #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002 249 #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004 250 #define BRCMF_D2H_DEV_FWHALT 0x10000000 251 252 #define BRCMF_H2D_HOST_D3_INFORM 0x00000001 253 #define BRCMF_H2D_HOST_DS_ACK 0x00000002 254 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008 255 #define BRCMF_H2D_HOST_D0_INFORM 0x00000010 256 257 #define BRCMF_PCIE_MBDATA_TIMEOUT msecs_to_jiffies(2000) 258 259 #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4 260 #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C 261 #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58 262 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C 263 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60 264 #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64 265 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC 266 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC 267 #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228 268 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248 269 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0 270 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4 271 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3 272 273 /* Magic number at a magic location to find RAM size */ 274 #define BRCMF_RAMSIZE_MAGIC 0x534d4152 /* SMAR */ 275 #define BRCMF_RAMSIZE_OFFSET 0x6c 276 277 278 struct brcmf_pcie_console { 279 u32 base_addr; 280 u32 buf_addr; 281 u32 bufsize; 282 u32 read_idx; 283 u8 log_str[256]; 284 u8 log_idx; 285 }; 286 287 struct brcmf_pcie_shared_info { 288 u32 tcm_base_address; 289 u32 flags; 290 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS]; 291 struct brcmf_pcie_ringbuf *flowrings; 292 u16 max_rxbufpost; 293 u16 max_flowrings; 294 u16 max_submissionrings; 295 u16 max_completionrings; 296 u32 rx_dataoffset; 297 u32 htod_mb_data_addr; 298 u32 dtoh_mb_data_addr; 299 u32 ring_info_addr; 300 struct brcmf_pcie_console console; 301 void *scratch; 302 dma_addr_t scratch_dmahandle; 303 void *ringupd; 304 dma_addr_t ringupd_dmahandle; 305 u8 version; 306 }; 307 308 struct brcmf_pcie_core_info { 309 u32 base; 310 u32 wrapbase; 311 }; 312 313 #define BRCMF_OTP_MAX_PARAM_LEN 16 314 315 struct brcmf_otp_params { 316 char module[BRCMF_OTP_MAX_PARAM_LEN]; 317 char vendor[BRCMF_OTP_MAX_PARAM_LEN]; 318 char version[BRCMF_OTP_MAX_PARAM_LEN]; 319 bool valid; 320 }; 321 322 struct brcmf_pciedev_info { 323 enum brcmf_pcie_state state; 324 bool in_irq; 325 struct pci_dev *pdev; 326 char fw_name[BRCMF_FW_NAME_LEN]; 327 char nvram_name[BRCMF_FW_NAME_LEN]; 328 char clm_name[BRCMF_FW_NAME_LEN]; 329 const struct firmware *clm_fw; 330 const struct brcmf_pcie_reginfo *reginfo; 331 void __iomem *regs; 332 void __iomem *tcm; 333 u32 ram_base; 334 u32 ram_size; 335 struct brcmf_chip *ci; 336 u32 coreid; 337 struct brcmf_pcie_shared_info shared; 338 wait_queue_head_t mbdata_resp_wait; 339 bool mbdata_completed; 340 bool irq_allocated; 341 bool wowl_enabled; 342 u8 dma_idx_sz; 343 void *idxbuf; 344 u32 idxbuf_sz; 345 dma_addr_t idxbuf_dmahandle; 346 u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset); 347 void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 348 u16 value); 349 struct brcmf_mp_device *settings; 350 struct brcmf_otp_params otp; 351 #ifdef DEBUG 352 u32 console_interval; 353 bool console_active; 354 struct timer_list timer; 355 #endif 356 }; 357 358 struct brcmf_pcie_ringbuf { 359 struct brcmf_commonring commonring; 360 dma_addr_t dma_handle; 361 u32 w_idx_addr; 362 u32 r_idx_addr; 363 struct brcmf_pciedev_info *devinfo; 364 u8 id; 365 }; 366 367 /** 368 * struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info 369 * 370 * @ringmem: dongle memory pointer to ring memory location 371 * @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers 372 * @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers 373 * @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers 374 * @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers 375 * @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers 376 * @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers 377 * @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers 378 * @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers 379 * @max_flowrings: maximum number of tx flow rings supported. 380 * @max_submissionrings: maximum number of submission rings(h2d) supported. 381 * @max_completionrings: maximum number of completion rings(d2h) supported. 382 */ 383 struct brcmf_pcie_dhi_ringinfo { 384 __le32 ringmem; 385 __le32 h2d_w_idx_ptr; 386 __le32 h2d_r_idx_ptr; 387 __le32 d2h_w_idx_ptr; 388 __le32 d2h_r_idx_ptr; 389 struct msgbuf_buf_addr h2d_w_idx_hostaddr; 390 struct msgbuf_buf_addr h2d_r_idx_hostaddr; 391 struct msgbuf_buf_addr d2h_w_idx_hostaddr; 392 struct msgbuf_buf_addr d2h_r_idx_hostaddr; 393 __le16 max_flowrings; 394 __le16 max_submissionrings; 395 __le16 max_completionrings; 396 }; 397 398 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = { 399 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM, 400 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM, 401 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM, 402 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM, 403 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM 404 }; 405 406 static const u32 brcmf_ring_itemsize_pre_v7[BRCMF_NROF_COMMON_MSGRINGS] = { 407 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 408 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 409 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 410 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7, 411 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7 412 }; 413 414 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = { 415 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 416 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 417 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 418 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE, 419 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE 420 }; 421 422 struct brcmf_pcie_reginfo { 423 u32 intmask; 424 u32 mailboxint; 425 u32 mailboxmask; 426 u32 h2d_mailbox_0; 427 u32 h2d_mailbox_1; 428 u32 int_d2h_db; 429 u32 int_fn0; 430 }; 431 432 static const struct brcmf_pcie_reginfo brcmf_reginfo_default = { 433 .intmask = BRCMF_PCIE_PCIE2REG_INTMASK, 434 .mailboxint = BRCMF_PCIE_PCIE2REG_MAILBOXINT, 435 .mailboxmask = BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 436 .h2d_mailbox_0 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0, 437 .h2d_mailbox_1 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1, 438 .int_d2h_db = BRCMF_PCIE_MB_INT_D2H_DB, 439 .int_fn0 = BRCMF_PCIE_MB_INT_FN0, 440 }; 441 442 static const struct brcmf_pcie_reginfo brcmf_reginfo_64 = { 443 .intmask = BRCMF_PCIE_64_PCIE2REG_INTMASK, 444 .mailboxint = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT, 445 .mailboxmask = BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK, 446 .h2d_mailbox_0 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0, 447 .h2d_mailbox_1 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1, 448 .int_d2h_db = BRCMF_PCIE_64_MB_INT_D2H_DB, 449 .int_fn0 = 0, 450 }; 451 452 static void brcmf_pcie_setup(struct device *dev, int ret, 453 struct brcmf_fw_request *fwreq); 454 static struct brcmf_fw_request * 455 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo); 456 static void 457 brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active); 458 static void brcmf_pcie_debugfs_create(struct device *dev); 459 460 static u16 461 brcmf_pcie_read_reg16(struct brcmf_pciedev_info *devinfo, u32 reg_offset) 462 { 463 void __iomem *address = devinfo->regs + reg_offset; 464 465 return ioread16(address); 466 } 467 468 static u32 469 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset) 470 { 471 void __iomem *address = devinfo->regs + reg_offset; 472 473 return (ioread32(address)); 474 } 475 476 477 static void 478 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset, 479 u32 value) 480 { 481 void __iomem *address = devinfo->regs + reg_offset; 482 483 iowrite32(value, address); 484 } 485 486 487 static u8 488 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 489 { 490 void __iomem *address = devinfo->tcm + mem_offset; 491 492 return (ioread8(address)); 493 } 494 495 496 static u16 497 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 498 { 499 void __iomem *address = devinfo->tcm + mem_offset; 500 501 return (ioread16(address)); 502 } 503 504 505 static void 506 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 507 u16 value) 508 { 509 void __iomem *address = devinfo->tcm + mem_offset; 510 511 iowrite16(value, address); 512 } 513 514 515 static u16 516 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 517 { 518 u16 *address = devinfo->idxbuf + mem_offset; 519 520 return (*(address)); 521 } 522 523 524 static void 525 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 526 u16 value) 527 { 528 u16 *address = devinfo->idxbuf + mem_offset; 529 530 *(address) = value; 531 } 532 533 534 static u32 535 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 536 { 537 void __iomem *address = devinfo->tcm + mem_offset; 538 539 return (ioread32(address)); 540 } 541 542 543 static void 544 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 545 u32 value) 546 { 547 void __iomem *address = devinfo->tcm + mem_offset; 548 549 iowrite32(value, address); 550 } 551 552 553 static u32 554 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 555 { 556 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 557 558 return (ioread32(addr)); 559 } 560 561 562 static void 563 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 564 u32 value) 565 { 566 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 567 568 iowrite32(value, addr); 569 } 570 571 572 static void 573 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 574 void *dstaddr, u32 len) 575 { 576 void __iomem *address = devinfo->tcm + mem_offset; 577 __le32 *dst32; 578 __le16 *dst16; 579 u8 *dst8; 580 581 if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) { 582 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) { 583 dst8 = (u8 *)dstaddr; 584 while (len) { 585 *dst8 = ioread8(address); 586 address++; 587 dst8++; 588 len--; 589 } 590 } else { 591 len = len / 2; 592 dst16 = (__le16 *)dstaddr; 593 while (len) { 594 *dst16 = cpu_to_le16(ioread16(address)); 595 address += 2; 596 dst16++; 597 len--; 598 } 599 } 600 } else { 601 len = len / 4; 602 dst32 = (__le32 *)dstaddr; 603 while (len) { 604 *dst32 = cpu_to_le32(ioread32(address)); 605 address += 4; 606 dst32++; 607 len--; 608 } 609 } 610 } 611 612 613 #define READCC32(devinfo, reg) brcmf_pcie_read_reg32(devinfo, \ 614 CHIPCREGOFFS(reg)) 615 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \ 616 CHIPCREGOFFS(reg), value) 617 618 619 static void 620 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid) 621 { 622 const struct pci_dev *pdev = devinfo->pdev; 623 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 624 struct brcmf_core *core; 625 u32 bar0_win; 626 627 core = brcmf_chip_get_core(devinfo->ci, coreid); 628 if (core) { 629 bar0_win = core->base; 630 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win); 631 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, 632 &bar0_win) == 0) { 633 if (bar0_win != core->base) { 634 bar0_win = core->base; 635 pci_write_config_dword(pdev, 636 BRCMF_PCIE_BAR0_WINDOW, 637 bar0_win); 638 } 639 } 640 } else { 641 brcmf_err(bus, "Unsupported core selected %x\n", coreid); 642 } 643 } 644 645 646 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo) 647 { 648 struct brcmf_core *core; 649 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD, 650 BRCMF_PCIE_CFGREG_PM_CSR, 651 BRCMF_PCIE_CFGREG_MSI_CAP, 652 BRCMF_PCIE_CFGREG_MSI_ADDR_L, 653 BRCMF_PCIE_CFGREG_MSI_ADDR_H, 654 BRCMF_PCIE_CFGREG_MSI_DATA, 655 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2, 656 BRCMF_PCIE_CFGREG_RBAR_CTRL, 657 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1, 658 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG, 659 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG }; 660 u32 i; 661 u32 val; 662 u32 lsc; 663 664 if (!devinfo->ci) 665 return; 666 667 /* Disable ASPM */ 668 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 669 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 670 &lsc); 671 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB); 672 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 673 val); 674 675 /* Watchdog reset */ 676 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON); 677 WRITECC32(devinfo, watchdog, 4); 678 msleep(100); 679 680 /* Restore ASPM */ 681 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 682 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 683 lsc); 684 685 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 686 if (core->rev <= 13) { 687 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) { 688 brcmf_pcie_write_reg32(devinfo, 689 BRCMF_PCIE_PCIE2REG_CONFIGADDR, 690 cfg_offset[i]); 691 val = brcmf_pcie_read_reg32(devinfo, 692 BRCMF_PCIE_PCIE2REG_CONFIGDATA); 693 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n", 694 cfg_offset[i], val); 695 brcmf_pcie_write_reg32(devinfo, 696 BRCMF_PCIE_PCIE2REG_CONFIGDATA, 697 val); 698 } 699 } 700 } 701 702 703 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo) 704 { 705 u32 config; 706 707 /* BAR1 window may not be sized properly */ 708 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 709 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0); 710 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA); 711 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config); 712 713 device_wakeup_enable(&devinfo->pdev->dev); 714 } 715 716 717 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo) 718 { 719 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 720 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4); 721 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 722 5); 723 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 724 0); 725 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 726 7); 727 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 728 0); 729 } 730 return 0; 731 } 732 733 734 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo, 735 u32 resetintr) 736 { 737 struct brcmf_core *core; 738 739 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 740 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM); 741 brcmf_chip_resetcore(core, 0, 0, 0); 742 } 743 744 if (!brcmf_chip_set_active(devinfo->ci, resetintr)) 745 return -EIO; 746 return 0; 747 } 748 749 750 static int 751 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data) 752 { 753 struct brcmf_pcie_shared_info *shared; 754 struct brcmf_core *core; 755 u32 addr; 756 u32 cur_htod_mb_data; 757 u32 i; 758 759 shared = &devinfo->shared; 760 addr = shared->htod_mb_data_addr; 761 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 762 763 if (cur_htod_mb_data != 0) 764 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n", 765 cur_htod_mb_data); 766 767 i = 0; 768 while (cur_htod_mb_data != 0) { 769 msleep(10); 770 i++; 771 if (i > 100) 772 return -EIO; 773 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 774 } 775 776 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data); 777 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 778 779 /* Send mailbox interrupt twice as a hardware workaround */ 780 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 781 if (core->rev <= 13) 782 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 783 784 return 0; 785 } 786 787 788 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo) 789 { 790 struct brcmf_pcie_shared_info *shared; 791 u32 addr; 792 u32 dtoh_mb_data; 793 794 shared = &devinfo->shared; 795 addr = shared->dtoh_mb_data_addr; 796 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 797 798 if (!dtoh_mb_data) 799 return; 800 801 brcmf_pcie_write_tcm32(devinfo, addr, 0); 802 803 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data); 804 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) { 805 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n"); 806 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK); 807 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n"); 808 } 809 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE) 810 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n"); 811 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) { 812 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n"); 813 devinfo->mbdata_completed = true; 814 wake_up(&devinfo->mbdata_resp_wait); 815 } 816 if (dtoh_mb_data & BRCMF_D2H_DEV_FWHALT) { 817 brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n"); 818 brcmf_fw_crashed(&devinfo->pdev->dev); 819 } 820 } 821 822 823 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo) 824 { 825 struct brcmf_pcie_shared_info *shared; 826 struct brcmf_pcie_console *console; 827 u32 addr; 828 829 shared = &devinfo->shared; 830 console = &shared->console; 831 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET; 832 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr); 833 834 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET; 835 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr); 836 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET; 837 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr); 838 839 brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n", 840 console->base_addr, console->buf_addr, console->bufsize); 841 } 842 843 /** 844 * brcmf_pcie_bus_console_read - reads firmware messages 845 * 846 * @devinfo: pointer to the device data structure 847 * @error: specifies if error has occurred (prints messages unconditionally) 848 */ 849 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo, 850 bool error) 851 { 852 struct pci_dev *pdev = devinfo->pdev; 853 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 854 struct brcmf_pcie_console *console; 855 u32 addr; 856 u8 ch; 857 u32 newidx; 858 859 if (!error && !BRCMF_FWCON_ON()) 860 return; 861 862 console = &devinfo->shared.console; 863 if (!console->base_addr) 864 return; 865 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET; 866 newidx = brcmf_pcie_read_tcm32(devinfo, addr); 867 while (newidx != console->read_idx) { 868 addr = console->buf_addr + console->read_idx; 869 ch = brcmf_pcie_read_tcm8(devinfo, addr); 870 console->read_idx++; 871 if (console->read_idx == console->bufsize) 872 console->read_idx = 0; 873 if (ch == '\r') 874 continue; 875 console->log_str[console->log_idx] = ch; 876 console->log_idx++; 877 if ((ch != '\n') && 878 (console->log_idx == (sizeof(console->log_str) - 2))) { 879 ch = '\n'; 880 console->log_str[console->log_idx] = ch; 881 console->log_idx++; 882 } 883 if (ch == '\n') { 884 console->log_str[console->log_idx] = 0; 885 if (error) 886 __brcmf_err(bus, __func__, "CONSOLE: %s", 887 console->log_str); 888 else 889 pr_debug("CONSOLE: %s", console->log_str); 890 console->log_idx = 0; 891 } 892 } 893 } 894 895 896 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo) 897 { 898 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask, 0); 899 } 900 901 902 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo) 903 { 904 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask, 905 devinfo->reginfo->int_d2h_db | 906 devinfo->reginfo->int_fn0); 907 } 908 909 static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo) 910 { 911 if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1) 912 brcmf_pcie_write_reg32(devinfo, 913 devinfo->reginfo->h2d_mailbox_1, 1); 914 } 915 916 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg) 917 { 918 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 919 920 if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint)) { 921 brcmf_pcie_intr_disable(devinfo); 922 brcmf_dbg(PCIE, "Enter\n"); 923 return IRQ_WAKE_THREAD; 924 } 925 return IRQ_NONE; 926 } 927 928 929 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg) 930 { 931 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 932 u32 status; 933 934 devinfo->in_irq = true; 935 status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint); 936 brcmf_dbg(PCIE, "Enter %x\n", status); 937 if (status) { 938 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint, 939 status); 940 if (status & devinfo->reginfo->int_fn0) 941 brcmf_pcie_handle_mb_data(devinfo); 942 if (status & devinfo->reginfo->int_d2h_db) { 943 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 944 brcmf_proto_msgbuf_rx_trigger( 945 &devinfo->pdev->dev); 946 } 947 } 948 brcmf_pcie_bus_console_read(devinfo, false); 949 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 950 brcmf_pcie_intr_enable(devinfo); 951 devinfo->in_irq = false; 952 return IRQ_HANDLED; 953 } 954 955 956 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo) 957 { 958 struct pci_dev *pdev = devinfo->pdev; 959 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 960 961 brcmf_pcie_intr_disable(devinfo); 962 963 brcmf_dbg(PCIE, "Enter\n"); 964 965 pci_enable_msi(pdev); 966 if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr, 967 brcmf_pcie_isr_thread, IRQF_SHARED, 968 "brcmf_pcie_intr", devinfo)) { 969 pci_disable_msi(pdev); 970 brcmf_err(bus, "Failed to request IRQ %d\n", pdev->irq); 971 return -EIO; 972 } 973 devinfo->irq_allocated = true; 974 return 0; 975 } 976 977 978 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo) 979 { 980 struct pci_dev *pdev = devinfo->pdev; 981 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 982 u32 status; 983 u32 count; 984 985 if (!devinfo->irq_allocated) 986 return; 987 988 brcmf_pcie_intr_disable(devinfo); 989 free_irq(pdev->irq, devinfo); 990 pci_disable_msi(pdev); 991 992 msleep(50); 993 count = 0; 994 while ((devinfo->in_irq) && (count < 20)) { 995 msleep(50); 996 count++; 997 } 998 if (devinfo->in_irq) 999 brcmf_err(bus, "Still in IRQ (processing) !!!\n"); 1000 1001 status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint); 1002 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint, status); 1003 1004 devinfo->irq_allocated = false; 1005 } 1006 1007 1008 static int brcmf_pcie_ring_mb_write_rptr(void *ctx) 1009 { 1010 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1011 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1012 struct brcmf_commonring *commonring = &ring->commonring; 1013 1014 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1015 return -EIO; 1016 1017 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr, 1018 commonring->w_ptr, ring->id); 1019 1020 devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr); 1021 1022 return 0; 1023 } 1024 1025 1026 static int brcmf_pcie_ring_mb_write_wptr(void *ctx) 1027 { 1028 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1029 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1030 struct brcmf_commonring *commonring = &ring->commonring; 1031 1032 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1033 return -EIO; 1034 1035 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr, 1036 commonring->r_ptr, ring->id); 1037 1038 devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr); 1039 1040 return 0; 1041 } 1042 1043 1044 static int brcmf_pcie_ring_mb_ring_bell(void *ctx) 1045 { 1046 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1047 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1048 1049 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1050 return -EIO; 1051 1052 brcmf_dbg(PCIE, "RING !\n"); 1053 /* Any arbitrary value will do, lets use 1 */ 1054 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->h2d_mailbox_0, 1); 1055 1056 return 0; 1057 } 1058 1059 1060 static int brcmf_pcie_ring_mb_update_rptr(void *ctx) 1061 { 1062 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1063 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1064 struct brcmf_commonring *commonring = &ring->commonring; 1065 1066 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1067 return -EIO; 1068 1069 commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr); 1070 1071 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr, 1072 commonring->w_ptr, ring->id); 1073 1074 return 0; 1075 } 1076 1077 1078 static int brcmf_pcie_ring_mb_update_wptr(void *ctx) 1079 { 1080 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1081 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1082 struct brcmf_commonring *commonring = &ring->commonring; 1083 1084 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1085 return -EIO; 1086 1087 commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr); 1088 1089 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr, 1090 commonring->r_ptr, ring->id); 1091 1092 return 0; 1093 } 1094 1095 1096 static void * 1097 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo, 1098 u32 size, u32 tcm_dma_phys_addr, 1099 dma_addr_t *dma_handle) 1100 { 1101 void *ring; 1102 u64 address; 1103 1104 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle, 1105 GFP_KERNEL); 1106 if (!ring) 1107 return NULL; 1108 1109 address = (u64)*dma_handle; 1110 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr, 1111 address & 0xffffffff); 1112 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32); 1113 1114 return (ring); 1115 } 1116 1117 1118 static struct brcmf_pcie_ringbuf * 1119 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id, 1120 u32 tcm_ring_phys_addr) 1121 { 1122 void *dma_buf; 1123 dma_addr_t dma_handle; 1124 struct brcmf_pcie_ringbuf *ring; 1125 u32 size; 1126 u32 addr; 1127 const u32 *ring_itemsize_array; 1128 1129 if (devinfo->shared.version < BRCMF_PCIE_SHARED_VERSION_7) 1130 ring_itemsize_array = brcmf_ring_itemsize_pre_v7; 1131 else 1132 ring_itemsize_array = brcmf_ring_itemsize; 1133 1134 size = brcmf_ring_max_item[ring_id] * ring_itemsize_array[ring_id]; 1135 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size, 1136 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET, 1137 &dma_handle); 1138 if (!dma_buf) 1139 return NULL; 1140 1141 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET; 1142 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]); 1143 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET; 1144 brcmf_pcie_write_tcm16(devinfo, addr, ring_itemsize_array[ring_id]); 1145 1146 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 1147 if (!ring) { 1148 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf, 1149 dma_handle); 1150 return NULL; 1151 } 1152 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id], 1153 ring_itemsize_array[ring_id], dma_buf); 1154 ring->dma_handle = dma_handle; 1155 ring->devinfo = devinfo; 1156 brcmf_commonring_register_cb(&ring->commonring, 1157 brcmf_pcie_ring_mb_ring_bell, 1158 brcmf_pcie_ring_mb_update_rptr, 1159 brcmf_pcie_ring_mb_update_wptr, 1160 brcmf_pcie_ring_mb_write_rptr, 1161 brcmf_pcie_ring_mb_write_wptr, ring); 1162 1163 return (ring); 1164 } 1165 1166 1167 static void brcmf_pcie_release_ringbuffer(struct device *dev, 1168 struct brcmf_pcie_ringbuf *ring) 1169 { 1170 void *dma_buf; 1171 u32 size; 1172 1173 if (!ring) 1174 return; 1175 1176 dma_buf = ring->commonring.buf_addr; 1177 if (dma_buf) { 1178 size = ring->commonring.depth * ring->commonring.item_len; 1179 dma_free_coherent(dev, size, dma_buf, ring->dma_handle); 1180 } 1181 kfree(ring); 1182 } 1183 1184 1185 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo) 1186 { 1187 u32 i; 1188 1189 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1190 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev, 1191 devinfo->shared.commonrings[i]); 1192 devinfo->shared.commonrings[i] = NULL; 1193 } 1194 kfree(devinfo->shared.flowrings); 1195 devinfo->shared.flowrings = NULL; 1196 if (devinfo->idxbuf) { 1197 dma_free_coherent(&devinfo->pdev->dev, 1198 devinfo->idxbuf_sz, 1199 devinfo->idxbuf, 1200 devinfo->idxbuf_dmahandle); 1201 devinfo->idxbuf = NULL; 1202 } 1203 } 1204 1205 1206 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo) 1207 { 1208 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1209 struct brcmf_pcie_ringbuf *ring; 1210 struct brcmf_pcie_ringbuf *rings; 1211 u32 d2h_w_idx_ptr; 1212 u32 d2h_r_idx_ptr; 1213 u32 h2d_w_idx_ptr; 1214 u32 h2d_r_idx_ptr; 1215 u32 ring_mem_ptr; 1216 u32 i; 1217 u64 address; 1218 u32 bufsz; 1219 u8 idx_offset; 1220 struct brcmf_pcie_dhi_ringinfo ringinfo; 1221 u16 max_flowrings; 1222 u16 max_submissionrings; 1223 u16 max_completionrings; 1224 1225 memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr, 1226 sizeof(ringinfo)); 1227 if (devinfo->shared.version >= 6) { 1228 max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings); 1229 max_flowrings = le16_to_cpu(ringinfo.max_flowrings); 1230 max_completionrings = le16_to_cpu(ringinfo.max_completionrings); 1231 } else { 1232 max_submissionrings = le16_to_cpu(ringinfo.max_flowrings); 1233 max_flowrings = max_submissionrings - 1234 BRCMF_NROF_H2D_COMMON_MSGRINGS; 1235 max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS; 1236 } 1237 if (max_flowrings > 512) { 1238 brcmf_err(bus, "invalid max_flowrings(%d)\n", max_flowrings); 1239 return -EIO; 1240 } 1241 1242 if (devinfo->dma_idx_sz != 0) { 1243 bufsz = (max_submissionrings + max_completionrings) * 1244 devinfo->dma_idx_sz * 2; 1245 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz, 1246 &devinfo->idxbuf_dmahandle, 1247 GFP_KERNEL); 1248 if (!devinfo->idxbuf) 1249 devinfo->dma_idx_sz = 0; 1250 } 1251 1252 if (devinfo->dma_idx_sz == 0) { 1253 d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr); 1254 d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr); 1255 h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr); 1256 h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr); 1257 idx_offset = sizeof(u32); 1258 devinfo->write_ptr = brcmf_pcie_write_tcm16; 1259 devinfo->read_ptr = brcmf_pcie_read_tcm16; 1260 brcmf_dbg(PCIE, "Using TCM indices\n"); 1261 } else { 1262 memset(devinfo->idxbuf, 0, bufsz); 1263 devinfo->idxbuf_sz = bufsz; 1264 idx_offset = devinfo->dma_idx_sz; 1265 devinfo->write_ptr = brcmf_pcie_write_idx; 1266 devinfo->read_ptr = brcmf_pcie_read_idx; 1267 1268 h2d_w_idx_ptr = 0; 1269 address = (u64)devinfo->idxbuf_dmahandle; 1270 ringinfo.h2d_w_idx_hostaddr.low_addr = 1271 cpu_to_le32(address & 0xffffffff); 1272 ringinfo.h2d_w_idx_hostaddr.high_addr = 1273 cpu_to_le32(address >> 32); 1274 1275 h2d_r_idx_ptr = h2d_w_idx_ptr + 1276 max_submissionrings * idx_offset; 1277 address += max_submissionrings * idx_offset; 1278 ringinfo.h2d_r_idx_hostaddr.low_addr = 1279 cpu_to_le32(address & 0xffffffff); 1280 ringinfo.h2d_r_idx_hostaddr.high_addr = 1281 cpu_to_le32(address >> 32); 1282 1283 d2h_w_idx_ptr = h2d_r_idx_ptr + 1284 max_submissionrings * idx_offset; 1285 address += max_submissionrings * idx_offset; 1286 ringinfo.d2h_w_idx_hostaddr.low_addr = 1287 cpu_to_le32(address & 0xffffffff); 1288 ringinfo.d2h_w_idx_hostaddr.high_addr = 1289 cpu_to_le32(address >> 32); 1290 1291 d2h_r_idx_ptr = d2h_w_idx_ptr + 1292 max_completionrings * idx_offset; 1293 address += max_completionrings * idx_offset; 1294 ringinfo.d2h_r_idx_hostaddr.low_addr = 1295 cpu_to_le32(address & 0xffffffff); 1296 ringinfo.d2h_r_idx_hostaddr.high_addr = 1297 cpu_to_le32(address >> 32); 1298 1299 memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr, 1300 &ringinfo, sizeof(ringinfo)); 1301 brcmf_dbg(PCIE, "Using host memory indices\n"); 1302 } 1303 1304 ring_mem_ptr = le32_to_cpu(ringinfo.ringmem); 1305 1306 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) { 1307 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1308 if (!ring) 1309 goto fail; 1310 ring->w_idx_addr = h2d_w_idx_ptr; 1311 ring->r_idx_addr = h2d_r_idx_ptr; 1312 ring->id = i; 1313 devinfo->shared.commonrings[i] = ring; 1314 1315 h2d_w_idx_ptr += idx_offset; 1316 h2d_r_idx_ptr += idx_offset; 1317 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1318 } 1319 1320 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS; 1321 i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1322 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1323 if (!ring) 1324 goto fail; 1325 ring->w_idx_addr = d2h_w_idx_ptr; 1326 ring->r_idx_addr = d2h_r_idx_ptr; 1327 ring->id = i; 1328 devinfo->shared.commonrings[i] = ring; 1329 1330 d2h_w_idx_ptr += idx_offset; 1331 d2h_r_idx_ptr += idx_offset; 1332 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1333 } 1334 1335 devinfo->shared.max_flowrings = max_flowrings; 1336 devinfo->shared.max_submissionrings = max_submissionrings; 1337 devinfo->shared.max_completionrings = max_completionrings; 1338 rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL); 1339 if (!rings) 1340 goto fail; 1341 1342 brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings); 1343 1344 for (i = 0; i < max_flowrings; i++) { 1345 ring = &rings[i]; 1346 ring->devinfo = devinfo; 1347 ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART; 1348 brcmf_commonring_register_cb(&ring->commonring, 1349 brcmf_pcie_ring_mb_ring_bell, 1350 brcmf_pcie_ring_mb_update_rptr, 1351 brcmf_pcie_ring_mb_update_wptr, 1352 brcmf_pcie_ring_mb_write_rptr, 1353 brcmf_pcie_ring_mb_write_wptr, 1354 ring); 1355 ring->w_idx_addr = h2d_w_idx_ptr; 1356 ring->r_idx_addr = h2d_r_idx_ptr; 1357 h2d_w_idx_ptr += idx_offset; 1358 h2d_r_idx_ptr += idx_offset; 1359 } 1360 devinfo->shared.flowrings = rings; 1361 1362 return 0; 1363 1364 fail: 1365 brcmf_err(bus, "Allocating ring buffers failed\n"); 1366 brcmf_pcie_release_ringbuffers(devinfo); 1367 return -ENOMEM; 1368 } 1369 1370 1371 static void 1372 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1373 { 1374 if (devinfo->shared.scratch) 1375 dma_free_coherent(&devinfo->pdev->dev, 1376 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1377 devinfo->shared.scratch, 1378 devinfo->shared.scratch_dmahandle); 1379 if (devinfo->shared.ringupd) 1380 dma_free_coherent(&devinfo->pdev->dev, 1381 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1382 devinfo->shared.ringupd, 1383 devinfo->shared.ringupd_dmahandle); 1384 } 1385 1386 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1387 { 1388 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1389 u64 address; 1390 u32 addr; 1391 1392 devinfo->shared.scratch = 1393 dma_alloc_coherent(&devinfo->pdev->dev, 1394 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1395 &devinfo->shared.scratch_dmahandle, 1396 GFP_KERNEL); 1397 if (!devinfo->shared.scratch) 1398 goto fail; 1399 1400 addr = devinfo->shared.tcm_base_address + 1401 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET; 1402 address = (u64)devinfo->shared.scratch_dmahandle; 1403 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1404 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1405 addr = devinfo->shared.tcm_base_address + 1406 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET; 1407 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); 1408 1409 devinfo->shared.ringupd = 1410 dma_alloc_coherent(&devinfo->pdev->dev, 1411 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1412 &devinfo->shared.ringupd_dmahandle, 1413 GFP_KERNEL); 1414 if (!devinfo->shared.ringupd) 1415 goto fail; 1416 1417 addr = devinfo->shared.tcm_base_address + 1418 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET; 1419 address = (u64)devinfo->shared.ringupd_dmahandle; 1420 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1421 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1422 addr = devinfo->shared.tcm_base_address + 1423 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET; 1424 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); 1425 return 0; 1426 1427 fail: 1428 brcmf_err(bus, "Allocating scratch buffers failed\n"); 1429 brcmf_pcie_release_scratchbuffers(devinfo); 1430 return -ENOMEM; 1431 } 1432 1433 1434 static void brcmf_pcie_down(struct device *dev) 1435 { 1436 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1437 struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie; 1438 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo; 1439 1440 brcmf_pcie_fwcon_timer(devinfo, false); 1441 } 1442 1443 static int brcmf_pcie_preinit(struct device *dev) 1444 { 1445 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1446 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1447 1448 brcmf_dbg(PCIE, "Enter\n"); 1449 1450 brcmf_pcie_intr_enable(buspub->devinfo); 1451 brcmf_pcie_hostready(buspub->devinfo); 1452 1453 return 0; 1454 } 1455 1456 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb) 1457 { 1458 return 0; 1459 } 1460 1461 1462 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg, 1463 uint len) 1464 { 1465 return 0; 1466 } 1467 1468 1469 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg, 1470 uint len) 1471 { 1472 return 0; 1473 } 1474 1475 1476 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled) 1477 { 1478 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1479 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1480 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1481 1482 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled); 1483 devinfo->wowl_enabled = enabled; 1484 } 1485 1486 1487 static size_t brcmf_pcie_get_ramsize(struct device *dev) 1488 { 1489 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1490 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1491 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1492 1493 return devinfo->ci->ramsize - devinfo->ci->srsize; 1494 } 1495 1496 1497 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len) 1498 { 1499 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1500 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1501 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1502 1503 brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len); 1504 brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len); 1505 return 0; 1506 } 1507 1508 static int brcmf_pcie_get_blob(struct device *dev, const struct firmware **fw, 1509 enum brcmf_blob_type type) 1510 { 1511 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1512 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1513 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1514 1515 switch (type) { 1516 case BRCMF_BLOB_CLM: 1517 *fw = devinfo->clm_fw; 1518 devinfo->clm_fw = NULL; 1519 break; 1520 default: 1521 return -ENOENT; 1522 } 1523 1524 if (!*fw) 1525 return -ENOENT; 1526 1527 return 0; 1528 } 1529 1530 static int brcmf_pcie_reset(struct device *dev) 1531 { 1532 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1533 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1534 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1535 struct brcmf_fw_request *fwreq; 1536 int err; 1537 1538 brcmf_pcie_intr_disable(devinfo); 1539 1540 brcmf_pcie_bus_console_read(devinfo, true); 1541 1542 brcmf_detach(dev); 1543 1544 brcmf_pcie_release_irq(devinfo); 1545 brcmf_pcie_release_scratchbuffers(devinfo); 1546 brcmf_pcie_release_ringbuffers(devinfo); 1547 brcmf_pcie_reset_device(devinfo); 1548 1549 fwreq = brcmf_pcie_prepare_fw_request(devinfo); 1550 if (!fwreq) { 1551 dev_err(dev, "Failed to prepare FW request\n"); 1552 return -ENOMEM; 1553 } 1554 1555 err = brcmf_fw_get_firmwares(dev, fwreq, brcmf_pcie_setup); 1556 if (err) { 1557 dev_err(dev, "Failed to prepare FW request\n"); 1558 kfree(fwreq); 1559 } 1560 1561 return err; 1562 } 1563 1564 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = { 1565 .preinit = brcmf_pcie_preinit, 1566 .txdata = brcmf_pcie_tx, 1567 .stop = brcmf_pcie_down, 1568 .txctl = brcmf_pcie_tx_ctlpkt, 1569 .rxctl = brcmf_pcie_rx_ctlpkt, 1570 .wowl_config = brcmf_pcie_wowl_config, 1571 .get_ramsize = brcmf_pcie_get_ramsize, 1572 .get_memdump = brcmf_pcie_get_memdump, 1573 .get_blob = brcmf_pcie_get_blob, 1574 .reset = brcmf_pcie_reset, 1575 .debugfs_create = brcmf_pcie_debugfs_create, 1576 }; 1577 1578 1579 static void 1580 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data, 1581 u32 data_len) 1582 { 1583 __le32 *field; 1584 u32 newsize; 1585 1586 if (data_len < BRCMF_RAMSIZE_OFFSET + 8) 1587 return; 1588 1589 field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET]; 1590 if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC) 1591 return; 1592 field++; 1593 newsize = le32_to_cpup(field); 1594 1595 brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n", 1596 newsize); 1597 devinfo->ci->ramsize = newsize; 1598 } 1599 1600 1601 static int 1602 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo, 1603 u32 sharedram_addr) 1604 { 1605 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1606 struct brcmf_pcie_shared_info *shared; 1607 u32 addr; 1608 1609 shared = &devinfo->shared; 1610 shared->tcm_base_address = sharedram_addr; 1611 1612 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr); 1613 shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK); 1614 brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version); 1615 if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) || 1616 (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) { 1617 brcmf_err(bus, "Unsupported PCIE version %d\n", 1618 shared->version); 1619 return -EINVAL; 1620 } 1621 1622 /* check firmware support dma indicies */ 1623 if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) { 1624 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX) 1625 devinfo->dma_idx_sz = sizeof(u16); 1626 else 1627 devinfo->dma_idx_sz = sizeof(u32); 1628 } 1629 1630 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET; 1631 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr); 1632 if (shared->max_rxbufpost == 0) 1633 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST; 1634 1635 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET; 1636 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr); 1637 1638 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET; 1639 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1640 1641 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET; 1642 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1643 1644 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET; 1645 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1646 1647 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n", 1648 shared->max_rxbufpost, shared->rx_dataoffset); 1649 1650 brcmf_pcie_bus_console_init(devinfo); 1651 brcmf_pcie_bus_console_read(devinfo, false); 1652 1653 return 0; 1654 } 1655 1656 1657 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo, 1658 const struct firmware *fw, void *nvram, 1659 u32 nvram_len) 1660 { 1661 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1662 u32 sharedram_addr; 1663 u32 sharedram_addr_written; 1664 u32 loop_counter; 1665 int err; 1666 u32 address; 1667 u32 resetintr; 1668 1669 brcmf_dbg(PCIE, "Halt ARM.\n"); 1670 err = brcmf_pcie_enter_download_state(devinfo); 1671 if (err) 1672 return err; 1673 1674 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name); 1675 memcpy_toio(devinfo->tcm + devinfo->ci->rambase, 1676 (void *)fw->data, fw->size); 1677 1678 resetintr = get_unaligned_le32(fw->data); 1679 release_firmware(fw); 1680 1681 /* reset last 4 bytes of RAM address. to be used for shared 1682 * area. This identifies when FW is running 1683 */ 1684 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0); 1685 1686 if (nvram) { 1687 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name); 1688 address = devinfo->ci->rambase + devinfo->ci->ramsize - 1689 nvram_len; 1690 memcpy_toio(devinfo->tcm + address, nvram, nvram_len); 1691 brcmf_fw_nvram_free(nvram); 1692 } else { 1693 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n", 1694 devinfo->nvram_name); 1695 } 1696 1697 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo, 1698 devinfo->ci->ramsize - 1699 4); 1700 brcmf_dbg(PCIE, "Bring ARM in running state\n"); 1701 err = brcmf_pcie_exit_download_state(devinfo, resetintr); 1702 if (err) 1703 return err; 1704 1705 brcmf_dbg(PCIE, "Wait for FW init\n"); 1706 sharedram_addr = sharedram_addr_written; 1707 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50; 1708 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) { 1709 msleep(50); 1710 sharedram_addr = brcmf_pcie_read_ram32(devinfo, 1711 devinfo->ci->ramsize - 1712 4); 1713 loop_counter--; 1714 } 1715 if (sharedram_addr == sharedram_addr_written) { 1716 brcmf_err(bus, "FW failed to initialize\n"); 1717 return -ENODEV; 1718 } 1719 if (sharedram_addr < devinfo->ci->rambase || 1720 sharedram_addr >= devinfo->ci->rambase + devinfo->ci->ramsize) { 1721 brcmf_err(bus, "Invalid shared RAM address 0x%08x\n", 1722 sharedram_addr); 1723 return -ENODEV; 1724 } 1725 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr); 1726 1727 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr)); 1728 } 1729 1730 1731 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo) 1732 { 1733 struct pci_dev *pdev = devinfo->pdev; 1734 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 1735 int err; 1736 phys_addr_t bar0_addr, bar1_addr; 1737 ulong bar1_size; 1738 1739 err = pci_enable_device(pdev); 1740 if (err) { 1741 brcmf_err(bus, "pci_enable_device failed err=%d\n", err); 1742 return err; 1743 } 1744 1745 pci_set_master(pdev); 1746 1747 /* Bar-0 mapped address */ 1748 bar0_addr = pci_resource_start(pdev, 0); 1749 /* Bar-1 mapped address */ 1750 bar1_addr = pci_resource_start(pdev, 2); 1751 /* read Bar-1 mapped memory range */ 1752 bar1_size = pci_resource_len(pdev, 2); 1753 if ((bar1_size == 0) || (bar1_addr == 0)) { 1754 brcmf_err(bus, "BAR1 Not enabled, device size=%ld, addr=%#016llx\n", 1755 bar1_size, (unsigned long long)bar1_addr); 1756 return -EINVAL; 1757 } 1758 1759 devinfo->regs = ioremap(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE); 1760 devinfo->tcm = ioremap(bar1_addr, bar1_size); 1761 1762 if (!devinfo->regs || !devinfo->tcm) { 1763 brcmf_err(bus, "ioremap() failed (%p,%p)\n", devinfo->regs, 1764 devinfo->tcm); 1765 return -EINVAL; 1766 } 1767 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n", 1768 devinfo->regs, (unsigned long long)bar0_addr); 1769 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n", 1770 devinfo->tcm, (unsigned long long)bar1_addr, 1771 (unsigned int)bar1_size); 1772 1773 return 0; 1774 } 1775 1776 1777 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo) 1778 { 1779 if (devinfo->tcm) 1780 iounmap(devinfo->tcm); 1781 if (devinfo->regs) 1782 iounmap(devinfo->regs); 1783 1784 pci_disable_device(devinfo->pdev); 1785 } 1786 1787 1788 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr) 1789 { 1790 u32 ret_addr; 1791 1792 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1); 1793 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1); 1794 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr); 1795 1796 return ret_addr; 1797 } 1798 1799 1800 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr) 1801 { 1802 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1803 1804 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1805 return brcmf_pcie_read_reg32(devinfo, addr); 1806 } 1807 1808 1809 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value) 1810 { 1811 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1812 1813 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1814 brcmf_pcie_write_reg32(devinfo, addr, value); 1815 } 1816 1817 1818 static int brcmf_pcie_buscoreprep(void *ctx) 1819 { 1820 return brcmf_pcie_get_resource(ctx); 1821 } 1822 1823 1824 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip) 1825 { 1826 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1827 struct brcmf_core *core; 1828 u32 val, reg; 1829 1830 devinfo->ci = chip; 1831 brcmf_pcie_reset_device(devinfo); 1832 1833 /* reginfo is not ready yet */ 1834 core = brcmf_chip_get_core(chip, BCMA_CORE_PCIE2); 1835 if (core->rev >= 64) 1836 reg = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT; 1837 else 1838 reg = BRCMF_PCIE_PCIE2REG_MAILBOXINT; 1839 1840 val = brcmf_pcie_read_reg32(devinfo, reg); 1841 if (val != 0xffffffff) 1842 brcmf_pcie_write_reg32(devinfo, reg, val); 1843 1844 return 0; 1845 } 1846 1847 1848 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip, 1849 u32 rstvec) 1850 { 1851 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1852 1853 brcmf_pcie_write_tcm32(devinfo, 0, rstvec); 1854 } 1855 1856 1857 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = { 1858 .prepare = brcmf_pcie_buscoreprep, 1859 .reset = brcmf_pcie_buscore_reset, 1860 .activate = brcmf_pcie_buscore_activate, 1861 .read32 = brcmf_pcie_buscore_read32, 1862 .write32 = brcmf_pcie_buscore_write32, 1863 }; 1864 1865 #define BRCMF_OTP_SYS_VENDOR 0x15 1866 #define BRCMF_OTP_BRCM_CIS 0x80 1867 1868 #define BRCMF_OTP_VENDOR_HDR 0x00000008 1869 1870 static int 1871 brcmf_pcie_parse_otp_sys_vendor(struct brcmf_pciedev_info *devinfo, 1872 u8 *data, size_t size) 1873 { 1874 int idx = 4; 1875 const char *chip_params; 1876 const char *board_params; 1877 const char *p; 1878 1879 /* 4-byte header and two empty strings */ 1880 if (size < 6) 1881 return -EINVAL; 1882 1883 if (get_unaligned_le32(data) != BRCMF_OTP_VENDOR_HDR) 1884 return -EINVAL; 1885 1886 chip_params = &data[idx]; 1887 1888 /* Skip first string, including terminator */ 1889 idx += strnlen(chip_params, size - idx) + 1; 1890 if (idx >= size) 1891 return -EINVAL; 1892 1893 board_params = &data[idx]; 1894 1895 /* Skip to terminator of second string */ 1896 idx += strnlen(board_params, size - idx); 1897 if (idx >= size) 1898 return -EINVAL; 1899 1900 /* At this point both strings are guaranteed NUL-terminated */ 1901 brcmf_dbg(PCIE, "OTP: chip_params='%s' board_params='%s'\n", 1902 chip_params, board_params); 1903 1904 p = skip_spaces(board_params); 1905 while (*p) { 1906 char tag = *p++; 1907 const char *end; 1908 size_t len; 1909 1910 if (*p++ != '=') /* implicit NUL check */ 1911 return -EINVAL; 1912 1913 /* *p might be NUL here, if so end == p and len == 0 */ 1914 end = strchrnul(p, ' '); 1915 len = end - p; 1916 1917 /* leave 1 byte for NUL in destination string */ 1918 if (len > (BRCMF_OTP_MAX_PARAM_LEN - 1)) 1919 return -EINVAL; 1920 1921 /* Copy len characters plus a NUL terminator */ 1922 switch (tag) { 1923 case 'M': 1924 strscpy(devinfo->otp.module, p, len + 1); 1925 break; 1926 case 'V': 1927 strscpy(devinfo->otp.vendor, p, len + 1); 1928 break; 1929 case 'm': 1930 strscpy(devinfo->otp.version, p, len + 1); 1931 break; 1932 } 1933 1934 /* Skip to next arg, if any */ 1935 p = skip_spaces(end); 1936 } 1937 1938 brcmf_dbg(PCIE, "OTP: module=%s vendor=%s version=%s\n", 1939 devinfo->otp.module, devinfo->otp.vendor, 1940 devinfo->otp.version); 1941 1942 if (!devinfo->otp.module[0] || 1943 !devinfo->otp.vendor[0] || 1944 !devinfo->otp.version[0]) 1945 return -EINVAL; 1946 1947 devinfo->otp.valid = true; 1948 return 0; 1949 } 1950 1951 static int 1952 brcmf_pcie_parse_otp(struct brcmf_pciedev_info *devinfo, u8 *otp, size_t size) 1953 { 1954 int p = 0; 1955 int ret = -EINVAL; 1956 1957 brcmf_dbg(PCIE, "parse_otp size=%zd\n", size); 1958 1959 while (p < (size - 1)) { 1960 u8 type = otp[p]; 1961 u8 length = otp[p + 1]; 1962 1963 if (type == 0) 1964 break; 1965 1966 if ((p + 2 + length) > size) 1967 break; 1968 1969 switch (type) { 1970 case BRCMF_OTP_SYS_VENDOR: 1971 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): SYS_VENDOR\n", 1972 p, length); 1973 ret = brcmf_pcie_parse_otp_sys_vendor(devinfo, 1974 &otp[p + 2], 1975 length); 1976 break; 1977 case BRCMF_OTP_BRCM_CIS: 1978 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): BRCM_CIS\n", 1979 p, length); 1980 break; 1981 default: 1982 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): Unknown type 0x%x\n", 1983 p, length, type); 1984 break; 1985 } 1986 1987 p += 2 + length; 1988 } 1989 1990 return ret; 1991 } 1992 1993 static int brcmf_pcie_read_otp(struct brcmf_pciedev_info *devinfo) 1994 { 1995 const struct pci_dev *pdev = devinfo->pdev; 1996 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 1997 u32 coreid, base, words, idx, sromctl; 1998 u16 *otp; 1999 struct brcmf_core *core; 2000 int ret; 2001 2002 switch (devinfo->ci->chip) { 2003 case BRCM_CC_4355_CHIP_ID: 2004 coreid = BCMA_CORE_CHIPCOMMON; 2005 base = 0x8c0; 2006 words = 0xb2; 2007 break; 2008 case BRCM_CC_4364_CHIP_ID: 2009 coreid = BCMA_CORE_CHIPCOMMON; 2010 base = 0x8c0; 2011 words = 0x1a0; 2012 break; 2013 case BRCM_CC_4377_CHIP_ID: 2014 case BRCM_CC_4378_CHIP_ID: 2015 coreid = BCMA_CORE_GCI; 2016 base = 0x1120; 2017 words = 0x170; 2018 break; 2019 default: 2020 /* OTP not supported on this chip */ 2021 return 0; 2022 } 2023 2024 core = brcmf_chip_get_core(devinfo->ci, coreid); 2025 if (!core) { 2026 brcmf_err(bus, "No OTP core\n"); 2027 return -ENODEV; 2028 } 2029 2030 if (coreid == BCMA_CORE_CHIPCOMMON) { 2031 /* Chips with OTP accessed via ChipCommon need additional 2032 * handling to access the OTP 2033 */ 2034 brcmf_pcie_select_core(devinfo, coreid); 2035 sromctl = READCC32(devinfo, sromcontrol); 2036 2037 if (!(sromctl & BCMA_CC_SROM_CONTROL_OTP_PRESENT)) { 2038 /* Chip lacks OTP, try without it... */ 2039 brcmf_err(bus, 2040 "OTP unavailable, using default firmware\n"); 2041 return 0; 2042 } 2043 2044 /* Map OTP to shadow area */ 2045 WRITECC32(devinfo, sromcontrol, 2046 sromctl | BCMA_CC_SROM_CONTROL_OTPSEL); 2047 } 2048 2049 otp = kcalloc(words, sizeof(u16), GFP_KERNEL); 2050 if (!otp) 2051 return -ENOMEM; 2052 2053 /* Map bus window to SROM/OTP shadow area in core */ 2054 base = brcmf_pcie_buscore_prep_addr(devinfo->pdev, base + core->base); 2055 2056 brcmf_dbg(PCIE, "OTP data:\n"); 2057 for (idx = 0; idx < words; idx++) { 2058 otp[idx] = brcmf_pcie_read_reg16(devinfo, base + 2 * idx); 2059 brcmf_dbg(PCIE, "[%8x] 0x%04x\n", base + 2 * idx, otp[idx]); 2060 } 2061 2062 if (coreid == BCMA_CORE_CHIPCOMMON) { 2063 brcmf_pcie_select_core(devinfo, coreid); 2064 WRITECC32(devinfo, sromcontrol, sromctl); 2065 } 2066 2067 ret = brcmf_pcie_parse_otp(devinfo, (u8 *)otp, 2 * words); 2068 kfree(otp); 2069 2070 return ret; 2071 } 2072 2073 #define BRCMF_PCIE_FW_CODE 0 2074 #define BRCMF_PCIE_FW_NVRAM 1 2075 #define BRCMF_PCIE_FW_CLM 2 2076 2077 static void brcmf_pcie_setup(struct device *dev, int ret, 2078 struct brcmf_fw_request *fwreq) 2079 { 2080 const struct firmware *fw; 2081 void *nvram; 2082 struct brcmf_bus *bus; 2083 struct brcmf_pciedev *pcie_bus_dev; 2084 struct brcmf_pciedev_info *devinfo; 2085 struct brcmf_commonring **flowrings; 2086 u32 i, nvram_len; 2087 2088 bus = dev_get_drvdata(dev); 2089 pcie_bus_dev = bus->bus_priv.pcie; 2090 devinfo = pcie_bus_dev->devinfo; 2091 2092 /* check firmware loading result */ 2093 if (ret) 2094 goto fail; 2095 2096 brcmf_pcie_attach(devinfo); 2097 2098 fw = fwreq->items[BRCMF_PCIE_FW_CODE].binary; 2099 nvram = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.data; 2100 nvram_len = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.len; 2101 devinfo->clm_fw = fwreq->items[BRCMF_PCIE_FW_CLM].binary; 2102 kfree(fwreq); 2103 2104 ret = brcmf_chip_get_raminfo(devinfo->ci); 2105 if (ret) { 2106 brcmf_err(bus, "Failed to get RAM info\n"); 2107 release_firmware(fw); 2108 brcmf_fw_nvram_free(nvram); 2109 goto fail; 2110 } 2111 2112 /* Some of the firmwares have the size of the memory of the device 2113 * defined inside the firmware. This is because part of the memory in 2114 * the device is shared and the devision is determined by FW. Parse 2115 * the firmware and adjust the chip memory size now. 2116 */ 2117 brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size); 2118 2119 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len); 2120 if (ret) 2121 goto fail; 2122 2123 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 2124 2125 ret = brcmf_pcie_init_ringbuffers(devinfo); 2126 if (ret) 2127 goto fail; 2128 2129 ret = brcmf_pcie_init_scratchbuffers(devinfo); 2130 if (ret) 2131 goto fail; 2132 2133 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 2134 ret = brcmf_pcie_request_irq(devinfo); 2135 if (ret) 2136 goto fail; 2137 2138 /* hook the commonrings in the bus structure. */ 2139 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) 2140 bus->msgbuf->commonrings[i] = 2141 &devinfo->shared.commonrings[i]->commonring; 2142 2143 flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings), 2144 GFP_KERNEL); 2145 if (!flowrings) 2146 goto fail; 2147 2148 for (i = 0; i < devinfo->shared.max_flowrings; i++) 2149 flowrings[i] = &devinfo->shared.flowrings[i].commonring; 2150 bus->msgbuf->flowrings = flowrings; 2151 2152 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset; 2153 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost; 2154 bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings; 2155 2156 init_waitqueue_head(&devinfo->mbdata_resp_wait); 2157 2158 ret = brcmf_attach(&devinfo->pdev->dev); 2159 if (ret) 2160 goto fail; 2161 2162 brcmf_pcie_bus_console_read(devinfo, false); 2163 2164 brcmf_pcie_fwcon_timer(devinfo, true); 2165 2166 return; 2167 2168 fail: 2169 brcmf_err(bus, "Dongle setup failed\n"); 2170 brcmf_pcie_bus_console_read(devinfo, true); 2171 brcmf_fw_crashed(dev); 2172 device_release_driver(dev); 2173 } 2174 2175 static struct brcmf_fw_request * 2176 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo) 2177 { 2178 struct brcmf_fw_request *fwreq; 2179 struct brcmf_fw_name fwnames[] = { 2180 { ".bin", devinfo->fw_name }, 2181 { ".txt", devinfo->nvram_name }, 2182 { ".clm_blob", devinfo->clm_name }, 2183 }; 2184 2185 fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev, 2186 brcmf_pcie_fwnames, 2187 ARRAY_SIZE(brcmf_pcie_fwnames), 2188 fwnames, ARRAY_SIZE(fwnames)); 2189 if (!fwreq) 2190 return NULL; 2191 2192 fwreq->items[BRCMF_PCIE_FW_CODE].type = BRCMF_FW_TYPE_BINARY; 2193 fwreq->items[BRCMF_PCIE_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM; 2194 fwreq->items[BRCMF_PCIE_FW_NVRAM].flags = BRCMF_FW_REQF_OPTIONAL; 2195 fwreq->items[BRCMF_PCIE_FW_CLM].type = BRCMF_FW_TYPE_BINARY; 2196 fwreq->items[BRCMF_PCIE_FW_CLM].flags = BRCMF_FW_REQF_OPTIONAL; 2197 /* NVRAM reserves PCI domain 0 for Broadcom's SDK faked bus */ 2198 fwreq->domain_nr = pci_domain_nr(devinfo->pdev->bus) + 1; 2199 fwreq->bus_nr = devinfo->pdev->bus->number; 2200 2201 /* Apple platforms with fancy firmware/NVRAM selection */ 2202 if (devinfo->settings->board_type && 2203 devinfo->settings->antenna_sku && 2204 devinfo->otp.valid) { 2205 const struct brcmf_otp_params *otp = &devinfo->otp; 2206 struct device *dev = &devinfo->pdev->dev; 2207 const char **bt = fwreq->board_types; 2208 2209 brcmf_dbg(PCIE, "Apple board: %s\n", 2210 devinfo->settings->board_type); 2211 2212 /* Example: apple,shikoku-RASP-m-6.11-X3 */ 2213 bt[0] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s-%s", 2214 devinfo->settings->board_type, 2215 otp->module, otp->vendor, otp->version, 2216 devinfo->settings->antenna_sku); 2217 bt[1] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s", 2218 devinfo->settings->board_type, 2219 otp->module, otp->vendor, otp->version); 2220 bt[2] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s", 2221 devinfo->settings->board_type, 2222 otp->module, otp->vendor); 2223 bt[3] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s", 2224 devinfo->settings->board_type, 2225 otp->module); 2226 bt[4] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s", 2227 devinfo->settings->board_type, 2228 devinfo->settings->antenna_sku); 2229 bt[5] = devinfo->settings->board_type; 2230 2231 if (!bt[0] || !bt[1] || !bt[2] || !bt[3] || !bt[4]) { 2232 kfree(fwreq); 2233 return NULL; 2234 } 2235 } else { 2236 brcmf_dbg(PCIE, "Board: %s\n", devinfo->settings->board_type); 2237 fwreq->board_types[0] = devinfo->settings->board_type; 2238 } 2239 2240 return fwreq; 2241 } 2242 2243 #ifdef DEBUG 2244 static void 2245 brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active) 2246 { 2247 if (!active) { 2248 if (devinfo->console_active) { 2249 del_timer_sync(&devinfo->timer); 2250 devinfo->console_active = false; 2251 } 2252 return; 2253 } 2254 2255 /* don't start the timer */ 2256 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP || 2257 !devinfo->console_interval || !BRCMF_FWCON_ON()) 2258 return; 2259 2260 if (!devinfo->console_active) { 2261 devinfo->timer.expires = jiffies + devinfo->console_interval; 2262 add_timer(&devinfo->timer); 2263 devinfo->console_active = true; 2264 } else { 2265 /* Reschedule the timer */ 2266 mod_timer(&devinfo->timer, jiffies + devinfo->console_interval); 2267 } 2268 } 2269 2270 static void 2271 brcmf_pcie_fwcon(struct timer_list *t) 2272 { 2273 struct brcmf_pciedev_info *devinfo = from_timer(devinfo, t, timer); 2274 2275 if (!devinfo->console_active) 2276 return; 2277 2278 brcmf_pcie_bus_console_read(devinfo, false); 2279 2280 /* Reschedule the timer if console interval is not zero */ 2281 mod_timer(&devinfo->timer, jiffies + devinfo->console_interval); 2282 } 2283 2284 static int brcmf_pcie_console_interval_get(void *data, u64 *val) 2285 { 2286 struct brcmf_pciedev_info *devinfo = data; 2287 2288 *val = devinfo->console_interval; 2289 2290 return 0; 2291 } 2292 2293 static int brcmf_pcie_console_interval_set(void *data, u64 val) 2294 { 2295 struct brcmf_pciedev_info *devinfo = data; 2296 2297 if (val > MAX_CONSOLE_INTERVAL) 2298 return -EINVAL; 2299 2300 devinfo->console_interval = val; 2301 2302 if (!val && devinfo->console_active) 2303 brcmf_pcie_fwcon_timer(devinfo, false); 2304 else if (val) 2305 brcmf_pcie_fwcon_timer(devinfo, true); 2306 2307 return 0; 2308 } 2309 2310 DEFINE_SIMPLE_ATTRIBUTE(brcmf_pcie_console_interval_fops, 2311 brcmf_pcie_console_interval_get, 2312 brcmf_pcie_console_interval_set, 2313 "%llu\n"); 2314 2315 static void brcmf_pcie_debugfs_create(struct device *dev) 2316 { 2317 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2318 struct brcmf_pub *drvr = bus_if->drvr; 2319 struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie; 2320 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo; 2321 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); 2322 2323 if (IS_ERR_OR_NULL(dentry)) 2324 return; 2325 2326 devinfo->console_interval = BRCMF_CONSOLE; 2327 2328 debugfs_create_file("console_interval", 0644, dentry, devinfo, 2329 &brcmf_pcie_console_interval_fops); 2330 } 2331 2332 #else 2333 void brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active) 2334 { 2335 } 2336 2337 static void brcmf_pcie_debugfs_create(struct device *dev) 2338 { 2339 } 2340 #endif 2341 2342 static int 2343 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2344 { 2345 int ret; 2346 struct brcmf_fw_request *fwreq; 2347 struct brcmf_pciedev_info *devinfo; 2348 struct brcmf_pciedev *pcie_bus_dev; 2349 struct brcmf_core *core; 2350 struct brcmf_bus *bus; 2351 2352 brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device); 2353 2354 ret = -ENOMEM; 2355 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL); 2356 if (devinfo == NULL) 2357 return ret; 2358 2359 devinfo->pdev = pdev; 2360 pcie_bus_dev = NULL; 2361 devinfo->ci = brcmf_chip_attach(devinfo, pdev->device, 2362 &brcmf_pcie_buscore_ops); 2363 if (IS_ERR(devinfo->ci)) { 2364 ret = PTR_ERR(devinfo->ci); 2365 devinfo->ci = NULL; 2366 goto fail; 2367 } 2368 2369 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 2370 if (core->rev >= 64) 2371 devinfo->reginfo = &brcmf_reginfo_64; 2372 else 2373 devinfo->reginfo = &brcmf_reginfo_default; 2374 2375 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL); 2376 if (pcie_bus_dev == NULL) { 2377 ret = -ENOMEM; 2378 goto fail; 2379 } 2380 2381 devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev, 2382 BRCMF_BUSTYPE_PCIE, 2383 devinfo->ci->chip, 2384 devinfo->ci->chiprev); 2385 if (!devinfo->settings) { 2386 ret = -ENOMEM; 2387 goto fail; 2388 } 2389 2390 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 2391 if (!bus) { 2392 ret = -ENOMEM; 2393 goto fail; 2394 } 2395 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL); 2396 if (!bus->msgbuf) { 2397 ret = -ENOMEM; 2398 kfree(bus); 2399 goto fail; 2400 } 2401 2402 /* hook it all together. */ 2403 pcie_bus_dev->devinfo = devinfo; 2404 pcie_bus_dev->bus = bus; 2405 bus->dev = &pdev->dev; 2406 bus->bus_priv.pcie = pcie_bus_dev; 2407 bus->ops = &brcmf_pcie_bus_ops; 2408 bus->proto_type = BRCMF_PROTO_MSGBUF; 2409 bus->fwvid = id->driver_data; 2410 bus->chip = devinfo->coreid; 2411 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot); 2412 dev_set_drvdata(&pdev->dev, bus); 2413 2414 ret = brcmf_alloc(&devinfo->pdev->dev, devinfo->settings); 2415 if (ret) 2416 goto fail_bus; 2417 2418 ret = brcmf_pcie_read_otp(devinfo); 2419 if (ret) { 2420 brcmf_err(bus, "failed to parse OTP\n"); 2421 goto fail_brcmf; 2422 } 2423 2424 #ifdef DEBUG 2425 /* Set up the fwcon timer */ 2426 timer_setup(&devinfo->timer, brcmf_pcie_fwcon, 0); 2427 #endif 2428 2429 fwreq = brcmf_pcie_prepare_fw_request(devinfo); 2430 if (!fwreq) { 2431 ret = -ENOMEM; 2432 goto fail_brcmf; 2433 } 2434 2435 ret = brcmf_fw_get_firmwares(bus->dev, fwreq, brcmf_pcie_setup); 2436 if (ret < 0) { 2437 kfree(fwreq); 2438 goto fail_brcmf; 2439 } 2440 return 0; 2441 2442 fail_brcmf: 2443 brcmf_free(&devinfo->pdev->dev); 2444 fail_bus: 2445 kfree(bus->msgbuf); 2446 kfree(bus); 2447 fail: 2448 brcmf_err(NULL, "failed %x:%x\n", pdev->vendor, pdev->device); 2449 brcmf_pcie_release_resource(devinfo); 2450 if (devinfo->ci) 2451 brcmf_chip_detach(devinfo->ci); 2452 if (devinfo->settings) 2453 brcmf_release_module_param(devinfo->settings); 2454 kfree(pcie_bus_dev); 2455 kfree(devinfo); 2456 return ret; 2457 } 2458 2459 2460 static void 2461 brcmf_pcie_remove(struct pci_dev *pdev) 2462 { 2463 struct brcmf_pciedev_info *devinfo; 2464 struct brcmf_bus *bus; 2465 2466 brcmf_dbg(PCIE, "Enter\n"); 2467 2468 bus = dev_get_drvdata(&pdev->dev); 2469 if (bus == NULL) 2470 return; 2471 2472 devinfo = bus->bus_priv.pcie->devinfo; 2473 brcmf_pcie_bus_console_read(devinfo, false); 2474 brcmf_pcie_fwcon_timer(devinfo, false); 2475 2476 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 2477 if (devinfo->ci) 2478 brcmf_pcie_intr_disable(devinfo); 2479 2480 brcmf_detach(&pdev->dev); 2481 brcmf_free(&pdev->dev); 2482 2483 kfree(bus->bus_priv.pcie); 2484 kfree(bus->msgbuf->flowrings); 2485 kfree(bus->msgbuf); 2486 kfree(bus); 2487 2488 brcmf_pcie_release_irq(devinfo); 2489 brcmf_pcie_release_scratchbuffers(devinfo); 2490 brcmf_pcie_release_ringbuffers(devinfo); 2491 brcmf_pcie_reset_device(devinfo); 2492 brcmf_pcie_release_resource(devinfo); 2493 release_firmware(devinfo->clm_fw); 2494 2495 if (devinfo->ci) 2496 brcmf_chip_detach(devinfo->ci); 2497 if (devinfo->settings) 2498 brcmf_release_module_param(devinfo->settings); 2499 2500 kfree(devinfo); 2501 dev_set_drvdata(&pdev->dev, NULL); 2502 } 2503 2504 2505 #ifdef CONFIG_PM 2506 2507 2508 static int brcmf_pcie_pm_enter_D3(struct device *dev) 2509 { 2510 struct brcmf_pciedev_info *devinfo; 2511 struct brcmf_bus *bus; 2512 2513 brcmf_dbg(PCIE, "Enter\n"); 2514 2515 bus = dev_get_drvdata(dev); 2516 devinfo = bus->bus_priv.pcie->devinfo; 2517 2518 brcmf_pcie_fwcon_timer(devinfo, false); 2519 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN); 2520 2521 devinfo->mbdata_completed = false; 2522 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM); 2523 2524 wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed, 2525 BRCMF_PCIE_MBDATA_TIMEOUT); 2526 if (!devinfo->mbdata_completed) { 2527 brcmf_err(bus, "Timeout on response for entering D3 substate\n"); 2528 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 2529 return -EIO; 2530 } 2531 2532 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 2533 2534 return 0; 2535 } 2536 2537 2538 static int brcmf_pcie_pm_leave_D3(struct device *dev) 2539 { 2540 struct brcmf_pciedev_info *devinfo; 2541 struct brcmf_bus *bus; 2542 struct pci_dev *pdev; 2543 int err; 2544 2545 brcmf_dbg(PCIE, "Enter\n"); 2546 2547 bus = dev_get_drvdata(dev); 2548 devinfo = bus->bus_priv.pcie->devinfo; 2549 brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus); 2550 2551 /* Check if device is still up and running, if so we are ready */ 2552 if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->intmask) != 0) { 2553 brcmf_dbg(PCIE, "Try to wakeup device....\n"); 2554 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM)) 2555 goto cleanup; 2556 brcmf_dbg(PCIE, "Hot resume, continue....\n"); 2557 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 2558 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 2559 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 2560 brcmf_pcie_intr_enable(devinfo); 2561 brcmf_pcie_hostready(devinfo); 2562 brcmf_pcie_fwcon_timer(devinfo, true); 2563 return 0; 2564 } 2565 2566 cleanup: 2567 brcmf_chip_detach(devinfo->ci); 2568 devinfo->ci = NULL; 2569 pdev = devinfo->pdev; 2570 brcmf_pcie_remove(pdev); 2571 2572 err = brcmf_pcie_probe(pdev, NULL); 2573 if (err) 2574 __brcmf_err(NULL, __func__, "probe after resume failed, err=%d\n", err); 2575 2576 return err; 2577 } 2578 2579 2580 static const struct dev_pm_ops brcmf_pciedrvr_pm = { 2581 .suspend = brcmf_pcie_pm_enter_D3, 2582 .resume = brcmf_pcie_pm_leave_D3, 2583 .freeze = brcmf_pcie_pm_enter_D3, 2584 .restore = brcmf_pcie_pm_leave_D3, 2585 }; 2586 2587 2588 #endif /* CONFIG_PM */ 2589 2590 2591 #define BRCMF_PCIE_DEVICE(dev_id, fw_vend) \ 2592 { \ 2593 BRCM_PCIE_VENDOR_ID_BROADCOM, (dev_id), \ 2594 PCI_ANY_ID, PCI_ANY_ID, \ 2595 PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, \ 2596 BRCMF_FWVENDOR_ ## fw_vend \ 2597 } 2598 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev, fw_vend) \ 2599 { \ 2600 BRCM_PCIE_VENDOR_ID_BROADCOM, (dev_id), \ 2601 (subvend), (subdev), \ 2602 PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, \ 2603 BRCMF_FWVENDOR_ ## fw_vend \ 2604 } 2605 2606 static const struct pci_device_id brcmf_pcie_devid_table[] = { 2607 BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID, WCC), 2608 BRCMF_PCIE_DEVICE_SUB(0x4355, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4355, WCC), 2609 BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_RAW_DEVICE_ID, WCC), 2610 BRCMF_PCIE_DEVICE(BRCM_PCIE_4355_DEVICE_ID, WCC), 2611 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID, WCC), 2612 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID, WCC), 2613 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID, WCC), 2614 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_RAW_DEVICE_ID, WCC), 2615 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID, WCC), 2616 BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID, WCC), 2617 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID, WCC), 2618 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID, WCC), 2619 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID, WCC), 2620 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID, WCC), 2621 BRCMF_PCIE_DEVICE(BRCM_PCIE_4364_DEVICE_ID, WCC), 2622 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID, BCA), 2623 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID, BCA), 2624 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID, BCA), 2625 BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365, BCA), 2626 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID, BCA), 2627 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID, BCA), 2628 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID, BCA), 2629 BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID, WCC), 2630 BRCMF_PCIE_DEVICE(BRCM_PCIE_43596_DEVICE_ID, CYW), 2631 BRCMF_PCIE_DEVICE(BRCM_PCIE_4377_DEVICE_ID, WCC), 2632 BRCMF_PCIE_DEVICE(BRCM_PCIE_4378_DEVICE_ID, WCC), 2633 2634 { /* end: all zeroes */ } 2635 }; 2636 2637 2638 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table); 2639 2640 2641 static struct pci_driver brcmf_pciedrvr = { 2642 .node = {}, 2643 .name = KBUILD_MODNAME, 2644 .id_table = brcmf_pcie_devid_table, 2645 .probe = brcmf_pcie_probe, 2646 .remove = brcmf_pcie_remove, 2647 #ifdef CONFIG_PM 2648 .driver.pm = &brcmf_pciedrvr_pm, 2649 #endif 2650 .driver.coredump = brcmf_dev_coredump, 2651 }; 2652 2653 2654 int brcmf_pcie_register(void) 2655 { 2656 brcmf_dbg(PCIE, "Enter\n"); 2657 return pci_register_driver(&brcmf_pciedrvr); 2658 } 2659 2660 2661 void brcmf_pcie_exit(void) 2662 { 2663 brcmf_dbg(PCIE, "Enter\n"); 2664 pci_unregister_driver(&brcmf_pciedrvr); 2665 } 2666