1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2014 Broadcom Corporation 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/firmware.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/bcma/bcma.h> 14 #include <linux/sched.h> 15 #include <linux/io.h> 16 #include <asm/unaligned.h> 17 18 #include <soc.h> 19 #include <chipcommon.h> 20 #include <brcmu_utils.h> 21 #include <brcmu_wifi.h> 22 #include <brcm_hw_ids.h> 23 24 /* Custom brcmf_err() that takes bus arg and passes it further */ 25 #define brcmf_err(bus, fmt, ...) \ 26 do { \ 27 if (IS_ENABLED(CONFIG_BRCMDBG) || \ 28 IS_ENABLED(CONFIG_BRCM_TRACING) || \ 29 net_ratelimit()) \ 30 __brcmf_err(bus, __func__, fmt, ##__VA_ARGS__); \ 31 } while (0) 32 33 #include "debug.h" 34 #include "bus.h" 35 #include "commonring.h" 36 #include "msgbuf.h" 37 #include "pcie.h" 38 #include "firmware.h" 39 #include "chip.h" 40 #include "core.h" 41 #include "common.h" 42 43 44 enum brcmf_pcie_state { 45 BRCMFMAC_PCIE_STATE_DOWN, 46 BRCMFMAC_PCIE_STATE_UP 47 }; 48 49 BRCMF_FW_DEF(43602, "brcmfmac43602-pcie"); 50 BRCMF_FW_DEF(4350, "brcmfmac4350-pcie"); 51 BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie"); 52 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-pcie"); 53 BRCMF_FW_CLM_DEF(43570, "brcmfmac43570-pcie"); 54 BRCMF_FW_DEF(4358, "brcmfmac4358-pcie"); 55 BRCMF_FW_DEF(4359, "brcmfmac4359-pcie"); 56 BRCMF_FW_DEF(4364, "brcmfmac4364-pcie"); 57 BRCMF_FW_DEF(4365B, "brcmfmac4365b-pcie"); 58 BRCMF_FW_DEF(4365C, "brcmfmac4365c-pcie"); 59 BRCMF_FW_DEF(4366B, "brcmfmac4366b-pcie"); 60 BRCMF_FW_DEF(4366C, "brcmfmac4366c-pcie"); 61 BRCMF_FW_DEF(4371, "brcmfmac4371-pcie"); 62 63 /* firmware config files */ 64 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt"); 65 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txt"); 66 67 /* per-board firmware binaries */ 68 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.bin"); 69 70 static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = { 71 BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602), 72 BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C), 73 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C), 74 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350), 75 BRCMF_FW_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C), 76 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 77 BRCMF_FW_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570), 78 BRCMF_FW_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570), 79 BRCMF_FW_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570), 80 BRCMF_FW_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358), 81 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359), 82 BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0xFFFFFFFF, 4364), 83 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B), 84 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C), 85 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B), 86 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C), 87 BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C), 88 BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C), 89 BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371), 90 }; 91 92 #define BRCMF_PCIE_FW_UP_TIMEOUT 5000 /* msec */ 93 94 #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024) 95 96 /* backplane addres space accessed by BAR0 */ 97 #define BRCMF_PCIE_BAR0_WINDOW 0x80 98 #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000 99 #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70 100 101 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000 102 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000 103 104 #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40 105 #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C 106 107 #define BRCMF_PCIE_REG_INTSTATUS 0x90 108 #define BRCMF_PCIE_REG_INTMASK 0x94 109 #define BRCMF_PCIE_REG_SBMBX 0x98 110 111 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC 112 113 #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24 114 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48 115 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C 116 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120 117 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124 118 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0 0x140 119 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1 0x144 120 121 #define BRCMF_PCIE2_INTA 0x01 122 #define BRCMF_PCIE2_INTB 0x02 123 124 #define BRCMF_PCIE_INT_0 0x01 125 #define BRCMF_PCIE_INT_1 0x02 126 #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \ 127 BRCMF_PCIE_INT_1) 128 129 #define BRCMF_PCIE_MB_INT_FN0_0 0x0100 130 #define BRCMF_PCIE_MB_INT_FN0_1 0x0200 131 #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000 132 #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000 133 #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000 134 #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000 135 #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000 136 #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000 137 #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000 138 #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000 139 140 #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \ 141 BRCMF_PCIE_MB_INT_D2H0_DB1 | \ 142 BRCMF_PCIE_MB_INT_D2H1_DB0 | \ 143 BRCMF_PCIE_MB_INT_D2H1_DB1 | \ 144 BRCMF_PCIE_MB_INT_D2H2_DB0 | \ 145 BRCMF_PCIE_MB_INT_D2H2_DB1 | \ 146 BRCMF_PCIE_MB_INT_D2H3_DB0 | \ 147 BRCMF_PCIE_MB_INT_D2H3_DB1) 148 149 #define BRCMF_PCIE_SHARED_VERSION_7 7 150 #define BRCMF_PCIE_MIN_SHARED_VERSION 5 151 #define BRCMF_PCIE_MAX_SHARED_VERSION BRCMF_PCIE_SHARED_VERSION_7 152 #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF 153 #define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000 154 #define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000 155 #define BRCMF_PCIE_SHARED_HOSTRDY_DB1 0x10000000 156 157 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000 158 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000 159 160 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34 161 #define BRCMF_SHARED_RING_BASE_OFFSET 52 162 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36 163 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20 164 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40 165 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44 166 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48 167 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52 168 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56 169 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64 170 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68 171 172 #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0 173 #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1 174 #define BRCMF_RING_H2D_RING_MEM_OFFSET 4 175 #define BRCMF_RING_H2D_RING_STATE_OFFSET 8 176 177 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8 178 #define BRCMF_RING_MAX_ITEM_OFFSET 4 179 #define BRCMF_RING_LEN_ITEMS_OFFSET 6 180 #define BRCMF_RING_MEM_SZ 16 181 #define BRCMF_RING_STATE_SZ 8 182 183 #define BRCMF_DEF_MAX_RXBUFPOST 255 184 185 #define BRCMF_CONSOLE_BUFADDR_OFFSET 8 186 #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12 187 #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16 188 189 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8 190 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024 191 192 #define BRCMF_D2H_DEV_D3_ACK 0x00000001 193 #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002 194 #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004 195 #define BRCMF_D2H_DEV_FWHALT 0x10000000 196 197 #define BRCMF_H2D_HOST_D3_INFORM 0x00000001 198 #define BRCMF_H2D_HOST_DS_ACK 0x00000002 199 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008 200 #define BRCMF_H2D_HOST_D0_INFORM 0x00000010 201 202 #define BRCMF_PCIE_MBDATA_TIMEOUT msecs_to_jiffies(2000) 203 204 #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4 205 #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C 206 #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58 207 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C 208 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60 209 #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64 210 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC 211 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC 212 #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228 213 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248 214 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0 215 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4 216 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3 217 218 /* Magic number at a magic location to find RAM size */ 219 #define BRCMF_RAMSIZE_MAGIC 0x534d4152 /* SMAR */ 220 #define BRCMF_RAMSIZE_OFFSET 0x6c 221 222 223 struct brcmf_pcie_console { 224 u32 base_addr; 225 u32 buf_addr; 226 u32 bufsize; 227 u32 read_idx; 228 u8 log_str[256]; 229 u8 log_idx; 230 }; 231 232 struct brcmf_pcie_shared_info { 233 u32 tcm_base_address; 234 u32 flags; 235 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS]; 236 struct brcmf_pcie_ringbuf *flowrings; 237 u16 max_rxbufpost; 238 u16 max_flowrings; 239 u16 max_submissionrings; 240 u16 max_completionrings; 241 u32 rx_dataoffset; 242 u32 htod_mb_data_addr; 243 u32 dtoh_mb_data_addr; 244 u32 ring_info_addr; 245 struct brcmf_pcie_console console; 246 void *scratch; 247 dma_addr_t scratch_dmahandle; 248 void *ringupd; 249 dma_addr_t ringupd_dmahandle; 250 u8 version; 251 }; 252 253 struct brcmf_pcie_core_info { 254 u32 base; 255 u32 wrapbase; 256 }; 257 258 struct brcmf_pciedev_info { 259 enum brcmf_pcie_state state; 260 bool in_irq; 261 struct pci_dev *pdev; 262 char fw_name[BRCMF_FW_NAME_LEN]; 263 char nvram_name[BRCMF_FW_NAME_LEN]; 264 void __iomem *regs; 265 void __iomem *tcm; 266 u32 ram_base; 267 u32 ram_size; 268 struct brcmf_chip *ci; 269 u32 coreid; 270 struct brcmf_pcie_shared_info shared; 271 wait_queue_head_t mbdata_resp_wait; 272 bool mbdata_completed; 273 bool irq_allocated; 274 bool wowl_enabled; 275 u8 dma_idx_sz; 276 void *idxbuf; 277 u32 idxbuf_sz; 278 dma_addr_t idxbuf_dmahandle; 279 u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset); 280 void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 281 u16 value); 282 struct brcmf_mp_device *settings; 283 }; 284 285 struct brcmf_pcie_ringbuf { 286 struct brcmf_commonring commonring; 287 dma_addr_t dma_handle; 288 u32 w_idx_addr; 289 u32 r_idx_addr; 290 struct brcmf_pciedev_info *devinfo; 291 u8 id; 292 }; 293 294 /** 295 * struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info 296 * 297 * @ringmem: dongle memory pointer to ring memory location 298 * @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers 299 * @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers 300 * @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers 301 * @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers 302 * @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers 303 * @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers 304 * @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers 305 * @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers 306 * @max_flowrings: maximum number of tx flow rings supported. 307 * @max_submissionrings: maximum number of submission rings(h2d) supported. 308 * @max_completionrings: maximum number of completion rings(d2h) supported. 309 */ 310 struct brcmf_pcie_dhi_ringinfo { 311 __le32 ringmem; 312 __le32 h2d_w_idx_ptr; 313 __le32 h2d_r_idx_ptr; 314 __le32 d2h_w_idx_ptr; 315 __le32 d2h_r_idx_ptr; 316 struct msgbuf_buf_addr h2d_w_idx_hostaddr; 317 struct msgbuf_buf_addr h2d_r_idx_hostaddr; 318 struct msgbuf_buf_addr d2h_w_idx_hostaddr; 319 struct msgbuf_buf_addr d2h_r_idx_hostaddr; 320 __le16 max_flowrings; 321 __le16 max_submissionrings; 322 __le16 max_completionrings; 323 }; 324 325 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = { 326 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM, 327 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM, 328 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM, 329 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM, 330 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM 331 }; 332 333 static const u32 brcmf_ring_itemsize_pre_v7[BRCMF_NROF_COMMON_MSGRINGS] = { 334 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 335 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 336 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 337 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7, 338 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7 339 }; 340 341 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = { 342 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 343 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 344 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 345 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE, 346 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE 347 }; 348 349 static void brcmf_pcie_setup(struct device *dev, int ret, 350 struct brcmf_fw_request *fwreq); 351 static struct brcmf_fw_request * 352 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo); 353 354 static u32 355 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset) 356 { 357 void __iomem *address = devinfo->regs + reg_offset; 358 359 return (ioread32(address)); 360 } 361 362 363 static void 364 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset, 365 u32 value) 366 { 367 void __iomem *address = devinfo->regs + reg_offset; 368 369 iowrite32(value, address); 370 } 371 372 373 static u8 374 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 375 { 376 void __iomem *address = devinfo->tcm + mem_offset; 377 378 return (ioread8(address)); 379 } 380 381 382 static u16 383 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 384 { 385 void __iomem *address = devinfo->tcm + mem_offset; 386 387 return (ioread16(address)); 388 } 389 390 391 static void 392 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 393 u16 value) 394 { 395 void __iomem *address = devinfo->tcm + mem_offset; 396 397 iowrite16(value, address); 398 } 399 400 401 static u16 402 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 403 { 404 u16 *address = devinfo->idxbuf + mem_offset; 405 406 return (*(address)); 407 } 408 409 410 static void 411 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 412 u16 value) 413 { 414 u16 *address = devinfo->idxbuf + mem_offset; 415 416 *(address) = value; 417 } 418 419 420 static u32 421 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 422 { 423 void __iomem *address = devinfo->tcm + mem_offset; 424 425 return (ioread32(address)); 426 } 427 428 429 static void 430 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 431 u32 value) 432 { 433 void __iomem *address = devinfo->tcm + mem_offset; 434 435 iowrite32(value, address); 436 } 437 438 439 static u32 440 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 441 { 442 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 443 444 return (ioread32(addr)); 445 } 446 447 448 static void 449 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 450 u32 value) 451 { 452 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 453 454 iowrite32(value, addr); 455 } 456 457 458 static void 459 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 460 void *dstaddr, u32 len) 461 { 462 void __iomem *address = devinfo->tcm + mem_offset; 463 __le32 *dst32; 464 __le16 *dst16; 465 u8 *dst8; 466 467 if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) { 468 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) { 469 dst8 = (u8 *)dstaddr; 470 while (len) { 471 *dst8 = ioread8(address); 472 address++; 473 dst8++; 474 len--; 475 } 476 } else { 477 len = len / 2; 478 dst16 = (__le16 *)dstaddr; 479 while (len) { 480 *dst16 = cpu_to_le16(ioread16(address)); 481 address += 2; 482 dst16++; 483 len--; 484 } 485 } 486 } else { 487 len = len / 4; 488 dst32 = (__le32 *)dstaddr; 489 while (len) { 490 *dst32 = cpu_to_le32(ioread32(address)); 491 address += 4; 492 dst32++; 493 len--; 494 } 495 } 496 } 497 498 499 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \ 500 CHIPCREGOFFS(reg), value) 501 502 503 static void 504 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid) 505 { 506 const struct pci_dev *pdev = devinfo->pdev; 507 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 508 struct brcmf_core *core; 509 u32 bar0_win; 510 511 core = brcmf_chip_get_core(devinfo->ci, coreid); 512 if (core) { 513 bar0_win = core->base; 514 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win); 515 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, 516 &bar0_win) == 0) { 517 if (bar0_win != core->base) { 518 bar0_win = core->base; 519 pci_write_config_dword(pdev, 520 BRCMF_PCIE_BAR0_WINDOW, 521 bar0_win); 522 } 523 } 524 } else { 525 brcmf_err(bus, "Unsupported core selected %x\n", coreid); 526 } 527 } 528 529 530 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo) 531 { 532 struct brcmf_core *core; 533 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD, 534 BRCMF_PCIE_CFGREG_PM_CSR, 535 BRCMF_PCIE_CFGREG_MSI_CAP, 536 BRCMF_PCIE_CFGREG_MSI_ADDR_L, 537 BRCMF_PCIE_CFGREG_MSI_ADDR_H, 538 BRCMF_PCIE_CFGREG_MSI_DATA, 539 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2, 540 BRCMF_PCIE_CFGREG_RBAR_CTRL, 541 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1, 542 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG, 543 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG }; 544 u32 i; 545 u32 val; 546 u32 lsc; 547 548 if (!devinfo->ci) 549 return; 550 551 /* Disable ASPM */ 552 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 553 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 554 &lsc); 555 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB); 556 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 557 val); 558 559 /* Watchdog reset */ 560 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON); 561 WRITECC32(devinfo, watchdog, 4); 562 msleep(100); 563 564 /* Restore ASPM */ 565 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 566 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 567 lsc); 568 569 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 570 if (core->rev <= 13) { 571 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) { 572 brcmf_pcie_write_reg32(devinfo, 573 BRCMF_PCIE_PCIE2REG_CONFIGADDR, 574 cfg_offset[i]); 575 val = brcmf_pcie_read_reg32(devinfo, 576 BRCMF_PCIE_PCIE2REG_CONFIGDATA); 577 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n", 578 cfg_offset[i], val); 579 brcmf_pcie_write_reg32(devinfo, 580 BRCMF_PCIE_PCIE2REG_CONFIGDATA, 581 val); 582 } 583 } 584 } 585 586 587 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo) 588 { 589 u32 config; 590 591 /* BAR1 window may not be sized properly */ 592 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 593 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0); 594 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA); 595 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config); 596 597 device_wakeup_enable(&devinfo->pdev->dev); 598 } 599 600 601 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo) 602 { 603 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 604 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4); 605 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 606 5); 607 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 608 0); 609 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 610 7); 611 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 612 0); 613 } 614 return 0; 615 } 616 617 618 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo, 619 u32 resetintr) 620 { 621 struct brcmf_core *core; 622 623 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 624 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM); 625 brcmf_chip_resetcore(core, 0, 0, 0); 626 } 627 628 if (!brcmf_chip_set_active(devinfo->ci, resetintr)) 629 return -EINVAL; 630 return 0; 631 } 632 633 634 static int 635 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data) 636 { 637 struct brcmf_pcie_shared_info *shared; 638 struct brcmf_core *core; 639 u32 addr; 640 u32 cur_htod_mb_data; 641 u32 i; 642 643 shared = &devinfo->shared; 644 addr = shared->htod_mb_data_addr; 645 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 646 647 if (cur_htod_mb_data != 0) 648 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n", 649 cur_htod_mb_data); 650 651 i = 0; 652 while (cur_htod_mb_data != 0) { 653 msleep(10); 654 i++; 655 if (i > 100) 656 return -EIO; 657 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 658 } 659 660 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data); 661 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 662 663 /* Send mailbox interrupt twice as a hardware workaround */ 664 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 665 if (core->rev <= 13) 666 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 667 668 return 0; 669 } 670 671 672 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo) 673 { 674 struct brcmf_pcie_shared_info *shared; 675 u32 addr; 676 u32 dtoh_mb_data; 677 678 shared = &devinfo->shared; 679 addr = shared->dtoh_mb_data_addr; 680 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 681 682 if (!dtoh_mb_data) 683 return; 684 685 brcmf_pcie_write_tcm32(devinfo, addr, 0); 686 687 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data); 688 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) { 689 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n"); 690 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK); 691 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n"); 692 } 693 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE) 694 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n"); 695 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) { 696 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n"); 697 devinfo->mbdata_completed = true; 698 wake_up(&devinfo->mbdata_resp_wait); 699 } 700 if (dtoh_mb_data & BRCMF_D2H_DEV_FWHALT) { 701 brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n"); 702 brcmf_fw_crashed(&devinfo->pdev->dev); 703 } 704 } 705 706 707 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo) 708 { 709 struct brcmf_pcie_shared_info *shared; 710 struct brcmf_pcie_console *console; 711 u32 addr; 712 713 shared = &devinfo->shared; 714 console = &shared->console; 715 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET; 716 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr); 717 718 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET; 719 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr); 720 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET; 721 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr); 722 723 brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n", 724 console->base_addr, console->buf_addr, console->bufsize); 725 } 726 727 /** 728 * brcmf_pcie_bus_console_read - reads firmware messages 729 * 730 * @devinfo: pointer to the device data structure 731 * @error: specifies if error has occurred (prints messages unconditionally) 732 */ 733 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo, 734 bool error) 735 { 736 struct pci_dev *pdev = devinfo->pdev; 737 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 738 struct brcmf_pcie_console *console; 739 u32 addr; 740 u8 ch; 741 u32 newidx; 742 743 if (!error && !BRCMF_FWCON_ON()) 744 return; 745 746 console = &devinfo->shared.console; 747 if (!console->base_addr) 748 return; 749 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET; 750 newidx = brcmf_pcie_read_tcm32(devinfo, addr); 751 while (newidx != console->read_idx) { 752 addr = console->buf_addr + console->read_idx; 753 ch = brcmf_pcie_read_tcm8(devinfo, addr); 754 console->read_idx++; 755 if (console->read_idx == console->bufsize) 756 console->read_idx = 0; 757 if (ch == '\r') 758 continue; 759 console->log_str[console->log_idx] = ch; 760 console->log_idx++; 761 if ((ch != '\n') && 762 (console->log_idx == (sizeof(console->log_str) - 2))) { 763 ch = '\n'; 764 console->log_str[console->log_idx] = ch; 765 console->log_idx++; 766 } 767 if (ch == '\n') { 768 console->log_str[console->log_idx] = 0; 769 if (error) 770 __brcmf_err(bus, __func__, "CONSOLE: %s", 771 console->log_str); 772 else 773 pr_debug("CONSOLE: %s", console->log_str); 774 console->log_idx = 0; 775 } 776 } 777 } 778 779 780 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo) 781 { 782 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 0); 783 } 784 785 786 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo) 787 { 788 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 789 BRCMF_PCIE_MB_INT_D2H_DB | 790 BRCMF_PCIE_MB_INT_FN0_0 | 791 BRCMF_PCIE_MB_INT_FN0_1); 792 } 793 794 static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo) 795 { 796 if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1) 797 brcmf_pcie_write_reg32(devinfo, 798 BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1, 1); 799 } 800 801 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg) 802 { 803 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 804 805 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) { 806 brcmf_pcie_intr_disable(devinfo); 807 brcmf_dbg(PCIE, "Enter\n"); 808 return IRQ_WAKE_THREAD; 809 } 810 return IRQ_NONE; 811 } 812 813 814 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg) 815 { 816 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 817 u32 status; 818 819 devinfo->in_irq = true; 820 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 821 brcmf_dbg(PCIE, "Enter %x\n", status); 822 if (status) { 823 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, 824 status); 825 if (status & (BRCMF_PCIE_MB_INT_FN0_0 | 826 BRCMF_PCIE_MB_INT_FN0_1)) 827 brcmf_pcie_handle_mb_data(devinfo); 828 if (status & BRCMF_PCIE_MB_INT_D2H_DB) { 829 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 830 brcmf_proto_msgbuf_rx_trigger( 831 &devinfo->pdev->dev); 832 } 833 } 834 brcmf_pcie_bus_console_read(devinfo, false); 835 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 836 brcmf_pcie_intr_enable(devinfo); 837 devinfo->in_irq = false; 838 return IRQ_HANDLED; 839 } 840 841 842 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo) 843 { 844 struct pci_dev *pdev = devinfo->pdev; 845 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 846 847 brcmf_pcie_intr_disable(devinfo); 848 849 brcmf_dbg(PCIE, "Enter\n"); 850 851 pci_enable_msi(pdev); 852 if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr, 853 brcmf_pcie_isr_thread, IRQF_SHARED, 854 "brcmf_pcie_intr", devinfo)) { 855 pci_disable_msi(pdev); 856 brcmf_err(bus, "Failed to request IRQ %d\n", pdev->irq); 857 return -EIO; 858 } 859 devinfo->irq_allocated = true; 860 return 0; 861 } 862 863 864 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo) 865 { 866 struct pci_dev *pdev = devinfo->pdev; 867 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 868 u32 status; 869 u32 count; 870 871 if (!devinfo->irq_allocated) 872 return; 873 874 brcmf_pcie_intr_disable(devinfo); 875 free_irq(pdev->irq, devinfo); 876 pci_disable_msi(pdev); 877 878 msleep(50); 879 count = 0; 880 while ((devinfo->in_irq) && (count < 20)) { 881 msleep(50); 882 count++; 883 } 884 if (devinfo->in_irq) 885 brcmf_err(bus, "Still in IRQ (processing) !!!\n"); 886 887 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 888 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, status); 889 890 devinfo->irq_allocated = false; 891 } 892 893 894 static int brcmf_pcie_ring_mb_write_rptr(void *ctx) 895 { 896 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 897 struct brcmf_pciedev_info *devinfo = ring->devinfo; 898 struct brcmf_commonring *commonring = &ring->commonring; 899 900 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 901 return -EIO; 902 903 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr, 904 commonring->w_ptr, ring->id); 905 906 devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr); 907 908 return 0; 909 } 910 911 912 static int brcmf_pcie_ring_mb_write_wptr(void *ctx) 913 { 914 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 915 struct brcmf_pciedev_info *devinfo = ring->devinfo; 916 struct brcmf_commonring *commonring = &ring->commonring; 917 918 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 919 return -EIO; 920 921 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr, 922 commonring->r_ptr, ring->id); 923 924 devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr); 925 926 return 0; 927 } 928 929 930 static int brcmf_pcie_ring_mb_ring_bell(void *ctx) 931 { 932 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 933 struct brcmf_pciedev_info *devinfo = ring->devinfo; 934 935 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 936 return -EIO; 937 938 brcmf_dbg(PCIE, "RING !\n"); 939 /* Any arbitrary value will do, lets use 1 */ 940 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0, 1); 941 942 return 0; 943 } 944 945 946 static int brcmf_pcie_ring_mb_update_rptr(void *ctx) 947 { 948 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 949 struct brcmf_pciedev_info *devinfo = ring->devinfo; 950 struct brcmf_commonring *commonring = &ring->commonring; 951 952 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 953 return -EIO; 954 955 commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr); 956 957 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr, 958 commonring->w_ptr, ring->id); 959 960 return 0; 961 } 962 963 964 static int brcmf_pcie_ring_mb_update_wptr(void *ctx) 965 { 966 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 967 struct brcmf_pciedev_info *devinfo = ring->devinfo; 968 struct brcmf_commonring *commonring = &ring->commonring; 969 970 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 971 return -EIO; 972 973 commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr); 974 975 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr, 976 commonring->r_ptr, ring->id); 977 978 return 0; 979 } 980 981 982 static void * 983 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo, 984 u32 size, u32 tcm_dma_phys_addr, 985 dma_addr_t *dma_handle) 986 { 987 void *ring; 988 u64 address; 989 990 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle, 991 GFP_KERNEL); 992 if (!ring) 993 return NULL; 994 995 address = (u64)*dma_handle; 996 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr, 997 address & 0xffffffff); 998 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32); 999 1000 return (ring); 1001 } 1002 1003 1004 static struct brcmf_pcie_ringbuf * 1005 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id, 1006 u32 tcm_ring_phys_addr) 1007 { 1008 void *dma_buf; 1009 dma_addr_t dma_handle; 1010 struct brcmf_pcie_ringbuf *ring; 1011 u32 size; 1012 u32 addr; 1013 const u32 *ring_itemsize_array; 1014 1015 if (devinfo->shared.version < BRCMF_PCIE_SHARED_VERSION_7) 1016 ring_itemsize_array = brcmf_ring_itemsize_pre_v7; 1017 else 1018 ring_itemsize_array = brcmf_ring_itemsize; 1019 1020 size = brcmf_ring_max_item[ring_id] * ring_itemsize_array[ring_id]; 1021 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size, 1022 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET, 1023 &dma_handle); 1024 if (!dma_buf) 1025 return NULL; 1026 1027 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET; 1028 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]); 1029 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET; 1030 brcmf_pcie_write_tcm16(devinfo, addr, ring_itemsize_array[ring_id]); 1031 1032 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 1033 if (!ring) { 1034 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf, 1035 dma_handle); 1036 return NULL; 1037 } 1038 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id], 1039 ring_itemsize_array[ring_id], dma_buf); 1040 ring->dma_handle = dma_handle; 1041 ring->devinfo = devinfo; 1042 brcmf_commonring_register_cb(&ring->commonring, 1043 brcmf_pcie_ring_mb_ring_bell, 1044 brcmf_pcie_ring_mb_update_rptr, 1045 brcmf_pcie_ring_mb_update_wptr, 1046 brcmf_pcie_ring_mb_write_rptr, 1047 brcmf_pcie_ring_mb_write_wptr, ring); 1048 1049 return (ring); 1050 } 1051 1052 1053 static void brcmf_pcie_release_ringbuffer(struct device *dev, 1054 struct brcmf_pcie_ringbuf *ring) 1055 { 1056 void *dma_buf; 1057 u32 size; 1058 1059 if (!ring) 1060 return; 1061 1062 dma_buf = ring->commonring.buf_addr; 1063 if (dma_buf) { 1064 size = ring->commonring.depth * ring->commonring.item_len; 1065 dma_free_coherent(dev, size, dma_buf, ring->dma_handle); 1066 } 1067 kfree(ring); 1068 } 1069 1070 1071 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo) 1072 { 1073 u32 i; 1074 1075 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1076 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev, 1077 devinfo->shared.commonrings[i]); 1078 devinfo->shared.commonrings[i] = NULL; 1079 } 1080 kfree(devinfo->shared.flowrings); 1081 devinfo->shared.flowrings = NULL; 1082 if (devinfo->idxbuf) { 1083 dma_free_coherent(&devinfo->pdev->dev, 1084 devinfo->idxbuf_sz, 1085 devinfo->idxbuf, 1086 devinfo->idxbuf_dmahandle); 1087 devinfo->idxbuf = NULL; 1088 } 1089 } 1090 1091 1092 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo) 1093 { 1094 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1095 struct brcmf_pcie_ringbuf *ring; 1096 struct brcmf_pcie_ringbuf *rings; 1097 u32 d2h_w_idx_ptr; 1098 u32 d2h_r_idx_ptr; 1099 u32 h2d_w_idx_ptr; 1100 u32 h2d_r_idx_ptr; 1101 u32 ring_mem_ptr; 1102 u32 i; 1103 u64 address; 1104 u32 bufsz; 1105 u8 idx_offset; 1106 struct brcmf_pcie_dhi_ringinfo ringinfo; 1107 u16 max_flowrings; 1108 u16 max_submissionrings; 1109 u16 max_completionrings; 1110 1111 memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr, 1112 sizeof(ringinfo)); 1113 if (devinfo->shared.version >= 6) { 1114 max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings); 1115 max_flowrings = le16_to_cpu(ringinfo.max_flowrings); 1116 max_completionrings = le16_to_cpu(ringinfo.max_completionrings); 1117 } else { 1118 max_submissionrings = le16_to_cpu(ringinfo.max_flowrings); 1119 max_flowrings = max_submissionrings - 1120 BRCMF_NROF_H2D_COMMON_MSGRINGS; 1121 max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS; 1122 } 1123 1124 if (devinfo->dma_idx_sz != 0) { 1125 bufsz = (max_submissionrings + max_completionrings) * 1126 devinfo->dma_idx_sz * 2; 1127 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz, 1128 &devinfo->idxbuf_dmahandle, 1129 GFP_KERNEL); 1130 if (!devinfo->idxbuf) 1131 devinfo->dma_idx_sz = 0; 1132 } 1133 1134 if (devinfo->dma_idx_sz == 0) { 1135 d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr); 1136 d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr); 1137 h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr); 1138 h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr); 1139 idx_offset = sizeof(u32); 1140 devinfo->write_ptr = brcmf_pcie_write_tcm16; 1141 devinfo->read_ptr = brcmf_pcie_read_tcm16; 1142 brcmf_dbg(PCIE, "Using TCM indices\n"); 1143 } else { 1144 memset(devinfo->idxbuf, 0, bufsz); 1145 devinfo->idxbuf_sz = bufsz; 1146 idx_offset = devinfo->dma_idx_sz; 1147 devinfo->write_ptr = brcmf_pcie_write_idx; 1148 devinfo->read_ptr = brcmf_pcie_read_idx; 1149 1150 h2d_w_idx_ptr = 0; 1151 address = (u64)devinfo->idxbuf_dmahandle; 1152 ringinfo.h2d_w_idx_hostaddr.low_addr = 1153 cpu_to_le32(address & 0xffffffff); 1154 ringinfo.h2d_w_idx_hostaddr.high_addr = 1155 cpu_to_le32(address >> 32); 1156 1157 h2d_r_idx_ptr = h2d_w_idx_ptr + 1158 max_submissionrings * idx_offset; 1159 address += max_submissionrings * idx_offset; 1160 ringinfo.h2d_r_idx_hostaddr.low_addr = 1161 cpu_to_le32(address & 0xffffffff); 1162 ringinfo.h2d_r_idx_hostaddr.high_addr = 1163 cpu_to_le32(address >> 32); 1164 1165 d2h_w_idx_ptr = h2d_r_idx_ptr + 1166 max_submissionrings * idx_offset; 1167 address += max_submissionrings * idx_offset; 1168 ringinfo.d2h_w_idx_hostaddr.low_addr = 1169 cpu_to_le32(address & 0xffffffff); 1170 ringinfo.d2h_w_idx_hostaddr.high_addr = 1171 cpu_to_le32(address >> 32); 1172 1173 d2h_r_idx_ptr = d2h_w_idx_ptr + 1174 max_completionrings * idx_offset; 1175 address += max_completionrings * idx_offset; 1176 ringinfo.d2h_r_idx_hostaddr.low_addr = 1177 cpu_to_le32(address & 0xffffffff); 1178 ringinfo.d2h_r_idx_hostaddr.high_addr = 1179 cpu_to_le32(address >> 32); 1180 1181 memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr, 1182 &ringinfo, sizeof(ringinfo)); 1183 brcmf_dbg(PCIE, "Using host memory indices\n"); 1184 } 1185 1186 ring_mem_ptr = le32_to_cpu(ringinfo.ringmem); 1187 1188 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) { 1189 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1190 if (!ring) 1191 goto fail; 1192 ring->w_idx_addr = h2d_w_idx_ptr; 1193 ring->r_idx_addr = h2d_r_idx_ptr; 1194 ring->id = i; 1195 devinfo->shared.commonrings[i] = ring; 1196 1197 h2d_w_idx_ptr += idx_offset; 1198 h2d_r_idx_ptr += idx_offset; 1199 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1200 } 1201 1202 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS; 1203 i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1204 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1205 if (!ring) 1206 goto fail; 1207 ring->w_idx_addr = d2h_w_idx_ptr; 1208 ring->r_idx_addr = d2h_r_idx_ptr; 1209 ring->id = i; 1210 devinfo->shared.commonrings[i] = ring; 1211 1212 d2h_w_idx_ptr += idx_offset; 1213 d2h_r_idx_ptr += idx_offset; 1214 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1215 } 1216 1217 devinfo->shared.max_flowrings = max_flowrings; 1218 devinfo->shared.max_submissionrings = max_submissionrings; 1219 devinfo->shared.max_completionrings = max_completionrings; 1220 rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL); 1221 if (!rings) 1222 goto fail; 1223 1224 brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings); 1225 1226 for (i = 0; i < max_flowrings; i++) { 1227 ring = &rings[i]; 1228 ring->devinfo = devinfo; 1229 ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART; 1230 brcmf_commonring_register_cb(&ring->commonring, 1231 brcmf_pcie_ring_mb_ring_bell, 1232 brcmf_pcie_ring_mb_update_rptr, 1233 brcmf_pcie_ring_mb_update_wptr, 1234 brcmf_pcie_ring_mb_write_rptr, 1235 brcmf_pcie_ring_mb_write_wptr, 1236 ring); 1237 ring->w_idx_addr = h2d_w_idx_ptr; 1238 ring->r_idx_addr = h2d_r_idx_ptr; 1239 h2d_w_idx_ptr += idx_offset; 1240 h2d_r_idx_ptr += idx_offset; 1241 } 1242 devinfo->shared.flowrings = rings; 1243 1244 return 0; 1245 1246 fail: 1247 brcmf_err(bus, "Allocating ring buffers failed\n"); 1248 brcmf_pcie_release_ringbuffers(devinfo); 1249 return -ENOMEM; 1250 } 1251 1252 1253 static void 1254 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1255 { 1256 if (devinfo->shared.scratch) 1257 dma_free_coherent(&devinfo->pdev->dev, 1258 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1259 devinfo->shared.scratch, 1260 devinfo->shared.scratch_dmahandle); 1261 if (devinfo->shared.ringupd) 1262 dma_free_coherent(&devinfo->pdev->dev, 1263 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1264 devinfo->shared.ringupd, 1265 devinfo->shared.ringupd_dmahandle); 1266 } 1267 1268 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1269 { 1270 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1271 u64 address; 1272 u32 addr; 1273 1274 devinfo->shared.scratch = 1275 dma_alloc_coherent(&devinfo->pdev->dev, 1276 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1277 &devinfo->shared.scratch_dmahandle, 1278 GFP_KERNEL); 1279 if (!devinfo->shared.scratch) 1280 goto fail; 1281 1282 addr = devinfo->shared.tcm_base_address + 1283 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET; 1284 address = (u64)devinfo->shared.scratch_dmahandle; 1285 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1286 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1287 addr = devinfo->shared.tcm_base_address + 1288 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET; 1289 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); 1290 1291 devinfo->shared.ringupd = 1292 dma_alloc_coherent(&devinfo->pdev->dev, 1293 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1294 &devinfo->shared.ringupd_dmahandle, 1295 GFP_KERNEL); 1296 if (!devinfo->shared.ringupd) 1297 goto fail; 1298 1299 addr = devinfo->shared.tcm_base_address + 1300 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET; 1301 address = (u64)devinfo->shared.ringupd_dmahandle; 1302 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1303 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1304 addr = devinfo->shared.tcm_base_address + 1305 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET; 1306 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); 1307 return 0; 1308 1309 fail: 1310 brcmf_err(bus, "Allocating scratch buffers failed\n"); 1311 brcmf_pcie_release_scratchbuffers(devinfo); 1312 return -ENOMEM; 1313 } 1314 1315 1316 static void brcmf_pcie_down(struct device *dev) 1317 { 1318 } 1319 1320 static int brcmf_pcie_preinit(struct device *dev) 1321 { 1322 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1323 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1324 1325 brcmf_dbg(PCIE, "Enter\n"); 1326 1327 brcmf_pcie_intr_enable(buspub->devinfo); 1328 brcmf_pcie_hostready(buspub->devinfo); 1329 1330 return 0; 1331 } 1332 1333 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb) 1334 { 1335 return 0; 1336 } 1337 1338 1339 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg, 1340 uint len) 1341 { 1342 return 0; 1343 } 1344 1345 1346 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg, 1347 uint len) 1348 { 1349 return 0; 1350 } 1351 1352 1353 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled) 1354 { 1355 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1356 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1357 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1358 1359 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled); 1360 devinfo->wowl_enabled = enabled; 1361 } 1362 1363 1364 static size_t brcmf_pcie_get_ramsize(struct device *dev) 1365 { 1366 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1367 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1368 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1369 1370 return devinfo->ci->ramsize - devinfo->ci->srsize; 1371 } 1372 1373 1374 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len) 1375 { 1376 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1377 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1378 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1379 1380 brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len); 1381 brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len); 1382 return 0; 1383 } 1384 1385 static 1386 int brcmf_pcie_get_fwname(struct device *dev, const char *ext, u8 *fw_name) 1387 { 1388 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1389 struct brcmf_fw_request *fwreq; 1390 struct brcmf_fw_name fwnames[] = { 1391 { ext, fw_name }, 1392 }; 1393 1394 fwreq = brcmf_fw_alloc_request(bus_if->chip, bus_if->chiprev, 1395 brcmf_pcie_fwnames, 1396 ARRAY_SIZE(brcmf_pcie_fwnames), 1397 fwnames, ARRAY_SIZE(fwnames)); 1398 if (!fwreq) 1399 return -ENOMEM; 1400 1401 kfree(fwreq); 1402 return 0; 1403 } 1404 1405 static int brcmf_pcie_reset(struct device *dev) 1406 { 1407 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1408 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1409 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1410 struct brcmf_fw_request *fwreq; 1411 int err; 1412 1413 brcmf_pcie_intr_disable(devinfo); 1414 1415 brcmf_pcie_bus_console_read(devinfo, true); 1416 1417 brcmf_detach(dev); 1418 1419 brcmf_pcie_release_irq(devinfo); 1420 brcmf_pcie_release_scratchbuffers(devinfo); 1421 brcmf_pcie_release_ringbuffers(devinfo); 1422 brcmf_pcie_reset_device(devinfo); 1423 1424 fwreq = brcmf_pcie_prepare_fw_request(devinfo); 1425 if (!fwreq) { 1426 dev_err(dev, "Failed to prepare FW request\n"); 1427 return -ENOMEM; 1428 } 1429 1430 err = brcmf_fw_get_firmwares(dev, fwreq, brcmf_pcie_setup); 1431 if (err) { 1432 dev_err(dev, "Failed to prepare FW request\n"); 1433 kfree(fwreq); 1434 } 1435 1436 return err; 1437 } 1438 1439 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = { 1440 .preinit = brcmf_pcie_preinit, 1441 .txdata = brcmf_pcie_tx, 1442 .stop = brcmf_pcie_down, 1443 .txctl = brcmf_pcie_tx_ctlpkt, 1444 .rxctl = brcmf_pcie_rx_ctlpkt, 1445 .wowl_config = brcmf_pcie_wowl_config, 1446 .get_ramsize = brcmf_pcie_get_ramsize, 1447 .get_memdump = brcmf_pcie_get_memdump, 1448 .get_fwname = brcmf_pcie_get_fwname, 1449 .reset = brcmf_pcie_reset, 1450 }; 1451 1452 1453 static void 1454 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data, 1455 u32 data_len) 1456 { 1457 __le32 *field; 1458 u32 newsize; 1459 1460 if (data_len < BRCMF_RAMSIZE_OFFSET + 8) 1461 return; 1462 1463 field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET]; 1464 if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC) 1465 return; 1466 field++; 1467 newsize = le32_to_cpup(field); 1468 1469 brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n", 1470 newsize); 1471 devinfo->ci->ramsize = newsize; 1472 } 1473 1474 1475 static int 1476 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo, 1477 u32 sharedram_addr) 1478 { 1479 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1480 struct brcmf_pcie_shared_info *shared; 1481 u32 addr; 1482 1483 shared = &devinfo->shared; 1484 shared->tcm_base_address = sharedram_addr; 1485 1486 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr); 1487 shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK); 1488 brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version); 1489 if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) || 1490 (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) { 1491 brcmf_err(bus, "Unsupported PCIE version %d\n", 1492 shared->version); 1493 return -EINVAL; 1494 } 1495 1496 /* check firmware support dma indicies */ 1497 if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) { 1498 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX) 1499 devinfo->dma_idx_sz = sizeof(u16); 1500 else 1501 devinfo->dma_idx_sz = sizeof(u32); 1502 } 1503 1504 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET; 1505 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr); 1506 if (shared->max_rxbufpost == 0) 1507 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST; 1508 1509 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET; 1510 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr); 1511 1512 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET; 1513 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1514 1515 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET; 1516 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1517 1518 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET; 1519 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1520 1521 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n", 1522 shared->max_rxbufpost, shared->rx_dataoffset); 1523 1524 brcmf_pcie_bus_console_init(devinfo); 1525 brcmf_pcie_bus_console_read(devinfo, false); 1526 1527 return 0; 1528 } 1529 1530 1531 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo, 1532 const struct firmware *fw, void *nvram, 1533 u32 nvram_len) 1534 { 1535 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1536 u32 sharedram_addr; 1537 u32 sharedram_addr_written; 1538 u32 loop_counter; 1539 int err; 1540 u32 address; 1541 u32 resetintr; 1542 1543 brcmf_dbg(PCIE, "Halt ARM.\n"); 1544 err = brcmf_pcie_enter_download_state(devinfo); 1545 if (err) 1546 return err; 1547 1548 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name); 1549 memcpy_toio(devinfo->tcm + devinfo->ci->rambase, 1550 (void *)fw->data, fw->size); 1551 1552 resetintr = get_unaligned_le32(fw->data); 1553 release_firmware(fw); 1554 1555 /* reset last 4 bytes of RAM address. to be used for shared 1556 * area. This identifies when FW is running 1557 */ 1558 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0); 1559 1560 if (nvram) { 1561 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name); 1562 address = devinfo->ci->rambase + devinfo->ci->ramsize - 1563 nvram_len; 1564 memcpy_toio(devinfo->tcm + address, nvram, nvram_len); 1565 brcmf_fw_nvram_free(nvram); 1566 } else { 1567 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n", 1568 devinfo->nvram_name); 1569 } 1570 1571 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo, 1572 devinfo->ci->ramsize - 1573 4); 1574 brcmf_dbg(PCIE, "Bring ARM in running state\n"); 1575 err = brcmf_pcie_exit_download_state(devinfo, resetintr); 1576 if (err) 1577 return err; 1578 1579 brcmf_dbg(PCIE, "Wait for FW init\n"); 1580 sharedram_addr = sharedram_addr_written; 1581 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50; 1582 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) { 1583 msleep(50); 1584 sharedram_addr = brcmf_pcie_read_ram32(devinfo, 1585 devinfo->ci->ramsize - 1586 4); 1587 loop_counter--; 1588 } 1589 if (sharedram_addr == sharedram_addr_written) { 1590 brcmf_err(bus, "FW failed to initialize\n"); 1591 return -ENODEV; 1592 } 1593 if (sharedram_addr < devinfo->ci->rambase || 1594 sharedram_addr >= devinfo->ci->rambase + devinfo->ci->ramsize) { 1595 brcmf_err(bus, "Invalid shared RAM address 0x%08x\n", 1596 sharedram_addr); 1597 return -ENODEV; 1598 } 1599 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr); 1600 1601 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr)); 1602 } 1603 1604 1605 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo) 1606 { 1607 struct pci_dev *pdev = devinfo->pdev; 1608 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 1609 int err; 1610 phys_addr_t bar0_addr, bar1_addr; 1611 ulong bar1_size; 1612 1613 err = pci_enable_device(pdev); 1614 if (err) { 1615 brcmf_err(bus, "pci_enable_device failed err=%d\n", err); 1616 return err; 1617 } 1618 1619 pci_set_master(pdev); 1620 1621 /* Bar-0 mapped address */ 1622 bar0_addr = pci_resource_start(pdev, 0); 1623 /* Bar-1 mapped address */ 1624 bar1_addr = pci_resource_start(pdev, 2); 1625 /* read Bar-1 mapped memory range */ 1626 bar1_size = pci_resource_len(pdev, 2); 1627 if ((bar1_size == 0) || (bar1_addr == 0)) { 1628 brcmf_err(bus, "BAR1 Not enabled, device size=%ld, addr=%#016llx\n", 1629 bar1_size, (unsigned long long)bar1_addr); 1630 return -EINVAL; 1631 } 1632 1633 devinfo->regs = ioremap(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE); 1634 devinfo->tcm = ioremap(bar1_addr, bar1_size); 1635 1636 if (!devinfo->regs || !devinfo->tcm) { 1637 brcmf_err(bus, "ioremap() failed (%p,%p)\n", devinfo->regs, 1638 devinfo->tcm); 1639 return -EINVAL; 1640 } 1641 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n", 1642 devinfo->regs, (unsigned long long)bar0_addr); 1643 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n", 1644 devinfo->tcm, (unsigned long long)bar1_addr, 1645 (unsigned int)bar1_size); 1646 1647 return 0; 1648 } 1649 1650 1651 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo) 1652 { 1653 if (devinfo->tcm) 1654 iounmap(devinfo->tcm); 1655 if (devinfo->regs) 1656 iounmap(devinfo->regs); 1657 1658 pci_disable_device(devinfo->pdev); 1659 } 1660 1661 1662 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr) 1663 { 1664 u32 ret_addr; 1665 1666 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1); 1667 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1); 1668 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr); 1669 1670 return ret_addr; 1671 } 1672 1673 1674 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr) 1675 { 1676 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1677 1678 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1679 return brcmf_pcie_read_reg32(devinfo, addr); 1680 } 1681 1682 1683 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value) 1684 { 1685 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1686 1687 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1688 brcmf_pcie_write_reg32(devinfo, addr, value); 1689 } 1690 1691 1692 static int brcmf_pcie_buscoreprep(void *ctx) 1693 { 1694 return brcmf_pcie_get_resource(ctx); 1695 } 1696 1697 1698 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip) 1699 { 1700 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1701 u32 val; 1702 1703 devinfo->ci = chip; 1704 brcmf_pcie_reset_device(devinfo); 1705 1706 val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 1707 if (val != 0xffffffff) 1708 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, 1709 val); 1710 1711 return 0; 1712 } 1713 1714 1715 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip, 1716 u32 rstvec) 1717 { 1718 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1719 1720 brcmf_pcie_write_tcm32(devinfo, 0, rstvec); 1721 } 1722 1723 1724 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = { 1725 .prepare = brcmf_pcie_buscoreprep, 1726 .reset = brcmf_pcie_buscore_reset, 1727 .activate = brcmf_pcie_buscore_activate, 1728 .read32 = brcmf_pcie_buscore_read32, 1729 .write32 = brcmf_pcie_buscore_write32, 1730 }; 1731 1732 #define BRCMF_PCIE_FW_CODE 0 1733 #define BRCMF_PCIE_FW_NVRAM 1 1734 1735 static void brcmf_pcie_setup(struct device *dev, int ret, 1736 struct brcmf_fw_request *fwreq) 1737 { 1738 const struct firmware *fw; 1739 void *nvram; 1740 struct brcmf_bus *bus; 1741 struct brcmf_pciedev *pcie_bus_dev; 1742 struct brcmf_pciedev_info *devinfo; 1743 struct brcmf_commonring **flowrings; 1744 u32 i, nvram_len; 1745 1746 /* check firmware loading result */ 1747 if (ret) 1748 goto fail; 1749 1750 bus = dev_get_drvdata(dev); 1751 pcie_bus_dev = bus->bus_priv.pcie; 1752 devinfo = pcie_bus_dev->devinfo; 1753 brcmf_pcie_attach(devinfo); 1754 1755 fw = fwreq->items[BRCMF_PCIE_FW_CODE].binary; 1756 nvram = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.data; 1757 nvram_len = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.len; 1758 kfree(fwreq); 1759 1760 ret = brcmf_chip_get_raminfo(devinfo->ci); 1761 if (ret) { 1762 brcmf_err(bus, "Failed to get RAM info\n"); 1763 release_firmware(fw); 1764 brcmf_fw_nvram_free(nvram); 1765 goto fail; 1766 } 1767 1768 /* Some of the firmwares have the size of the memory of the device 1769 * defined inside the firmware. This is because part of the memory in 1770 * the device is shared and the devision is determined by FW. Parse 1771 * the firmware and adjust the chip memory size now. 1772 */ 1773 brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size); 1774 1775 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len); 1776 if (ret) 1777 goto fail; 1778 1779 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 1780 1781 ret = brcmf_pcie_init_ringbuffers(devinfo); 1782 if (ret) 1783 goto fail; 1784 1785 ret = brcmf_pcie_init_scratchbuffers(devinfo); 1786 if (ret) 1787 goto fail; 1788 1789 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 1790 ret = brcmf_pcie_request_irq(devinfo); 1791 if (ret) 1792 goto fail; 1793 1794 /* hook the commonrings in the bus structure. */ 1795 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) 1796 bus->msgbuf->commonrings[i] = 1797 &devinfo->shared.commonrings[i]->commonring; 1798 1799 flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings), 1800 GFP_KERNEL); 1801 if (!flowrings) 1802 goto fail; 1803 1804 for (i = 0; i < devinfo->shared.max_flowrings; i++) 1805 flowrings[i] = &devinfo->shared.flowrings[i].commonring; 1806 bus->msgbuf->flowrings = flowrings; 1807 1808 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset; 1809 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost; 1810 bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings; 1811 1812 init_waitqueue_head(&devinfo->mbdata_resp_wait); 1813 1814 ret = brcmf_attach(&devinfo->pdev->dev); 1815 if (ret) 1816 goto fail; 1817 1818 brcmf_pcie_bus_console_read(devinfo, false); 1819 1820 return; 1821 1822 fail: 1823 device_release_driver(dev); 1824 } 1825 1826 static struct brcmf_fw_request * 1827 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo) 1828 { 1829 struct brcmf_fw_request *fwreq; 1830 struct brcmf_fw_name fwnames[] = { 1831 { ".bin", devinfo->fw_name }, 1832 { ".txt", devinfo->nvram_name }, 1833 }; 1834 1835 fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev, 1836 brcmf_pcie_fwnames, 1837 ARRAY_SIZE(brcmf_pcie_fwnames), 1838 fwnames, ARRAY_SIZE(fwnames)); 1839 if (!fwreq) 1840 return NULL; 1841 1842 fwreq->items[BRCMF_PCIE_FW_CODE].type = BRCMF_FW_TYPE_BINARY; 1843 fwreq->items[BRCMF_PCIE_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM; 1844 fwreq->items[BRCMF_PCIE_FW_NVRAM].flags = BRCMF_FW_REQF_OPTIONAL; 1845 fwreq->board_type = devinfo->settings->board_type; 1846 /* NVRAM reserves PCI domain 0 for Broadcom's SDK faked bus */ 1847 fwreq->domain_nr = pci_domain_nr(devinfo->pdev->bus) + 1; 1848 fwreq->bus_nr = devinfo->pdev->bus->number; 1849 1850 return fwreq; 1851 } 1852 1853 static int 1854 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1855 { 1856 int ret; 1857 struct brcmf_fw_request *fwreq; 1858 struct brcmf_pciedev_info *devinfo; 1859 struct brcmf_pciedev *pcie_bus_dev; 1860 struct brcmf_bus *bus; 1861 1862 brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device); 1863 1864 ret = -ENOMEM; 1865 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL); 1866 if (devinfo == NULL) 1867 return ret; 1868 1869 devinfo->pdev = pdev; 1870 pcie_bus_dev = NULL; 1871 devinfo->ci = brcmf_chip_attach(devinfo, pdev->device, 1872 &brcmf_pcie_buscore_ops); 1873 if (IS_ERR(devinfo->ci)) { 1874 ret = PTR_ERR(devinfo->ci); 1875 devinfo->ci = NULL; 1876 goto fail; 1877 } 1878 1879 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL); 1880 if (pcie_bus_dev == NULL) { 1881 ret = -ENOMEM; 1882 goto fail; 1883 } 1884 1885 devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev, 1886 BRCMF_BUSTYPE_PCIE, 1887 devinfo->ci->chip, 1888 devinfo->ci->chiprev); 1889 if (!devinfo->settings) { 1890 ret = -ENOMEM; 1891 goto fail; 1892 } 1893 1894 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 1895 if (!bus) { 1896 ret = -ENOMEM; 1897 goto fail; 1898 } 1899 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL); 1900 if (!bus->msgbuf) { 1901 ret = -ENOMEM; 1902 kfree(bus); 1903 goto fail; 1904 } 1905 1906 /* hook it all together. */ 1907 pcie_bus_dev->devinfo = devinfo; 1908 pcie_bus_dev->bus = bus; 1909 bus->dev = &pdev->dev; 1910 bus->bus_priv.pcie = pcie_bus_dev; 1911 bus->ops = &brcmf_pcie_bus_ops; 1912 bus->proto_type = BRCMF_PROTO_MSGBUF; 1913 bus->chip = devinfo->coreid; 1914 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot); 1915 dev_set_drvdata(&pdev->dev, bus); 1916 1917 ret = brcmf_alloc(&devinfo->pdev->dev, devinfo->settings); 1918 if (ret) 1919 goto fail_bus; 1920 1921 fwreq = brcmf_pcie_prepare_fw_request(devinfo); 1922 if (!fwreq) { 1923 ret = -ENOMEM; 1924 goto fail_brcmf; 1925 } 1926 1927 ret = brcmf_fw_get_firmwares(bus->dev, fwreq, brcmf_pcie_setup); 1928 if (ret < 0) { 1929 kfree(fwreq); 1930 goto fail_brcmf; 1931 } 1932 return 0; 1933 1934 fail_brcmf: 1935 brcmf_free(&devinfo->pdev->dev); 1936 fail_bus: 1937 kfree(bus->msgbuf); 1938 kfree(bus); 1939 fail: 1940 brcmf_err(NULL, "failed %x:%x\n", pdev->vendor, pdev->device); 1941 brcmf_pcie_release_resource(devinfo); 1942 if (devinfo->ci) 1943 brcmf_chip_detach(devinfo->ci); 1944 if (devinfo->settings) 1945 brcmf_release_module_param(devinfo->settings); 1946 kfree(pcie_bus_dev); 1947 kfree(devinfo); 1948 return ret; 1949 } 1950 1951 1952 static void 1953 brcmf_pcie_remove(struct pci_dev *pdev) 1954 { 1955 struct brcmf_pciedev_info *devinfo; 1956 struct brcmf_bus *bus; 1957 1958 brcmf_dbg(PCIE, "Enter\n"); 1959 1960 bus = dev_get_drvdata(&pdev->dev); 1961 if (bus == NULL) 1962 return; 1963 1964 devinfo = bus->bus_priv.pcie->devinfo; 1965 brcmf_pcie_bus_console_read(devinfo, false); 1966 1967 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 1968 if (devinfo->ci) 1969 brcmf_pcie_intr_disable(devinfo); 1970 1971 brcmf_detach(&pdev->dev); 1972 brcmf_free(&pdev->dev); 1973 1974 kfree(bus->bus_priv.pcie); 1975 kfree(bus->msgbuf->flowrings); 1976 kfree(bus->msgbuf); 1977 kfree(bus); 1978 1979 brcmf_pcie_release_irq(devinfo); 1980 brcmf_pcie_release_scratchbuffers(devinfo); 1981 brcmf_pcie_release_ringbuffers(devinfo); 1982 brcmf_pcie_reset_device(devinfo); 1983 brcmf_pcie_release_resource(devinfo); 1984 1985 if (devinfo->ci) 1986 brcmf_chip_detach(devinfo->ci); 1987 if (devinfo->settings) 1988 brcmf_release_module_param(devinfo->settings); 1989 1990 kfree(devinfo); 1991 dev_set_drvdata(&pdev->dev, NULL); 1992 } 1993 1994 1995 #ifdef CONFIG_PM 1996 1997 1998 static int brcmf_pcie_pm_enter_D3(struct device *dev) 1999 { 2000 struct brcmf_pciedev_info *devinfo; 2001 struct brcmf_bus *bus; 2002 2003 brcmf_dbg(PCIE, "Enter\n"); 2004 2005 bus = dev_get_drvdata(dev); 2006 devinfo = bus->bus_priv.pcie->devinfo; 2007 2008 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN); 2009 2010 devinfo->mbdata_completed = false; 2011 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM); 2012 2013 wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed, 2014 BRCMF_PCIE_MBDATA_TIMEOUT); 2015 if (!devinfo->mbdata_completed) { 2016 brcmf_err(bus, "Timeout on response for entering D3 substate\n"); 2017 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 2018 return -EIO; 2019 } 2020 2021 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 2022 2023 return 0; 2024 } 2025 2026 2027 static int brcmf_pcie_pm_leave_D3(struct device *dev) 2028 { 2029 struct brcmf_pciedev_info *devinfo; 2030 struct brcmf_bus *bus; 2031 struct pci_dev *pdev; 2032 int err; 2033 2034 brcmf_dbg(PCIE, "Enter\n"); 2035 2036 bus = dev_get_drvdata(dev); 2037 devinfo = bus->bus_priv.pcie->devinfo; 2038 brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus); 2039 2040 /* Check if device is still up and running, if so we are ready */ 2041 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0) { 2042 brcmf_dbg(PCIE, "Try to wakeup device....\n"); 2043 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM)) 2044 goto cleanup; 2045 brcmf_dbg(PCIE, "Hot resume, continue....\n"); 2046 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 2047 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 2048 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 2049 brcmf_pcie_intr_enable(devinfo); 2050 brcmf_pcie_hostready(devinfo); 2051 return 0; 2052 } 2053 2054 cleanup: 2055 brcmf_chip_detach(devinfo->ci); 2056 devinfo->ci = NULL; 2057 pdev = devinfo->pdev; 2058 brcmf_pcie_remove(pdev); 2059 2060 err = brcmf_pcie_probe(pdev, NULL); 2061 if (err) 2062 __brcmf_err(NULL, __func__, "probe after resume failed, err=%d\n", err); 2063 2064 return err; 2065 } 2066 2067 2068 static const struct dev_pm_ops brcmf_pciedrvr_pm = { 2069 .suspend = brcmf_pcie_pm_enter_D3, 2070 .resume = brcmf_pcie_pm_leave_D3, 2071 .freeze = brcmf_pcie_pm_enter_D3, 2072 .restore = brcmf_pcie_pm_leave_D3, 2073 }; 2074 2075 2076 #endif /* CONFIG_PM */ 2077 2078 2079 #define BRCMF_PCIE_DEVICE(dev_id) { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\ 2080 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 } 2081 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev) { \ 2082 BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\ 2083 subvend, subdev, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 } 2084 2085 static const struct pci_device_id brcmf_pcie_devid_table[] = { 2086 BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID), 2087 BRCMF_PCIE_DEVICE_SUB(0x4355, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4355), 2088 BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_RAW_DEVICE_ID), 2089 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID), 2090 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID), 2091 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID), 2092 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_RAW_DEVICE_ID), 2093 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID), 2094 BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID), 2095 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID), 2096 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID), 2097 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID), 2098 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID), 2099 BRCMF_PCIE_DEVICE(BRCM_PCIE_4364_DEVICE_ID), 2100 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID), 2101 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID), 2102 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID), 2103 BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365), 2104 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID), 2105 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID), 2106 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID), 2107 BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID), 2108 { /* end: all zeroes */ } 2109 }; 2110 2111 2112 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table); 2113 2114 2115 static struct pci_driver brcmf_pciedrvr = { 2116 .node = {}, 2117 .name = KBUILD_MODNAME, 2118 .id_table = brcmf_pcie_devid_table, 2119 .probe = brcmf_pcie_probe, 2120 .remove = brcmf_pcie_remove, 2121 #ifdef CONFIG_PM 2122 .driver.pm = &brcmf_pciedrvr_pm, 2123 #endif 2124 .driver.coredump = brcmf_dev_coredump, 2125 }; 2126 2127 2128 int brcmf_pcie_register(void) 2129 { 2130 brcmf_dbg(PCIE, "Enter\n"); 2131 return pci_register_driver(&brcmf_pciedrvr); 2132 } 2133 2134 2135 void brcmf_pcie_exit(void) 2136 { 2137 brcmf_dbg(PCIE, "Enter\n"); 2138 pci_unregister_driver(&brcmf_pciedrvr); 2139 } 2140