1 /* Copyright (c) 2014 Broadcom Corporation 2 * 3 * Permission to use, copy, modify, and/or distribute this software for any 4 * purpose with or without fee is hereby granted, provided that the above 5 * copyright notice and this permission notice appear in all copies. 6 * 7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 10 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 12 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 13 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/firmware.h> 19 #include <linux/pci.h> 20 #include <linux/vmalloc.h> 21 #include <linux/delay.h> 22 #include <linux/interrupt.h> 23 #include <linux/bcma/bcma.h> 24 #include <linux/sched.h> 25 #include <asm/unaligned.h> 26 27 #include <soc.h> 28 #include <chipcommon.h> 29 #include <brcmu_utils.h> 30 #include <brcmu_wifi.h> 31 #include <brcm_hw_ids.h> 32 33 #include "debug.h" 34 #include "bus.h" 35 #include "commonring.h" 36 #include "msgbuf.h" 37 #include "pcie.h" 38 #include "firmware.h" 39 #include "chip.h" 40 #include "core.h" 41 #include "common.h" 42 43 44 enum brcmf_pcie_state { 45 BRCMFMAC_PCIE_STATE_DOWN, 46 BRCMFMAC_PCIE_STATE_UP 47 }; 48 49 BRCMF_FW_NVRAM_DEF(43602, "brcmfmac43602-pcie.bin", "brcmfmac43602-pcie.txt"); 50 BRCMF_FW_NVRAM_DEF(4350, "brcmfmac4350-pcie.bin", "brcmfmac4350-pcie.txt"); 51 BRCMF_FW_NVRAM_DEF(4350C, "brcmfmac4350c2-pcie.bin", "brcmfmac4350c2-pcie.txt"); 52 BRCMF_FW_NVRAM_DEF(4356, "brcmfmac4356-pcie.bin", "brcmfmac4356-pcie.txt"); 53 BRCMF_FW_NVRAM_DEF(43570, "brcmfmac43570-pcie.bin", "brcmfmac43570-pcie.txt"); 54 BRCMF_FW_NVRAM_DEF(4358, "brcmfmac4358-pcie.bin", "brcmfmac4358-pcie.txt"); 55 BRCMF_FW_NVRAM_DEF(4359, "brcmfmac4359-pcie.bin", "brcmfmac4359-pcie.txt"); 56 BRCMF_FW_NVRAM_DEF(4365B, "brcmfmac4365b-pcie.bin", "brcmfmac4365b-pcie.txt"); 57 BRCMF_FW_NVRAM_DEF(4366B, "brcmfmac4366b-pcie.bin", "brcmfmac4366b-pcie.txt"); 58 BRCMF_FW_NVRAM_DEF(4366C, "brcmfmac4366c-pcie.bin", "brcmfmac4366c-pcie.txt"); 59 BRCMF_FW_NVRAM_DEF(4371, "brcmfmac4371-pcie.bin", "brcmfmac4371-pcie.txt"); 60 61 static struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = { 62 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602), 63 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C), 64 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350), 65 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 66 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570), 67 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570), 68 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570), 69 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358), 70 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359), 71 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFFF, 4365B), 72 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B), 73 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C), 74 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371), 75 }; 76 77 #define BRCMF_PCIE_FW_UP_TIMEOUT 2000 /* msec */ 78 79 #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024) 80 81 /* backplane addres space accessed by BAR0 */ 82 #define BRCMF_PCIE_BAR0_WINDOW 0x80 83 #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000 84 #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70 85 86 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000 87 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000 88 89 #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40 90 #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C 91 92 #define BRCMF_PCIE_REG_INTSTATUS 0x90 93 #define BRCMF_PCIE_REG_INTMASK 0x94 94 #define BRCMF_PCIE_REG_SBMBX 0x98 95 96 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC 97 98 #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24 99 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48 100 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C 101 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120 102 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124 103 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX 0x140 104 105 #define BRCMF_PCIE2_INTA 0x01 106 #define BRCMF_PCIE2_INTB 0x02 107 108 #define BRCMF_PCIE_INT_0 0x01 109 #define BRCMF_PCIE_INT_1 0x02 110 #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \ 111 BRCMF_PCIE_INT_1) 112 113 #define BRCMF_PCIE_MB_INT_FN0_0 0x0100 114 #define BRCMF_PCIE_MB_INT_FN0_1 0x0200 115 #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000 116 #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000 117 #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000 118 #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000 119 #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000 120 #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000 121 #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000 122 #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000 123 124 #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \ 125 BRCMF_PCIE_MB_INT_D2H0_DB1 | \ 126 BRCMF_PCIE_MB_INT_D2H1_DB0 | \ 127 BRCMF_PCIE_MB_INT_D2H1_DB1 | \ 128 BRCMF_PCIE_MB_INT_D2H2_DB0 | \ 129 BRCMF_PCIE_MB_INT_D2H2_DB1 | \ 130 BRCMF_PCIE_MB_INT_D2H3_DB0 | \ 131 BRCMF_PCIE_MB_INT_D2H3_DB1) 132 133 #define BRCMF_PCIE_MIN_SHARED_VERSION 5 134 #define BRCMF_PCIE_MAX_SHARED_VERSION 5 135 #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF 136 #define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000 137 #define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000 138 139 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000 140 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000 141 142 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34 143 #define BRCMF_SHARED_RING_BASE_OFFSET 52 144 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36 145 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20 146 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40 147 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44 148 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48 149 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52 150 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56 151 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64 152 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68 153 154 #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0 155 #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1 156 #define BRCMF_RING_H2D_RING_MEM_OFFSET 4 157 #define BRCMF_RING_H2D_RING_STATE_OFFSET 8 158 159 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8 160 #define BRCMF_RING_MAX_ITEM_OFFSET 4 161 #define BRCMF_RING_LEN_ITEMS_OFFSET 6 162 #define BRCMF_RING_MEM_SZ 16 163 #define BRCMF_RING_STATE_SZ 8 164 165 #define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET 4 166 #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET 8 167 #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET 12 168 #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET 16 169 #define BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET 20 170 #define BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET 28 171 #define BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET 36 172 #define BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET 44 173 #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET 0 174 #define BRCMF_SHARED_RING_MAX_SUB_QUEUES 52 175 176 #define BRCMF_DEF_MAX_RXBUFPOST 255 177 178 #define BRCMF_CONSOLE_BUFADDR_OFFSET 8 179 #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12 180 #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16 181 182 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8 183 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024 184 185 #define BRCMF_D2H_DEV_D3_ACK 0x00000001 186 #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002 187 #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004 188 189 #define BRCMF_H2D_HOST_D3_INFORM 0x00000001 190 #define BRCMF_H2D_HOST_DS_ACK 0x00000002 191 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008 192 #define BRCMF_H2D_HOST_D0_INFORM 0x00000010 193 194 #define BRCMF_PCIE_MBDATA_TIMEOUT msecs_to_jiffies(2000) 195 196 #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4 197 #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C 198 #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58 199 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C 200 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60 201 #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64 202 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC 203 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC 204 #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228 205 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248 206 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0 207 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4 208 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3 209 210 /* Magic number at a magic location to find RAM size */ 211 #define BRCMF_RAMSIZE_MAGIC 0x534d4152 /* SMAR */ 212 #define BRCMF_RAMSIZE_OFFSET 0x6c 213 214 215 struct brcmf_pcie_console { 216 u32 base_addr; 217 u32 buf_addr; 218 u32 bufsize; 219 u32 read_idx; 220 u8 log_str[256]; 221 u8 log_idx; 222 }; 223 224 struct brcmf_pcie_shared_info { 225 u32 tcm_base_address; 226 u32 flags; 227 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS]; 228 struct brcmf_pcie_ringbuf *flowrings; 229 u16 max_rxbufpost; 230 u32 nrof_flowrings; 231 u32 rx_dataoffset; 232 u32 htod_mb_data_addr; 233 u32 dtoh_mb_data_addr; 234 u32 ring_info_addr; 235 struct brcmf_pcie_console console; 236 void *scratch; 237 dma_addr_t scratch_dmahandle; 238 void *ringupd; 239 dma_addr_t ringupd_dmahandle; 240 }; 241 242 struct brcmf_pcie_core_info { 243 u32 base; 244 u32 wrapbase; 245 }; 246 247 struct brcmf_pciedev_info { 248 enum brcmf_pcie_state state; 249 bool in_irq; 250 struct pci_dev *pdev; 251 char fw_name[BRCMF_FW_NAME_LEN]; 252 char nvram_name[BRCMF_FW_NAME_LEN]; 253 void __iomem *regs; 254 void __iomem *tcm; 255 u32 ram_base; 256 u32 ram_size; 257 struct brcmf_chip *ci; 258 u32 coreid; 259 struct brcmf_pcie_shared_info shared; 260 wait_queue_head_t mbdata_resp_wait; 261 bool mbdata_completed; 262 bool irq_allocated; 263 bool wowl_enabled; 264 u8 dma_idx_sz; 265 void *idxbuf; 266 u32 idxbuf_sz; 267 dma_addr_t idxbuf_dmahandle; 268 u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset); 269 void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 270 u16 value); 271 struct brcmf_mp_device *settings; 272 }; 273 274 struct brcmf_pcie_ringbuf { 275 struct brcmf_commonring commonring; 276 dma_addr_t dma_handle; 277 u32 w_idx_addr; 278 u32 r_idx_addr; 279 struct brcmf_pciedev_info *devinfo; 280 u8 id; 281 }; 282 283 284 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = { 285 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM, 286 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM, 287 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM, 288 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM, 289 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM 290 }; 291 292 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = { 293 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 294 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 295 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 296 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE, 297 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE 298 }; 299 300 301 static u32 302 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset) 303 { 304 void __iomem *address = devinfo->regs + reg_offset; 305 306 return (ioread32(address)); 307 } 308 309 310 static void 311 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset, 312 u32 value) 313 { 314 void __iomem *address = devinfo->regs + reg_offset; 315 316 iowrite32(value, address); 317 } 318 319 320 static u8 321 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 322 { 323 void __iomem *address = devinfo->tcm + mem_offset; 324 325 return (ioread8(address)); 326 } 327 328 329 static u16 330 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 331 { 332 void __iomem *address = devinfo->tcm + mem_offset; 333 334 return (ioread16(address)); 335 } 336 337 338 static void 339 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 340 u16 value) 341 { 342 void __iomem *address = devinfo->tcm + mem_offset; 343 344 iowrite16(value, address); 345 } 346 347 348 static u16 349 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 350 { 351 u16 *address = devinfo->idxbuf + mem_offset; 352 353 return (*(address)); 354 } 355 356 357 static void 358 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 359 u16 value) 360 { 361 u16 *address = devinfo->idxbuf + mem_offset; 362 363 *(address) = value; 364 } 365 366 367 static u32 368 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 369 { 370 void __iomem *address = devinfo->tcm + mem_offset; 371 372 return (ioread32(address)); 373 } 374 375 376 static void 377 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 378 u32 value) 379 { 380 void __iomem *address = devinfo->tcm + mem_offset; 381 382 iowrite32(value, address); 383 } 384 385 386 static u32 387 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 388 { 389 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 390 391 return (ioread32(addr)); 392 } 393 394 395 static void 396 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 397 u32 value) 398 { 399 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 400 401 iowrite32(value, addr); 402 } 403 404 405 static void 406 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 407 void *srcaddr, u32 len) 408 { 409 void __iomem *address = devinfo->tcm + mem_offset; 410 __le32 *src32; 411 __le16 *src16; 412 u8 *src8; 413 414 if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) { 415 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) { 416 src8 = (u8 *)srcaddr; 417 while (len) { 418 iowrite8(*src8, address); 419 address++; 420 src8++; 421 len--; 422 } 423 } else { 424 len = len / 2; 425 src16 = (__le16 *)srcaddr; 426 while (len) { 427 iowrite16(le16_to_cpu(*src16), address); 428 address += 2; 429 src16++; 430 len--; 431 } 432 } 433 } else { 434 len = len / 4; 435 src32 = (__le32 *)srcaddr; 436 while (len) { 437 iowrite32(le32_to_cpu(*src32), address); 438 address += 4; 439 src32++; 440 len--; 441 } 442 } 443 } 444 445 446 static void 447 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 448 void *dstaddr, u32 len) 449 { 450 void __iomem *address = devinfo->tcm + mem_offset; 451 __le32 *dst32; 452 __le16 *dst16; 453 u8 *dst8; 454 455 if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) { 456 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) { 457 dst8 = (u8 *)dstaddr; 458 while (len) { 459 *dst8 = ioread8(address); 460 address++; 461 dst8++; 462 len--; 463 } 464 } else { 465 len = len / 2; 466 dst16 = (__le16 *)dstaddr; 467 while (len) { 468 *dst16 = cpu_to_le16(ioread16(address)); 469 address += 2; 470 dst16++; 471 len--; 472 } 473 } 474 } else { 475 len = len / 4; 476 dst32 = (__le32 *)dstaddr; 477 while (len) { 478 *dst32 = cpu_to_le32(ioread32(address)); 479 address += 4; 480 dst32++; 481 len--; 482 } 483 } 484 } 485 486 487 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \ 488 CHIPCREGOFFS(reg), value) 489 490 491 static void 492 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid) 493 { 494 const struct pci_dev *pdev = devinfo->pdev; 495 struct brcmf_core *core; 496 u32 bar0_win; 497 498 core = brcmf_chip_get_core(devinfo->ci, coreid); 499 if (core) { 500 bar0_win = core->base; 501 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win); 502 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, 503 &bar0_win) == 0) { 504 if (bar0_win != core->base) { 505 bar0_win = core->base; 506 pci_write_config_dword(pdev, 507 BRCMF_PCIE_BAR0_WINDOW, 508 bar0_win); 509 } 510 } 511 } else { 512 brcmf_err("Unsupported core selected %x\n", coreid); 513 } 514 } 515 516 517 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo) 518 { 519 struct brcmf_core *core; 520 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD, 521 BRCMF_PCIE_CFGREG_PM_CSR, 522 BRCMF_PCIE_CFGREG_MSI_CAP, 523 BRCMF_PCIE_CFGREG_MSI_ADDR_L, 524 BRCMF_PCIE_CFGREG_MSI_ADDR_H, 525 BRCMF_PCIE_CFGREG_MSI_DATA, 526 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2, 527 BRCMF_PCIE_CFGREG_RBAR_CTRL, 528 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1, 529 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG, 530 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG }; 531 u32 i; 532 u32 val; 533 u32 lsc; 534 535 if (!devinfo->ci) 536 return; 537 538 /* Disable ASPM */ 539 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 540 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 541 &lsc); 542 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB); 543 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 544 val); 545 546 /* Watchdog reset */ 547 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON); 548 WRITECC32(devinfo, watchdog, 4); 549 msleep(100); 550 551 /* Restore ASPM */ 552 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 553 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 554 lsc); 555 556 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 557 if (core->rev <= 13) { 558 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) { 559 brcmf_pcie_write_reg32(devinfo, 560 BRCMF_PCIE_PCIE2REG_CONFIGADDR, 561 cfg_offset[i]); 562 val = brcmf_pcie_read_reg32(devinfo, 563 BRCMF_PCIE_PCIE2REG_CONFIGDATA); 564 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n", 565 cfg_offset[i], val); 566 brcmf_pcie_write_reg32(devinfo, 567 BRCMF_PCIE_PCIE2REG_CONFIGDATA, 568 val); 569 } 570 } 571 } 572 573 574 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo) 575 { 576 u32 config; 577 578 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 579 /* BAR1 window may not be sized properly */ 580 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 581 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0); 582 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA); 583 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config); 584 585 device_wakeup_enable(&devinfo->pdev->dev); 586 } 587 588 589 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo) 590 { 591 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 592 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4); 593 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 594 5); 595 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 596 0); 597 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 598 7); 599 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 600 0); 601 } 602 return 0; 603 } 604 605 606 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo, 607 u32 resetintr) 608 { 609 struct brcmf_core *core; 610 611 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 612 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM); 613 brcmf_chip_resetcore(core, 0, 0, 0); 614 } 615 616 if (!brcmf_chip_set_active(devinfo->ci, resetintr)) 617 return -EINVAL; 618 return 0; 619 } 620 621 622 static int 623 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data) 624 { 625 struct brcmf_pcie_shared_info *shared; 626 u32 addr; 627 u32 cur_htod_mb_data; 628 u32 i; 629 630 shared = &devinfo->shared; 631 addr = shared->htod_mb_data_addr; 632 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 633 634 if (cur_htod_mb_data != 0) 635 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n", 636 cur_htod_mb_data); 637 638 i = 0; 639 while (cur_htod_mb_data != 0) { 640 msleep(10); 641 i++; 642 if (i > 100) 643 return -EIO; 644 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 645 } 646 647 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data); 648 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 649 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 650 651 return 0; 652 } 653 654 655 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo) 656 { 657 struct brcmf_pcie_shared_info *shared; 658 u32 addr; 659 u32 dtoh_mb_data; 660 661 shared = &devinfo->shared; 662 addr = shared->dtoh_mb_data_addr; 663 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 664 665 if (!dtoh_mb_data) 666 return; 667 668 brcmf_pcie_write_tcm32(devinfo, addr, 0); 669 670 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data); 671 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) { 672 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n"); 673 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK); 674 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n"); 675 } 676 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE) 677 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n"); 678 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) { 679 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n"); 680 devinfo->mbdata_completed = true; 681 wake_up(&devinfo->mbdata_resp_wait); 682 } 683 } 684 685 686 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo) 687 { 688 struct brcmf_pcie_shared_info *shared; 689 struct brcmf_pcie_console *console; 690 u32 addr; 691 692 shared = &devinfo->shared; 693 console = &shared->console; 694 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET; 695 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr); 696 697 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET; 698 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr); 699 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET; 700 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr); 701 702 brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n", 703 console->base_addr, console->buf_addr, console->bufsize); 704 } 705 706 707 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo) 708 { 709 struct brcmf_pcie_console *console; 710 u32 addr; 711 u8 ch; 712 u32 newidx; 713 714 if (!BRCMF_FWCON_ON()) 715 return; 716 717 console = &devinfo->shared.console; 718 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET; 719 newidx = brcmf_pcie_read_tcm32(devinfo, addr); 720 while (newidx != console->read_idx) { 721 addr = console->buf_addr + console->read_idx; 722 ch = brcmf_pcie_read_tcm8(devinfo, addr); 723 console->read_idx++; 724 if (console->read_idx == console->bufsize) 725 console->read_idx = 0; 726 if (ch == '\r') 727 continue; 728 console->log_str[console->log_idx] = ch; 729 console->log_idx++; 730 if ((ch != '\n') && 731 (console->log_idx == (sizeof(console->log_str) - 2))) { 732 ch = '\n'; 733 console->log_str[console->log_idx] = ch; 734 console->log_idx++; 735 } 736 if (ch == '\n') { 737 console->log_str[console->log_idx] = 0; 738 pr_debug("CONSOLE: %s", console->log_str); 739 console->log_idx = 0; 740 } 741 } 742 } 743 744 745 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo) 746 { 747 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 0); 748 } 749 750 751 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo) 752 { 753 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 754 BRCMF_PCIE_MB_INT_D2H_DB | 755 BRCMF_PCIE_MB_INT_FN0_0 | 756 BRCMF_PCIE_MB_INT_FN0_1); 757 } 758 759 760 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg) 761 { 762 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 763 764 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) { 765 brcmf_pcie_intr_disable(devinfo); 766 brcmf_dbg(PCIE, "Enter\n"); 767 return IRQ_WAKE_THREAD; 768 } 769 return IRQ_NONE; 770 } 771 772 773 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg) 774 { 775 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 776 u32 status; 777 778 devinfo->in_irq = true; 779 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 780 brcmf_dbg(PCIE, "Enter %x\n", status); 781 if (status) { 782 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, 783 status); 784 if (status & (BRCMF_PCIE_MB_INT_FN0_0 | 785 BRCMF_PCIE_MB_INT_FN0_1)) 786 brcmf_pcie_handle_mb_data(devinfo); 787 if (status & BRCMF_PCIE_MB_INT_D2H_DB) { 788 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 789 brcmf_proto_msgbuf_rx_trigger( 790 &devinfo->pdev->dev); 791 } 792 } 793 brcmf_pcie_bus_console_read(devinfo); 794 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 795 brcmf_pcie_intr_enable(devinfo); 796 devinfo->in_irq = false; 797 return IRQ_HANDLED; 798 } 799 800 801 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo) 802 { 803 struct pci_dev *pdev; 804 805 pdev = devinfo->pdev; 806 807 brcmf_pcie_intr_disable(devinfo); 808 809 brcmf_dbg(PCIE, "Enter\n"); 810 811 pci_enable_msi(pdev); 812 if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr, 813 brcmf_pcie_isr_thread, IRQF_SHARED, 814 "brcmf_pcie_intr", devinfo)) { 815 pci_disable_msi(pdev); 816 brcmf_err("Failed to request IRQ %d\n", pdev->irq); 817 return -EIO; 818 } 819 devinfo->irq_allocated = true; 820 return 0; 821 } 822 823 824 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo) 825 { 826 struct pci_dev *pdev; 827 u32 status; 828 u32 count; 829 830 if (!devinfo->irq_allocated) 831 return; 832 833 pdev = devinfo->pdev; 834 835 brcmf_pcie_intr_disable(devinfo); 836 free_irq(pdev->irq, devinfo); 837 pci_disable_msi(pdev); 838 839 msleep(50); 840 count = 0; 841 while ((devinfo->in_irq) && (count < 20)) { 842 msleep(50); 843 count++; 844 } 845 if (devinfo->in_irq) 846 brcmf_err("Still in IRQ (processing) !!!\n"); 847 848 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 849 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, status); 850 851 devinfo->irq_allocated = false; 852 } 853 854 855 static int brcmf_pcie_ring_mb_write_rptr(void *ctx) 856 { 857 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 858 struct brcmf_pciedev_info *devinfo = ring->devinfo; 859 struct brcmf_commonring *commonring = &ring->commonring; 860 861 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 862 return -EIO; 863 864 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr, 865 commonring->w_ptr, ring->id); 866 867 devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr); 868 869 return 0; 870 } 871 872 873 static int brcmf_pcie_ring_mb_write_wptr(void *ctx) 874 { 875 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 876 struct brcmf_pciedev_info *devinfo = ring->devinfo; 877 struct brcmf_commonring *commonring = &ring->commonring; 878 879 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 880 return -EIO; 881 882 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr, 883 commonring->r_ptr, ring->id); 884 885 devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr); 886 887 return 0; 888 } 889 890 891 static int brcmf_pcie_ring_mb_ring_bell(void *ctx) 892 { 893 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 894 struct brcmf_pciedev_info *devinfo = ring->devinfo; 895 896 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 897 return -EIO; 898 899 brcmf_dbg(PCIE, "RING !\n"); 900 /* Any arbitrary value will do, lets use 1 */ 901 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1); 902 903 return 0; 904 } 905 906 907 static int brcmf_pcie_ring_mb_update_rptr(void *ctx) 908 { 909 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 910 struct brcmf_pciedev_info *devinfo = ring->devinfo; 911 struct brcmf_commonring *commonring = &ring->commonring; 912 913 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 914 return -EIO; 915 916 commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr); 917 918 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr, 919 commonring->w_ptr, ring->id); 920 921 return 0; 922 } 923 924 925 static int brcmf_pcie_ring_mb_update_wptr(void *ctx) 926 { 927 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 928 struct brcmf_pciedev_info *devinfo = ring->devinfo; 929 struct brcmf_commonring *commonring = &ring->commonring; 930 931 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 932 return -EIO; 933 934 commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr); 935 936 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr, 937 commonring->r_ptr, ring->id); 938 939 return 0; 940 } 941 942 943 static void * 944 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo, 945 u32 size, u32 tcm_dma_phys_addr, 946 dma_addr_t *dma_handle) 947 { 948 void *ring; 949 u64 address; 950 951 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle, 952 GFP_KERNEL); 953 if (!ring) 954 return NULL; 955 956 address = (u64)*dma_handle; 957 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr, 958 address & 0xffffffff); 959 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32); 960 961 memset(ring, 0, size); 962 963 return (ring); 964 } 965 966 967 static struct brcmf_pcie_ringbuf * 968 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id, 969 u32 tcm_ring_phys_addr) 970 { 971 void *dma_buf; 972 dma_addr_t dma_handle; 973 struct brcmf_pcie_ringbuf *ring; 974 u32 size; 975 u32 addr; 976 977 size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id]; 978 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size, 979 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET, 980 &dma_handle); 981 if (!dma_buf) 982 return NULL; 983 984 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET; 985 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]); 986 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET; 987 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]); 988 989 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 990 if (!ring) { 991 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf, 992 dma_handle); 993 return NULL; 994 } 995 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id], 996 brcmf_ring_itemsize[ring_id], dma_buf); 997 ring->dma_handle = dma_handle; 998 ring->devinfo = devinfo; 999 brcmf_commonring_register_cb(&ring->commonring, 1000 brcmf_pcie_ring_mb_ring_bell, 1001 brcmf_pcie_ring_mb_update_rptr, 1002 brcmf_pcie_ring_mb_update_wptr, 1003 brcmf_pcie_ring_mb_write_rptr, 1004 brcmf_pcie_ring_mb_write_wptr, ring); 1005 1006 return (ring); 1007 } 1008 1009 1010 static void brcmf_pcie_release_ringbuffer(struct device *dev, 1011 struct brcmf_pcie_ringbuf *ring) 1012 { 1013 void *dma_buf; 1014 u32 size; 1015 1016 if (!ring) 1017 return; 1018 1019 dma_buf = ring->commonring.buf_addr; 1020 if (dma_buf) { 1021 size = ring->commonring.depth * ring->commonring.item_len; 1022 dma_free_coherent(dev, size, dma_buf, ring->dma_handle); 1023 } 1024 kfree(ring); 1025 } 1026 1027 1028 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo) 1029 { 1030 u32 i; 1031 1032 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1033 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev, 1034 devinfo->shared.commonrings[i]); 1035 devinfo->shared.commonrings[i] = NULL; 1036 } 1037 kfree(devinfo->shared.flowrings); 1038 devinfo->shared.flowrings = NULL; 1039 if (devinfo->idxbuf) { 1040 dma_free_coherent(&devinfo->pdev->dev, 1041 devinfo->idxbuf_sz, 1042 devinfo->idxbuf, 1043 devinfo->idxbuf_dmahandle); 1044 devinfo->idxbuf = NULL; 1045 } 1046 } 1047 1048 1049 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo) 1050 { 1051 struct brcmf_pcie_ringbuf *ring; 1052 struct brcmf_pcie_ringbuf *rings; 1053 u32 ring_addr; 1054 u32 d2h_w_idx_ptr; 1055 u32 d2h_r_idx_ptr; 1056 u32 h2d_w_idx_ptr; 1057 u32 h2d_r_idx_ptr; 1058 u32 addr; 1059 u32 ring_mem_ptr; 1060 u32 i; 1061 u64 address; 1062 u32 bufsz; 1063 u16 max_sub_queues; 1064 u8 idx_offset; 1065 1066 ring_addr = devinfo->shared.ring_info_addr; 1067 brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr); 1068 addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES; 1069 max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr); 1070 1071 if (devinfo->dma_idx_sz != 0) { 1072 bufsz = (BRCMF_NROF_D2H_COMMON_MSGRINGS + max_sub_queues) * 1073 devinfo->dma_idx_sz * 2; 1074 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz, 1075 &devinfo->idxbuf_dmahandle, 1076 GFP_KERNEL); 1077 if (!devinfo->idxbuf) 1078 devinfo->dma_idx_sz = 0; 1079 } 1080 1081 if (devinfo->dma_idx_sz == 0) { 1082 addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET; 1083 d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr); 1084 addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET; 1085 d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr); 1086 addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET; 1087 h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr); 1088 addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET; 1089 h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr); 1090 idx_offset = sizeof(u32); 1091 devinfo->write_ptr = brcmf_pcie_write_tcm16; 1092 devinfo->read_ptr = brcmf_pcie_read_tcm16; 1093 brcmf_dbg(PCIE, "Using TCM indices\n"); 1094 } else { 1095 memset(devinfo->idxbuf, 0, bufsz); 1096 devinfo->idxbuf_sz = bufsz; 1097 idx_offset = devinfo->dma_idx_sz; 1098 devinfo->write_ptr = brcmf_pcie_write_idx; 1099 devinfo->read_ptr = brcmf_pcie_read_idx; 1100 1101 h2d_w_idx_ptr = 0; 1102 addr = ring_addr + BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET; 1103 address = (u64)devinfo->idxbuf_dmahandle; 1104 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1105 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1106 1107 h2d_r_idx_ptr = h2d_w_idx_ptr + max_sub_queues * idx_offset; 1108 addr = ring_addr + BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET; 1109 address += max_sub_queues * idx_offset; 1110 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1111 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1112 1113 d2h_w_idx_ptr = h2d_r_idx_ptr + max_sub_queues * idx_offset; 1114 addr = ring_addr + BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET; 1115 address += max_sub_queues * idx_offset; 1116 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1117 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1118 1119 d2h_r_idx_ptr = d2h_w_idx_ptr + 1120 BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset; 1121 addr = ring_addr + BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET; 1122 address += BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset; 1123 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1124 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1125 brcmf_dbg(PCIE, "Using host memory indices\n"); 1126 } 1127 1128 addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET; 1129 ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr); 1130 1131 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) { 1132 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1133 if (!ring) 1134 goto fail; 1135 ring->w_idx_addr = h2d_w_idx_ptr; 1136 ring->r_idx_addr = h2d_r_idx_ptr; 1137 ring->id = i; 1138 devinfo->shared.commonrings[i] = ring; 1139 1140 h2d_w_idx_ptr += idx_offset; 1141 h2d_r_idx_ptr += idx_offset; 1142 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1143 } 1144 1145 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS; 1146 i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1147 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1148 if (!ring) 1149 goto fail; 1150 ring->w_idx_addr = d2h_w_idx_ptr; 1151 ring->r_idx_addr = d2h_r_idx_ptr; 1152 ring->id = i; 1153 devinfo->shared.commonrings[i] = ring; 1154 1155 d2h_w_idx_ptr += idx_offset; 1156 d2h_r_idx_ptr += idx_offset; 1157 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1158 } 1159 1160 devinfo->shared.nrof_flowrings = 1161 max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS; 1162 rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring), 1163 GFP_KERNEL); 1164 if (!rings) 1165 goto fail; 1166 1167 brcmf_dbg(PCIE, "Nr of flowrings is %d\n", 1168 devinfo->shared.nrof_flowrings); 1169 1170 for (i = 0; i < devinfo->shared.nrof_flowrings; i++) { 1171 ring = &rings[i]; 1172 ring->devinfo = devinfo; 1173 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS; 1174 brcmf_commonring_register_cb(&ring->commonring, 1175 brcmf_pcie_ring_mb_ring_bell, 1176 brcmf_pcie_ring_mb_update_rptr, 1177 brcmf_pcie_ring_mb_update_wptr, 1178 brcmf_pcie_ring_mb_write_rptr, 1179 brcmf_pcie_ring_mb_write_wptr, 1180 ring); 1181 ring->w_idx_addr = h2d_w_idx_ptr; 1182 ring->r_idx_addr = h2d_r_idx_ptr; 1183 h2d_w_idx_ptr += idx_offset; 1184 h2d_r_idx_ptr += idx_offset; 1185 } 1186 devinfo->shared.flowrings = rings; 1187 1188 return 0; 1189 1190 fail: 1191 brcmf_err("Allocating ring buffers failed\n"); 1192 brcmf_pcie_release_ringbuffers(devinfo); 1193 return -ENOMEM; 1194 } 1195 1196 1197 static void 1198 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1199 { 1200 if (devinfo->shared.scratch) 1201 dma_free_coherent(&devinfo->pdev->dev, 1202 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1203 devinfo->shared.scratch, 1204 devinfo->shared.scratch_dmahandle); 1205 if (devinfo->shared.ringupd) 1206 dma_free_coherent(&devinfo->pdev->dev, 1207 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1208 devinfo->shared.ringupd, 1209 devinfo->shared.ringupd_dmahandle); 1210 } 1211 1212 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1213 { 1214 u64 address; 1215 u32 addr; 1216 1217 devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev, 1218 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1219 &devinfo->shared.scratch_dmahandle, GFP_KERNEL); 1220 if (!devinfo->shared.scratch) 1221 goto fail; 1222 1223 memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); 1224 1225 addr = devinfo->shared.tcm_base_address + 1226 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET; 1227 address = (u64)devinfo->shared.scratch_dmahandle; 1228 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1229 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1230 addr = devinfo->shared.tcm_base_address + 1231 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET; 1232 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); 1233 1234 devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev, 1235 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1236 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL); 1237 if (!devinfo->shared.ringupd) 1238 goto fail; 1239 1240 memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); 1241 1242 addr = devinfo->shared.tcm_base_address + 1243 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET; 1244 address = (u64)devinfo->shared.ringupd_dmahandle; 1245 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1246 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1247 addr = devinfo->shared.tcm_base_address + 1248 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET; 1249 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); 1250 return 0; 1251 1252 fail: 1253 brcmf_err("Allocating scratch buffers failed\n"); 1254 brcmf_pcie_release_scratchbuffers(devinfo); 1255 return -ENOMEM; 1256 } 1257 1258 1259 static void brcmf_pcie_down(struct device *dev) 1260 { 1261 } 1262 1263 1264 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb) 1265 { 1266 return 0; 1267 } 1268 1269 1270 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg, 1271 uint len) 1272 { 1273 return 0; 1274 } 1275 1276 1277 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg, 1278 uint len) 1279 { 1280 return 0; 1281 } 1282 1283 1284 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled) 1285 { 1286 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1287 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1288 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1289 1290 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled); 1291 devinfo->wowl_enabled = enabled; 1292 } 1293 1294 1295 static size_t brcmf_pcie_get_ramsize(struct device *dev) 1296 { 1297 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1298 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1299 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1300 1301 return devinfo->ci->ramsize - devinfo->ci->srsize; 1302 } 1303 1304 1305 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len) 1306 { 1307 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1308 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1309 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1310 1311 brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len); 1312 brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len); 1313 return 0; 1314 } 1315 1316 1317 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = { 1318 .txdata = brcmf_pcie_tx, 1319 .stop = brcmf_pcie_down, 1320 .txctl = brcmf_pcie_tx_ctlpkt, 1321 .rxctl = brcmf_pcie_rx_ctlpkt, 1322 .wowl_config = brcmf_pcie_wowl_config, 1323 .get_ramsize = brcmf_pcie_get_ramsize, 1324 .get_memdump = brcmf_pcie_get_memdump, 1325 }; 1326 1327 1328 static void 1329 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data, 1330 u32 data_len) 1331 { 1332 __le32 *field; 1333 u32 newsize; 1334 1335 if (data_len < BRCMF_RAMSIZE_OFFSET + 8) 1336 return; 1337 1338 field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET]; 1339 if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC) 1340 return; 1341 field++; 1342 newsize = le32_to_cpup(field); 1343 1344 brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n", 1345 newsize); 1346 devinfo->ci->ramsize = newsize; 1347 } 1348 1349 1350 static int 1351 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo, 1352 u32 sharedram_addr) 1353 { 1354 struct brcmf_pcie_shared_info *shared; 1355 u32 addr; 1356 u32 version; 1357 1358 shared = &devinfo->shared; 1359 shared->tcm_base_address = sharedram_addr; 1360 1361 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr); 1362 version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK; 1363 brcmf_dbg(PCIE, "PCIe protocol version %d\n", version); 1364 if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) || 1365 (version < BRCMF_PCIE_MIN_SHARED_VERSION)) { 1366 brcmf_err("Unsupported PCIE version %d\n", version); 1367 return -EINVAL; 1368 } 1369 1370 /* check firmware support dma indicies */ 1371 if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) { 1372 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX) 1373 devinfo->dma_idx_sz = sizeof(u16); 1374 else 1375 devinfo->dma_idx_sz = sizeof(u32); 1376 } 1377 1378 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET; 1379 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr); 1380 if (shared->max_rxbufpost == 0) 1381 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST; 1382 1383 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET; 1384 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr); 1385 1386 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET; 1387 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1388 1389 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET; 1390 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1391 1392 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET; 1393 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1394 1395 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n", 1396 shared->max_rxbufpost, shared->rx_dataoffset); 1397 1398 brcmf_pcie_bus_console_init(devinfo); 1399 1400 return 0; 1401 } 1402 1403 1404 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo, 1405 const struct firmware *fw, void *nvram, 1406 u32 nvram_len) 1407 { 1408 u32 sharedram_addr; 1409 u32 sharedram_addr_written; 1410 u32 loop_counter; 1411 int err; 1412 u32 address; 1413 u32 resetintr; 1414 1415 brcmf_dbg(PCIE, "Halt ARM.\n"); 1416 err = brcmf_pcie_enter_download_state(devinfo); 1417 if (err) 1418 return err; 1419 1420 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name); 1421 brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase, 1422 (void *)fw->data, fw->size); 1423 1424 resetintr = get_unaligned_le32(fw->data); 1425 release_firmware(fw); 1426 1427 /* reset last 4 bytes of RAM address. to be used for shared 1428 * area. This identifies when FW is running 1429 */ 1430 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0); 1431 1432 if (nvram) { 1433 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name); 1434 address = devinfo->ci->rambase + devinfo->ci->ramsize - 1435 nvram_len; 1436 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len); 1437 brcmf_fw_nvram_free(nvram); 1438 } else { 1439 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n", 1440 devinfo->nvram_name); 1441 } 1442 1443 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo, 1444 devinfo->ci->ramsize - 1445 4); 1446 brcmf_dbg(PCIE, "Bring ARM in running state\n"); 1447 err = brcmf_pcie_exit_download_state(devinfo, resetintr); 1448 if (err) 1449 return err; 1450 1451 brcmf_dbg(PCIE, "Wait for FW init\n"); 1452 sharedram_addr = sharedram_addr_written; 1453 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50; 1454 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) { 1455 msleep(50); 1456 sharedram_addr = brcmf_pcie_read_ram32(devinfo, 1457 devinfo->ci->ramsize - 1458 4); 1459 loop_counter--; 1460 } 1461 if (sharedram_addr == sharedram_addr_written) { 1462 brcmf_err("FW failed to initialize\n"); 1463 return -ENODEV; 1464 } 1465 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr); 1466 1467 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr)); 1468 } 1469 1470 1471 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo) 1472 { 1473 struct pci_dev *pdev; 1474 int err; 1475 phys_addr_t bar0_addr, bar1_addr; 1476 ulong bar1_size; 1477 1478 pdev = devinfo->pdev; 1479 1480 err = pci_enable_device(pdev); 1481 if (err) { 1482 brcmf_err("pci_enable_device failed err=%d\n", err); 1483 return err; 1484 } 1485 1486 pci_set_master(pdev); 1487 1488 /* Bar-0 mapped address */ 1489 bar0_addr = pci_resource_start(pdev, 0); 1490 /* Bar-1 mapped address */ 1491 bar1_addr = pci_resource_start(pdev, 2); 1492 /* read Bar-1 mapped memory range */ 1493 bar1_size = pci_resource_len(pdev, 2); 1494 if ((bar1_size == 0) || (bar1_addr == 0)) { 1495 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n", 1496 bar1_size, (unsigned long long)bar1_addr); 1497 return -EINVAL; 1498 } 1499 1500 devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE); 1501 devinfo->tcm = ioremap_nocache(bar1_addr, bar1_size); 1502 1503 if (!devinfo->regs || !devinfo->tcm) { 1504 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs, 1505 devinfo->tcm); 1506 return -EINVAL; 1507 } 1508 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n", 1509 devinfo->regs, (unsigned long long)bar0_addr); 1510 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n", 1511 devinfo->tcm, (unsigned long long)bar1_addr, 1512 (unsigned int)bar1_size); 1513 1514 return 0; 1515 } 1516 1517 1518 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo) 1519 { 1520 if (devinfo->tcm) 1521 iounmap(devinfo->tcm); 1522 if (devinfo->regs) 1523 iounmap(devinfo->regs); 1524 1525 pci_disable_device(devinfo->pdev); 1526 } 1527 1528 1529 static int brcmf_pcie_attach_bus(struct brcmf_pciedev_info *devinfo) 1530 { 1531 int ret; 1532 1533 /* Attach to the common driver interface */ 1534 ret = brcmf_attach(&devinfo->pdev->dev, devinfo->settings); 1535 if (ret) { 1536 brcmf_err("brcmf_attach failed\n"); 1537 } else { 1538 ret = brcmf_bus_start(&devinfo->pdev->dev); 1539 if (ret) 1540 brcmf_err("dongle is not responding\n"); 1541 } 1542 1543 return ret; 1544 } 1545 1546 1547 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr) 1548 { 1549 u32 ret_addr; 1550 1551 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1); 1552 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1); 1553 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr); 1554 1555 return ret_addr; 1556 } 1557 1558 1559 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr) 1560 { 1561 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1562 1563 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1564 return brcmf_pcie_read_reg32(devinfo, addr); 1565 } 1566 1567 1568 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value) 1569 { 1570 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1571 1572 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1573 brcmf_pcie_write_reg32(devinfo, addr, value); 1574 } 1575 1576 1577 static int brcmf_pcie_buscoreprep(void *ctx) 1578 { 1579 return brcmf_pcie_get_resource(ctx); 1580 } 1581 1582 1583 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip) 1584 { 1585 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1586 u32 val; 1587 1588 devinfo->ci = chip; 1589 brcmf_pcie_reset_device(devinfo); 1590 1591 val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 1592 if (val != 0xffffffff) 1593 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, 1594 val); 1595 1596 return 0; 1597 } 1598 1599 1600 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip, 1601 u32 rstvec) 1602 { 1603 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1604 1605 brcmf_pcie_write_tcm32(devinfo, 0, rstvec); 1606 } 1607 1608 1609 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = { 1610 .prepare = brcmf_pcie_buscoreprep, 1611 .reset = brcmf_pcie_buscore_reset, 1612 .activate = brcmf_pcie_buscore_activate, 1613 .read32 = brcmf_pcie_buscore_read32, 1614 .write32 = brcmf_pcie_buscore_write32, 1615 }; 1616 1617 static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw, 1618 void *nvram, u32 nvram_len) 1619 { 1620 struct brcmf_bus *bus = dev_get_drvdata(dev); 1621 struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie; 1622 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo; 1623 struct brcmf_commonring **flowrings; 1624 int ret; 1625 u32 i; 1626 1627 brcmf_pcie_attach(devinfo); 1628 1629 /* Some of the firmwares have the size of the memory of the device 1630 * defined inside the firmware. This is because part of the memory in 1631 * the device is shared and the devision is determined by FW. Parse 1632 * the firmware and adjust the chip memory size now. 1633 */ 1634 brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size); 1635 1636 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len); 1637 if (ret) 1638 goto fail; 1639 1640 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 1641 1642 ret = brcmf_pcie_init_ringbuffers(devinfo); 1643 if (ret) 1644 goto fail; 1645 1646 ret = brcmf_pcie_init_scratchbuffers(devinfo); 1647 if (ret) 1648 goto fail; 1649 1650 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 1651 ret = brcmf_pcie_request_irq(devinfo); 1652 if (ret) 1653 goto fail; 1654 1655 /* hook the commonrings in the bus structure. */ 1656 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) 1657 bus->msgbuf->commonrings[i] = 1658 &devinfo->shared.commonrings[i]->commonring; 1659 1660 flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*flowrings), 1661 GFP_KERNEL); 1662 if (!flowrings) 1663 goto fail; 1664 1665 for (i = 0; i < devinfo->shared.nrof_flowrings; i++) 1666 flowrings[i] = &devinfo->shared.flowrings[i].commonring; 1667 bus->msgbuf->flowrings = flowrings; 1668 1669 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset; 1670 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost; 1671 bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings; 1672 1673 init_waitqueue_head(&devinfo->mbdata_resp_wait); 1674 1675 brcmf_pcie_intr_enable(devinfo); 1676 if (brcmf_pcie_attach_bus(devinfo) == 0) 1677 return; 1678 1679 brcmf_pcie_bus_console_read(devinfo); 1680 1681 fail: 1682 device_release_driver(dev); 1683 } 1684 1685 static int 1686 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1687 { 1688 int ret; 1689 struct brcmf_pciedev_info *devinfo; 1690 struct brcmf_pciedev *pcie_bus_dev; 1691 struct brcmf_bus *bus; 1692 u16 domain_nr; 1693 u16 bus_nr; 1694 1695 domain_nr = pci_domain_nr(pdev->bus) + 1; 1696 bus_nr = pdev->bus->number; 1697 brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device, 1698 domain_nr, bus_nr); 1699 1700 ret = -ENOMEM; 1701 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL); 1702 if (devinfo == NULL) 1703 return ret; 1704 1705 devinfo->pdev = pdev; 1706 pcie_bus_dev = NULL; 1707 devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops); 1708 if (IS_ERR(devinfo->ci)) { 1709 ret = PTR_ERR(devinfo->ci); 1710 devinfo->ci = NULL; 1711 goto fail; 1712 } 1713 1714 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL); 1715 if (pcie_bus_dev == NULL) { 1716 ret = -ENOMEM; 1717 goto fail; 1718 } 1719 1720 devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev, 1721 BRCMF_BUSTYPE_PCIE, 1722 devinfo->ci->chip, 1723 devinfo->ci->chiprev); 1724 if (!devinfo->settings) { 1725 ret = -ENOMEM; 1726 goto fail; 1727 } 1728 1729 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 1730 if (!bus) { 1731 ret = -ENOMEM; 1732 goto fail; 1733 } 1734 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL); 1735 if (!bus->msgbuf) { 1736 ret = -ENOMEM; 1737 kfree(bus); 1738 goto fail; 1739 } 1740 1741 /* hook it all together. */ 1742 pcie_bus_dev->devinfo = devinfo; 1743 pcie_bus_dev->bus = bus; 1744 bus->dev = &pdev->dev; 1745 bus->bus_priv.pcie = pcie_bus_dev; 1746 bus->ops = &brcmf_pcie_bus_ops; 1747 bus->proto_type = BRCMF_PROTO_MSGBUF; 1748 bus->chip = devinfo->coreid; 1749 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot); 1750 dev_set_drvdata(&pdev->dev, bus); 1751 1752 ret = brcmf_fw_map_chip_to_name(devinfo->ci->chip, devinfo->ci->chiprev, 1753 brcmf_pcie_fwnames, 1754 ARRAY_SIZE(brcmf_pcie_fwnames), 1755 devinfo->fw_name, devinfo->nvram_name); 1756 if (ret) 1757 goto fail_bus; 1758 1759 ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM | 1760 BRCMF_FW_REQ_NV_OPTIONAL, 1761 devinfo->fw_name, devinfo->nvram_name, 1762 brcmf_pcie_setup, domain_nr, bus_nr); 1763 if (ret == 0) 1764 return 0; 1765 fail_bus: 1766 kfree(bus->msgbuf); 1767 kfree(bus); 1768 fail: 1769 brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device); 1770 brcmf_pcie_release_resource(devinfo); 1771 if (devinfo->ci) 1772 brcmf_chip_detach(devinfo->ci); 1773 if (devinfo->settings) 1774 brcmf_release_module_param(devinfo->settings); 1775 kfree(pcie_bus_dev); 1776 kfree(devinfo); 1777 return ret; 1778 } 1779 1780 1781 static void 1782 brcmf_pcie_remove(struct pci_dev *pdev) 1783 { 1784 struct brcmf_pciedev_info *devinfo; 1785 struct brcmf_bus *bus; 1786 1787 brcmf_dbg(PCIE, "Enter\n"); 1788 1789 bus = dev_get_drvdata(&pdev->dev); 1790 if (bus == NULL) 1791 return; 1792 1793 devinfo = bus->bus_priv.pcie->devinfo; 1794 1795 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 1796 if (devinfo->ci) 1797 brcmf_pcie_intr_disable(devinfo); 1798 1799 brcmf_detach(&pdev->dev); 1800 1801 kfree(bus->bus_priv.pcie); 1802 kfree(bus->msgbuf->flowrings); 1803 kfree(bus->msgbuf); 1804 kfree(bus); 1805 1806 brcmf_pcie_release_irq(devinfo); 1807 brcmf_pcie_release_scratchbuffers(devinfo); 1808 brcmf_pcie_release_ringbuffers(devinfo); 1809 brcmf_pcie_reset_device(devinfo); 1810 brcmf_pcie_release_resource(devinfo); 1811 1812 if (devinfo->ci) 1813 brcmf_chip_detach(devinfo->ci); 1814 if (devinfo->settings) 1815 brcmf_release_module_param(devinfo->settings); 1816 1817 kfree(devinfo); 1818 dev_set_drvdata(&pdev->dev, NULL); 1819 } 1820 1821 1822 #ifdef CONFIG_PM 1823 1824 1825 static int brcmf_pcie_pm_enter_D3(struct device *dev) 1826 { 1827 struct brcmf_pciedev_info *devinfo; 1828 struct brcmf_bus *bus; 1829 1830 brcmf_dbg(PCIE, "Enter\n"); 1831 1832 bus = dev_get_drvdata(dev); 1833 devinfo = bus->bus_priv.pcie->devinfo; 1834 1835 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN); 1836 1837 devinfo->mbdata_completed = false; 1838 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM); 1839 1840 wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed, 1841 BRCMF_PCIE_MBDATA_TIMEOUT); 1842 if (!devinfo->mbdata_completed) { 1843 brcmf_err("Timeout on response for entering D3 substate\n"); 1844 return -EIO; 1845 } 1846 1847 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 1848 1849 return 0; 1850 } 1851 1852 1853 static int brcmf_pcie_pm_leave_D3(struct device *dev) 1854 { 1855 struct brcmf_pciedev_info *devinfo; 1856 struct brcmf_bus *bus; 1857 struct pci_dev *pdev; 1858 int err; 1859 1860 brcmf_dbg(PCIE, "Enter\n"); 1861 1862 bus = dev_get_drvdata(dev); 1863 devinfo = bus->bus_priv.pcie->devinfo; 1864 brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus); 1865 1866 /* Check if device is still up and running, if so we are ready */ 1867 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0) { 1868 brcmf_dbg(PCIE, "Try to wakeup device....\n"); 1869 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM)) 1870 goto cleanup; 1871 brcmf_dbg(PCIE, "Hot resume, continue....\n"); 1872 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 1873 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 1874 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 1875 brcmf_pcie_intr_enable(devinfo); 1876 return 0; 1877 } 1878 1879 cleanup: 1880 brcmf_chip_detach(devinfo->ci); 1881 devinfo->ci = NULL; 1882 pdev = devinfo->pdev; 1883 brcmf_pcie_remove(pdev); 1884 1885 err = brcmf_pcie_probe(pdev, NULL); 1886 if (err) 1887 brcmf_err("probe after resume failed, err=%d\n", err); 1888 1889 return err; 1890 } 1891 1892 1893 static const struct dev_pm_ops brcmf_pciedrvr_pm = { 1894 .suspend = brcmf_pcie_pm_enter_D3, 1895 .resume = brcmf_pcie_pm_leave_D3, 1896 .freeze = brcmf_pcie_pm_enter_D3, 1897 .restore = brcmf_pcie_pm_leave_D3, 1898 }; 1899 1900 1901 #endif /* CONFIG_PM */ 1902 1903 1904 #define BRCMF_PCIE_DEVICE(dev_id) { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\ 1905 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 } 1906 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev) { \ 1907 BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\ 1908 subvend, subdev, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 } 1909 1910 static struct pci_device_id brcmf_pcie_devid_table[] = { 1911 BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID), 1912 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID), 1913 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID), 1914 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID), 1915 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID), 1916 BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID), 1917 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID), 1918 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID), 1919 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID), 1920 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID), 1921 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID), 1922 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID), 1923 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID), 1924 BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365), 1925 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID), 1926 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID), 1927 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID), 1928 BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID), 1929 { /* end: all zeroes */ } 1930 }; 1931 1932 1933 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table); 1934 1935 1936 static struct pci_driver brcmf_pciedrvr = { 1937 .node = {}, 1938 .name = KBUILD_MODNAME, 1939 .id_table = brcmf_pcie_devid_table, 1940 .probe = brcmf_pcie_probe, 1941 .remove = brcmf_pcie_remove, 1942 #ifdef CONFIG_PM 1943 .driver.pm = &brcmf_pciedrvr_pm, 1944 #endif 1945 }; 1946 1947 1948 void brcmf_pcie_register(void) 1949 { 1950 int err; 1951 1952 brcmf_dbg(PCIE, "Enter\n"); 1953 err = pci_register_driver(&brcmf_pciedrvr); 1954 if (err) 1955 brcmf_err("PCIE driver registration failed, err=%d\n", err); 1956 } 1957 1958 1959 void brcmf_pcie_exit(void) 1960 { 1961 brcmf_dbg(PCIE, "Enter\n"); 1962 pci_unregister_driver(&brcmf_pciedrvr); 1963 } 1964