1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2014 Broadcom Corporation 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/firmware.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/bcma/bcma.h> 14 #include <linux/sched.h> 15 #include <linux/io.h> 16 #include <asm/unaligned.h> 17 18 #include <soc.h> 19 #include <chipcommon.h> 20 #include <brcmu_utils.h> 21 #include <brcmu_wifi.h> 22 #include <brcm_hw_ids.h> 23 24 /* Custom brcmf_err() that takes bus arg and passes it further */ 25 #define brcmf_err(bus, fmt, ...) \ 26 do { \ 27 if (IS_ENABLED(CONFIG_BRCMDBG) || \ 28 IS_ENABLED(CONFIG_BRCM_TRACING) || \ 29 net_ratelimit()) \ 30 __brcmf_err(bus, __func__, fmt, ##__VA_ARGS__); \ 31 } while (0) 32 33 #include "debug.h" 34 #include "bus.h" 35 #include "commonring.h" 36 #include "msgbuf.h" 37 #include "pcie.h" 38 #include "firmware.h" 39 #include "chip.h" 40 #include "core.h" 41 #include "common.h" 42 43 44 enum brcmf_pcie_state { 45 BRCMFMAC_PCIE_STATE_DOWN, 46 BRCMFMAC_PCIE_STATE_UP 47 }; 48 49 BRCMF_FW_DEF(43602, "brcmfmac43602-pcie"); 50 BRCMF_FW_DEF(4350, "brcmfmac4350-pcie"); 51 BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie"); 52 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-pcie"); 53 BRCMF_FW_CLM_DEF(43570, "brcmfmac43570-pcie"); 54 BRCMF_FW_DEF(4358, "brcmfmac4358-pcie"); 55 BRCMF_FW_DEF(4359, "brcmfmac4359-pcie"); 56 BRCMF_FW_DEF(4364, "brcmfmac4364-pcie"); 57 BRCMF_FW_DEF(4365B, "brcmfmac4365b-pcie"); 58 BRCMF_FW_DEF(4365C, "brcmfmac4365c-pcie"); 59 BRCMF_FW_DEF(4366B, "brcmfmac4366b-pcie"); 60 BRCMF_FW_DEF(4366C, "brcmfmac4366c-pcie"); 61 BRCMF_FW_DEF(4371, "brcmfmac4371-pcie"); 62 BRCMF_FW_CLM_DEF(4378B1, "brcmfmac4378b1-pcie"); 63 BRCMF_FW_DEF(4355, "brcmfmac89459-pcie"); 64 65 /* firmware config files */ 66 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt"); 67 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txt"); 68 69 /* per-board firmware binaries */ 70 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.bin"); 71 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.clm_blob"); 72 73 static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = { 74 BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602), 75 BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C), 76 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C), 77 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350), 78 BRCMF_FW_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C), 79 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 80 BRCMF_FW_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570), 81 BRCMF_FW_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570), 82 BRCMF_FW_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570), 83 BRCMF_FW_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358), 84 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359), 85 BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0xFFFFFFFF, 4364), 86 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B), 87 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C), 88 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B), 89 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C), 90 BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C), 91 BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C), 92 BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371), 93 BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFFF, 4378B1), /* revision ID 3 */ 94 BRCMF_FW_ENTRY(CY_CC_89459_CHIP_ID, 0xFFFFFFFF, 4355), 95 }; 96 97 #define BRCMF_PCIE_FW_UP_TIMEOUT 5000 /* msec */ 98 99 #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024) 100 101 /* backplane addres space accessed by BAR0 */ 102 #define BRCMF_PCIE_BAR0_WINDOW 0x80 103 #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000 104 #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70 105 106 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000 107 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000 108 109 #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40 110 #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C 111 112 #define BRCMF_PCIE_REG_INTSTATUS 0x90 113 #define BRCMF_PCIE_REG_INTMASK 0x94 114 #define BRCMF_PCIE_REG_SBMBX 0x98 115 116 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC 117 118 #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24 119 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48 120 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C 121 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120 122 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124 123 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0 0x140 124 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1 0x144 125 126 #define BRCMF_PCIE_64_PCIE2REG_INTMASK 0xC14 127 #define BRCMF_PCIE_64_PCIE2REG_MAILBOXINT 0xC30 128 #define BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK 0xC34 129 #define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0 0xA20 130 #define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1 0xA24 131 132 #define BRCMF_PCIE2_INTA 0x01 133 #define BRCMF_PCIE2_INTB 0x02 134 135 #define BRCMF_PCIE_INT_0 0x01 136 #define BRCMF_PCIE_INT_1 0x02 137 #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \ 138 BRCMF_PCIE_INT_1) 139 140 #define BRCMF_PCIE_MB_INT_FN0_0 0x0100 141 #define BRCMF_PCIE_MB_INT_FN0_1 0x0200 142 #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000 143 #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000 144 #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000 145 #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000 146 #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000 147 #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000 148 #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000 149 #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000 150 151 #define BRCMF_PCIE_MB_INT_FN0 (BRCMF_PCIE_MB_INT_FN0_0 | \ 152 BRCMF_PCIE_MB_INT_FN0_1) 153 #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \ 154 BRCMF_PCIE_MB_INT_D2H0_DB1 | \ 155 BRCMF_PCIE_MB_INT_D2H1_DB0 | \ 156 BRCMF_PCIE_MB_INT_D2H1_DB1 | \ 157 BRCMF_PCIE_MB_INT_D2H2_DB0 | \ 158 BRCMF_PCIE_MB_INT_D2H2_DB1 | \ 159 BRCMF_PCIE_MB_INT_D2H3_DB0 | \ 160 BRCMF_PCIE_MB_INT_D2H3_DB1) 161 162 #define BRCMF_PCIE_64_MB_INT_D2H0_DB0 0x1 163 #define BRCMF_PCIE_64_MB_INT_D2H0_DB1 0x2 164 #define BRCMF_PCIE_64_MB_INT_D2H1_DB0 0x4 165 #define BRCMF_PCIE_64_MB_INT_D2H1_DB1 0x8 166 #define BRCMF_PCIE_64_MB_INT_D2H2_DB0 0x10 167 #define BRCMF_PCIE_64_MB_INT_D2H2_DB1 0x20 168 #define BRCMF_PCIE_64_MB_INT_D2H3_DB0 0x40 169 #define BRCMF_PCIE_64_MB_INT_D2H3_DB1 0x80 170 #define BRCMF_PCIE_64_MB_INT_D2H4_DB0 0x100 171 #define BRCMF_PCIE_64_MB_INT_D2H4_DB1 0x200 172 #define BRCMF_PCIE_64_MB_INT_D2H5_DB0 0x400 173 #define BRCMF_PCIE_64_MB_INT_D2H5_DB1 0x800 174 #define BRCMF_PCIE_64_MB_INT_D2H6_DB0 0x1000 175 #define BRCMF_PCIE_64_MB_INT_D2H6_DB1 0x2000 176 #define BRCMF_PCIE_64_MB_INT_D2H7_DB0 0x4000 177 #define BRCMF_PCIE_64_MB_INT_D2H7_DB1 0x8000 178 179 #define BRCMF_PCIE_64_MB_INT_D2H_DB (BRCMF_PCIE_64_MB_INT_D2H0_DB0 | \ 180 BRCMF_PCIE_64_MB_INT_D2H0_DB1 | \ 181 BRCMF_PCIE_64_MB_INT_D2H1_DB0 | \ 182 BRCMF_PCIE_64_MB_INT_D2H1_DB1 | \ 183 BRCMF_PCIE_64_MB_INT_D2H2_DB0 | \ 184 BRCMF_PCIE_64_MB_INT_D2H2_DB1 | \ 185 BRCMF_PCIE_64_MB_INT_D2H3_DB0 | \ 186 BRCMF_PCIE_64_MB_INT_D2H3_DB1 | \ 187 BRCMF_PCIE_64_MB_INT_D2H4_DB0 | \ 188 BRCMF_PCIE_64_MB_INT_D2H4_DB1 | \ 189 BRCMF_PCIE_64_MB_INT_D2H5_DB0 | \ 190 BRCMF_PCIE_64_MB_INT_D2H5_DB1 | \ 191 BRCMF_PCIE_64_MB_INT_D2H6_DB0 | \ 192 BRCMF_PCIE_64_MB_INT_D2H6_DB1 | \ 193 BRCMF_PCIE_64_MB_INT_D2H7_DB0 | \ 194 BRCMF_PCIE_64_MB_INT_D2H7_DB1) 195 196 #define BRCMF_PCIE_SHARED_VERSION_7 7 197 #define BRCMF_PCIE_MIN_SHARED_VERSION 5 198 #define BRCMF_PCIE_MAX_SHARED_VERSION BRCMF_PCIE_SHARED_VERSION_7 199 #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF 200 #define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000 201 #define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000 202 #define BRCMF_PCIE_SHARED_HOSTRDY_DB1 0x10000000 203 204 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000 205 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000 206 207 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34 208 #define BRCMF_SHARED_RING_BASE_OFFSET 52 209 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36 210 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20 211 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40 212 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44 213 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48 214 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52 215 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56 216 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64 217 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68 218 219 #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0 220 #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1 221 #define BRCMF_RING_H2D_RING_MEM_OFFSET 4 222 #define BRCMF_RING_H2D_RING_STATE_OFFSET 8 223 224 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8 225 #define BRCMF_RING_MAX_ITEM_OFFSET 4 226 #define BRCMF_RING_LEN_ITEMS_OFFSET 6 227 #define BRCMF_RING_MEM_SZ 16 228 #define BRCMF_RING_STATE_SZ 8 229 230 #define BRCMF_DEF_MAX_RXBUFPOST 255 231 232 #define BRCMF_CONSOLE_BUFADDR_OFFSET 8 233 #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12 234 #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16 235 236 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8 237 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024 238 239 #define BRCMF_D2H_DEV_D3_ACK 0x00000001 240 #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002 241 #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004 242 #define BRCMF_D2H_DEV_FWHALT 0x10000000 243 244 #define BRCMF_H2D_HOST_D3_INFORM 0x00000001 245 #define BRCMF_H2D_HOST_DS_ACK 0x00000002 246 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008 247 #define BRCMF_H2D_HOST_D0_INFORM 0x00000010 248 249 #define BRCMF_PCIE_MBDATA_TIMEOUT msecs_to_jiffies(2000) 250 251 #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4 252 #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C 253 #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58 254 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C 255 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60 256 #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64 257 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC 258 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC 259 #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228 260 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248 261 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0 262 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4 263 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3 264 265 /* Magic number at a magic location to find RAM size */ 266 #define BRCMF_RAMSIZE_MAGIC 0x534d4152 /* SMAR */ 267 #define BRCMF_RAMSIZE_OFFSET 0x6c 268 269 270 struct brcmf_pcie_console { 271 u32 base_addr; 272 u32 buf_addr; 273 u32 bufsize; 274 u32 read_idx; 275 u8 log_str[256]; 276 u8 log_idx; 277 }; 278 279 struct brcmf_pcie_shared_info { 280 u32 tcm_base_address; 281 u32 flags; 282 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS]; 283 struct brcmf_pcie_ringbuf *flowrings; 284 u16 max_rxbufpost; 285 u16 max_flowrings; 286 u16 max_submissionrings; 287 u16 max_completionrings; 288 u32 rx_dataoffset; 289 u32 htod_mb_data_addr; 290 u32 dtoh_mb_data_addr; 291 u32 ring_info_addr; 292 struct brcmf_pcie_console console; 293 void *scratch; 294 dma_addr_t scratch_dmahandle; 295 void *ringupd; 296 dma_addr_t ringupd_dmahandle; 297 u8 version; 298 }; 299 300 struct brcmf_pcie_core_info { 301 u32 base; 302 u32 wrapbase; 303 }; 304 305 #define BRCMF_OTP_MAX_PARAM_LEN 16 306 307 struct brcmf_otp_params { 308 char module[BRCMF_OTP_MAX_PARAM_LEN]; 309 char vendor[BRCMF_OTP_MAX_PARAM_LEN]; 310 char version[BRCMF_OTP_MAX_PARAM_LEN]; 311 bool valid; 312 }; 313 314 struct brcmf_pciedev_info { 315 enum brcmf_pcie_state state; 316 bool in_irq; 317 struct pci_dev *pdev; 318 char fw_name[BRCMF_FW_NAME_LEN]; 319 char nvram_name[BRCMF_FW_NAME_LEN]; 320 char clm_name[BRCMF_FW_NAME_LEN]; 321 const struct firmware *clm_fw; 322 const struct brcmf_pcie_reginfo *reginfo; 323 void __iomem *regs; 324 void __iomem *tcm; 325 u32 ram_base; 326 u32 ram_size; 327 struct brcmf_chip *ci; 328 u32 coreid; 329 struct brcmf_pcie_shared_info shared; 330 wait_queue_head_t mbdata_resp_wait; 331 bool mbdata_completed; 332 bool irq_allocated; 333 bool wowl_enabled; 334 u8 dma_idx_sz; 335 void *idxbuf; 336 u32 idxbuf_sz; 337 dma_addr_t idxbuf_dmahandle; 338 u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset); 339 void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 340 u16 value); 341 struct brcmf_mp_device *settings; 342 struct brcmf_otp_params otp; 343 }; 344 345 struct brcmf_pcie_ringbuf { 346 struct brcmf_commonring commonring; 347 dma_addr_t dma_handle; 348 u32 w_idx_addr; 349 u32 r_idx_addr; 350 struct brcmf_pciedev_info *devinfo; 351 u8 id; 352 }; 353 354 /** 355 * struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info 356 * 357 * @ringmem: dongle memory pointer to ring memory location 358 * @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers 359 * @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers 360 * @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers 361 * @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers 362 * @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers 363 * @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers 364 * @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers 365 * @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers 366 * @max_flowrings: maximum number of tx flow rings supported. 367 * @max_submissionrings: maximum number of submission rings(h2d) supported. 368 * @max_completionrings: maximum number of completion rings(d2h) supported. 369 */ 370 struct brcmf_pcie_dhi_ringinfo { 371 __le32 ringmem; 372 __le32 h2d_w_idx_ptr; 373 __le32 h2d_r_idx_ptr; 374 __le32 d2h_w_idx_ptr; 375 __le32 d2h_r_idx_ptr; 376 struct msgbuf_buf_addr h2d_w_idx_hostaddr; 377 struct msgbuf_buf_addr h2d_r_idx_hostaddr; 378 struct msgbuf_buf_addr d2h_w_idx_hostaddr; 379 struct msgbuf_buf_addr d2h_r_idx_hostaddr; 380 __le16 max_flowrings; 381 __le16 max_submissionrings; 382 __le16 max_completionrings; 383 }; 384 385 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = { 386 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM, 387 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM, 388 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM, 389 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM, 390 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM 391 }; 392 393 static const u32 brcmf_ring_itemsize_pre_v7[BRCMF_NROF_COMMON_MSGRINGS] = { 394 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 395 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 396 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 397 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7, 398 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7 399 }; 400 401 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = { 402 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 403 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 404 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 405 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE, 406 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE 407 }; 408 409 struct brcmf_pcie_reginfo { 410 u32 intmask; 411 u32 mailboxint; 412 u32 mailboxmask; 413 u32 h2d_mailbox_0; 414 u32 h2d_mailbox_1; 415 u32 int_d2h_db; 416 u32 int_fn0; 417 }; 418 419 static const struct brcmf_pcie_reginfo brcmf_reginfo_default = { 420 .intmask = BRCMF_PCIE_PCIE2REG_INTMASK, 421 .mailboxint = BRCMF_PCIE_PCIE2REG_MAILBOXINT, 422 .mailboxmask = BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 423 .h2d_mailbox_0 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0, 424 .h2d_mailbox_1 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1, 425 .int_d2h_db = BRCMF_PCIE_MB_INT_D2H_DB, 426 .int_fn0 = BRCMF_PCIE_MB_INT_FN0, 427 }; 428 429 static const struct brcmf_pcie_reginfo brcmf_reginfo_64 = { 430 .intmask = BRCMF_PCIE_64_PCIE2REG_INTMASK, 431 .mailboxint = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT, 432 .mailboxmask = BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK, 433 .h2d_mailbox_0 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0, 434 .h2d_mailbox_1 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1, 435 .int_d2h_db = BRCMF_PCIE_64_MB_INT_D2H_DB, 436 .int_fn0 = 0, 437 }; 438 439 static void brcmf_pcie_setup(struct device *dev, int ret, 440 struct brcmf_fw_request *fwreq); 441 static struct brcmf_fw_request * 442 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo); 443 444 static u16 445 brcmf_pcie_read_reg16(struct brcmf_pciedev_info *devinfo, u32 reg_offset) 446 { 447 void __iomem *address = devinfo->regs + reg_offset; 448 449 return ioread16(address); 450 } 451 452 static u32 453 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset) 454 { 455 void __iomem *address = devinfo->regs + reg_offset; 456 457 return (ioread32(address)); 458 } 459 460 461 static void 462 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset, 463 u32 value) 464 { 465 void __iomem *address = devinfo->regs + reg_offset; 466 467 iowrite32(value, address); 468 } 469 470 471 static u8 472 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 473 { 474 void __iomem *address = devinfo->tcm + mem_offset; 475 476 return (ioread8(address)); 477 } 478 479 480 static u16 481 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 482 { 483 void __iomem *address = devinfo->tcm + mem_offset; 484 485 return (ioread16(address)); 486 } 487 488 489 static void 490 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 491 u16 value) 492 { 493 void __iomem *address = devinfo->tcm + mem_offset; 494 495 iowrite16(value, address); 496 } 497 498 499 static u16 500 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 501 { 502 u16 *address = devinfo->idxbuf + mem_offset; 503 504 return (*(address)); 505 } 506 507 508 static void 509 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 510 u16 value) 511 { 512 u16 *address = devinfo->idxbuf + mem_offset; 513 514 *(address) = value; 515 } 516 517 518 static u32 519 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 520 { 521 void __iomem *address = devinfo->tcm + mem_offset; 522 523 return (ioread32(address)); 524 } 525 526 527 static void 528 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 529 u32 value) 530 { 531 void __iomem *address = devinfo->tcm + mem_offset; 532 533 iowrite32(value, address); 534 } 535 536 537 static u32 538 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 539 { 540 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 541 542 return (ioread32(addr)); 543 } 544 545 546 static void 547 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 548 u32 value) 549 { 550 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 551 552 iowrite32(value, addr); 553 } 554 555 556 static void 557 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 558 void *dstaddr, u32 len) 559 { 560 void __iomem *address = devinfo->tcm + mem_offset; 561 __le32 *dst32; 562 __le16 *dst16; 563 u8 *dst8; 564 565 if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) { 566 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) { 567 dst8 = (u8 *)dstaddr; 568 while (len) { 569 *dst8 = ioread8(address); 570 address++; 571 dst8++; 572 len--; 573 } 574 } else { 575 len = len / 2; 576 dst16 = (__le16 *)dstaddr; 577 while (len) { 578 *dst16 = cpu_to_le16(ioread16(address)); 579 address += 2; 580 dst16++; 581 len--; 582 } 583 } 584 } else { 585 len = len / 4; 586 dst32 = (__le32 *)dstaddr; 587 while (len) { 588 *dst32 = cpu_to_le32(ioread32(address)); 589 address += 4; 590 dst32++; 591 len--; 592 } 593 } 594 } 595 596 597 #define READCC32(devinfo, reg) brcmf_pcie_read_reg32(devinfo, \ 598 CHIPCREGOFFS(reg)) 599 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \ 600 CHIPCREGOFFS(reg), value) 601 602 603 static void 604 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid) 605 { 606 const struct pci_dev *pdev = devinfo->pdev; 607 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 608 struct brcmf_core *core; 609 u32 bar0_win; 610 611 core = brcmf_chip_get_core(devinfo->ci, coreid); 612 if (core) { 613 bar0_win = core->base; 614 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win); 615 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, 616 &bar0_win) == 0) { 617 if (bar0_win != core->base) { 618 bar0_win = core->base; 619 pci_write_config_dword(pdev, 620 BRCMF_PCIE_BAR0_WINDOW, 621 bar0_win); 622 } 623 } 624 } else { 625 brcmf_err(bus, "Unsupported core selected %x\n", coreid); 626 } 627 } 628 629 630 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo) 631 { 632 struct brcmf_core *core; 633 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD, 634 BRCMF_PCIE_CFGREG_PM_CSR, 635 BRCMF_PCIE_CFGREG_MSI_CAP, 636 BRCMF_PCIE_CFGREG_MSI_ADDR_L, 637 BRCMF_PCIE_CFGREG_MSI_ADDR_H, 638 BRCMF_PCIE_CFGREG_MSI_DATA, 639 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2, 640 BRCMF_PCIE_CFGREG_RBAR_CTRL, 641 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1, 642 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG, 643 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG }; 644 u32 i; 645 u32 val; 646 u32 lsc; 647 648 if (!devinfo->ci) 649 return; 650 651 /* Disable ASPM */ 652 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 653 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 654 &lsc); 655 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB); 656 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 657 val); 658 659 /* Watchdog reset */ 660 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON); 661 WRITECC32(devinfo, watchdog, 4); 662 msleep(100); 663 664 /* Restore ASPM */ 665 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 666 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 667 lsc); 668 669 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 670 if (core->rev <= 13) { 671 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) { 672 brcmf_pcie_write_reg32(devinfo, 673 BRCMF_PCIE_PCIE2REG_CONFIGADDR, 674 cfg_offset[i]); 675 val = brcmf_pcie_read_reg32(devinfo, 676 BRCMF_PCIE_PCIE2REG_CONFIGDATA); 677 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n", 678 cfg_offset[i], val); 679 brcmf_pcie_write_reg32(devinfo, 680 BRCMF_PCIE_PCIE2REG_CONFIGDATA, 681 val); 682 } 683 } 684 } 685 686 687 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo) 688 { 689 u32 config; 690 691 /* BAR1 window may not be sized properly */ 692 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 693 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0); 694 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA); 695 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config); 696 697 device_wakeup_enable(&devinfo->pdev->dev); 698 } 699 700 701 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo) 702 { 703 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 704 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4); 705 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 706 5); 707 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 708 0); 709 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 710 7); 711 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 712 0); 713 } 714 return 0; 715 } 716 717 718 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo, 719 u32 resetintr) 720 { 721 struct brcmf_core *core; 722 723 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 724 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM); 725 brcmf_chip_resetcore(core, 0, 0, 0); 726 } 727 728 if (!brcmf_chip_set_active(devinfo->ci, resetintr)) 729 return -EINVAL; 730 return 0; 731 } 732 733 734 static int 735 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data) 736 { 737 struct brcmf_pcie_shared_info *shared; 738 struct brcmf_core *core; 739 u32 addr; 740 u32 cur_htod_mb_data; 741 u32 i; 742 743 shared = &devinfo->shared; 744 addr = shared->htod_mb_data_addr; 745 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 746 747 if (cur_htod_mb_data != 0) 748 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n", 749 cur_htod_mb_data); 750 751 i = 0; 752 while (cur_htod_mb_data != 0) { 753 msleep(10); 754 i++; 755 if (i > 100) 756 return -EIO; 757 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 758 } 759 760 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data); 761 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 762 763 /* Send mailbox interrupt twice as a hardware workaround */ 764 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 765 if (core->rev <= 13) 766 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 767 768 return 0; 769 } 770 771 772 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo) 773 { 774 struct brcmf_pcie_shared_info *shared; 775 u32 addr; 776 u32 dtoh_mb_data; 777 778 shared = &devinfo->shared; 779 addr = shared->dtoh_mb_data_addr; 780 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 781 782 if (!dtoh_mb_data) 783 return; 784 785 brcmf_pcie_write_tcm32(devinfo, addr, 0); 786 787 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data); 788 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) { 789 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n"); 790 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK); 791 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n"); 792 } 793 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE) 794 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n"); 795 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) { 796 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n"); 797 devinfo->mbdata_completed = true; 798 wake_up(&devinfo->mbdata_resp_wait); 799 } 800 if (dtoh_mb_data & BRCMF_D2H_DEV_FWHALT) { 801 brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n"); 802 brcmf_fw_crashed(&devinfo->pdev->dev); 803 } 804 } 805 806 807 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo) 808 { 809 struct brcmf_pcie_shared_info *shared; 810 struct brcmf_pcie_console *console; 811 u32 addr; 812 813 shared = &devinfo->shared; 814 console = &shared->console; 815 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET; 816 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr); 817 818 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET; 819 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr); 820 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET; 821 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr); 822 823 brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n", 824 console->base_addr, console->buf_addr, console->bufsize); 825 } 826 827 /** 828 * brcmf_pcie_bus_console_read - reads firmware messages 829 * 830 * @devinfo: pointer to the device data structure 831 * @error: specifies if error has occurred (prints messages unconditionally) 832 */ 833 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo, 834 bool error) 835 { 836 struct pci_dev *pdev = devinfo->pdev; 837 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 838 struct brcmf_pcie_console *console; 839 u32 addr; 840 u8 ch; 841 u32 newidx; 842 843 if (!error && !BRCMF_FWCON_ON()) 844 return; 845 846 console = &devinfo->shared.console; 847 if (!console->base_addr) 848 return; 849 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET; 850 newidx = brcmf_pcie_read_tcm32(devinfo, addr); 851 while (newidx != console->read_idx) { 852 addr = console->buf_addr + console->read_idx; 853 ch = brcmf_pcie_read_tcm8(devinfo, addr); 854 console->read_idx++; 855 if (console->read_idx == console->bufsize) 856 console->read_idx = 0; 857 if (ch == '\r') 858 continue; 859 console->log_str[console->log_idx] = ch; 860 console->log_idx++; 861 if ((ch != '\n') && 862 (console->log_idx == (sizeof(console->log_str) - 2))) { 863 ch = '\n'; 864 console->log_str[console->log_idx] = ch; 865 console->log_idx++; 866 } 867 if (ch == '\n') { 868 console->log_str[console->log_idx] = 0; 869 if (error) 870 __brcmf_err(bus, __func__, "CONSOLE: %s", 871 console->log_str); 872 else 873 pr_debug("CONSOLE: %s", console->log_str); 874 console->log_idx = 0; 875 } 876 } 877 } 878 879 880 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo) 881 { 882 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask, 0); 883 } 884 885 886 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo) 887 { 888 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask, 889 devinfo->reginfo->int_d2h_db | 890 devinfo->reginfo->int_fn0); 891 } 892 893 static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo) 894 { 895 if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1) 896 brcmf_pcie_write_reg32(devinfo, 897 devinfo->reginfo->h2d_mailbox_1, 1); 898 } 899 900 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg) 901 { 902 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 903 904 if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint)) { 905 brcmf_pcie_intr_disable(devinfo); 906 brcmf_dbg(PCIE, "Enter\n"); 907 return IRQ_WAKE_THREAD; 908 } 909 return IRQ_NONE; 910 } 911 912 913 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg) 914 { 915 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 916 u32 status; 917 918 devinfo->in_irq = true; 919 status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint); 920 brcmf_dbg(PCIE, "Enter %x\n", status); 921 if (status) { 922 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint, 923 status); 924 if (status & devinfo->reginfo->int_fn0) 925 brcmf_pcie_handle_mb_data(devinfo); 926 if (status & devinfo->reginfo->int_d2h_db) { 927 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 928 brcmf_proto_msgbuf_rx_trigger( 929 &devinfo->pdev->dev); 930 } 931 } 932 brcmf_pcie_bus_console_read(devinfo, false); 933 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 934 brcmf_pcie_intr_enable(devinfo); 935 devinfo->in_irq = false; 936 return IRQ_HANDLED; 937 } 938 939 940 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo) 941 { 942 struct pci_dev *pdev = devinfo->pdev; 943 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 944 945 brcmf_pcie_intr_disable(devinfo); 946 947 brcmf_dbg(PCIE, "Enter\n"); 948 949 pci_enable_msi(pdev); 950 if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr, 951 brcmf_pcie_isr_thread, IRQF_SHARED, 952 "brcmf_pcie_intr", devinfo)) { 953 pci_disable_msi(pdev); 954 brcmf_err(bus, "Failed to request IRQ %d\n", pdev->irq); 955 return -EIO; 956 } 957 devinfo->irq_allocated = true; 958 return 0; 959 } 960 961 962 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo) 963 { 964 struct pci_dev *pdev = devinfo->pdev; 965 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 966 u32 status; 967 u32 count; 968 969 if (!devinfo->irq_allocated) 970 return; 971 972 brcmf_pcie_intr_disable(devinfo); 973 free_irq(pdev->irq, devinfo); 974 pci_disable_msi(pdev); 975 976 msleep(50); 977 count = 0; 978 while ((devinfo->in_irq) && (count < 20)) { 979 msleep(50); 980 count++; 981 } 982 if (devinfo->in_irq) 983 brcmf_err(bus, "Still in IRQ (processing) !!!\n"); 984 985 status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint); 986 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint, status); 987 988 devinfo->irq_allocated = false; 989 } 990 991 992 static int brcmf_pcie_ring_mb_write_rptr(void *ctx) 993 { 994 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 995 struct brcmf_pciedev_info *devinfo = ring->devinfo; 996 struct brcmf_commonring *commonring = &ring->commonring; 997 998 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 999 return -EIO; 1000 1001 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr, 1002 commonring->w_ptr, ring->id); 1003 1004 devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr); 1005 1006 return 0; 1007 } 1008 1009 1010 static int brcmf_pcie_ring_mb_write_wptr(void *ctx) 1011 { 1012 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1013 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1014 struct brcmf_commonring *commonring = &ring->commonring; 1015 1016 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1017 return -EIO; 1018 1019 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr, 1020 commonring->r_ptr, ring->id); 1021 1022 devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr); 1023 1024 return 0; 1025 } 1026 1027 1028 static int brcmf_pcie_ring_mb_ring_bell(void *ctx) 1029 { 1030 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1031 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1032 1033 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1034 return -EIO; 1035 1036 brcmf_dbg(PCIE, "RING !\n"); 1037 /* Any arbitrary value will do, lets use 1 */ 1038 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->h2d_mailbox_0, 1); 1039 1040 return 0; 1041 } 1042 1043 1044 static int brcmf_pcie_ring_mb_update_rptr(void *ctx) 1045 { 1046 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1047 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1048 struct brcmf_commonring *commonring = &ring->commonring; 1049 1050 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1051 return -EIO; 1052 1053 commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr); 1054 1055 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr, 1056 commonring->w_ptr, ring->id); 1057 1058 return 0; 1059 } 1060 1061 1062 static int brcmf_pcie_ring_mb_update_wptr(void *ctx) 1063 { 1064 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1065 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1066 struct brcmf_commonring *commonring = &ring->commonring; 1067 1068 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1069 return -EIO; 1070 1071 commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr); 1072 1073 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr, 1074 commonring->r_ptr, ring->id); 1075 1076 return 0; 1077 } 1078 1079 1080 static void * 1081 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo, 1082 u32 size, u32 tcm_dma_phys_addr, 1083 dma_addr_t *dma_handle) 1084 { 1085 void *ring; 1086 u64 address; 1087 1088 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle, 1089 GFP_KERNEL); 1090 if (!ring) 1091 return NULL; 1092 1093 address = (u64)*dma_handle; 1094 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr, 1095 address & 0xffffffff); 1096 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32); 1097 1098 return (ring); 1099 } 1100 1101 1102 static struct brcmf_pcie_ringbuf * 1103 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id, 1104 u32 tcm_ring_phys_addr) 1105 { 1106 void *dma_buf; 1107 dma_addr_t dma_handle; 1108 struct brcmf_pcie_ringbuf *ring; 1109 u32 size; 1110 u32 addr; 1111 const u32 *ring_itemsize_array; 1112 1113 if (devinfo->shared.version < BRCMF_PCIE_SHARED_VERSION_7) 1114 ring_itemsize_array = brcmf_ring_itemsize_pre_v7; 1115 else 1116 ring_itemsize_array = brcmf_ring_itemsize; 1117 1118 size = brcmf_ring_max_item[ring_id] * ring_itemsize_array[ring_id]; 1119 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size, 1120 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET, 1121 &dma_handle); 1122 if (!dma_buf) 1123 return NULL; 1124 1125 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET; 1126 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]); 1127 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET; 1128 brcmf_pcie_write_tcm16(devinfo, addr, ring_itemsize_array[ring_id]); 1129 1130 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 1131 if (!ring) { 1132 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf, 1133 dma_handle); 1134 return NULL; 1135 } 1136 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id], 1137 ring_itemsize_array[ring_id], dma_buf); 1138 ring->dma_handle = dma_handle; 1139 ring->devinfo = devinfo; 1140 brcmf_commonring_register_cb(&ring->commonring, 1141 brcmf_pcie_ring_mb_ring_bell, 1142 brcmf_pcie_ring_mb_update_rptr, 1143 brcmf_pcie_ring_mb_update_wptr, 1144 brcmf_pcie_ring_mb_write_rptr, 1145 brcmf_pcie_ring_mb_write_wptr, ring); 1146 1147 return (ring); 1148 } 1149 1150 1151 static void brcmf_pcie_release_ringbuffer(struct device *dev, 1152 struct brcmf_pcie_ringbuf *ring) 1153 { 1154 void *dma_buf; 1155 u32 size; 1156 1157 if (!ring) 1158 return; 1159 1160 dma_buf = ring->commonring.buf_addr; 1161 if (dma_buf) { 1162 size = ring->commonring.depth * ring->commonring.item_len; 1163 dma_free_coherent(dev, size, dma_buf, ring->dma_handle); 1164 } 1165 kfree(ring); 1166 } 1167 1168 1169 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo) 1170 { 1171 u32 i; 1172 1173 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1174 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev, 1175 devinfo->shared.commonrings[i]); 1176 devinfo->shared.commonrings[i] = NULL; 1177 } 1178 kfree(devinfo->shared.flowrings); 1179 devinfo->shared.flowrings = NULL; 1180 if (devinfo->idxbuf) { 1181 dma_free_coherent(&devinfo->pdev->dev, 1182 devinfo->idxbuf_sz, 1183 devinfo->idxbuf, 1184 devinfo->idxbuf_dmahandle); 1185 devinfo->idxbuf = NULL; 1186 } 1187 } 1188 1189 1190 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo) 1191 { 1192 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1193 struct brcmf_pcie_ringbuf *ring; 1194 struct brcmf_pcie_ringbuf *rings; 1195 u32 d2h_w_idx_ptr; 1196 u32 d2h_r_idx_ptr; 1197 u32 h2d_w_idx_ptr; 1198 u32 h2d_r_idx_ptr; 1199 u32 ring_mem_ptr; 1200 u32 i; 1201 u64 address; 1202 u32 bufsz; 1203 u8 idx_offset; 1204 struct brcmf_pcie_dhi_ringinfo ringinfo; 1205 u16 max_flowrings; 1206 u16 max_submissionrings; 1207 u16 max_completionrings; 1208 1209 memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr, 1210 sizeof(ringinfo)); 1211 if (devinfo->shared.version >= 6) { 1212 max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings); 1213 max_flowrings = le16_to_cpu(ringinfo.max_flowrings); 1214 max_completionrings = le16_to_cpu(ringinfo.max_completionrings); 1215 } else { 1216 max_submissionrings = le16_to_cpu(ringinfo.max_flowrings); 1217 max_flowrings = max_submissionrings - 1218 BRCMF_NROF_H2D_COMMON_MSGRINGS; 1219 max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS; 1220 } 1221 1222 if (devinfo->dma_idx_sz != 0) { 1223 bufsz = (max_submissionrings + max_completionrings) * 1224 devinfo->dma_idx_sz * 2; 1225 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz, 1226 &devinfo->idxbuf_dmahandle, 1227 GFP_KERNEL); 1228 if (!devinfo->idxbuf) 1229 devinfo->dma_idx_sz = 0; 1230 } 1231 1232 if (devinfo->dma_idx_sz == 0) { 1233 d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr); 1234 d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr); 1235 h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr); 1236 h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr); 1237 idx_offset = sizeof(u32); 1238 devinfo->write_ptr = brcmf_pcie_write_tcm16; 1239 devinfo->read_ptr = brcmf_pcie_read_tcm16; 1240 brcmf_dbg(PCIE, "Using TCM indices\n"); 1241 } else { 1242 memset(devinfo->idxbuf, 0, bufsz); 1243 devinfo->idxbuf_sz = bufsz; 1244 idx_offset = devinfo->dma_idx_sz; 1245 devinfo->write_ptr = brcmf_pcie_write_idx; 1246 devinfo->read_ptr = brcmf_pcie_read_idx; 1247 1248 h2d_w_idx_ptr = 0; 1249 address = (u64)devinfo->idxbuf_dmahandle; 1250 ringinfo.h2d_w_idx_hostaddr.low_addr = 1251 cpu_to_le32(address & 0xffffffff); 1252 ringinfo.h2d_w_idx_hostaddr.high_addr = 1253 cpu_to_le32(address >> 32); 1254 1255 h2d_r_idx_ptr = h2d_w_idx_ptr + 1256 max_submissionrings * idx_offset; 1257 address += max_submissionrings * idx_offset; 1258 ringinfo.h2d_r_idx_hostaddr.low_addr = 1259 cpu_to_le32(address & 0xffffffff); 1260 ringinfo.h2d_r_idx_hostaddr.high_addr = 1261 cpu_to_le32(address >> 32); 1262 1263 d2h_w_idx_ptr = h2d_r_idx_ptr + 1264 max_submissionrings * idx_offset; 1265 address += max_submissionrings * idx_offset; 1266 ringinfo.d2h_w_idx_hostaddr.low_addr = 1267 cpu_to_le32(address & 0xffffffff); 1268 ringinfo.d2h_w_idx_hostaddr.high_addr = 1269 cpu_to_le32(address >> 32); 1270 1271 d2h_r_idx_ptr = d2h_w_idx_ptr + 1272 max_completionrings * idx_offset; 1273 address += max_completionrings * idx_offset; 1274 ringinfo.d2h_r_idx_hostaddr.low_addr = 1275 cpu_to_le32(address & 0xffffffff); 1276 ringinfo.d2h_r_idx_hostaddr.high_addr = 1277 cpu_to_le32(address >> 32); 1278 1279 memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr, 1280 &ringinfo, sizeof(ringinfo)); 1281 brcmf_dbg(PCIE, "Using host memory indices\n"); 1282 } 1283 1284 ring_mem_ptr = le32_to_cpu(ringinfo.ringmem); 1285 1286 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) { 1287 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1288 if (!ring) 1289 goto fail; 1290 ring->w_idx_addr = h2d_w_idx_ptr; 1291 ring->r_idx_addr = h2d_r_idx_ptr; 1292 ring->id = i; 1293 devinfo->shared.commonrings[i] = ring; 1294 1295 h2d_w_idx_ptr += idx_offset; 1296 h2d_r_idx_ptr += idx_offset; 1297 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1298 } 1299 1300 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS; 1301 i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1302 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1303 if (!ring) 1304 goto fail; 1305 ring->w_idx_addr = d2h_w_idx_ptr; 1306 ring->r_idx_addr = d2h_r_idx_ptr; 1307 ring->id = i; 1308 devinfo->shared.commonrings[i] = ring; 1309 1310 d2h_w_idx_ptr += idx_offset; 1311 d2h_r_idx_ptr += idx_offset; 1312 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1313 } 1314 1315 devinfo->shared.max_flowrings = max_flowrings; 1316 devinfo->shared.max_submissionrings = max_submissionrings; 1317 devinfo->shared.max_completionrings = max_completionrings; 1318 rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL); 1319 if (!rings) 1320 goto fail; 1321 1322 brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings); 1323 1324 for (i = 0; i < max_flowrings; i++) { 1325 ring = &rings[i]; 1326 ring->devinfo = devinfo; 1327 ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART; 1328 brcmf_commonring_register_cb(&ring->commonring, 1329 brcmf_pcie_ring_mb_ring_bell, 1330 brcmf_pcie_ring_mb_update_rptr, 1331 brcmf_pcie_ring_mb_update_wptr, 1332 brcmf_pcie_ring_mb_write_rptr, 1333 brcmf_pcie_ring_mb_write_wptr, 1334 ring); 1335 ring->w_idx_addr = h2d_w_idx_ptr; 1336 ring->r_idx_addr = h2d_r_idx_ptr; 1337 h2d_w_idx_ptr += idx_offset; 1338 h2d_r_idx_ptr += idx_offset; 1339 } 1340 devinfo->shared.flowrings = rings; 1341 1342 return 0; 1343 1344 fail: 1345 brcmf_err(bus, "Allocating ring buffers failed\n"); 1346 brcmf_pcie_release_ringbuffers(devinfo); 1347 return -ENOMEM; 1348 } 1349 1350 1351 static void 1352 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1353 { 1354 if (devinfo->shared.scratch) 1355 dma_free_coherent(&devinfo->pdev->dev, 1356 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1357 devinfo->shared.scratch, 1358 devinfo->shared.scratch_dmahandle); 1359 if (devinfo->shared.ringupd) 1360 dma_free_coherent(&devinfo->pdev->dev, 1361 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1362 devinfo->shared.ringupd, 1363 devinfo->shared.ringupd_dmahandle); 1364 } 1365 1366 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1367 { 1368 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1369 u64 address; 1370 u32 addr; 1371 1372 devinfo->shared.scratch = 1373 dma_alloc_coherent(&devinfo->pdev->dev, 1374 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1375 &devinfo->shared.scratch_dmahandle, 1376 GFP_KERNEL); 1377 if (!devinfo->shared.scratch) 1378 goto fail; 1379 1380 addr = devinfo->shared.tcm_base_address + 1381 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET; 1382 address = (u64)devinfo->shared.scratch_dmahandle; 1383 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1384 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1385 addr = devinfo->shared.tcm_base_address + 1386 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET; 1387 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); 1388 1389 devinfo->shared.ringupd = 1390 dma_alloc_coherent(&devinfo->pdev->dev, 1391 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1392 &devinfo->shared.ringupd_dmahandle, 1393 GFP_KERNEL); 1394 if (!devinfo->shared.ringupd) 1395 goto fail; 1396 1397 addr = devinfo->shared.tcm_base_address + 1398 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET; 1399 address = (u64)devinfo->shared.ringupd_dmahandle; 1400 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1401 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1402 addr = devinfo->shared.tcm_base_address + 1403 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET; 1404 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); 1405 return 0; 1406 1407 fail: 1408 brcmf_err(bus, "Allocating scratch buffers failed\n"); 1409 brcmf_pcie_release_scratchbuffers(devinfo); 1410 return -ENOMEM; 1411 } 1412 1413 1414 static void brcmf_pcie_down(struct device *dev) 1415 { 1416 } 1417 1418 static int brcmf_pcie_preinit(struct device *dev) 1419 { 1420 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1421 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1422 1423 brcmf_dbg(PCIE, "Enter\n"); 1424 1425 brcmf_pcie_intr_enable(buspub->devinfo); 1426 brcmf_pcie_hostready(buspub->devinfo); 1427 1428 return 0; 1429 } 1430 1431 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb) 1432 { 1433 return 0; 1434 } 1435 1436 1437 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg, 1438 uint len) 1439 { 1440 return 0; 1441 } 1442 1443 1444 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg, 1445 uint len) 1446 { 1447 return 0; 1448 } 1449 1450 1451 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled) 1452 { 1453 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1454 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1455 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1456 1457 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled); 1458 devinfo->wowl_enabled = enabled; 1459 } 1460 1461 1462 static size_t brcmf_pcie_get_ramsize(struct device *dev) 1463 { 1464 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1465 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1466 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1467 1468 return devinfo->ci->ramsize - devinfo->ci->srsize; 1469 } 1470 1471 1472 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len) 1473 { 1474 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1475 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1476 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1477 1478 brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len); 1479 brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len); 1480 return 0; 1481 } 1482 1483 static int brcmf_pcie_get_blob(struct device *dev, const struct firmware **fw, 1484 enum brcmf_blob_type type) 1485 { 1486 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1487 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1488 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1489 1490 switch (type) { 1491 case BRCMF_BLOB_CLM: 1492 *fw = devinfo->clm_fw; 1493 devinfo->clm_fw = NULL; 1494 break; 1495 default: 1496 return -ENOENT; 1497 } 1498 1499 if (!*fw) 1500 return -ENOENT; 1501 1502 return 0; 1503 } 1504 1505 static int brcmf_pcie_reset(struct device *dev) 1506 { 1507 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1508 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1509 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1510 struct brcmf_fw_request *fwreq; 1511 int err; 1512 1513 brcmf_pcie_intr_disable(devinfo); 1514 1515 brcmf_pcie_bus_console_read(devinfo, true); 1516 1517 brcmf_detach(dev); 1518 1519 brcmf_pcie_release_irq(devinfo); 1520 brcmf_pcie_release_scratchbuffers(devinfo); 1521 brcmf_pcie_release_ringbuffers(devinfo); 1522 brcmf_pcie_reset_device(devinfo); 1523 1524 fwreq = brcmf_pcie_prepare_fw_request(devinfo); 1525 if (!fwreq) { 1526 dev_err(dev, "Failed to prepare FW request\n"); 1527 return -ENOMEM; 1528 } 1529 1530 err = brcmf_fw_get_firmwares(dev, fwreq, brcmf_pcie_setup); 1531 if (err) { 1532 dev_err(dev, "Failed to prepare FW request\n"); 1533 kfree(fwreq); 1534 } 1535 1536 return err; 1537 } 1538 1539 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = { 1540 .preinit = brcmf_pcie_preinit, 1541 .txdata = brcmf_pcie_tx, 1542 .stop = brcmf_pcie_down, 1543 .txctl = brcmf_pcie_tx_ctlpkt, 1544 .rxctl = brcmf_pcie_rx_ctlpkt, 1545 .wowl_config = brcmf_pcie_wowl_config, 1546 .get_ramsize = brcmf_pcie_get_ramsize, 1547 .get_memdump = brcmf_pcie_get_memdump, 1548 .get_blob = brcmf_pcie_get_blob, 1549 .reset = brcmf_pcie_reset, 1550 }; 1551 1552 1553 static void 1554 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data, 1555 u32 data_len) 1556 { 1557 __le32 *field; 1558 u32 newsize; 1559 1560 if (data_len < BRCMF_RAMSIZE_OFFSET + 8) 1561 return; 1562 1563 field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET]; 1564 if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC) 1565 return; 1566 field++; 1567 newsize = le32_to_cpup(field); 1568 1569 brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n", 1570 newsize); 1571 devinfo->ci->ramsize = newsize; 1572 } 1573 1574 1575 static int 1576 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo, 1577 u32 sharedram_addr) 1578 { 1579 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1580 struct brcmf_pcie_shared_info *shared; 1581 u32 addr; 1582 1583 shared = &devinfo->shared; 1584 shared->tcm_base_address = sharedram_addr; 1585 1586 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr); 1587 shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK); 1588 brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version); 1589 if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) || 1590 (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) { 1591 brcmf_err(bus, "Unsupported PCIE version %d\n", 1592 shared->version); 1593 return -EINVAL; 1594 } 1595 1596 /* check firmware support dma indicies */ 1597 if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) { 1598 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX) 1599 devinfo->dma_idx_sz = sizeof(u16); 1600 else 1601 devinfo->dma_idx_sz = sizeof(u32); 1602 } 1603 1604 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET; 1605 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr); 1606 if (shared->max_rxbufpost == 0) 1607 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST; 1608 1609 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET; 1610 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr); 1611 1612 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET; 1613 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1614 1615 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET; 1616 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1617 1618 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET; 1619 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1620 1621 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n", 1622 shared->max_rxbufpost, shared->rx_dataoffset); 1623 1624 brcmf_pcie_bus_console_init(devinfo); 1625 brcmf_pcie_bus_console_read(devinfo, false); 1626 1627 return 0; 1628 } 1629 1630 1631 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo, 1632 const struct firmware *fw, void *nvram, 1633 u32 nvram_len) 1634 { 1635 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1636 u32 sharedram_addr; 1637 u32 sharedram_addr_written; 1638 u32 loop_counter; 1639 int err; 1640 u32 address; 1641 u32 resetintr; 1642 1643 brcmf_dbg(PCIE, "Halt ARM.\n"); 1644 err = brcmf_pcie_enter_download_state(devinfo); 1645 if (err) 1646 return err; 1647 1648 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name); 1649 memcpy_toio(devinfo->tcm + devinfo->ci->rambase, 1650 (void *)fw->data, fw->size); 1651 1652 resetintr = get_unaligned_le32(fw->data); 1653 release_firmware(fw); 1654 1655 /* reset last 4 bytes of RAM address. to be used for shared 1656 * area. This identifies when FW is running 1657 */ 1658 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0); 1659 1660 if (nvram) { 1661 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name); 1662 address = devinfo->ci->rambase + devinfo->ci->ramsize - 1663 nvram_len; 1664 memcpy_toio(devinfo->tcm + address, nvram, nvram_len); 1665 brcmf_fw_nvram_free(nvram); 1666 } else { 1667 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n", 1668 devinfo->nvram_name); 1669 } 1670 1671 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo, 1672 devinfo->ci->ramsize - 1673 4); 1674 brcmf_dbg(PCIE, "Bring ARM in running state\n"); 1675 err = brcmf_pcie_exit_download_state(devinfo, resetintr); 1676 if (err) 1677 return err; 1678 1679 brcmf_dbg(PCIE, "Wait for FW init\n"); 1680 sharedram_addr = sharedram_addr_written; 1681 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50; 1682 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) { 1683 msleep(50); 1684 sharedram_addr = brcmf_pcie_read_ram32(devinfo, 1685 devinfo->ci->ramsize - 1686 4); 1687 loop_counter--; 1688 } 1689 if (sharedram_addr == sharedram_addr_written) { 1690 brcmf_err(bus, "FW failed to initialize\n"); 1691 return -ENODEV; 1692 } 1693 if (sharedram_addr < devinfo->ci->rambase || 1694 sharedram_addr >= devinfo->ci->rambase + devinfo->ci->ramsize) { 1695 brcmf_err(bus, "Invalid shared RAM address 0x%08x\n", 1696 sharedram_addr); 1697 return -ENODEV; 1698 } 1699 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr); 1700 1701 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr)); 1702 } 1703 1704 1705 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo) 1706 { 1707 struct pci_dev *pdev = devinfo->pdev; 1708 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 1709 int err; 1710 phys_addr_t bar0_addr, bar1_addr; 1711 ulong bar1_size; 1712 1713 err = pci_enable_device(pdev); 1714 if (err) { 1715 brcmf_err(bus, "pci_enable_device failed err=%d\n", err); 1716 return err; 1717 } 1718 1719 pci_set_master(pdev); 1720 1721 /* Bar-0 mapped address */ 1722 bar0_addr = pci_resource_start(pdev, 0); 1723 /* Bar-1 mapped address */ 1724 bar1_addr = pci_resource_start(pdev, 2); 1725 /* read Bar-1 mapped memory range */ 1726 bar1_size = pci_resource_len(pdev, 2); 1727 if ((bar1_size == 0) || (bar1_addr == 0)) { 1728 brcmf_err(bus, "BAR1 Not enabled, device size=%ld, addr=%#016llx\n", 1729 bar1_size, (unsigned long long)bar1_addr); 1730 return -EINVAL; 1731 } 1732 1733 devinfo->regs = ioremap(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE); 1734 devinfo->tcm = ioremap(bar1_addr, bar1_size); 1735 1736 if (!devinfo->regs || !devinfo->tcm) { 1737 brcmf_err(bus, "ioremap() failed (%p,%p)\n", devinfo->regs, 1738 devinfo->tcm); 1739 return -EINVAL; 1740 } 1741 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n", 1742 devinfo->regs, (unsigned long long)bar0_addr); 1743 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n", 1744 devinfo->tcm, (unsigned long long)bar1_addr, 1745 (unsigned int)bar1_size); 1746 1747 return 0; 1748 } 1749 1750 1751 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo) 1752 { 1753 if (devinfo->tcm) 1754 iounmap(devinfo->tcm); 1755 if (devinfo->regs) 1756 iounmap(devinfo->regs); 1757 1758 pci_disable_device(devinfo->pdev); 1759 } 1760 1761 1762 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr) 1763 { 1764 u32 ret_addr; 1765 1766 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1); 1767 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1); 1768 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr); 1769 1770 return ret_addr; 1771 } 1772 1773 1774 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr) 1775 { 1776 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1777 1778 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1779 return brcmf_pcie_read_reg32(devinfo, addr); 1780 } 1781 1782 1783 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value) 1784 { 1785 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1786 1787 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1788 brcmf_pcie_write_reg32(devinfo, addr, value); 1789 } 1790 1791 1792 static int brcmf_pcie_buscoreprep(void *ctx) 1793 { 1794 return brcmf_pcie_get_resource(ctx); 1795 } 1796 1797 1798 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip) 1799 { 1800 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1801 struct brcmf_core *core; 1802 u32 val, reg; 1803 1804 devinfo->ci = chip; 1805 brcmf_pcie_reset_device(devinfo); 1806 1807 /* reginfo is not ready yet */ 1808 core = brcmf_chip_get_core(chip, BCMA_CORE_PCIE2); 1809 if (core->rev >= 64) 1810 reg = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT; 1811 else 1812 reg = BRCMF_PCIE_PCIE2REG_MAILBOXINT; 1813 1814 val = brcmf_pcie_read_reg32(devinfo, reg); 1815 if (val != 0xffffffff) 1816 brcmf_pcie_write_reg32(devinfo, reg, val); 1817 1818 return 0; 1819 } 1820 1821 1822 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip, 1823 u32 rstvec) 1824 { 1825 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1826 1827 brcmf_pcie_write_tcm32(devinfo, 0, rstvec); 1828 } 1829 1830 1831 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = { 1832 .prepare = brcmf_pcie_buscoreprep, 1833 .reset = brcmf_pcie_buscore_reset, 1834 .activate = brcmf_pcie_buscore_activate, 1835 .read32 = brcmf_pcie_buscore_read32, 1836 .write32 = brcmf_pcie_buscore_write32, 1837 }; 1838 1839 #define BRCMF_OTP_SYS_VENDOR 0x15 1840 #define BRCMF_OTP_BRCM_CIS 0x80 1841 1842 #define BRCMF_OTP_VENDOR_HDR 0x00000008 1843 1844 static int 1845 brcmf_pcie_parse_otp_sys_vendor(struct brcmf_pciedev_info *devinfo, 1846 u8 *data, size_t size) 1847 { 1848 int idx = 4; 1849 const char *chip_params; 1850 const char *board_params; 1851 const char *p; 1852 1853 /* 4-byte header and two empty strings */ 1854 if (size < 6) 1855 return -EINVAL; 1856 1857 if (get_unaligned_le32(data) != BRCMF_OTP_VENDOR_HDR) 1858 return -EINVAL; 1859 1860 chip_params = &data[idx]; 1861 1862 /* Skip first string, including terminator */ 1863 idx += strnlen(chip_params, size - idx) + 1; 1864 if (idx >= size) 1865 return -EINVAL; 1866 1867 board_params = &data[idx]; 1868 1869 /* Skip to terminator of second string */ 1870 idx += strnlen(board_params, size - idx); 1871 if (idx >= size) 1872 return -EINVAL; 1873 1874 /* At this point both strings are guaranteed NUL-terminated */ 1875 brcmf_dbg(PCIE, "OTP: chip_params='%s' board_params='%s'\n", 1876 chip_params, board_params); 1877 1878 p = skip_spaces(board_params); 1879 while (*p) { 1880 char tag = *p++; 1881 const char *end; 1882 size_t len; 1883 1884 if (*p++ != '=') /* implicit NUL check */ 1885 return -EINVAL; 1886 1887 /* *p might be NUL here, if so end == p and len == 0 */ 1888 end = strchrnul(p, ' '); 1889 len = end - p; 1890 1891 /* leave 1 byte for NUL in destination string */ 1892 if (len > (BRCMF_OTP_MAX_PARAM_LEN - 1)) 1893 return -EINVAL; 1894 1895 /* Copy len characters plus a NUL terminator */ 1896 switch (tag) { 1897 case 'M': 1898 strscpy(devinfo->otp.module, p, len + 1); 1899 break; 1900 case 'V': 1901 strscpy(devinfo->otp.vendor, p, len + 1); 1902 break; 1903 case 'm': 1904 strscpy(devinfo->otp.version, p, len + 1); 1905 break; 1906 } 1907 1908 /* Skip to next arg, if any */ 1909 p = skip_spaces(end); 1910 } 1911 1912 brcmf_dbg(PCIE, "OTP: module=%s vendor=%s version=%s\n", 1913 devinfo->otp.module, devinfo->otp.vendor, 1914 devinfo->otp.version); 1915 1916 if (!devinfo->otp.module[0] || 1917 !devinfo->otp.vendor[0] || 1918 !devinfo->otp.version[0]) 1919 return -EINVAL; 1920 1921 devinfo->otp.valid = true; 1922 return 0; 1923 } 1924 1925 static int 1926 brcmf_pcie_parse_otp(struct brcmf_pciedev_info *devinfo, u8 *otp, size_t size) 1927 { 1928 int p = 0; 1929 int ret = -EINVAL; 1930 1931 brcmf_dbg(PCIE, "parse_otp size=%zd\n", size); 1932 1933 while (p < (size - 1)) { 1934 u8 type = otp[p]; 1935 u8 length = otp[p + 1]; 1936 1937 if (type == 0) 1938 break; 1939 1940 if ((p + 2 + length) > size) 1941 break; 1942 1943 switch (type) { 1944 case BRCMF_OTP_SYS_VENDOR: 1945 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): SYS_VENDOR\n", 1946 p, length); 1947 ret = brcmf_pcie_parse_otp_sys_vendor(devinfo, 1948 &otp[p + 2], 1949 length); 1950 break; 1951 case BRCMF_OTP_BRCM_CIS: 1952 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): BRCM_CIS\n", 1953 p, length); 1954 break; 1955 default: 1956 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): Unknown type 0x%x\n", 1957 p, length, type); 1958 break; 1959 } 1960 1961 p += 2 + length; 1962 } 1963 1964 return ret; 1965 } 1966 1967 static int brcmf_pcie_read_otp(struct brcmf_pciedev_info *devinfo) 1968 { 1969 const struct pci_dev *pdev = devinfo->pdev; 1970 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 1971 u32 coreid, base, words, idx, sromctl; 1972 u16 *otp; 1973 struct brcmf_core *core; 1974 int ret; 1975 1976 switch (devinfo->ci->chip) { 1977 case BRCM_CC_4378_CHIP_ID: 1978 coreid = BCMA_CORE_GCI; 1979 base = 0x1120; 1980 words = 0x170; 1981 break; 1982 default: 1983 /* OTP not supported on this chip */ 1984 return 0; 1985 } 1986 1987 core = brcmf_chip_get_core(devinfo->ci, coreid); 1988 if (!core) { 1989 brcmf_err(bus, "No OTP core\n"); 1990 return -ENODEV; 1991 } 1992 1993 if (coreid == BCMA_CORE_CHIPCOMMON) { 1994 /* Chips with OTP accessed via ChipCommon need additional 1995 * handling to access the OTP 1996 */ 1997 brcmf_pcie_select_core(devinfo, coreid); 1998 sromctl = READCC32(devinfo, sromcontrol); 1999 2000 if (!(sromctl & BCMA_CC_SROM_CONTROL_OTP_PRESENT)) { 2001 /* Chip lacks OTP, try without it... */ 2002 brcmf_err(bus, 2003 "OTP unavailable, using default firmware\n"); 2004 return 0; 2005 } 2006 2007 /* Map OTP to shadow area */ 2008 WRITECC32(devinfo, sromcontrol, 2009 sromctl | BCMA_CC_SROM_CONTROL_OTPSEL); 2010 } 2011 2012 otp = kcalloc(words, sizeof(u16), GFP_KERNEL); 2013 if (!otp) 2014 return -ENOMEM; 2015 2016 /* Map bus window to SROM/OTP shadow area in core */ 2017 base = brcmf_pcie_buscore_prep_addr(devinfo->pdev, base + core->base); 2018 2019 brcmf_dbg(PCIE, "OTP data:\n"); 2020 for (idx = 0; idx < words; idx++) { 2021 otp[idx] = brcmf_pcie_read_reg16(devinfo, base + 2 * idx); 2022 brcmf_dbg(PCIE, "[%8x] 0x%04x\n", base + 2 * idx, otp[idx]); 2023 } 2024 2025 if (coreid == BCMA_CORE_CHIPCOMMON) { 2026 brcmf_pcie_select_core(devinfo, coreid); 2027 WRITECC32(devinfo, sromcontrol, sromctl); 2028 } 2029 2030 ret = brcmf_pcie_parse_otp(devinfo, (u8 *)otp, 2 * words); 2031 kfree(otp); 2032 2033 return ret; 2034 } 2035 2036 #define BRCMF_PCIE_FW_CODE 0 2037 #define BRCMF_PCIE_FW_NVRAM 1 2038 #define BRCMF_PCIE_FW_CLM 2 2039 2040 static void brcmf_pcie_setup(struct device *dev, int ret, 2041 struct brcmf_fw_request *fwreq) 2042 { 2043 const struct firmware *fw; 2044 void *nvram; 2045 struct brcmf_bus *bus; 2046 struct brcmf_pciedev *pcie_bus_dev; 2047 struct brcmf_pciedev_info *devinfo; 2048 struct brcmf_commonring **flowrings; 2049 u32 i, nvram_len; 2050 2051 /* check firmware loading result */ 2052 if (ret) 2053 goto fail; 2054 2055 bus = dev_get_drvdata(dev); 2056 pcie_bus_dev = bus->bus_priv.pcie; 2057 devinfo = pcie_bus_dev->devinfo; 2058 brcmf_pcie_attach(devinfo); 2059 2060 fw = fwreq->items[BRCMF_PCIE_FW_CODE].binary; 2061 nvram = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.data; 2062 nvram_len = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.len; 2063 devinfo->clm_fw = fwreq->items[BRCMF_PCIE_FW_CLM].binary; 2064 kfree(fwreq); 2065 2066 ret = brcmf_chip_get_raminfo(devinfo->ci); 2067 if (ret) { 2068 brcmf_err(bus, "Failed to get RAM info\n"); 2069 release_firmware(fw); 2070 brcmf_fw_nvram_free(nvram); 2071 goto fail; 2072 } 2073 2074 /* Some of the firmwares have the size of the memory of the device 2075 * defined inside the firmware. This is because part of the memory in 2076 * the device is shared and the devision is determined by FW. Parse 2077 * the firmware and adjust the chip memory size now. 2078 */ 2079 brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size); 2080 2081 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len); 2082 if (ret) 2083 goto fail; 2084 2085 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 2086 2087 ret = brcmf_pcie_init_ringbuffers(devinfo); 2088 if (ret) 2089 goto fail; 2090 2091 ret = brcmf_pcie_init_scratchbuffers(devinfo); 2092 if (ret) 2093 goto fail; 2094 2095 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 2096 ret = brcmf_pcie_request_irq(devinfo); 2097 if (ret) 2098 goto fail; 2099 2100 /* hook the commonrings in the bus structure. */ 2101 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) 2102 bus->msgbuf->commonrings[i] = 2103 &devinfo->shared.commonrings[i]->commonring; 2104 2105 flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings), 2106 GFP_KERNEL); 2107 if (!flowrings) 2108 goto fail; 2109 2110 for (i = 0; i < devinfo->shared.max_flowrings; i++) 2111 flowrings[i] = &devinfo->shared.flowrings[i].commonring; 2112 bus->msgbuf->flowrings = flowrings; 2113 2114 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset; 2115 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost; 2116 bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings; 2117 2118 init_waitqueue_head(&devinfo->mbdata_resp_wait); 2119 2120 ret = brcmf_attach(&devinfo->pdev->dev); 2121 if (ret) 2122 goto fail; 2123 2124 brcmf_pcie_bus_console_read(devinfo, false); 2125 2126 return; 2127 2128 fail: 2129 device_release_driver(dev); 2130 } 2131 2132 static struct brcmf_fw_request * 2133 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo) 2134 { 2135 struct brcmf_fw_request *fwreq; 2136 struct brcmf_fw_name fwnames[] = { 2137 { ".bin", devinfo->fw_name }, 2138 { ".txt", devinfo->nvram_name }, 2139 { ".clm_blob", devinfo->clm_name }, 2140 }; 2141 2142 fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev, 2143 brcmf_pcie_fwnames, 2144 ARRAY_SIZE(brcmf_pcie_fwnames), 2145 fwnames, ARRAY_SIZE(fwnames)); 2146 if (!fwreq) 2147 return NULL; 2148 2149 fwreq->items[BRCMF_PCIE_FW_CODE].type = BRCMF_FW_TYPE_BINARY; 2150 fwreq->items[BRCMF_PCIE_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM; 2151 fwreq->items[BRCMF_PCIE_FW_NVRAM].flags = BRCMF_FW_REQF_OPTIONAL; 2152 fwreq->items[BRCMF_PCIE_FW_CLM].type = BRCMF_FW_TYPE_BINARY; 2153 fwreq->items[BRCMF_PCIE_FW_CLM].flags = BRCMF_FW_REQF_OPTIONAL; 2154 /* NVRAM reserves PCI domain 0 for Broadcom's SDK faked bus */ 2155 fwreq->domain_nr = pci_domain_nr(devinfo->pdev->bus) + 1; 2156 fwreq->bus_nr = devinfo->pdev->bus->number; 2157 2158 /* Apple platforms with fancy firmware/NVRAM selection */ 2159 if (devinfo->settings->board_type && 2160 devinfo->settings->antenna_sku && 2161 devinfo->otp.valid) { 2162 const struct brcmf_otp_params *otp = &devinfo->otp; 2163 struct device *dev = &devinfo->pdev->dev; 2164 const char **bt = fwreq->board_types; 2165 2166 brcmf_dbg(PCIE, "Apple board: %s\n", 2167 devinfo->settings->board_type); 2168 2169 /* Example: apple,shikoku-RASP-m-6.11-X3 */ 2170 bt[0] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s-%s", 2171 devinfo->settings->board_type, 2172 otp->module, otp->vendor, otp->version, 2173 devinfo->settings->antenna_sku); 2174 bt[1] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s", 2175 devinfo->settings->board_type, 2176 otp->module, otp->vendor, otp->version); 2177 bt[2] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s", 2178 devinfo->settings->board_type, 2179 otp->module, otp->vendor); 2180 bt[3] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s", 2181 devinfo->settings->board_type, 2182 otp->module); 2183 bt[4] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s", 2184 devinfo->settings->board_type, 2185 devinfo->settings->antenna_sku); 2186 bt[5] = devinfo->settings->board_type; 2187 2188 if (!bt[0] || !bt[1] || !bt[2] || !bt[3] || !bt[4]) { 2189 kfree(fwreq); 2190 return NULL; 2191 } 2192 } else { 2193 brcmf_dbg(PCIE, "Board: %s\n", devinfo->settings->board_type); 2194 fwreq->board_types[0] = devinfo->settings->board_type; 2195 } 2196 2197 return fwreq; 2198 } 2199 2200 static int 2201 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2202 { 2203 int ret; 2204 struct brcmf_fw_request *fwreq; 2205 struct brcmf_pciedev_info *devinfo; 2206 struct brcmf_pciedev *pcie_bus_dev; 2207 struct brcmf_core *core; 2208 struct brcmf_bus *bus; 2209 2210 brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device); 2211 2212 ret = -ENOMEM; 2213 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL); 2214 if (devinfo == NULL) 2215 return ret; 2216 2217 devinfo->pdev = pdev; 2218 pcie_bus_dev = NULL; 2219 devinfo->ci = brcmf_chip_attach(devinfo, pdev->device, 2220 &brcmf_pcie_buscore_ops); 2221 if (IS_ERR(devinfo->ci)) { 2222 ret = PTR_ERR(devinfo->ci); 2223 devinfo->ci = NULL; 2224 goto fail; 2225 } 2226 2227 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 2228 if (core->rev >= 64) 2229 devinfo->reginfo = &brcmf_reginfo_64; 2230 else 2231 devinfo->reginfo = &brcmf_reginfo_default; 2232 2233 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL); 2234 if (pcie_bus_dev == NULL) { 2235 ret = -ENOMEM; 2236 goto fail; 2237 } 2238 2239 devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev, 2240 BRCMF_BUSTYPE_PCIE, 2241 devinfo->ci->chip, 2242 devinfo->ci->chiprev); 2243 if (!devinfo->settings) { 2244 ret = -ENOMEM; 2245 goto fail; 2246 } 2247 2248 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 2249 if (!bus) { 2250 ret = -ENOMEM; 2251 goto fail; 2252 } 2253 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL); 2254 if (!bus->msgbuf) { 2255 ret = -ENOMEM; 2256 kfree(bus); 2257 goto fail; 2258 } 2259 2260 /* hook it all together. */ 2261 pcie_bus_dev->devinfo = devinfo; 2262 pcie_bus_dev->bus = bus; 2263 bus->dev = &pdev->dev; 2264 bus->bus_priv.pcie = pcie_bus_dev; 2265 bus->ops = &brcmf_pcie_bus_ops; 2266 bus->proto_type = BRCMF_PROTO_MSGBUF; 2267 bus->chip = devinfo->coreid; 2268 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot); 2269 dev_set_drvdata(&pdev->dev, bus); 2270 2271 ret = brcmf_alloc(&devinfo->pdev->dev, devinfo->settings); 2272 if (ret) 2273 goto fail_bus; 2274 2275 ret = brcmf_pcie_read_otp(devinfo); 2276 if (ret) { 2277 brcmf_err(bus, "failed to parse OTP\n"); 2278 goto fail_brcmf; 2279 } 2280 2281 fwreq = brcmf_pcie_prepare_fw_request(devinfo); 2282 if (!fwreq) { 2283 ret = -ENOMEM; 2284 goto fail_brcmf; 2285 } 2286 2287 ret = brcmf_fw_get_firmwares(bus->dev, fwreq, brcmf_pcie_setup); 2288 if (ret < 0) { 2289 kfree(fwreq); 2290 goto fail_brcmf; 2291 } 2292 return 0; 2293 2294 fail_brcmf: 2295 brcmf_free(&devinfo->pdev->dev); 2296 fail_bus: 2297 kfree(bus->msgbuf); 2298 kfree(bus); 2299 fail: 2300 brcmf_err(NULL, "failed %x:%x\n", pdev->vendor, pdev->device); 2301 brcmf_pcie_release_resource(devinfo); 2302 if (devinfo->ci) 2303 brcmf_chip_detach(devinfo->ci); 2304 if (devinfo->settings) 2305 brcmf_release_module_param(devinfo->settings); 2306 kfree(pcie_bus_dev); 2307 kfree(devinfo); 2308 return ret; 2309 } 2310 2311 2312 static void 2313 brcmf_pcie_remove(struct pci_dev *pdev) 2314 { 2315 struct brcmf_pciedev_info *devinfo; 2316 struct brcmf_bus *bus; 2317 2318 brcmf_dbg(PCIE, "Enter\n"); 2319 2320 bus = dev_get_drvdata(&pdev->dev); 2321 if (bus == NULL) 2322 return; 2323 2324 devinfo = bus->bus_priv.pcie->devinfo; 2325 brcmf_pcie_bus_console_read(devinfo, false); 2326 2327 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 2328 if (devinfo->ci) 2329 brcmf_pcie_intr_disable(devinfo); 2330 2331 brcmf_detach(&pdev->dev); 2332 brcmf_free(&pdev->dev); 2333 2334 kfree(bus->bus_priv.pcie); 2335 kfree(bus->msgbuf->flowrings); 2336 kfree(bus->msgbuf); 2337 kfree(bus); 2338 2339 brcmf_pcie_release_irq(devinfo); 2340 brcmf_pcie_release_scratchbuffers(devinfo); 2341 brcmf_pcie_release_ringbuffers(devinfo); 2342 brcmf_pcie_reset_device(devinfo); 2343 brcmf_pcie_release_resource(devinfo); 2344 release_firmware(devinfo->clm_fw); 2345 2346 if (devinfo->ci) 2347 brcmf_chip_detach(devinfo->ci); 2348 if (devinfo->settings) 2349 brcmf_release_module_param(devinfo->settings); 2350 2351 kfree(devinfo); 2352 dev_set_drvdata(&pdev->dev, NULL); 2353 } 2354 2355 2356 #ifdef CONFIG_PM 2357 2358 2359 static int brcmf_pcie_pm_enter_D3(struct device *dev) 2360 { 2361 struct brcmf_pciedev_info *devinfo; 2362 struct brcmf_bus *bus; 2363 2364 brcmf_dbg(PCIE, "Enter\n"); 2365 2366 bus = dev_get_drvdata(dev); 2367 devinfo = bus->bus_priv.pcie->devinfo; 2368 2369 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN); 2370 2371 devinfo->mbdata_completed = false; 2372 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM); 2373 2374 wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed, 2375 BRCMF_PCIE_MBDATA_TIMEOUT); 2376 if (!devinfo->mbdata_completed) { 2377 brcmf_err(bus, "Timeout on response for entering D3 substate\n"); 2378 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 2379 return -EIO; 2380 } 2381 2382 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 2383 2384 return 0; 2385 } 2386 2387 2388 static int brcmf_pcie_pm_leave_D3(struct device *dev) 2389 { 2390 struct brcmf_pciedev_info *devinfo; 2391 struct brcmf_bus *bus; 2392 struct pci_dev *pdev; 2393 int err; 2394 2395 brcmf_dbg(PCIE, "Enter\n"); 2396 2397 bus = dev_get_drvdata(dev); 2398 devinfo = bus->bus_priv.pcie->devinfo; 2399 brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus); 2400 2401 /* Check if device is still up and running, if so we are ready */ 2402 if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->intmask) != 0) { 2403 brcmf_dbg(PCIE, "Try to wakeup device....\n"); 2404 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM)) 2405 goto cleanup; 2406 brcmf_dbg(PCIE, "Hot resume, continue....\n"); 2407 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 2408 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 2409 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 2410 brcmf_pcie_intr_enable(devinfo); 2411 brcmf_pcie_hostready(devinfo); 2412 return 0; 2413 } 2414 2415 cleanup: 2416 brcmf_chip_detach(devinfo->ci); 2417 devinfo->ci = NULL; 2418 pdev = devinfo->pdev; 2419 brcmf_pcie_remove(pdev); 2420 2421 err = brcmf_pcie_probe(pdev, NULL); 2422 if (err) 2423 __brcmf_err(NULL, __func__, "probe after resume failed, err=%d\n", err); 2424 2425 return err; 2426 } 2427 2428 2429 static const struct dev_pm_ops brcmf_pciedrvr_pm = { 2430 .suspend = brcmf_pcie_pm_enter_D3, 2431 .resume = brcmf_pcie_pm_leave_D3, 2432 .freeze = brcmf_pcie_pm_enter_D3, 2433 .restore = brcmf_pcie_pm_leave_D3, 2434 }; 2435 2436 2437 #endif /* CONFIG_PM */ 2438 2439 2440 #define BRCMF_PCIE_DEVICE(dev_id) { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\ 2441 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 } 2442 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev) { \ 2443 BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\ 2444 subvend, subdev, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 } 2445 2446 static const struct pci_device_id brcmf_pcie_devid_table[] = { 2447 BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID), 2448 BRCMF_PCIE_DEVICE_SUB(0x4355, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4355), 2449 BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_RAW_DEVICE_ID), 2450 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID), 2451 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID), 2452 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID), 2453 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_RAW_DEVICE_ID), 2454 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID), 2455 BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID), 2456 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID), 2457 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID), 2458 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID), 2459 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID), 2460 BRCMF_PCIE_DEVICE(BRCM_PCIE_4364_DEVICE_ID), 2461 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID), 2462 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID), 2463 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID), 2464 BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365), 2465 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID), 2466 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID), 2467 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID), 2468 BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID), 2469 BRCMF_PCIE_DEVICE(BRCM_PCIE_4378_DEVICE_ID), 2470 BRCMF_PCIE_DEVICE(CY_PCIE_89459_DEVICE_ID), 2471 BRCMF_PCIE_DEVICE(CY_PCIE_89459_RAW_DEVICE_ID), 2472 { /* end: all zeroes */ } 2473 }; 2474 2475 2476 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table); 2477 2478 2479 static struct pci_driver brcmf_pciedrvr = { 2480 .node = {}, 2481 .name = KBUILD_MODNAME, 2482 .id_table = brcmf_pcie_devid_table, 2483 .probe = brcmf_pcie_probe, 2484 .remove = brcmf_pcie_remove, 2485 #ifdef CONFIG_PM 2486 .driver.pm = &brcmf_pciedrvr_pm, 2487 #endif 2488 .driver.coredump = brcmf_dev_coredump, 2489 }; 2490 2491 2492 int brcmf_pcie_register(void) 2493 { 2494 brcmf_dbg(PCIE, "Enter\n"); 2495 return pci_register_driver(&brcmf_pciedrvr); 2496 } 2497 2498 2499 void brcmf_pcie_exit(void) 2500 { 2501 brcmf_dbg(PCIE, "Enter\n"); 2502 pci_unregister_driver(&brcmf_pciedrvr); 2503 } 2504