1 /* Copyright (c) 2014 Broadcom Corporation 2 * 3 * Permission to use, copy, modify, and/or distribute this software for any 4 * purpose with or without fee is hereby granted, provided that the above 5 * copyright notice and this permission notice appear in all copies. 6 * 7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 10 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 12 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 13 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/firmware.h> 19 #include <linux/pci.h> 20 #include <linux/vmalloc.h> 21 #include <linux/delay.h> 22 #include <linux/interrupt.h> 23 #include <linux/bcma/bcma.h> 24 #include <linux/sched.h> 25 #include <asm/unaligned.h> 26 27 #include <soc.h> 28 #include <chipcommon.h> 29 #include <brcmu_utils.h> 30 #include <brcmu_wifi.h> 31 #include <brcm_hw_ids.h> 32 33 /* Custom brcmf_err() that takes bus arg and passes it further */ 34 #define brcmf_err(bus, fmt, ...) \ 35 do { \ 36 if (IS_ENABLED(CONFIG_BRCMDBG) || \ 37 IS_ENABLED(CONFIG_BRCM_TRACING) || \ 38 net_ratelimit()) \ 39 __brcmf_err(bus, __func__, fmt, ##__VA_ARGS__); \ 40 } while (0) 41 42 #include "debug.h" 43 #include "bus.h" 44 #include "commonring.h" 45 #include "msgbuf.h" 46 #include "pcie.h" 47 #include "firmware.h" 48 #include "chip.h" 49 #include "core.h" 50 #include "common.h" 51 52 53 enum brcmf_pcie_state { 54 BRCMFMAC_PCIE_STATE_DOWN, 55 BRCMFMAC_PCIE_STATE_UP 56 }; 57 58 BRCMF_FW_DEF(43602, "brcmfmac43602-pcie"); 59 BRCMF_FW_DEF(4350, "brcmfmac4350-pcie"); 60 BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie"); 61 BRCMF_FW_DEF(4356, "brcmfmac4356-pcie"); 62 BRCMF_FW_DEF(43570, "brcmfmac43570-pcie"); 63 BRCMF_FW_DEF(4358, "brcmfmac4358-pcie"); 64 BRCMF_FW_DEF(4359, "brcmfmac4359-pcie"); 65 BRCMF_FW_DEF(4365B, "brcmfmac4365b-pcie"); 66 BRCMF_FW_DEF(4365C, "brcmfmac4365c-pcie"); 67 BRCMF_FW_DEF(4366B, "brcmfmac4366b-pcie"); 68 BRCMF_FW_DEF(4366C, "brcmfmac4366c-pcie"); 69 BRCMF_FW_DEF(4371, "brcmfmac4371-pcie"); 70 71 static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = { 72 BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602), 73 BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C), 74 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C), 75 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350), 76 BRCMF_FW_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C), 77 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 78 BRCMF_FW_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570), 79 BRCMF_FW_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570), 80 BRCMF_FW_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570), 81 BRCMF_FW_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358), 82 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359), 83 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B), 84 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C), 85 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B), 86 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C), 87 BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C), 88 BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371), 89 }; 90 91 #define BRCMF_PCIE_FW_UP_TIMEOUT 2000 /* msec */ 92 93 #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024) 94 95 /* backplane addres space accessed by BAR0 */ 96 #define BRCMF_PCIE_BAR0_WINDOW 0x80 97 #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000 98 #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70 99 100 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000 101 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000 102 103 #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40 104 #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C 105 106 #define BRCMF_PCIE_REG_INTSTATUS 0x90 107 #define BRCMF_PCIE_REG_INTMASK 0x94 108 #define BRCMF_PCIE_REG_SBMBX 0x98 109 110 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC 111 112 #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24 113 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48 114 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C 115 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120 116 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124 117 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0 0x140 118 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1 0x144 119 120 #define BRCMF_PCIE2_INTA 0x01 121 #define BRCMF_PCIE2_INTB 0x02 122 123 #define BRCMF_PCIE_INT_0 0x01 124 #define BRCMF_PCIE_INT_1 0x02 125 #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \ 126 BRCMF_PCIE_INT_1) 127 128 #define BRCMF_PCIE_MB_INT_FN0_0 0x0100 129 #define BRCMF_PCIE_MB_INT_FN0_1 0x0200 130 #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000 131 #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000 132 #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000 133 #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000 134 #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000 135 #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000 136 #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000 137 #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000 138 139 #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \ 140 BRCMF_PCIE_MB_INT_D2H0_DB1 | \ 141 BRCMF_PCIE_MB_INT_D2H1_DB0 | \ 142 BRCMF_PCIE_MB_INT_D2H1_DB1 | \ 143 BRCMF_PCIE_MB_INT_D2H2_DB0 | \ 144 BRCMF_PCIE_MB_INT_D2H2_DB1 | \ 145 BRCMF_PCIE_MB_INT_D2H3_DB0 | \ 146 BRCMF_PCIE_MB_INT_D2H3_DB1) 147 148 #define BRCMF_PCIE_SHARED_VERSION_7 7 149 #define BRCMF_PCIE_MIN_SHARED_VERSION 5 150 #define BRCMF_PCIE_MAX_SHARED_VERSION BRCMF_PCIE_SHARED_VERSION_7 151 #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF 152 #define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000 153 #define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000 154 #define BRCMF_PCIE_SHARED_HOSTRDY_DB1 0x10000000 155 156 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000 157 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000 158 159 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34 160 #define BRCMF_SHARED_RING_BASE_OFFSET 52 161 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36 162 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20 163 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40 164 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44 165 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48 166 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52 167 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56 168 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64 169 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68 170 171 #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0 172 #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1 173 #define BRCMF_RING_H2D_RING_MEM_OFFSET 4 174 #define BRCMF_RING_H2D_RING_STATE_OFFSET 8 175 176 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8 177 #define BRCMF_RING_MAX_ITEM_OFFSET 4 178 #define BRCMF_RING_LEN_ITEMS_OFFSET 6 179 #define BRCMF_RING_MEM_SZ 16 180 #define BRCMF_RING_STATE_SZ 8 181 182 #define BRCMF_DEF_MAX_RXBUFPOST 255 183 184 #define BRCMF_CONSOLE_BUFADDR_OFFSET 8 185 #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12 186 #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16 187 188 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8 189 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024 190 191 #define BRCMF_D2H_DEV_D3_ACK 0x00000001 192 #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002 193 #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004 194 #define BRCMF_D2H_DEV_FWHALT 0x10000000 195 196 #define BRCMF_H2D_HOST_D3_INFORM 0x00000001 197 #define BRCMF_H2D_HOST_DS_ACK 0x00000002 198 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008 199 #define BRCMF_H2D_HOST_D0_INFORM 0x00000010 200 201 #define BRCMF_PCIE_MBDATA_TIMEOUT msecs_to_jiffies(2000) 202 203 #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4 204 #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C 205 #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58 206 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C 207 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60 208 #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64 209 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC 210 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC 211 #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228 212 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248 213 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0 214 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4 215 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3 216 217 /* Magic number at a magic location to find RAM size */ 218 #define BRCMF_RAMSIZE_MAGIC 0x534d4152 /* SMAR */ 219 #define BRCMF_RAMSIZE_OFFSET 0x6c 220 221 222 struct brcmf_pcie_console { 223 u32 base_addr; 224 u32 buf_addr; 225 u32 bufsize; 226 u32 read_idx; 227 u8 log_str[256]; 228 u8 log_idx; 229 }; 230 231 struct brcmf_pcie_shared_info { 232 u32 tcm_base_address; 233 u32 flags; 234 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS]; 235 struct brcmf_pcie_ringbuf *flowrings; 236 u16 max_rxbufpost; 237 u16 max_flowrings; 238 u16 max_submissionrings; 239 u16 max_completionrings; 240 u32 rx_dataoffset; 241 u32 htod_mb_data_addr; 242 u32 dtoh_mb_data_addr; 243 u32 ring_info_addr; 244 struct brcmf_pcie_console console; 245 void *scratch; 246 dma_addr_t scratch_dmahandle; 247 void *ringupd; 248 dma_addr_t ringupd_dmahandle; 249 u8 version; 250 }; 251 252 struct brcmf_pcie_core_info { 253 u32 base; 254 u32 wrapbase; 255 }; 256 257 struct brcmf_pciedev_info { 258 enum brcmf_pcie_state state; 259 bool in_irq; 260 struct pci_dev *pdev; 261 char fw_name[BRCMF_FW_NAME_LEN]; 262 char nvram_name[BRCMF_FW_NAME_LEN]; 263 void __iomem *regs; 264 void __iomem *tcm; 265 u32 ram_base; 266 u32 ram_size; 267 struct brcmf_chip *ci; 268 u32 coreid; 269 struct brcmf_pcie_shared_info shared; 270 wait_queue_head_t mbdata_resp_wait; 271 bool mbdata_completed; 272 bool irq_allocated; 273 bool wowl_enabled; 274 u8 dma_idx_sz; 275 void *idxbuf; 276 u32 idxbuf_sz; 277 dma_addr_t idxbuf_dmahandle; 278 u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset); 279 void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 280 u16 value); 281 struct brcmf_mp_device *settings; 282 }; 283 284 struct brcmf_pcie_ringbuf { 285 struct brcmf_commonring commonring; 286 dma_addr_t dma_handle; 287 u32 w_idx_addr; 288 u32 r_idx_addr; 289 struct brcmf_pciedev_info *devinfo; 290 u8 id; 291 }; 292 293 /** 294 * struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info 295 * 296 * @ringmem: dongle memory pointer to ring memory location 297 * @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers 298 * @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers 299 * @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers 300 * @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers 301 * @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers 302 * @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers 303 * @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers 304 * @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers 305 * @max_flowrings: maximum number of tx flow rings supported. 306 * @max_submissionrings: maximum number of submission rings(h2d) supported. 307 * @max_completionrings: maximum number of completion rings(d2h) supported. 308 */ 309 struct brcmf_pcie_dhi_ringinfo { 310 __le32 ringmem; 311 __le32 h2d_w_idx_ptr; 312 __le32 h2d_r_idx_ptr; 313 __le32 d2h_w_idx_ptr; 314 __le32 d2h_r_idx_ptr; 315 struct msgbuf_buf_addr h2d_w_idx_hostaddr; 316 struct msgbuf_buf_addr h2d_r_idx_hostaddr; 317 struct msgbuf_buf_addr d2h_w_idx_hostaddr; 318 struct msgbuf_buf_addr d2h_r_idx_hostaddr; 319 __le16 max_flowrings; 320 __le16 max_submissionrings; 321 __le16 max_completionrings; 322 }; 323 324 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = { 325 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM, 326 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM, 327 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM, 328 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM, 329 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM 330 }; 331 332 static const u32 brcmf_ring_itemsize_pre_v7[BRCMF_NROF_COMMON_MSGRINGS] = { 333 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 334 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 335 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 336 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7, 337 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7 338 }; 339 340 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = { 341 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 342 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 343 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 344 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE, 345 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE 346 }; 347 348 static void brcmf_pcie_setup(struct device *dev, int ret, 349 struct brcmf_fw_request *fwreq); 350 static struct brcmf_fw_request * 351 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo); 352 353 static u32 354 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset) 355 { 356 void __iomem *address = devinfo->regs + reg_offset; 357 358 return (ioread32(address)); 359 } 360 361 362 static void 363 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset, 364 u32 value) 365 { 366 void __iomem *address = devinfo->regs + reg_offset; 367 368 iowrite32(value, address); 369 } 370 371 372 static u8 373 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 374 { 375 void __iomem *address = devinfo->tcm + mem_offset; 376 377 return (ioread8(address)); 378 } 379 380 381 static u16 382 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 383 { 384 void __iomem *address = devinfo->tcm + mem_offset; 385 386 return (ioread16(address)); 387 } 388 389 390 static void 391 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 392 u16 value) 393 { 394 void __iomem *address = devinfo->tcm + mem_offset; 395 396 iowrite16(value, address); 397 } 398 399 400 static u16 401 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 402 { 403 u16 *address = devinfo->idxbuf + mem_offset; 404 405 return (*(address)); 406 } 407 408 409 static void 410 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 411 u16 value) 412 { 413 u16 *address = devinfo->idxbuf + mem_offset; 414 415 *(address) = value; 416 } 417 418 419 static u32 420 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 421 { 422 void __iomem *address = devinfo->tcm + mem_offset; 423 424 return (ioread32(address)); 425 } 426 427 428 static void 429 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 430 u32 value) 431 { 432 void __iomem *address = devinfo->tcm + mem_offset; 433 434 iowrite32(value, address); 435 } 436 437 438 static u32 439 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 440 { 441 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 442 443 return (ioread32(addr)); 444 } 445 446 447 static void 448 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 449 u32 value) 450 { 451 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 452 453 iowrite32(value, addr); 454 } 455 456 457 static void 458 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 459 void *srcaddr, u32 len) 460 { 461 void __iomem *address = devinfo->tcm + mem_offset; 462 __le32 *src32; 463 __le16 *src16; 464 u8 *src8; 465 466 if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) { 467 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) { 468 src8 = (u8 *)srcaddr; 469 while (len) { 470 iowrite8(*src8, address); 471 address++; 472 src8++; 473 len--; 474 } 475 } else { 476 len = len / 2; 477 src16 = (__le16 *)srcaddr; 478 while (len) { 479 iowrite16(le16_to_cpu(*src16), address); 480 address += 2; 481 src16++; 482 len--; 483 } 484 } 485 } else { 486 len = len / 4; 487 src32 = (__le32 *)srcaddr; 488 while (len) { 489 iowrite32(le32_to_cpu(*src32), address); 490 address += 4; 491 src32++; 492 len--; 493 } 494 } 495 } 496 497 498 static void 499 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 500 void *dstaddr, u32 len) 501 { 502 void __iomem *address = devinfo->tcm + mem_offset; 503 __le32 *dst32; 504 __le16 *dst16; 505 u8 *dst8; 506 507 if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) { 508 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) { 509 dst8 = (u8 *)dstaddr; 510 while (len) { 511 *dst8 = ioread8(address); 512 address++; 513 dst8++; 514 len--; 515 } 516 } else { 517 len = len / 2; 518 dst16 = (__le16 *)dstaddr; 519 while (len) { 520 *dst16 = cpu_to_le16(ioread16(address)); 521 address += 2; 522 dst16++; 523 len--; 524 } 525 } 526 } else { 527 len = len / 4; 528 dst32 = (__le32 *)dstaddr; 529 while (len) { 530 *dst32 = cpu_to_le32(ioread32(address)); 531 address += 4; 532 dst32++; 533 len--; 534 } 535 } 536 } 537 538 539 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \ 540 CHIPCREGOFFS(reg), value) 541 542 543 static void 544 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid) 545 { 546 const struct pci_dev *pdev = devinfo->pdev; 547 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 548 struct brcmf_core *core; 549 u32 bar0_win; 550 551 core = brcmf_chip_get_core(devinfo->ci, coreid); 552 if (core) { 553 bar0_win = core->base; 554 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win); 555 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, 556 &bar0_win) == 0) { 557 if (bar0_win != core->base) { 558 bar0_win = core->base; 559 pci_write_config_dword(pdev, 560 BRCMF_PCIE_BAR0_WINDOW, 561 bar0_win); 562 } 563 } 564 } else { 565 brcmf_err(bus, "Unsupported core selected %x\n", coreid); 566 } 567 } 568 569 570 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo) 571 { 572 struct brcmf_core *core; 573 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD, 574 BRCMF_PCIE_CFGREG_PM_CSR, 575 BRCMF_PCIE_CFGREG_MSI_CAP, 576 BRCMF_PCIE_CFGREG_MSI_ADDR_L, 577 BRCMF_PCIE_CFGREG_MSI_ADDR_H, 578 BRCMF_PCIE_CFGREG_MSI_DATA, 579 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2, 580 BRCMF_PCIE_CFGREG_RBAR_CTRL, 581 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1, 582 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG, 583 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG }; 584 u32 i; 585 u32 val; 586 u32 lsc; 587 588 if (!devinfo->ci) 589 return; 590 591 /* Disable ASPM */ 592 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 593 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 594 &lsc); 595 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB); 596 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 597 val); 598 599 /* Watchdog reset */ 600 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON); 601 WRITECC32(devinfo, watchdog, 4); 602 msleep(100); 603 604 /* Restore ASPM */ 605 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 606 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 607 lsc); 608 609 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 610 if (core->rev <= 13) { 611 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) { 612 brcmf_pcie_write_reg32(devinfo, 613 BRCMF_PCIE_PCIE2REG_CONFIGADDR, 614 cfg_offset[i]); 615 val = brcmf_pcie_read_reg32(devinfo, 616 BRCMF_PCIE_PCIE2REG_CONFIGDATA); 617 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n", 618 cfg_offset[i], val); 619 brcmf_pcie_write_reg32(devinfo, 620 BRCMF_PCIE_PCIE2REG_CONFIGDATA, 621 val); 622 } 623 } 624 } 625 626 627 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo) 628 { 629 u32 config; 630 631 /* BAR1 window may not be sized properly */ 632 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 633 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0); 634 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA); 635 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config); 636 637 device_wakeup_enable(&devinfo->pdev->dev); 638 } 639 640 641 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo) 642 { 643 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 644 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4); 645 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 646 5); 647 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 648 0); 649 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 650 7); 651 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 652 0); 653 } 654 return 0; 655 } 656 657 658 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo, 659 u32 resetintr) 660 { 661 struct brcmf_core *core; 662 663 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 664 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM); 665 brcmf_chip_resetcore(core, 0, 0, 0); 666 } 667 668 if (!brcmf_chip_set_active(devinfo->ci, resetintr)) 669 return -EINVAL; 670 return 0; 671 } 672 673 674 static int 675 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data) 676 { 677 struct brcmf_pcie_shared_info *shared; 678 u32 addr; 679 u32 cur_htod_mb_data; 680 u32 i; 681 682 shared = &devinfo->shared; 683 addr = shared->htod_mb_data_addr; 684 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 685 686 if (cur_htod_mb_data != 0) 687 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n", 688 cur_htod_mb_data); 689 690 i = 0; 691 while (cur_htod_mb_data != 0) { 692 msleep(10); 693 i++; 694 if (i > 100) 695 return -EIO; 696 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 697 } 698 699 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data); 700 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 701 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 702 703 return 0; 704 } 705 706 707 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo) 708 { 709 struct brcmf_pcie_shared_info *shared; 710 u32 addr; 711 u32 dtoh_mb_data; 712 713 shared = &devinfo->shared; 714 addr = shared->dtoh_mb_data_addr; 715 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 716 717 if (!dtoh_mb_data) 718 return; 719 720 brcmf_pcie_write_tcm32(devinfo, addr, 0); 721 722 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data); 723 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) { 724 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n"); 725 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK); 726 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n"); 727 } 728 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE) 729 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n"); 730 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) { 731 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n"); 732 devinfo->mbdata_completed = true; 733 wake_up(&devinfo->mbdata_resp_wait); 734 } 735 if (dtoh_mb_data & BRCMF_D2H_DEV_FWHALT) { 736 brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n"); 737 brcmf_fw_crashed(&devinfo->pdev->dev); 738 } 739 } 740 741 742 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo) 743 { 744 struct brcmf_pcie_shared_info *shared; 745 struct brcmf_pcie_console *console; 746 u32 addr; 747 748 shared = &devinfo->shared; 749 console = &shared->console; 750 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET; 751 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr); 752 753 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET; 754 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr); 755 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET; 756 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr); 757 758 brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n", 759 console->base_addr, console->buf_addr, console->bufsize); 760 } 761 762 763 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo) 764 { 765 struct brcmf_pcie_console *console; 766 u32 addr; 767 u8 ch; 768 u32 newidx; 769 770 if (!BRCMF_FWCON_ON()) 771 return; 772 773 console = &devinfo->shared.console; 774 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET; 775 newidx = brcmf_pcie_read_tcm32(devinfo, addr); 776 while (newidx != console->read_idx) { 777 addr = console->buf_addr + console->read_idx; 778 ch = brcmf_pcie_read_tcm8(devinfo, addr); 779 console->read_idx++; 780 if (console->read_idx == console->bufsize) 781 console->read_idx = 0; 782 if (ch == '\r') 783 continue; 784 console->log_str[console->log_idx] = ch; 785 console->log_idx++; 786 if ((ch != '\n') && 787 (console->log_idx == (sizeof(console->log_str) - 2))) { 788 ch = '\n'; 789 console->log_str[console->log_idx] = ch; 790 console->log_idx++; 791 } 792 if (ch == '\n') { 793 console->log_str[console->log_idx] = 0; 794 pr_debug("CONSOLE: %s", console->log_str); 795 console->log_idx = 0; 796 } 797 } 798 } 799 800 801 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo) 802 { 803 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 0); 804 } 805 806 807 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo) 808 { 809 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 810 BRCMF_PCIE_MB_INT_D2H_DB | 811 BRCMF_PCIE_MB_INT_FN0_0 | 812 BRCMF_PCIE_MB_INT_FN0_1); 813 } 814 815 static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo) 816 { 817 if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1) 818 brcmf_pcie_write_reg32(devinfo, 819 BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1, 1); 820 } 821 822 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg) 823 { 824 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 825 826 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) { 827 brcmf_pcie_intr_disable(devinfo); 828 brcmf_dbg(PCIE, "Enter\n"); 829 return IRQ_WAKE_THREAD; 830 } 831 return IRQ_NONE; 832 } 833 834 835 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg) 836 { 837 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 838 u32 status; 839 840 devinfo->in_irq = true; 841 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 842 brcmf_dbg(PCIE, "Enter %x\n", status); 843 if (status) { 844 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, 845 status); 846 if (status & (BRCMF_PCIE_MB_INT_FN0_0 | 847 BRCMF_PCIE_MB_INT_FN0_1)) 848 brcmf_pcie_handle_mb_data(devinfo); 849 if (status & BRCMF_PCIE_MB_INT_D2H_DB) { 850 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 851 brcmf_proto_msgbuf_rx_trigger( 852 &devinfo->pdev->dev); 853 } 854 } 855 brcmf_pcie_bus_console_read(devinfo); 856 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 857 brcmf_pcie_intr_enable(devinfo); 858 devinfo->in_irq = false; 859 return IRQ_HANDLED; 860 } 861 862 863 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo) 864 { 865 struct pci_dev *pdev = devinfo->pdev; 866 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 867 868 brcmf_pcie_intr_disable(devinfo); 869 870 brcmf_dbg(PCIE, "Enter\n"); 871 872 pci_enable_msi(pdev); 873 if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr, 874 brcmf_pcie_isr_thread, IRQF_SHARED, 875 "brcmf_pcie_intr", devinfo)) { 876 pci_disable_msi(pdev); 877 brcmf_err(bus, "Failed to request IRQ %d\n", pdev->irq); 878 return -EIO; 879 } 880 devinfo->irq_allocated = true; 881 return 0; 882 } 883 884 885 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo) 886 { 887 struct pci_dev *pdev = devinfo->pdev; 888 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 889 u32 status; 890 u32 count; 891 892 if (!devinfo->irq_allocated) 893 return; 894 895 brcmf_pcie_intr_disable(devinfo); 896 free_irq(pdev->irq, devinfo); 897 pci_disable_msi(pdev); 898 899 msleep(50); 900 count = 0; 901 while ((devinfo->in_irq) && (count < 20)) { 902 msleep(50); 903 count++; 904 } 905 if (devinfo->in_irq) 906 brcmf_err(bus, "Still in IRQ (processing) !!!\n"); 907 908 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 909 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, status); 910 911 devinfo->irq_allocated = false; 912 } 913 914 915 static int brcmf_pcie_ring_mb_write_rptr(void *ctx) 916 { 917 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 918 struct brcmf_pciedev_info *devinfo = ring->devinfo; 919 struct brcmf_commonring *commonring = &ring->commonring; 920 921 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 922 return -EIO; 923 924 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr, 925 commonring->w_ptr, ring->id); 926 927 devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr); 928 929 return 0; 930 } 931 932 933 static int brcmf_pcie_ring_mb_write_wptr(void *ctx) 934 { 935 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 936 struct brcmf_pciedev_info *devinfo = ring->devinfo; 937 struct brcmf_commonring *commonring = &ring->commonring; 938 939 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 940 return -EIO; 941 942 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr, 943 commonring->r_ptr, ring->id); 944 945 devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr); 946 947 return 0; 948 } 949 950 951 static int brcmf_pcie_ring_mb_ring_bell(void *ctx) 952 { 953 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 954 struct brcmf_pciedev_info *devinfo = ring->devinfo; 955 956 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 957 return -EIO; 958 959 brcmf_dbg(PCIE, "RING !\n"); 960 /* Any arbitrary value will do, lets use 1 */ 961 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0, 1); 962 963 return 0; 964 } 965 966 967 static int brcmf_pcie_ring_mb_update_rptr(void *ctx) 968 { 969 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 970 struct brcmf_pciedev_info *devinfo = ring->devinfo; 971 struct brcmf_commonring *commonring = &ring->commonring; 972 973 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 974 return -EIO; 975 976 commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr); 977 978 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr, 979 commonring->w_ptr, ring->id); 980 981 return 0; 982 } 983 984 985 static int brcmf_pcie_ring_mb_update_wptr(void *ctx) 986 { 987 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 988 struct brcmf_pciedev_info *devinfo = ring->devinfo; 989 struct brcmf_commonring *commonring = &ring->commonring; 990 991 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 992 return -EIO; 993 994 commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr); 995 996 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr, 997 commonring->r_ptr, ring->id); 998 999 return 0; 1000 } 1001 1002 1003 static void * 1004 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo, 1005 u32 size, u32 tcm_dma_phys_addr, 1006 dma_addr_t *dma_handle) 1007 { 1008 void *ring; 1009 u64 address; 1010 1011 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle, 1012 GFP_KERNEL); 1013 if (!ring) 1014 return NULL; 1015 1016 address = (u64)*dma_handle; 1017 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr, 1018 address & 0xffffffff); 1019 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32); 1020 1021 memset(ring, 0, size); 1022 1023 return (ring); 1024 } 1025 1026 1027 static struct brcmf_pcie_ringbuf * 1028 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id, 1029 u32 tcm_ring_phys_addr) 1030 { 1031 void *dma_buf; 1032 dma_addr_t dma_handle; 1033 struct brcmf_pcie_ringbuf *ring; 1034 u32 size; 1035 u32 addr; 1036 const u32 *ring_itemsize_array; 1037 1038 if (devinfo->shared.version < BRCMF_PCIE_SHARED_VERSION_7) 1039 ring_itemsize_array = brcmf_ring_itemsize_pre_v7; 1040 else 1041 ring_itemsize_array = brcmf_ring_itemsize; 1042 1043 size = brcmf_ring_max_item[ring_id] * ring_itemsize_array[ring_id]; 1044 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size, 1045 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET, 1046 &dma_handle); 1047 if (!dma_buf) 1048 return NULL; 1049 1050 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET; 1051 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]); 1052 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET; 1053 brcmf_pcie_write_tcm16(devinfo, addr, ring_itemsize_array[ring_id]); 1054 1055 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 1056 if (!ring) { 1057 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf, 1058 dma_handle); 1059 return NULL; 1060 } 1061 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id], 1062 ring_itemsize_array[ring_id], dma_buf); 1063 ring->dma_handle = dma_handle; 1064 ring->devinfo = devinfo; 1065 brcmf_commonring_register_cb(&ring->commonring, 1066 brcmf_pcie_ring_mb_ring_bell, 1067 brcmf_pcie_ring_mb_update_rptr, 1068 brcmf_pcie_ring_mb_update_wptr, 1069 brcmf_pcie_ring_mb_write_rptr, 1070 brcmf_pcie_ring_mb_write_wptr, ring); 1071 1072 return (ring); 1073 } 1074 1075 1076 static void brcmf_pcie_release_ringbuffer(struct device *dev, 1077 struct brcmf_pcie_ringbuf *ring) 1078 { 1079 void *dma_buf; 1080 u32 size; 1081 1082 if (!ring) 1083 return; 1084 1085 dma_buf = ring->commonring.buf_addr; 1086 if (dma_buf) { 1087 size = ring->commonring.depth * ring->commonring.item_len; 1088 dma_free_coherent(dev, size, dma_buf, ring->dma_handle); 1089 } 1090 kfree(ring); 1091 } 1092 1093 1094 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo) 1095 { 1096 u32 i; 1097 1098 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1099 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev, 1100 devinfo->shared.commonrings[i]); 1101 devinfo->shared.commonrings[i] = NULL; 1102 } 1103 kfree(devinfo->shared.flowrings); 1104 devinfo->shared.flowrings = NULL; 1105 if (devinfo->idxbuf) { 1106 dma_free_coherent(&devinfo->pdev->dev, 1107 devinfo->idxbuf_sz, 1108 devinfo->idxbuf, 1109 devinfo->idxbuf_dmahandle); 1110 devinfo->idxbuf = NULL; 1111 } 1112 } 1113 1114 1115 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo) 1116 { 1117 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1118 struct brcmf_pcie_ringbuf *ring; 1119 struct brcmf_pcie_ringbuf *rings; 1120 u32 d2h_w_idx_ptr; 1121 u32 d2h_r_idx_ptr; 1122 u32 h2d_w_idx_ptr; 1123 u32 h2d_r_idx_ptr; 1124 u32 ring_mem_ptr; 1125 u32 i; 1126 u64 address; 1127 u32 bufsz; 1128 u8 idx_offset; 1129 struct brcmf_pcie_dhi_ringinfo ringinfo; 1130 u16 max_flowrings; 1131 u16 max_submissionrings; 1132 u16 max_completionrings; 1133 1134 memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr, 1135 sizeof(ringinfo)); 1136 if (devinfo->shared.version >= 6) { 1137 max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings); 1138 max_flowrings = le16_to_cpu(ringinfo.max_flowrings); 1139 max_completionrings = le16_to_cpu(ringinfo.max_completionrings); 1140 } else { 1141 max_submissionrings = le16_to_cpu(ringinfo.max_flowrings); 1142 max_flowrings = max_submissionrings - 1143 BRCMF_NROF_H2D_COMMON_MSGRINGS; 1144 max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS; 1145 } 1146 1147 if (devinfo->dma_idx_sz != 0) { 1148 bufsz = (max_submissionrings + max_completionrings) * 1149 devinfo->dma_idx_sz * 2; 1150 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz, 1151 &devinfo->idxbuf_dmahandle, 1152 GFP_KERNEL); 1153 if (!devinfo->idxbuf) 1154 devinfo->dma_idx_sz = 0; 1155 } 1156 1157 if (devinfo->dma_idx_sz == 0) { 1158 d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr); 1159 d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr); 1160 h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr); 1161 h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr); 1162 idx_offset = sizeof(u32); 1163 devinfo->write_ptr = brcmf_pcie_write_tcm16; 1164 devinfo->read_ptr = brcmf_pcie_read_tcm16; 1165 brcmf_dbg(PCIE, "Using TCM indices\n"); 1166 } else { 1167 memset(devinfo->idxbuf, 0, bufsz); 1168 devinfo->idxbuf_sz = bufsz; 1169 idx_offset = devinfo->dma_idx_sz; 1170 devinfo->write_ptr = brcmf_pcie_write_idx; 1171 devinfo->read_ptr = brcmf_pcie_read_idx; 1172 1173 h2d_w_idx_ptr = 0; 1174 address = (u64)devinfo->idxbuf_dmahandle; 1175 ringinfo.h2d_w_idx_hostaddr.low_addr = 1176 cpu_to_le32(address & 0xffffffff); 1177 ringinfo.h2d_w_idx_hostaddr.high_addr = 1178 cpu_to_le32(address >> 32); 1179 1180 h2d_r_idx_ptr = h2d_w_idx_ptr + 1181 max_submissionrings * idx_offset; 1182 address += max_submissionrings * idx_offset; 1183 ringinfo.h2d_r_idx_hostaddr.low_addr = 1184 cpu_to_le32(address & 0xffffffff); 1185 ringinfo.h2d_r_idx_hostaddr.high_addr = 1186 cpu_to_le32(address >> 32); 1187 1188 d2h_w_idx_ptr = h2d_r_idx_ptr + 1189 max_submissionrings * idx_offset; 1190 address += max_submissionrings * idx_offset; 1191 ringinfo.d2h_w_idx_hostaddr.low_addr = 1192 cpu_to_le32(address & 0xffffffff); 1193 ringinfo.d2h_w_idx_hostaddr.high_addr = 1194 cpu_to_le32(address >> 32); 1195 1196 d2h_r_idx_ptr = d2h_w_idx_ptr + 1197 max_completionrings * idx_offset; 1198 address += max_completionrings * idx_offset; 1199 ringinfo.d2h_r_idx_hostaddr.low_addr = 1200 cpu_to_le32(address & 0xffffffff); 1201 ringinfo.d2h_r_idx_hostaddr.high_addr = 1202 cpu_to_le32(address >> 32); 1203 1204 memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr, 1205 &ringinfo, sizeof(ringinfo)); 1206 brcmf_dbg(PCIE, "Using host memory indices\n"); 1207 } 1208 1209 ring_mem_ptr = le32_to_cpu(ringinfo.ringmem); 1210 1211 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) { 1212 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1213 if (!ring) 1214 goto fail; 1215 ring->w_idx_addr = h2d_w_idx_ptr; 1216 ring->r_idx_addr = h2d_r_idx_ptr; 1217 ring->id = i; 1218 devinfo->shared.commonrings[i] = ring; 1219 1220 h2d_w_idx_ptr += idx_offset; 1221 h2d_r_idx_ptr += idx_offset; 1222 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1223 } 1224 1225 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS; 1226 i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1227 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1228 if (!ring) 1229 goto fail; 1230 ring->w_idx_addr = d2h_w_idx_ptr; 1231 ring->r_idx_addr = d2h_r_idx_ptr; 1232 ring->id = i; 1233 devinfo->shared.commonrings[i] = ring; 1234 1235 d2h_w_idx_ptr += idx_offset; 1236 d2h_r_idx_ptr += idx_offset; 1237 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1238 } 1239 1240 devinfo->shared.max_flowrings = max_flowrings; 1241 devinfo->shared.max_submissionrings = max_submissionrings; 1242 devinfo->shared.max_completionrings = max_completionrings; 1243 rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL); 1244 if (!rings) 1245 goto fail; 1246 1247 brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings); 1248 1249 for (i = 0; i < max_flowrings; i++) { 1250 ring = &rings[i]; 1251 ring->devinfo = devinfo; 1252 ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART; 1253 brcmf_commonring_register_cb(&ring->commonring, 1254 brcmf_pcie_ring_mb_ring_bell, 1255 brcmf_pcie_ring_mb_update_rptr, 1256 brcmf_pcie_ring_mb_update_wptr, 1257 brcmf_pcie_ring_mb_write_rptr, 1258 brcmf_pcie_ring_mb_write_wptr, 1259 ring); 1260 ring->w_idx_addr = h2d_w_idx_ptr; 1261 ring->r_idx_addr = h2d_r_idx_ptr; 1262 h2d_w_idx_ptr += idx_offset; 1263 h2d_r_idx_ptr += idx_offset; 1264 } 1265 devinfo->shared.flowrings = rings; 1266 1267 return 0; 1268 1269 fail: 1270 brcmf_err(bus, "Allocating ring buffers failed\n"); 1271 brcmf_pcie_release_ringbuffers(devinfo); 1272 return -ENOMEM; 1273 } 1274 1275 1276 static void 1277 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1278 { 1279 if (devinfo->shared.scratch) 1280 dma_free_coherent(&devinfo->pdev->dev, 1281 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1282 devinfo->shared.scratch, 1283 devinfo->shared.scratch_dmahandle); 1284 if (devinfo->shared.ringupd) 1285 dma_free_coherent(&devinfo->pdev->dev, 1286 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1287 devinfo->shared.ringupd, 1288 devinfo->shared.ringupd_dmahandle); 1289 } 1290 1291 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1292 { 1293 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1294 u64 address; 1295 u32 addr; 1296 1297 devinfo->shared.scratch = 1298 dma_alloc_coherent(&devinfo->pdev->dev, 1299 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1300 &devinfo->shared.scratch_dmahandle, 1301 GFP_KERNEL); 1302 if (!devinfo->shared.scratch) 1303 goto fail; 1304 1305 addr = devinfo->shared.tcm_base_address + 1306 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET; 1307 address = (u64)devinfo->shared.scratch_dmahandle; 1308 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1309 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1310 addr = devinfo->shared.tcm_base_address + 1311 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET; 1312 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); 1313 1314 devinfo->shared.ringupd = 1315 dma_alloc_coherent(&devinfo->pdev->dev, 1316 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1317 &devinfo->shared.ringupd_dmahandle, 1318 GFP_KERNEL); 1319 if (!devinfo->shared.ringupd) 1320 goto fail; 1321 1322 addr = devinfo->shared.tcm_base_address + 1323 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET; 1324 address = (u64)devinfo->shared.ringupd_dmahandle; 1325 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1326 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1327 addr = devinfo->shared.tcm_base_address + 1328 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET; 1329 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); 1330 return 0; 1331 1332 fail: 1333 brcmf_err(bus, "Allocating scratch buffers failed\n"); 1334 brcmf_pcie_release_scratchbuffers(devinfo); 1335 return -ENOMEM; 1336 } 1337 1338 1339 static void brcmf_pcie_down(struct device *dev) 1340 { 1341 } 1342 1343 1344 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb) 1345 { 1346 return 0; 1347 } 1348 1349 1350 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg, 1351 uint len) 1352 { 1353 return 0; 1354 } 1355 1356 1357 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg, 1358 uint len) 1359 { 1360 return 0; 1361 } 1362 1363 1364 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled) 1365 { 1366 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1367 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1368 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1369 1370 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled); 1371 devinfo->wowl_enabled = enabled; 1372 } 1373 1374 1375 static size_t brcmf_pcie_get_ramsize(struct device *dev) 1376 { 1377 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1378 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1379 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1380 1381 return devinfo->ci->ramsize - devinfo->ci->srsize; 1382 } 1383 1384 1385 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len) 1386 { 1387 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1388 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1389 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1390 1391 brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len); 1392 brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len); 1393 return 0; 1394 } 1395 1396 static 1397 int brcmf_pcie_get_fwname(struct device *dev, const char *ext, u8 *fw_name) 1398 { 1399 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1400 struct brcmf_fw_request *fwreq; 1401 struct brcmf_fw_name fwnames[] = { 1402 { ext, fw_name }, 1403 }; 1404 1405 fwreq = brcmf_fw_alloc_request(bus_if->chip, bus_if->chiprev, 1406 brcmf_pcie_fwnames, 1407 ARRAY_SIZE(brcmf_pcie_fwnames), 1408 fwnames, ARRAY_SIZE(fwnames)); 1409 if (!fwreq) 1410 return -ENOMEM; 1411 1412 kfree(fwreq); 1413 return 0; 1414 } 1415 1416 static int brcmf_pcie_reset(struct device *dev) 1417 { 1418 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1419 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1420 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1421 struct brcmf_fw_request *fwreq; 1422 int err; 1423 1424 brcmf_detach(dev); 1425 1426 brcmf_pcie_release_irq(devinfo); 1427 brcmf_pcie_release_scratchbuffers(devinfo); 1428 brcmf_pcie_release_ringbuffers(devinfo); 1429 brcmf_pcie_reset_device(devinfo); 1430 1431 fwreq = brcmf_pcie_prepare_fw_request(devinfo); 1432 if (!fwreq) { 1433 dev_err(dev, "Failed to prepare FW request\n"); 1434 return -ENOMEM; 1435 } 1436 1437 err = brcmf_fw_get_firmwares(dev, fwreq, brcmf_pcie_setup); 1438 if (err) { 1439 dev_err(dev, "Failed to prepare FW request\n"); 1440 kfree(fwreq); 1441 } 1442 1443 return err; 1444 } 1445 1446 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = { 1447 .txdata = brcmf_pcie_tx, 1448 .stop = brcmf_pcie_down, 1449 .txctl = brcmf_pcie_tx_ctlpkt, 1450 .rxctl = brcmf_pcie_rx_ctlpkt, 1451 .wowl_config = brcmf_pcie_wowl_config, 1452 .get_ramsize = brcmf_pcie_get_ramsize, 1453 .get_memdump = brcmf_pcie_get_memdump, 1454 .get_fwname = brcmf_pcie_get_fwname, 1455 .reset = brcmf_pcie_reset, 1456 }; 1457 1458 1459 static void 1460 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data, 1461 u32 data_len) 1462 { 1463 __le32 *field; 1464 u32 newsize; 1465 1466 if (data_len < BRCMF_RAMSIZE_OFFSET + 8) 1467 return; 1468 1469 field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET]; 1470 if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC) 1471 return; 1472 field++; 1473 newsize = le32_to_cpup(field); 1474 1475 brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n", 1476 newsize); 1477 devinfo->ci->ramsize = newsize; 1478 } 1479 1480 1481 static int 1482 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo, 1483 u32 sharedram_addr) 1484 { 1485 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1486 struct brcmf_pcie_shared_info *shared; 1487 u32 addr; 1488 1489 shared = &devinfo->shared; 1490 shared->tcm_base_address = sharedram_addr; 1491 1492 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr); 1493 shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK); 1494 brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version); 1495 if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) || 1496 (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) { 1497 brcmf_err(bus, "Unsupported PCIE version %d\n", 1498 shared->version); 1499 return -EINVAL; 1500 } 1501 1502 /* check firmware support dma indicies */ 1503 if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) { 1504 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX) 1505 devinfo->dma_idx_sz = sizeof(u16); 1506 else 1507 devinfo->dma_idx_sz = sizeof(u32); 1508 } 1509 1510 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET; 1511 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr); 1512 if (shared->max_rxbufpost == 0) 1513 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST; 1514 1515 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET; 1516 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr); 1517 1518 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET; 1519 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1520 1521 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET; 1522 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1523 1524 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET; 1525 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1526 1527 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n", 1528 shared->max_rxbufpost, shared->rx_dataoffset); 1529 1530 brcmf_pcie_bus_console_init(devinfo); 1531 1532 return 0; 1533 } 1534 1535 1536 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo, 1537 const struct firmware *fw, void *nvram, 1538 u32 nvram_len) 1539 { 1540 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1541 u32 sharedram_addr; 1542 u32 sharedram_addr_written; 1543 u32 loop_counter; 1544 int err; 1545 u32 address; 1546 u32 resetintr; 1547 1548 brcmf_dbg(PCIE, "Halt ARM.\n"); 1549 err = brcmf_pcie_enter_download_state(devinfo); 1550 if (err) 1551 return err; 1552 1553 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name); 1554 brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase, 1555 (void *)fw->data, fw->size); 1556 1557 resetintr = get_unaligned_le32(fw->data); 1558 release_firmware(fw); 1559 1560 /* reset last 4 bytes of RAM address. to be used for shared 1561 * area. This identifies when FW is running 1562 */ 1563 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0); 1564 1565 if (nvram) { 1566 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name); 1567 address = devinfo->ci->rambase + devinfo->ci->ramsize - 1568 nvram_len; 1569 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len); 1570 brcmf_fw_nvram_free(nvram); 1571 } else { 1572 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n", 1573 devinfo->nvram_name); 1574 } 1575 1576 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo, 1577 devinfo->ci->ramsize - 1578 4); 1579 brcmf_dbg(PCIE, "Bring ARM in running state\n"); 1580 err = brcmf_pcie_exit_download_state(devinfo, resetintr); 1581 if (err) 1582 return err; 1583 1584 brcmf_dbg(PCIE, "Wait for FW init\n"); 1585 sharedram_addr = sharedram_addr_written; 1586 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50; 1587 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) { 1588 msleep(50); 1589 sharedram_addr = brcmf_pcie_read_ram32(devinfo, 1590 devinfo->ci->ramsize - 1591 4); 1592 loop_counter--; 1593 } 1594 if (sharedram_addr == sharedram_addr_written) { 1595 brcmf_err(bus, "FW failed to initialize\n"); 1596 return -ENODEV; 1597 } 1598 if (sharedram_addr < devinfo->ci->rambase || 1599 sharedram_addr >= devinfo->ci->rambase + devinfo->ci->ramsize) { 1600 brcmf_err(bus, "Invalid shared RAM address 0x%08x\n", 1601 sharedram_addr); 1602 return -ENODEV; 1603 } 1604 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr); 1605 1606 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr)); 1607 } 1608 1609 1610 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo) 1611 { 1612 struct pci_dev *pdev = devinfo->pdev; 1613 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 1614 int err; 1615 phys_addr_t bar0_addr, bar1_addr; 1616 ulong bar1_size; 1617 1618 err = pci_enable_device(pdev); 1619 if (err) { 1620 brcmf_err(bus, "pci_enable_device failed err=%d\n", err); 1621 return err; 1622 } 1623 1624 pci_set_master(pdev); 1625 1626 /* Bar-0 mapped address */ 1627 bar0_addr = pci_resource_start(pdev, 0); 1628 /* Bar-1 mapped address */ 1629 bar1_addr = pci_resource_start(pdev, 2); 1630 /* read Bar-1 mapped memory range */ 1631 bar1_size = pci_resource_len(pdev, 2); 1632 if ((bar1_size == 0) || (bar1_addr == 0)) { 1633 brcmf_err(bus, "BAR1 Not enabled, device size=%ld, addr=%#016llx\n", 1634 bar1_size, (unsigned long long)bar1_addr); 1635 return -EINVAL; 1636 } 1637 1638 devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE); 1639 devinfo->tcm = ioremap_nocache(bar1_addr, bar1_size); 1640 1641 if (!devinfo->regs || !devinfo->tcm) { 1642 brcmf_err(bus, "ioremap() failed (%p,%p)\n", devinfo->regs, 1643 devinfo->tcm); 1644 return -EINVAL; 1645 } 1646 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n", 1647 devinfo->regs, (unsigned long long)bar0_addr); 1648 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n", 1649 devinfo->tcm, (unsigned long long)bar1_addr, 1650 (unsigned int)bar1_size); 1651 1652 return 0; 1653 } 1654 1655 1656 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo) 1657 { 1658 if (devinfo->tcm) 1659 iounmap(devinfo->tcm); 1660 if (devinfo->regs) 1661 iounmap(devinfo->regs); 1662 1663 pci_disable_device(devinfo->pdev); 1664 } 1665 1666 1667 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr) 1668 { 1669 u32 ret_addr; 1670 1671 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1); 1672 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1); 1673 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr); 1674 1675 return ret_addr; 1676 } 1677 1678 1679 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr) 1680 { 1681 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1682 1683 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1684 return brcmf_pcie_read_reg32(devinfo, addr); 1685 } 1686 1687 1688 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value) 1689 { 1690 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1691 1692 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1693 brcmf_pcie_write_reg32(devinfo, addr, value); 1694 } 1695 1696 1697 static int brcmf_pcie_buscoreprep(void *ctx) 1698 { 1699 return brcmf_pcie_get_resource(ctx); 1700 } 1701 1702 1703 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip) 1704 { 1705 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1706 u32 val; 1707 1708 devinfo->ci = chip; 1709 brcmf_pcie_reset_device(devinfo); 1710 1711 val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT); 1712 if (val != 0xffffffff) 1713 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, 1714 val); 1715 1716 return 0; 1717 } 1718 1719 1720 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip, 1721 u32 rstvec) 1722 { 1723 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1724 1725 brcmf_pcie_write_tcm32(devinfo, 0, rstvec); 1726 } 1727 1728 1729 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = { 1730 .prepare = brcmf_pcie_buscoreprep, 1731 .reset = brcmf_pcie_buscore_reset, 1732 .activate = brcmf_pcie_buscore_activate, 1733 .read32 = brcmf_pcie_buscore_read32, 1734 .write32 = brcmf_pcie_buscore_write32, 1735 }; 1736 1737 #define BRCMF_PCIE_FW_CODE 0 1738 #define BRCMF_PCIE_FW_NVRAM 1 1739 1740 static void brcmf_pcie_setup(struct device *dev, int ret, 1741 struct brcmf_fw_request *fwreq) 1742 { 1743 const struct firmware *fw; 1744 void *nvram; 1745 struct brcmf_bus *bus; 1746 struct brcmf_pciedev *pcie_bus_dev; 1747 struct brcmf_pciedev_info *devinfo; 1748 struct brcmf_commonring **flowrings; 1749 u32 i, nvram_len; 1750 1751 /* check firmware loading result */ 1752 if (ret) 1753 goto fail; 1754 1755 bus = dev_get_drvdata(dev); 1756 pcie_bus_dev = bus->bus_priv.pcie; 1757 devinfo = pcie_bus_dev->devinfo; 1758 brcmf_pcie_attach(devinfo); 1759 1760 fw = fwreq->items[BRCMF_PCIE_FW_CODE].binary; 1761 nvram = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.data; 1762 nvram_len = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.len; 1763 kfree(fwreq); 1764 1765 /* Some of the firmwares have the size of the memory of the device 1766 * defined inside the firmware. This is because part of the memory in 1767 * the device is shared and the devision is determined by FW. Parse 1768 * the firmware and adjust the chip memory size now. 1769 */ 1770 brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size); 1771 1772 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len); 1773 if (ret) 1774 goto fail; 1775 1776 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 1777 1778 ret = brcmf_pcie_init_ringbuffers(devinfo); 1779 if (ret) 1780 goto fail; 1781 1782 ret = brcmf_pcie_init_scratchbuffers(devinfo); 1783 if (ret) 1784 goto fail; 1785 1786 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 1787 ret = brcmf_pcie_request_irq(devinfo); 1788 if (ret) 1789 goto fail; 1790 1791 /* hook the commonrings in the bus structure. */ 1792 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) 1793 bus->msgbuf->commonrings[i] = 1794 &devinfo->shared.commonrings[i]->commonring; 1795 1796 flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings), 1797 GFP_KERNEL); 1798 if (!flowrings) 1799 goto fail; 1800 1801 for (i = 0; i < devinfo->shared.max_flowrings; i++) 1802 flowrings[i] = &devinfo->shared.flowrings[i].commonring; 1803 bus->msgbuf->flowrings = flowrings; 1804 1805 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset; 1806 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost; 1807 bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings; 1808 1809 init_waitqueue_head(&devinfo->mbdata_resp_wait); 1810 1811 brcmf_pcie_intr_enable(devinfo); 1812 brcmf_pcie_hostready(devinfo); 1813 if (brcmf_attach(&devinfo->pdev->dev, devinfo->settings) == 0) 1814 return; 1815 1816 brcmf_pcie_bus_console_read(devinfo); 1817 1818 fail: 1819 device_release_driver(dev); 1820 } 1821 1822 static struct brcmf_fw_request * 1823 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo) 1824 { 1825 struct brcmf_fw_request *fwreq; 1826 struct brcmf_fw_name fwnames[] = { 1827 { ".bin", devinfo->fw_name }, 1828 { ".txt", devinfo->nvram_name }, 1829 }; 1830 1831 fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev, 1832 brcmf_pcie_fwnames, 1833 ARRAY_SIZE(brcmf_pcie_fwnames), 1834 fwnames, ARRAY_SIZE(fwnames)); 1835 if (!fwreq) 1836 return NULL; 1837 1838 fwreq->items[BRCMF_PCIE_FW_CODE].type = BRCMF_FW_TYPE_BINARY; 1839 fwreq->items[BRCMF_PCIE_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM; 1840 fwreq->items[BRCMF_PCIE_FW_NVRAM].flags = BRCMF_FW_REQF_OPTIONAL; 1841 fwreq->board_type = devinfo->settings->board_type; 1842 /* NVRAM reserves PCI domain 0 for Broadcom's SDK faked bus */ 1843 fwreq->domain_nr = pci_domain_nr(devinfo->pdev->bus) + 1; 1844 fwreq->bus_nr = devinfo->pdev->bus->number; 1845 1846 return fwreq; 1847 } 1848 1849 static int 1850 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1851 { 1852 int ret; 1853 struct brcmf_fw_request *fwreq; 1854 struct brcmf_pciedev_info *devinfo; 1855 struct brcmf_pciedev *pcie_bus_dev; 1856 struct brcmf_bus *bus; 1857 1858 brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device); 1859 1860 ret = -ENOMEM; 1861 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL); 1862 if (devinfo == NULL) 1863 return ret; 1864 1865 devinfo->pdev = pdev; 1866 pcie_bus_dev = NULL; 1867 devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops); 1868 if (IS_ERR(devinfo->ci)) { 1869 ret = PTR_ERR(devinfo->ci); 1870 devinfo->ci = NULL; 1871 goto fail; 1872 } 1873 1874 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL); 1875 if (pcie_bus_dev == NULL) { 1876 ret = -ENOMEM; 1877 goto fail; 1878 } 1879 1880 devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev, 1881 BRCMF_BUSTYPE_PCIE, 1882 devinfo->ci->chip, 1883 devinfo->ci->chiprev); 1884 if (!devinfo->settings) { 1885 ret = -ENOMEM; 1886 goto fail; 1887 } 1888 1889 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 1890 if (!bus) { 1891 ret = -ENOMEM; 1892 goto fail; 1893 } 1894 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL); 1895 if (!bus->msgbuf) { 1896 ret = -ENOMEM; 1897 kfree(bus); 1898 goto fail; 1899 } 1900 1901 /* hook it all together. */ 1902 pcie_bus_dev->devinfo = devinfo; 1903 pcie_bus_dev->bus = bus; 1904 bus->dev = &pdev->dev; 1905 bus->bus_priv.pcie = pcie_bus_dev; 1906 bus->ops = &brcmf_pcie_bus_ops; 1907 bus->proto_type = BRCMF_PROTO_MSGBUF; 1908 bus->chip = devinfo->coreid; 1909 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot); 1910 dev_set_drvdata(&pdev->dev, bus); 1911 1912 fwreq = brcmf_pcie_prepare_fw_request(devinfo); 1913 if (!fwreq) { 1914 ret = -ENOMEM; 1915 goto fail_bus; 1916 } 1917 1918 ret = brcmf_fw_get_firmwares(bus->dev, fwreq, brcmf_pcie_setup); 1919 if (ret < 0) { 1920 kfree(fwreq); 1921 goto fail_bus; 1922 } 1923 return 0; 1924 1925 fail_bus: 1926 kfree(bus->msgbuf); 1927 kfree(bus); 1928 fail: 1929 brcmf_err(NULL, "failed %x:%x\n", pdev->vendor, pdev->device); 1930 brcmf_pcie_release_resource(devinfo); 1931 if (devinfo->ci) 1932 brcmf_chip_detach(devinfo->ci); 1933 if (devinfo->settings) 1934 brcmf_release_module_param(devinfo->settings); 1935 kfree(pcie_bus_dev); 1936 kfree(devinfo); 1937 return ret; 1938 } 1939 1940 1941 static void 1942 brcmf_pcie_remove(struct pci_dev *pdev) 1943 { 1944 struct brcmf_pciedev_info *devinfo; 1945 struct brcmf_bus *bus; 1946 1947 brcmf_dbg(PCIE, "Enter\n"); 1948 1949 bus = dev_get_drvdata(&pdev->dev); 1950 if (bus == NULL) 1951 return; 1952 1953 devinfo = bus->bus_priv.pcie->devinfo; 1954 1955 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 1956 if (devinfo->ci) 1957 brcmf_pcie_intr_disable(devinfo); 1958 1959 brcmf_detach(&pdev->dev); 1960 1961 kfree(bus->bus_priv.pcie); 1962 kfree(bus->msgbuf->flowrings); 1963 kfree(bus->msgbuf); 1964 kfree(bus); 1965 1966 brcmf_pcie_release_irq(devinfo); 1967 brcmf_pcie_release_scratchbuffers(devinfo); 1968 brcmf_pcie_release_ringbuffers(devinfo); 1969 brcmf_pcie_reset_device(devinfo); 1970 brcmf_pcie_release_resource(devinfo); 1971 1972 if (devinfo->ci) 1973 brcmf_chip_detach(devinfo->ci); 1974 if (devinfo->settings) 1975 brcmf_release_module_param(devinfo->settings); 1976 1977 kfree(devinfo); 1978 dev_set_drvdata(&pdev->dev, NULL); 1979 } 1980 1981 1982 #ifdef CONFIG_PM 1983 1984 1985 static int brcmf_pcie_pm_enter_D3(struct device *dev) 1986 { 1987 struct brcmf_pciedev_info *devinfo; 1988 struct brcmf_bus *bus; 1989 1990 brcmf_dbg(PCIE, "Enter\n"); 1991 1992 bus = dev_get_drvdata(dev); 1993 devinfo = bus->bus_priv.pcie->devinfo; 1994 1995 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN); 1996 1997 devinfo->mbdata_completed = false; 1998 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM); 1999 2000 wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed, 2001 BRCMF_PCIE_MBDATA_TIMEOUT); 2002 if (!devinfo->mbdata_completed) { 2003 brcmf_err(bus, "Timeout on response for entering D3 substate\n"); 2004 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 2005 return -EIO; 2006 } 2007 2008 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 2009 2010 return 0; 2011 } 2012 2013 2014 static int brcmf_pcie_pm_leave_D3(struct device *dev) 2015 { 2016 struct brcmf_pciedev_info *devinfo; 2017 struct brcmf_bus *bus; 2018 struct pci_dev *pdev; 2019 int err; 2020 2021 brcmf_dbg(PCIE, "Enter\n"); 2022 2023 bus = dev_get_drvdata(dev); 2024 devinfo = bus->bus_priv.pcie->devinfo; 2025 brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus); 2026 2027 /* Check if device is still up and running, if so we are ready */ 2028 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0) { 2029 brcmf_dbg(PCIE, "Try to wakeup device....\n"); 2030 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM)) 2031 goto cleanup; 2032 brcmf_dbg(PCIE, "Hot resume, continue....\n"); 2033 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 2034 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 2035 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 2036 brcmf_pcie_intr_enable(devinfo); 2037 brcmf_pcie_hostready(devinfo); 2038 return 0; 2039 } 2040 2041 cleanup: 2042 brcmf_chip_detach(devinfo->ci); 2043 devinfo->ci = NULL; 2044 pdev = devinfo->pdev; 2045 brcmf_pcie_remove(pdev); 2046 2047 err = brcmf_pcie_probe(pdev, NULL); 2048 if (err) 2049 brcmf_err(bus, "probe after resume failed, err=%d\n", err); 2050 2051 return err; 2052 } 2053 2054 2055 static const struct dev_pm_ops brcmf_pciedrvr_pm = { 2056 .suspend = brcmf_pcie_pm_enter_D3, 2057 .resume = brcmf_pcie_pm_leave_D3, 2058 .freeze = brcmf_pcie_pm_enter_D3, 2059 .restore = brcmf_pcie_pm_leave_D3, 2060 }; 2061 2062 2063 #endif /* CONFIG_PM */ 2064 2065 2066 #define BRCMF_PCIE_DEVICE(dev_id) { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\ 2067 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 } 2068 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev) { \ 2069 BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\ 2070 subvend, subdev, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 } 2071 2072 static const struct pci_device_id brcmf_pcie_devid_table[] = { 2073 BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID), 2074 BRCMF_PCIE_DEVICE_SUB(0x4355, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4355), 2075 BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_RAW_DEVICE_ID), 2076 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID), 2077 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID), 2078 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID), 2079 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID), 2080 BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID), 2081 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID), 2082 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID), 2083 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID), 2084 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID), 2085 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID), 2086 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID), 2087 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID), 2088 BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365), 2089 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID), 2090 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID), 2091 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID), 2092 BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID), 2093 { /* end: all zeroes */ } 2094 }; 2095 2096 2097 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table); 2098 2099 2100 static struct pci_driver brcmf_pciedrvr = { 2101 .node = {}, 2102 .name = KBUILD_MODNAME, 2103 .id_table = brcmf_pcie_devid_table, 2104 .probe = brcmf_pcie_probe, 2105 .remove = brcmf_pcie_remove, 2106 #ifdef CONFIG_PM 2107 .driver.pm = &brcmf_pciedrvr_pm, 2108 #endif 2109 .driver.coredump = brcmf_dev_coredump, 2110 }; 2111 2112 2113 void brcmf_pcie_register(void) 2114 { 2115 int err; 2116 2117 brcmf_dbg(PCIE, "Enter\n"); 2118 err = pci_register_driver(&brcmf_pciedrvr); 2119 if (err) 2120 brcmf_err(NULL, "PCIE driver registration failed, err=%d\n", 2121 err); 2122 } 2123 2124 2125 void brcmf_pcie_exit(void) 2126 { 2127 brcmf_dbg(PCIE, "Enter\n"); 2128 pci_unregister_driver(&brcmf_pciedrvr); 2129 } 2130