1 /* 2 * Copyright (c) 2014 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 #ifndef BRCMF_CHIP_H 17 #define BRCMF_CHIP_H 18 19 #include <linux/types.h> 20 21 #define CORE_CC_REG(base, field) \ 22 (base + offsetof(struct chipcregs, field)) 23 24 /** 25 * struct brcmf_chip - chip level information. 26 * 27 * @chip: chip identifier. 28 * @chiprev: chip revision. 29 * @cc_caps: chipcommon core capabilities. 30 * @cc_caps_ext: chipcommon core extended capabilities. 31 * @pmucaps: PMU capabilities. 32 * @pmurev: PMU revision. 33 * @rambase: RAM base address (only applicable for ARM CR4 chips). 34 * @ramsize: amount of RAM on chip including retention. 35 * @srsize: amount of retention RAM on chip. 36 * @name: string representation of the chip identifier. 37 */ 38 struct brcmf_chip { 39 u32 chip; 40 u32 chiprev; 41 u32 cc_caps; 42 u32 cc_caps_ext; 43 u32 pmucaps; 44 u32 pmurev; 45 u32 rambase; 46 u32 ramsize; 47 u32 srsize; 48 char name[8]; 49 }; 50 51 /** 52 * struct brcmf_core - core related information. 53 * 54 * @id: core identifier. 55 * @rev: core revision. 56 * @base: base address of core register space. 57 */ 58 struct brcmf_core { 59 u16 id; 60 u16 rev; 61 u32 base; 62 }; 63 64 /** 65 * struct brcmf_buscore_ops - buscore specific callbacks. 66 * 67 * @read32: read 32-bit value over bus. 68 * @write32: write 32-bit value over bus. 69 * @prepare: prepare bus for core configuration. 70 * @setup: bus-specific core setup. 71 * @active: chip becomes active. 72 * The callback should use the provided @rstvec when non-zero. 73 */ 74 struct brcmf_buscore_ops { 75 u32 (*read32)(void *ctx, u32 addr); 76 void (*write32)(void *ctx, u32 addr, u32 value); 77 int (*prepare)(void *ctx); 78 int (*reset)(void *ctx, struct brcmf_chip *chip); 79 int (*setup)(void *ctx, struct brcmf_chip *chip); 80 void (*activate)(void *ctx, struct brcmf_chip *chip, u32 rstvec); 81 }; 82 83 struct brcmf_chip *brcmf_chip_attach(void *ctx, 84 const struct brcmf_buscore_ops *ops); 85 void brcmf_chip_detach(struct brcmf_chip *chip); 86 struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *chip, u16 coreid); 87 struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *chip); 88 struct brcmf_core *brcmf_chip_get_pmu(struct brcmf_chip *pub); 89 bool brcmf_chip_iscoreup(struct brcmf_core *core); 90 void brcmf_chip_coredisable(struct brcmf_core *core, u32 prereset, u32 reset); 91 void brcmf_chip_resetcore(struct brcmf_core *core, u32 prereset, u32 reset, 92 u32 postreset); 93 void brcmf_chip_set_passive(struct brcmf_chip *ci); 94 bool brcmf_chip_set_active(struct brcmf_chip *ci, u32 rstvec); 95 bool brcmf_chip_sr_capable(struct brcmf_chip *pub); 96 97 #endif /* BRCMF_AXIDMP_H */ 98